KR20210063666A - Apparatus and Method for Interface Circuit - Google Patents

Abstract

The present invention relates to an apparatus and method for testing an interface circuit. In accordance with an embodiment of the present invention, the apparatus for testing the interface circuit comprises a physical layer test apparatus. The physical layer test apparatus can be configured to comprise: a test pattern generation unit which stores a plurality of test signals of a first bit, and a test pattern of a second bit, which is greater than the first bit corresponding to each of the plurality of test signals, in a lookup table; a transmission unit which, as a first test signal is transmitted from a test unit, refers to the lookup table, receives the test pattern corresponding to the first test signal as a transmission-side test signal, and converts the signal into a physical layer transmission signal; and a reception unit which converts a physical layer transmission signal provided from the transmission unit into a link layer transmission signal, generates a reception-side test pattern, extracts a second test signal corresponding to the reception-side test pattern from the lookup table, and transmits the signal to the test unit. The present invention aims to provide an apparatus and method for testing an interface circuit, which are able to minimize the number of pads required for a test chip.

Description

Interface Circuit Test Apparatus and Method {Apparatus and Method for Interface Circuit}

The present technology relates to a test apparatus, and more particularly, to an electromagnetic-to-electromagnetic interface circuit test apparatus and method.

An electronic device may perform a unique function alone or may perform a unique function while exchanging data with another electronic device. Interface technology is used to exchange data between electronic devices.

In order to perform communication between electronic devices, a link (or lane) connecting the electronic devices is formed, and data transmission/reception must be performed through this.

Therefore, it is necessary to verify in advance whether a link (lane) between electronic devices is normally formed and data is normally transmitted/received through the formed link (lane).

Embodiments of the present technology may provide an interface circuit test apparatus and method capable of minimizing the number of pads provided in a test chip.

An interface circuit test apparatus between electronic devices according to an embodiment of the present technology is an interface circuit test apparatus including a physical layer test apparatus, wherein the physical layer test apparatus includes a plurality of test signals of a first bit and the plurality of test signals a test pattern generator for storing a test pattern of a second bit larger than the first bit corresponding to each of the test patterns as a lookup table; a transmitter configured to receive a test pattern corresponding to the first test signal as a transmitter-side test signal and convert it into a physical layer transmission signal with reference to the lookup table as the first test signal is transmitted from the test unit; and converting the physical layer transmission signal provided from the transmitter into a link layer transmission signal to generate a reception side test pattern, and extracting a second test signal corresponding to the reception side test pattern from the lookup table to the test unit It may be configured to include; a receiving unit for transmitting.

The interface circuit test method between electronic devices according to an embodiment of the present technology is a test method of an interface circuit test apparatus including a physical layer test apparatus, wherein the physical layer test apparatus includes a plurality of test signals of a first bit and the plurality of test signals. storing a test pattern of a second bit larger than the first bit corresponding to each test signal in a lookup table; As the first test signal is transmitted from the test unit, the physical layer test apparatus extracts a test pattern corresponding to the first test signal as a transmitting-side test pattern based on the lookup table and converts it into a physical layer transmission signal step; generating, by the physical layer test device, a reception-side test pattern by converting the physical layer transmission signal into a link layer transmission signal; and extracting, by the physical layer test device, a second test signal corresponding to the receiving-side test pattern based on the lookup table and transmitting the second test signal to the test unit. It may be configured to include

According to the present technology, the number of pads required for the test chip can be minimized, so that the test chip can be miniaturized.

In addition, it is possible to reduce the test time by performing the test according to the test pattern composed of the lookup table.

1 is a diagram for describing an interface between electronic devices according to an exemplary embodiment.
2 is a block diagram of an apparatus for testing an interface circuit between electronic devices according to an exemplary embodiment.
3 is a block diagram of a physical layer test apparatus according to an embodiment.
4 is a block diagram of a physical layer test apparatus according to an embodiment.
5 is a flowchart illustrating a method for testing an interface circuit between electronic devices according to an exemplary embodiment.

Hereinafter, embodiments of the present technology will be described in more detail with reference to the accompanying drawings.

1 is a diagram for describing an interface between electronic devices according to an embodiment.

FIG. 1 illustrates an electronic system 100 in which a first electronic device 110 and a second electronic device 120 are electrically connected through a first interface circuit 111 and a second interface circuit 121 .

FIG. 1 is a simplified configuration diagram for helping understanding of the present invention. Of course, each of the first electronic device 110 and the second electronic device 120 may further include other components not shown in FIG. 1 .

In an embodiment, the first electronic device 110 may include a host device or an application processor. In an embodiment, the second electronic device 120 may be one of a data storage device, a display device, an image sensor, a wireless communication chip, and the like.

The first interface circuit 111 may include a first physical layer (PL1) and a first link layer (LL1). The first physical layer PL1 may include physical components for exchanging data with the second electronic device 120 . For example, the first physical layer PL1 may include one or more transmitters and one or more receivers for exchanging data with the second electronic device 120 . The first link layer LL1 may manage data transmission and composition. Furthermore, the first link layer LL1 may manage data integrity and errors.

In an embodiment, when the first electronic device 110 and the second electronic device 120 are mobile electronic devices, the first link layer LL1 may be defined by the UniPro specification, The first physical layer PL1 may be defined by the M-PHY standard. UniPro and M-PHY are interface protocols proposed by the Mobile Industry Processor Interface (MIPI) Alliance.

The first controller 113 may manage and control the overall operation of the first electronic device 110 . In particular, the first controller 113 may process and manage data exchanged through the first interface circuit 111 . Under the control of the first controller 115 , the first electronic device 110 may perform a unique function.

The second electronic device 120 may be connected to the first electronic device 110 through the second interface circuit 121 to exchange data.

The second interface circuit 121 may include a second physical layer PL2 and a second link layer LL2 . The second physical layer PL2 may include physical components for exchanging data with the first electronic device 110 . In an embodiment, the second physical layer PL2 may include one or more transmitters and one or more receivers for exchanging data with the first electronic device 110 . The second link layer LL2 may manage the transmission and combination of data. Furthermore, the second link layer LL2 may manage data integrity and errors.

In an embodiment, when the first electronic device 110 and the second electronic device 120 are mobile electronic devices, the second link layer LL2 may be defined by the UniPro standard, and the second physical layer PL2 ) may be defined by the M-PHY standard.

The second controller 123 may manage and control the overall operation of the second electronic device 120 . In particular, the second controller 123 may process and manage data exchanged through the second interface circuit 121 . According to the control of the second controller 123 , the second electronic device 120 may perform a unique function.

In an embodiment, when the second electronic device 120 is a storage device including a flash memory, the second controller 123 operates according to an interface protocol defined in a Universal Flash Storage (UFS) specification proposed by JEDEC. can do. In this embodiment, when the first electronic device 110 is a host, the first controller 115 may operate according to an interface protocol defined in a UFS Host Controller Interface (UFSHCI) specification.

It goes without saying that various forms constituting the first and second interface circuits 111 and 121 may be changed or modified according to the types of the first electronic device 110 and the second electronic device 120 .

The physical layer (PL) and the link layer (LL) transmit and receive data through numerous pins. When manufacturing an interface chip for testing to verify the interface circuit, a more efficient test method is required because a number of pins used in the interface circuit need to be extended to an external pad.

In this technology, only a minimum number of pads are designed in the interface chip for testing, and various test patterns can be generated through this.

2 is a configuration diagram of an apparatus for testing an interface circuit between electronic devices according to an exemplary embodiment.

Referring to FIG. 2 , the test apparatus 20 according to an embodiment may include a test unit 210 and a test chip 220 .

The test unit 210 may configure the test pattern generated in response to the plurality of test signals SIG1 and SIG2 as a lookup table LUT and store it in the test chip 220 . In the test mode, the test unit 210 generates a first test signal SIG1 and transmits it to the test chip 220 , and receives the second test signal SIG2 from the test chip 220 so that the test chip 220 is You can verify that it works normally.

The test chip 220 may include a link layer test device 221 and a physical layer test device 223 .

The link layer test device 221 receives the first test signal SIG1 from the test unit 210 and transmits it to the physical layer test device 223 , and the second test signal SIG2 from the physical layer test device 223 . may be configured to receive and transmit to the test unit 210 .

The physical layer test apparatus 221 may include a test pattern generator 225 , a transmitter TX, and a receiver RX.

The test pattern generator 225 may receive and store the lookup table from the test unit 210 . To this end, the test unit 210 and the test chip 220 may be connected through an Inter Integrated Circuit (I2C) interface or a Serial Peripheral Interface (SPI). The lookup table may be changed by an operator, and the changed lookup table may be transmitted from the test unit 210 to the test pattern generator 225 to be updated.

The lookup table may include a first LUT that is a lookup table for the transmitter TX and a second LUT that is a lookup table for the receiver RX. The first LUT may be mapping information of the transmitting-side test pattern TT corresponding to the first test signal SIG1. The second LUT may be mapping information of the second test signal SIG2 corresponding to the receiving-side test pattern RT generated by the receiving unit RX.

1st LUT 2nd LUT first test signal SIG1 Transmitting test pattern (TT) Receive side test pattern (RT) Second test signal SIG2

The transmitter TX may include m input pads, and ^{may sequentially receive 2 m} (branches) first test signals SIG1 through this.

As the m-bit first test signal SIG1 provided from the test unit 210 is transmitted to the physical layer test device 223 through the link layer test device 221 , the test pattern generator 225 generates the first An n (>m)-bit transmitting-side test pattern TT corresponding to the first test signal SIG1 may be transmitted to the transmitter TX with reference to the LUT.

The transmitting unit TX may convert the n-bit transmitting-side test pattern TT to correspond to the physical layer transmission signal of the interface protocol adopted by the test chip 220 and transmit (loopback) the n-bit transmission side test pattern TT to the receiving unit RX.

The reception unit RX may generate an n-bit reception side test pattern RT by converting a signal received from the transmission unit TX to correspond to a link layer transmission signal of a corresponding protocol.

The test pattern generator 225 may extract an m-bit second test signal SGI2 corresponding to the n-bit receiving-side test pattern RT with reference to the second LUT. The receiver RX may include m output pads, and the second test signal SIG2 may be transmitted to the link layer test apparatus 221 through the output pads.

As such, the physical layer test device 223 transmits/receives data to and from an external device, for example, the link layer test device 221 through m input pads and m output pads. On the other hand, the physical layer test device 223 may internally transmit and receive tests generated in units of n (>m) bits.

In the physical layer test device 223 , the data line through which the transmitter TX receives the test pattern TT on the transmitter side and the data line on which the receiver RX outputs the test pattern RT on the receiver side actually form an interface circuit. When applied to an electronic device, it may correspond to a pin connecting the physical layer and the link layer. There are 200 to 400 pins connecting the physical layer and the link layer. However, in this technology, each of these pins is not extended to an external pad, but the first test signal SIG1 is applied to the transmitter TX through m (10 to 16) input pads, and the test signal is n-bit It is possible to verify the data line corresponding to the pin connecting the link layer and the transmitter TX by converting it into the transmission-side test pattern TT. Similarly, a data line corresponding to a pin connecting the receiving unit RX and the link layer by converting the n-bit reception side test pattern RT generated by the receiving unit RX into an m-bit second test signal SIG2 can be verified.

As a result, since only m pads are used to verify the n data lines, the size of the test chip 220 can be miniaturized, and the manufacturing cost and time can be reduced.

3 is a block diagram of a physical layer test apparatus according to an embodiment.

Referring to FIG. 3 , the physical layer test apparatus 223 may include an encoder 2251 , a transmitter TX, a receiver RX, and a decoder 2253 . The encoder 2251 and the decoder 2253 may constitute the test pattern generator 225 .

The encoder 2251 may store the first lookup table LUT1. The encoder 2251 receives an m-bit first test signal (SIG1; IN[1:m]) from the link layer (LL) test device 221 , and refers to the first lookup table LUT1 for a first test The n-bit transmission-side test signal TT[1:n] corresponding to the signal SIG1; IN[1:m] may be extracted and transmitted to the transmission unit TX. The first test signal SIG1 ; IN[1:m] may be a signal provided from the test unit 210 .

The transmitting unit TX may convert the transmitting-side test signal TT[1:n] to correspond to a physical layer transmission signal of a corresponding interface protocol and transmit (loopback) to the receiving unit RX.

The receiving unit RX may convert the loopback signal to correspond to a link layer transmission signal of a corresponding protocol to generate an n-bit receiving-side test pattern (RT[1:n]).

The decoder 2253 is

A second lookup table LUT2 may be stored. The decoder 2253 refers to the second lookup table LUT2 and refers to the m-bit second test signal SIG2; OUT[1] corresponding to the reception-side test pattern RT[1:n] transmitted from the reception unit RX. :m]) can be extracted and transmitted to the link layer (LL) test device 221 .

The second test signal SIG2; OUT[1:m]) is transmitted to the test unit 210 , and the test unit 210 includes the first test signal SIG1; IN[1:m]) and the second test signal ( SIG2; OUT[1:m]) may be compared to verify whether the test chip 210 operates normally.

4 is a block diagram of a physical layer test apparatus according to an embodiment.

The physical layer test apparatus 223-1 shown in FIG. 4 is the same as the physical layer test apparatus 223 of FIG. 3 except for the skew control unit 227, and thus the description of overlapping components will be omitted. .

The skew controller 227 may receive the clock signal CLK from the transmitter TX and control the input timing of the first test signal SIG1 to the encoder 2251 to be the same as IN[1:m].

In an embodiment, the skew control unit 227 may include latch circuits L1 to Lm connected to each input pad to latch the input signal for a set time in synchronization with the clock signal CLK.

By controlling the input timing of the first test signal SIG1 ; IN[1:m] by the skew control unit 227 , it is possible to prevent malfunction of the test chip 220 .

5 is a flowchart illustrating a method for testing an interface circuit between electronic devices according to an exemplary embodiment.

Referring to FIG. 5 , a lookup table configured by an operator may be stored in the physical layer test apparatus 223 of the test chip 220 ( S101 ).

In an embodiment, the lookup table may include a first lookup table LUT1 for the transmitter TX and a second lookup table LUT2 for the receiver RX. The first LUT LUT1 may be mapping information of the transmission side test pattern TT corresponding to the first test signal SIG1 . The second LUT LUT2 may be mapping information of the second test signal SIG2 corresponding to the reception-side test pattern RT generated by the reception unit RX.

As the test mode starts, the first test signal SIG1 provided from the test unit 210 is transmitted to the physical layer test device 223 through the link layer test device 221 of the test chip 220 ( S103 ). ).

The test pattern generator 2251 of the physical layer test apparatus 223, and according to an embodiment, the encoder 2251 refers to the first LUT (LUT1) and n (>) corresponding to the m-bit first test signal SIG1. m) The transmission side test pattern TT of bits may be extracted and transmitted to the transmission unit TX (S105).

The transmitting unit TX may convert the n-bit transmitting side test pattern TT to correspond to the physical layer transmission signal of the interface protocol adopted by the test chip 220 and transmit (loopback) to the receiving unit RX (S107) .

The receiving unit RX may generate an n-bit receiving-side test pattern RT by converting the signal received from the transmitting unit TX to correspond to the link layer transmission signal of the corresponding protocol ( S109 ).

The test pattern generator 225 , according to an embodiment, the decoder 2253 refers to the second LUT (LUT2), and the m-bit second test signal SGI2 corresponding to the n-bit receiving-side test pattern RT. can be extracted. The receiver RX may include m output pads, and the second test signal SIG2 may be transmitted to the test unit 210 through the link layer test apparatus 221 through the output pads ( S111 ).

Check whether the test for the test pattern composed of the first and second lookup tables (LUT1, LUT2) is completed (S113). If the test is not completed, that is, if the test pattern that has not yet been tested remains, go to step S103 It may return and repeat the subsequent process (S113:N). When testing for all test patterns composed of the first and second lookup tables LUT1 and LUT2 is completed (S113:Y), it is checked whether the lookup table has been changed (S115).

When the lookup table is changed (S115:Y), the process returns to step S101 and the subsequent process is repeated. When the lookup table is not changed (S115:N), the test process can be ended.

In this way, when the test chip for testing the interface circuit is manufactured as a single chip, the interface circuit can be verified at high speed by generating various test patterns while minimizing the number of input/output pads.

Those skilled in the art to which the present invention pertains will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the claims to be described later rather than the detailed description, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention do.

100: electronic system
110. 120: electronic device
20: interface circuit test device
210: test unit
220: test chip

Claims (11)

An interface circuit test device comprising a physical layer test device, comprising:
The physical layer test device,
a test pattern generator configured to store a plurality of test signals of a first bit and a test pattern of a second bit larger than the first bit corresponding to each of the plurality of test signals as a lookup table;
a transmitter configured to receive a test pattern corresponding to the first test signal as a transmitter-side test signal and convert it into a physical layer transmission signal with reference to the lookup table when the first test signal is transmitted from the test unit; and
The physical layer transmission signal provided from the transmitter is converted into a link layer transmission signal to generate a reception side test pattern, and a second test signal corresponding to the reception side test pattern is extracted from the lookup table and transmitted to the test unit receiving unit;
An interface circuit test device configured to include a. The method of claim 1,
The test pattern generator may include: an encoder configured to store the first test signal and a corresponding transmitting-side test pattern as a first lookup table; and
a decoder for storing the second test signal and the corresponding first receiving-side test pattern as a second lookup table;
Interface circuit test device comprising a. The method of claim 1,
Interface further comprising a link layer test device for transmitting the first test signal received from the test unit to the physical layer test device, and transmitting the second test signal received from the physical layer test device to the test unit circuit test device. The method of claim 3,
The physical layer test device uses the M-PHY protocol and the link layer test device uses the UniPro protocol. The method of claim 1,
and a skew controller configured to receive a clock signal from the transmitter and control an input timing of each data included in the first test signal. The method of claim 1,
and the lookup table is changed through the test unit. A test method for an interface circuit test device comprising a physical layer test device, comprising:
storing, by the physical layer test apparatus, a plurality of first bit test signals and a test pattern of a second bit larger than the first bit corresponding to each of the plurality of test signals in a lookup table;
As the first test signal is transmitted from the test unit, the physical layer test device extracts a test pattern corresponding to the first test signal as a transmitting-side test pattern based on the lookup table and converts it into a physical layer transmission signal step;
generating, by the physical layer test device, a reception side test pattern by converting the physical layer transmission signal into a link layer transmission signal; and
extracting, by the physical layer test device, a second test signal corresponding to the receiving-side test pattern based on the lookup table and transmitting the second test signal to the test unit;
An interface circuit test method configured to include a. The method of claim 7,
The test device further includes a link layer test device,
receiving, by the link layer test device, the first test signal from the test unit and transmitting the first test signal to the physical layer test device; and
receiving, by the link layer test device, the second test signal from the physical layer test device and transmitting the second test signal to the test unit;
Interface circuit test method further comprising a. The method of claim 8,
The interface circuit test method wherein the physical layer test device uses the M-PHY protocol and the link layer test device uses the UniPro protocol. The method of claim 7,
The physical layer test apparatus includes a transmitter that extracts the test pattern on the transmitter side and converts it into the physical layer transmission signal, and a receiver that transmits the second test signal to the test unit,
and controlling an input timing of each data included in the first test signal in response to the clock signal transmitted from the transmitter. The method of claim 7,
and updating the lookup table via the test unit.

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