KR20210055480A - Driver integrated circuit and display device including the same - Google Patents

Abstract

A driver integrated circuit of the present invention comprises: a DAC unit which includes a plurality of DAC-AMPs and senses a sensing current of a pixel input to a sensing line, and in which in a first mode, a plurality of DAC-AMPs generate image data voltages, respectively, to supply data voltages to data lines to which pixels are connected, and in a second mode, each of the DAC-AMPs operates in a configuration for current sensing to supply a sensing data voltage to any one of pixels; and a switching unit respectively connecting the DAC-AMPs to the data lines in the first mode, and connecting any one of the DAC-AMPs to any one of the data lines in the second mode. Accordingly, by controlling the DACs for supplying a data voltage to operate as a current integrator, a comparator, a feedback DAC, and a DAC for generating a reference voltage for measuring a sensing current, it is possible to perform a current sensing function without a separate current sensing unit. Accordingly, since components such as a current integrator amplifier (CI-AMP) and an ADC for configuring the current sensing unit can be deleted, the size of a source driver IC (SD-IC) can be significantly reduced.

Description

DRIVER INTEGRATED CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a driver integrated circuit and a display device including the same.

The organic light emitting display device includes a driving element, that is, a driving TFT (Thin Film Transistor), that controls a driving current flowing through the OLED according to a voltage applied between a gate electrode and a source electrode of pixels each including OLED. The electrical characteristics of the OLED and the driving TFT may change due to temperature or deterioration, and if the electrical characteristics are different for each pixel, the luminance between the pixels for the same video data is different, making it difficult to realize a desired image.

Among technologies for compensating for changes in electrical characteristics for OLEDs or driving TFTs, external compensation technologies are known. The external compensation technology senses changes in the electrical characteristics of OLEDs or driving TFTs, and modulates digital video data based on the sensing results. In order to implement the external compensation technology, a current sensing unit for sensing currents of pixels is required. Typically, the current sensing unit is composed of a current integrator and an analog-to-digital converter (hereinafter referred to as ADC), and is embedded in a source driver integrated circuit (hereinafter referred to as SD-IC).

When the current sensing unit function is added, there is a problem in that the size of the SD-IC increases as a current integrator and ADC must be additionally designed in the SD-IC. Accordingly, research to minimize the increase in the size of the SD-IC while maintaining the current sensing function is being continued.

The present invention for solving the problems of the above-described background technology is to provide a driver integrated circuit and a display device including the same, which can minimize an increase in the chip size of a driver IC due to an increase in the number of ADCs for a current sensing function. The purpose.

As a means for solving the above-described problems, the driver integrated circuit of the present invention includes a plurality of DAC-AMPs, and in a first mode, the plurality of DAC-AMPs respectively generate an image data voltage to each data line to which a pixel is connected. When supplying a voltage and in the second mode, the plurality of DAC-AMPs each operate as a configuration for current sensing, supplying a sensing data voltage to any one of the pixels, and sensing the sensing current of the pixel input to a sensing line. A DAC unit including a plurality of DAC-AMPs; And a switching unit for connecting the plurality of DAC-AMPs to the data lines in the first mode, and connecting any one of the plurality of DAC-AMPs to any one of the data lines in the second mode. Includes.

The plurality of DAC-AMPs may include a DAC-AMP that operates as a current integrator in the second mode, a DAC-AMP that operates as a comparator, and a feedback DAC that feeds a voltage back to the comparator.

The DAC-AMP operating as the integrator includes an inverting input terminal to which the sensing current is input, a non-inverting input terminal connected to a reference voltage, and an output terminal to output an integral value of the sensing current, and between the non-inverting input terminal and the output terminal An integrating capacitor connected; And an initialization switch connected in parallel to the integrating capacitor.

It may further include a sampling and hold unit connected to the output terminal of the DAC-AMP operating as the integrator to store and output the integral value of the sensing current.

The DAC-AMP operating as the comparator includes an inverting input terminal to which the integrated value of the sensing current is input, a non-inverting input terminal connected to a feedback voltage, and an output terminal for outputting a comparison value of the integrated value of the sensing current and the feedback voltage. And a logic unit connected to the output terminal to output digital data according to an output value of the comparator; It may include.

The feedback DAC may be connected between the logic unit and the non-inverting input terminal of the comparator to convert the digital data output from the logic unit into an analog voltage to apply the feedback voltage.

When the output value of the comparator is the same as the integral value of the sensing current and the feedback voltage, the logic unit may output the digital data as sensing data of the sensing current.

According to the above-described problem solving means, the display device of the present invention includes: a display panel including a plurality of pixels and data lines and sensing lines connected to the pixels; And a source driver IC including a plurality of DAC-AMPs for supplying an image data voltage to the data line, wherein the source driver IC comprises: in a first mode, the plurality of DAC-AMPs provide the image data to the data line. When a voltage is applied and in the second mode, each of the plurality of DAC-AMPs operates as a configuration for current sensing, supplying a sensing data voltage to any one of the pixels, and sensing the sensing current of the pixel input through a sensing line. do.

In the first mode, the source driver IC connects the plurality of DAC-AMPs to the data lines, respectively, and in the second mode, the source driver IC connects any one of the plurality of DAC-AMPs to any one of the data lines. It may include a switching unit to connect.

In the second mode, the source driver IC may further include a timing controller for receiving sensing data of the sensing current of the pixel according to the sensing data voltage.

The plurality of DAC-AMPs may include a DAC-AMP that operates as a current integrator in the second mode, a DAC-AMP that operates as a comparator, and a feedback DAC that feeds a voltage back to the comparator.

The DAC-AMP operating as the integrator includes an inverting input terminal to which the sensing current is input, a non-inverting input terminal connected to a reference voltage, and an output terminal to output an integral value of the sensing current, and between the non-inverting input terminal and the output terminal An integrating capacitor connected; And an initialization switch connected in parallel to the integrating capacitor. And a sampling and holding unit connected to the output terminal of the DAC-AMP operating as the integrator to store and output an integral value of the sensing current.

The DAC-AMP operating as the comparator includes an inverting input terminal to which the integrated value of the sensing current is input, a non-inverting input terminal connected to a feedback voltage, and an output terminal for outputting a comparison value of the integrated value of the sensing current and the feedback voltage. And a logic unit connected to the output terminal to output digital data according to an output value of the comparator.

The feedback DAC may be connected between the logic unit and the non-inverting input terminal of the comparator to convert the digital data output from the logic unit into an analog voltage to apply the feedback voltage to the comparator.

When the output value of the comparator is the same as the integral value of the sensing current and the feedback voltage, the logic unit may output the digital data as sensing data of the sensing current.

The drive IC of the present invention and a display device including the same are provided with a separate current sensing unit by controlling the DACs supplying the data voltage to operate as a current integrator, a comparator, a feedback DAC, and a DAC for generating a reference voltage for measuring a sensing current, respectively. Current sensing function can be performed without the need. Accordingly, since the configuration of the current integrator amplifier (CI-AMP) and ADC for configuring the current sensing unit can be eliminated, the size of the source driver IC (SD-IC) can be significantly reduced.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.
2 is a diagram showing a schematic configuration example of a driver IC and a pixel array according to an embodiment of the present invention.
3 is a diagram showing a detailed configuration of the pixel array of FIG. 2.
4 is a diagram for explaining the configuration of a driver IC according to the first embodiment of the present invention.
5 is a diagram for explaining the configuration of a driver IC according to a second embodiment of the present invention.
6 is a diagram showing in detail the configuration of a driver IC and a pixel array according to a second embodiment of the present invention.
7 is a diagram for explaining the operation of a circuit in a first operation mode of a driver IC according to a second embodiment of the present invention.
FIG. 8 is a diagram illustrating a control waveform diagram for controlling a switch in the first operation mode of FIG. 7.
9 is a diagram for explaining circuit operation in a second operation mode of a driver IC according to a second embodiment of the present invention.
10 is a diagram illustrating a control waveform diagram for controlling a switch in a second operation mode of FIG. 9.
11 is a diagram illustrating an equivalent circuit in the second operation mode of FIG. 9.
12 is a diagram illustrating an operation flow of a driver IC in a second operation mode according to the second embodiment of the present invention.

Advantages and features of the present specification, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only the present embodiments are intended to complete the disclosure of the present specification, and common knowledge in the technical field to which the present specification pertains. It is provided to completely inform the scope of the invention to those who have, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and the present specification is not limited to the illustrated matters. The same reference numerals refer to the same elements throughout the specification. When'include','have','consists of' and the like mentioned in the present specification are used, other parts may be added unless'only' is used. In the case of expressing the constituent elements in the singular, it includes the case of including the plural unless specifically stated otherwise.

In interpreting the constituent elements, it is interpreted as including an error range even if there is no explicit description.

In the case of a description of the positional relationship, for example, if the positional relationship of the two parts is described as'on the top','on the top of the ~','the bottom of the','the next to the', etc.,'right' Or, unless'direct' is used, one or more other parts may be located between the two parts.

First, second, etc. may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be a second component within the technical idea of the present specification.

The same reference numerals refer to substantially the same constituent elements throughout the specification.

Hereinafter, exemplary embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device includes a display panel 10 in which a plurality of pixels are formed, a scan driver 13, a data driver 12, a timing controller 11, and the like.

A plurality of data lines 14A, a plurality of sensing lines 14B, and a plurality of scan lines 15 are disposed on the display panel 10. Pixels PXL are disposed in an intersection area of the plurality of data lines 14A, the plurality of sensing lines 14B, and the plurality of scan lines 15. Each of the pixels PXL includes an organic light-emitting device (hereinafter, referred to as OLED) that emits light, and a driving transistor (hereinafter, referred to as a driving TFT) for driving the same.

The timing controller 11 receives a data enable signal DE or a driving signal including a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and the like from the image processing unit and a data signal DATA. The timing controller 11 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 13 and a data timing control signal DDC for controlling the operation timing of the data driver 12 based on the driving signal. Prints.

The scan driver 13 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 11. The scan driver 13 outputs a scan signal consisting of a scan high voltage and a scan low voltage through the scan lines 15. The scan driver 13 may be formed in the form of an integrated circuit (IC) or may be formed on the display panel 10 in a gate-in panel method.

The data driver 12 converts the digital data signal DATA into an analog data voltage based on the gamma reference voltage in response to the data timing control signal DDC supplied from the timing controller 11.

An element such as an OLED or a driving TFT included in the pixels PXL may deteriorate in proportion to the driving time, and characteristics (eg, a threshold voltage) may be deteriorated. To compensate for this, the data driver 12 senses a characteristic of a device included in at least one of the pixels PXL and feeds back the sensed sensing data SD to the timing controller 11. The timing controller 11 may correct the data signal DATA to be written to the pixel P based on the sensing data SD fed back from the data driver 12. A circuit for sensing an element included in a pixel may be implemented as a separate sensing circuit other than the data driver 12. However, hereinafter, the sensing circuit included in the data driver 12 will be described as an example.

2 is a diagram illustrating a schematic configuration example of a data driver and a pixel array according to an embodiment of the present invention.

The data driver 12 includes at least one source driver IC (SD-IC). The source driver IC (SD-IC) senses a plurality of digital-analog converters 121 (hereinafter referred to as DACs) connected to each data line 14A, and a plurality of currents connected to each sensing line 14B through a sensing channel. It is provided with the chords 122.

The source driver IC (SD-IC) outputs digital video data input from the timing controller 11 to the pixel array through the DACs 121. During the image display operation, the DAC converts digital video data RGB input from the timing controller 11 into a data voltage for image display and supplies it to the data lines 14A. During the external compensation operation, the DAC may generate an external compensation data voltage of a predetermined level and supply it to the data lines 14A.

The current sensing unit 122 senses a pixel current input through the sensing line 14B, and converts a digital sensing value SD through analog-to-digital converters (hereinafter, ADC) and outputs the sensing result. The current sensing unit 122 may sense the pixel current using a current integrator and an amplifier capable of operating as a comparator.

3 is a diagram showing a detailed configuration of the pixel array of FIG. 2.

Referring to FIG. 3, each pixel P is on any one of the data lines 14A, on any of the sensing lines 14B, on any of the first gate lines 15A, and the second It may be connected to any one of the gate lines 15B. The pixels P constituting the pixel array are a red (R) pixel for displaying red, a green (G) pixel for displaying green, a blue (B) pixel for displaying blue, and a white pixel. Includes white (W) pixels. Four pixels including a red (R) pixel, a green (G) pixel, a blue (B) pixel, and a white (W) pixel may constitute one pixel unit UPXL. However, the configuration of the pixel unit UPXL is not limited thereto.

The pixels P constituting the same pixel unit UPXL may share one sensing line 14B. However, although not shown, the pixels P constituting the same pixel unit UPXL may be independently connected to different sensing lines.

Each of the pixels P receives a high-potential driving voltage EVDD and a low-potential driving voltage EVSS from a power generation unit (not shown).

The pixel P of the present invention may include an OLED, a driving TFT (DT), a storage capacitor (Cst), a first switch TFT (ST1), and a second switch TFT (ST2). The TFTs may be implemented as a P type, an N type, or a hybrid type in which a P type and an N type are mixed. Further, the semiconductor layer of the TFT may contain amorphous silicon, polysilicon, or oxide.

The OLED includes an anode electrode connected to a source node Ns, a cathode electrode connected to an input terminal of a low potential driving voltage EVSS, and an organic compound layer positioned between the anode electrode and the cathode electrode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL).

The driving TFT DT controls the magnitude of the source-drain current (hereinafter referred to as Ids) of the driving TFT DT input to the OLED according to the gate-source voltage (hereinafter referred to as Vgs). The driving TFT DT includes a gate electrode connected to the gate node Ng, a drain electrode connected to the input terminal of the high potential driving voltage EVDD, and a source electrode connected to the source node Ns. The storage capacitor Cst is connected between the gate node Ng and the source node Ns to maintain Vgs of the driving TFT DT for a predetermined period.

The first switch TFT ST1 switches the electrical connection between the data line 14A and the gate node Ng according to the scan control signal SCAN. The first switch TFT ST1 includes a gate electrode connected to the first gate line 15A, a drain electrode connected to the data line 14A, and a source electrode connected to the gate node Ng. The second switch TFT ST2 switches electrical connection between the source node Ns and the sensing line 14B according to the sensing control signal SEN. The second switch TFT ST2 includes a gate electrode connected to the second gate line 15B, a drain electrode connected to the sensing line 14B, and a source electrode connected to the source node Ns.

In the display device of the present invention having such a pixel array, the source driver IC (SD-IC) supplies a data voltage through a plurality of digital-analog converters 121 (hereinafter, DAC) connected to each data line 14A. . Also, the source driver IC SD-IC may sense a sensing current input from each sensing line 14B through a sensing channel and provide sensing data SD to the timing controller 11.

4 is a diagram for explaining the configuration of a source driver IC (SD-IC) according to the first embodiment of the present invention.

Referring to FIG. 4, the source driver IC SD-IC includes DACs that supply a data voltage to each pixel P included in the pixel unit UPXL. The DAC is provided for each pixel (P), a DAC (R) corresponding to a red (R) pixel, a DAC (W) corresponding to a white (W) pixel, a DAC (G) corresponding to a green (G) pixel, It includes a DAC (B) corresponding to the blue (B) pixel. Each of the DACs generates an analog data voltage according to digital image data and applies it to the data lines 14A of the corresponding pixels P.

The pixels P constituting the same pixel unit UPXL share one sensing line 14B. Accordingly, a sensing line 14B to which a red (R) pixel, a white (W) pixel, a green (G) pixel, and a blue (B) pixel is connected is connected to the current sensing unit 122.

The current sensing unit 122 includes a current integrator amplifier CI-AMP, an integrating capacitor CFB, and a reset switch RST. The current integrator amplifier CI-AMP includes an inverting input terminal (-) connected to the sensing line 14B, a non-inverting input terminal (+) to which a reference voltage Vpre is applied, and an output terminal for outputting an integral value. . The integrating capacitor CFB is connected between the inverting input terminal (-) and the output terminal of the current integrator amplifier CI-AMP to accumulate pixel current. The reset switch RST is connected in parallel with the integrating capacitor CFB between the inverting input terminal (-) and the output terminal of the current integrator amplifier CI-AMP. The output terminal of the current integrator amplifier (CI-AMP) includes a sampling switch (SAM), a sample and hold capacitor (CSH), and a holding switch (HOLD). When the sampling switch (SAM) is turned on, the output of the current integrator amplifier (CI-AMP) is stored in the sample and hold capacitor (CSH). When the holding switch HOLD is turned on, the sensing voltage stored in the sample and hold capacitor CSH is applied to the ADC.

With this configuration, the current sensing unit 122 may sense a pixel current input through a sensing channel, and convert a digital sensing value SD through an ADC and output the sensing result.

As described above, the source driver IC (SD-IC) according to the first embodiment of the present invention includes DACs supplying a data voltage and a current sensing unit 122 for sensing a current of a pixel. The current sensing unit 122 includes a current integrator amplifier (CI-AMP) and an ADC, and thus requires a large design area. Accordingly, the second embodiment of the present invention includes a source driver IC (SD-IC) that does not include a separate current sensing unit 122 and can perform the function of the current sensing unit using DACs that supply a data voltage. Suggest a configuration.

5 is a diagram for explaining the configuration of a driver IC according to a second embodiment of the present invention.

Referring to FIG. 5, a source driver IC (SD-IC) supplies a data voltage to the data line 14A to which each pixel P is connected in the first mode, and operates as a current sensing unit in the second mode. And a DAC unit 123 including the DACs of and a switching unit 500 for controlling connection between the DACs and the data lines 14A according to a pixel selected in the first mode and the second mode. Here, the first mode may be a display mode for displaying image data, and the second mode may be a sensing mode for sensing a current of a pixel.

The DAC unit 123 includes a DACr supplying a data voltage to a red (R) pixel, a DACw supplying a data voltage to a white (W) pixel, a DACg supplying a data voltage to a green (G) pixel, and a blue (B) pixel. It includes a DACb that supplies a data voltage to the device. DACs (DACr, DACw, DACg, and DACb) that supply data voltages to pixels can function as a current integrator or comparator, as well as a function of a DAC Amp that generates an analog voltage. Accordingly, the second embodiment of the present invention uses DACs (DACr, DACw, DACg, and DACb) as a DAC Amp supplying a data voltage to a pixel according to an operation mode of a source driver IC (SD-IC), or a current integrator, It operates as a comparator to perform the function of the current sensing unit.

In the first mode, each of the DACs (DACr, DACw, DACg, and DACb) of the DAC unit 123 converts digital image data into an analog image voltage and outputs it to the corresponding data line 14A.

In the second mode, the DACs (DACr, DACw, DACg, and DACb) of the DAC unit 123 function as a component for performing the function of the current sensing unit. For example, each of the DACs (DACr, DACw, DACg, and DACb) may function as a DAC, a current integrator, a comparator, and a feedback ADC that generate a reference data voltage. Specifically, among DACs (DACr, DACw, DACg, and DACb), DACb is a DAC that generates a reference data voltage for current sensing, DACr is a current integrator, DACw is a comparator, and DACg is a feedback ADC. have. Here, functions performed by each of the DACs (DACr, DACw, DACg, and DACb) are not limited to the above description and may be variously changed according to a design method. Each DAC (DACr, DACw, DACg) performing the functions of a current integrator, comparator, and feedback ADC is connected to a sample and hold unit 515 and a logic unit 550 provided together in a source driver IC (SD-IC). Acts as a current sensing unit.

In the first mode, the switching unit 500 includes first mode switches M1 and a second mode connecting each of the DACs (DACr, DACw, DACg, and DACb) and corresponding data lines 14Ar, 14Aw,, 14Ag, and 14Ab. And second mode switches M2 for selecting a pixel to be sensed. The second mode switches M2 may connect the data line 14A of the sensing target pixel to the DACb supplying the reference data voltage.

When the source driver IC SD-IC operates in the first mode, the first mode switches M1 are turned on, and each of the DACs (DACr, DACw, DACg, and DACb) of the DAC unit 123 and the corresponding data line 14Ar, are turned on. 14Aw,, 14Ag, 14Ab) connect. Each DAC (DACr, DACw, DACg, DACb) may apply a data voltage to each of the pixels R, W, G, and B connected to the corresponding data lines 14Ar, 14Aw,, 14Ag, and 14Ab.

When the source driver IC SD-IC operates in the second mode, the first mode switches M1 are turned off, and any one of the second mode switches M2 is turned on. When the second mode switch M2 is turned on, the DAC supplying the reference data voltage and the data line 14A of the selected pixel are connected. The remaining DACr, DACw, and DACg each operate as a configuration of a current sensing unit.

Referring to the equivalent circuit of the DAC unit 123 in the second mode operation, the DACs (DACr, DACw, and DACg) of the DAC unit 123 are respectively a current integrator 510, a comparator 520, a feedback DAC 530, and It operates as a voltage generation DAC 540 that outputs a reference voltage for sensing. Here, the DAC unit 123 feeds back the sample and hold unit 515 for sampling and outputting the output of the current integrator 510 and the output of the comparator 520 through the feedback DAC 530 and outputs sensing data. It further includes a logic unit 550 to perform.

The equivalent circuit of FIG. 5 illustrates the configuration of DACs in the second mode.

The DACb that supplies the data voltage to the blue (B) pixel operates as a DAC for outputting a reference data voltage for current sensing. DACr operates as a current integrator 510, DACw operates as a comparator 520, and DACg operates as a feedback DAC 530.

The inverting input terminal (-) of the DACr operating as the current integrator 510 is connected to the sensing line 14B, and the reference voltage Vpre is applied to the non-inverting input terminal (+). An integrating capacitor CFB accumulates a sensing current of a pixel input through the sensing line 14B between the inverting input terminal (-) of the DACr and the output terminal. A reset switch RST is connected in parallel with the integrating capacitor CFB between the inverting input terminal (-) of the DACr and the output terminal. A sample and hold unit 515 including a sampling switch SAM, a sample and hold capacitor CSH, and a holding switch HOLD is connected to the output terminal of the DACr.

The DACw operating as the comparator 520 compares the sensing voltage of the sample-and-hold unit 515 input through the inverting input terminal (-) with the input voltage of the non-inverting input terminal (+) and outputs a comparison result. A feedback DAC 530 that converts the output results of the logic unit 550 and the logic unit 550 into analog voltage values and feeds them back to the non-inverting input terminal (+) of the DACw is provided at the output terminal of the DACw operating as the comparator 520. Connected.

The logic unit 550 sequentially determines a digital output bit value from the most significant bit (MSB) in response to the comparison result of the comparator 520. The digital output bit value output from the logic unit 550 is converted into a voltage value by the feedback DAC 530 and fed back to the input terminal (+) of the DACw operating as the comparator 520.

The logic unit 550 sets the variable c for counting the bits of the logic unit 550 to "1" in step 1, initializes the logic unit 550 to "0", and then initializes the logic unit 550 to "0". "1" is allocated to the I bit of the sub 550. Therefore, the logic unit 550 has 1000... 000 is set. Thereafter, in step 3, the feedback DAC 530 converts the value of the logic unit 550 digital-to-analog and inputs it as a reference voltage to the non-inverting input terminal (+) of the comparator 520.

The comparator 520 compares the sensing voltage input from the sample and hold unit 515 with the reference voltage input from the feedback DAC 530. As a result of the comparison, if the sensing voltage is less than the reference voltage, the I bit of the logic unit 550 is cleared to "0" and the logic unit 550 displays 0000... 000 is set. On the other hand, if the sensing voltage is greater than or equal to the reference voltage in the above process, the value of the logic unit 550 is maintained as it is, and as a next step, the variable c and the logic unit for counting the bits of the logic unit 550 It is compared with the variable (N) representing the size of (550). As a result of the comparison, if the variable (c) is smaller than the variable (N) representing the size of the logic unit 550, feedback is performed to the second step, and if the variable (c) is equal to or greater than the variable (N), the comparison operation Will end. As such, the comparator 520 sets a value of “1” when the sensing voltage input from the sample and hold unit 515 is greater than or equal to the value of the logic unit 550, and a value of “0” when the sensing voltage is smaller than the value of the logic unit 550. Print it out. A value finally stored in the logic unit 550 after repeating the above process up to the N-th bit may be determined as digital data of the sensing voltage input from the sample and hold unit 515.

As described above, in the second embodiment of the present invention, a separate current sensing unit is provided by controlling the DACs supplying the data voltage to operate as a current integrator, a comparator, a feedback DAC, and a DAC for generating a reference voltage for measuring a sensing current. Current sensing function can be performed without the need. Accordingly, since the configuration of the current integrator amplifier (CI-AMP) and ADC for configuring the current sensing unit can be eliminated, the size of the source driver IC (SD-IC) can be significantly reduced.

6 is a diagram showing in detail the configuration of a driver IC and a pixel array according to a second embodiment of the present invention.

Referring to FIG. 6, a source driver IC (SD-IC) supplies a data voltage to a data line 14A to which each pixel P is connected in a first mode, and a DAC operates as a configuration of a current sensing unit in a second mode. And a DAC unit 123 including them, and a switching unit 500 for controlling a connection between each DAC and the data lines 14A and the sensing line 14B according to the first mode and the second mode. Here, the first mode may be a display mode for displaying image data, and the second mode may be a sensing mode for sensing a current of a pixel.

The DACr of the DAC unit 123 may function as a current integrator, DACw as a comparator, DACg as a feedback ADC, and DACb as a DAC for generating a reference data voltage for current sensing.

The inverting input terminal (-) of the DACr that operates as a current integrator is connected to the sensing line 14B, and a reference voltage (Vpre) is applied to the non-inverting input terminal (+). An integrating capacitor CFB is connected together with the second switch SW2 between the inverting input terminal (-) of the DACr and the output terminal. A first switch SW1, which is a reset switch RST, is connected in parallel to the integrating capacitor CFB. The sample and hold capacitor CSH is connected to the output terminal of the DACr through the third switch SW3 and the fourth switch SW4. The sensing voltage output from the current integrator is input to the inverting terminal (-) of DACw that performs a comparator function through the fifth switch SW5.

The DACw, which operates as a comparator, compares the sensing voltage of the sample-and-hold unit 515 input to the inverting input terminal (-) with the feedback voltage input to the non-inverting input terminal (+) and outputs a comparison result. A sixth switch SW6 for reset is connected between the output terminal of the DACw and the inverting input terminal (-). A seventh switch SW7 for controlling connection to the reference voltage is connected to the non-inverting input terminal (+) of the DACw. The eighth switch SW8 for controlling the connection to the logic unit 550 is connected to the output terminal of the DACw.

A DACg that converts the digital output result output from the logic unit 550 into an analog voltage value and feeds it back to the non-inverting input terminal (+) of the DACw is connected to the output terminal of the logic unit 550. The tenth switch SW10 is connected between the logic unit 550 and the feedback DACg, and the ninth switch SW9 is connected between the feedback DACg and the non-inverting input terminal (+) of the DACw.

As described above, each of the DACs (DACr, DACw, and DACg) performing the functions of a current integrator, comparator, and feedback ADC is a sample and hold unit 515 and a logic unit 550 provided together in a source driver IC (SD-IC). It is connected to and acts as a current sensing unit.

The first mode switches M1 of the switching unit 500 are all turned on during the first mode operation, and each of the DACs (DACr, DACw, DACg, and DACb) of the DAC unit 123 and the corresponding data lines 14Ar, 14Aw, and 14Ag are turned on. , 14Ab) connects. Accordingly, each of the DACs (DACr, DACw, DACg, and DACb) may apply a data voltage to each of the pixels R, W, G, and B connected to the corresponding data lines 14Ar, 14Aw, 14Ag, and 14Ab.

Any one of the second mode switches M2 is turned on during the second mode operation. When the second mode switch M2 is turned on, the DACb generating the reference data voltage for current sensing and the data line 14A of the selected pixel are connected. A pixel receiving a reference data voltage for current sensing outputs a current to the sensing line 14B according to the potential of the input data voltage. The current output from the pixel is input to the inverting input terminal (-) of the DACr operating as a current integrator through the sensing line 14B, so that sensing data may be output.

The circuit operation in the first operation mode will be described with reference to FIGS. 7 and 8.

FIG. 7 is a diagram for explaining circuit operation in a first operation mode of a driver IC according to a second embodiment of the present invention, and FIG. 8 is a view showing a control waveform diagram for switch control in the first operation mode of FIG. 7 to be.

The first mode is a display mode for displaying image data, and when a first mode selection signal is input to the switching unit 500, the first mode switches M1 correspond to each of the DACs (DACr, DACw, DACg, and DACb). The data lines 14Ar, 14Aw, 14Ag, and 14Ab are turned on to be connected. The first switch SW1, the third switch SW3, the sixth switch SW6, and the seventh switch SW7 are also turned on. Accordingly, each of the DACs (DACr, DACw, DACg, and DACb) may apply a data voltage to each of the pixels R, W, G, and B connected to the corresponding data lines 14Ar, 14Aw, 14Ag, and 14Ab.

In the first mode, the first switch SW1 is turned on, the second switch SW2 is turned off, the third switch SW3 is turned on, the fourth switch SW4 is turned off, and the fifth switch SW5 is turned on. ) Is turned off, the sixth switch SW6 is turned on, the seventh switch SW7 is turned on, the eighth switch SW8 is turned off, the ninth switch SW9 is turned off, and the tenth switch SW10 is turned off. ) Is off.

The first switch SW1, which is an initialization switch connecting the input terminal and the output terminal of the DACr, is turned on, so that the DACr operates as a unit gain buffer having a gain of 1. The second switch SW2 connecting the integrating capacitor CFB, the fourth switch SW4 connecting the sample-and-hold capacitor CFB, and the fifth switch SW5 connecting the output terminal to the DACw acting as a comparator are off. do. Accordingly, the red (R) pixel data DATA (R) input to the DACr is output as voltage data through the DACr, and the output is the data line 14A to which the red (R) pixel is connected through the third switch SW3. ) Is displayed.

The sixth switch SW6, which is an initialization switch connecting the input terminal and the output terminal of the DACw, is turned on, so that the DACw operates as a unit gain buffer having a gain of 1. The eighth switch SW8 connecting the output terminal of the DACw and the logic unit 550 and the ninth switch SW9 connecting the feedback line are all turned off, and the seventh switch connecting the reference voltage to the non-inverting input terminal (+) The switch SW7 is turned on. Accordingly, the white (W) pixel data DATA(W) input to the DACw is output as voltage data through the DACw, and the output thereof is output to the data line 14A to which the white (W) pixel is connected.

The DACg outputs the input green (G) pixel data DATA(G) as voltage data, and the output is output to the data line 14A to which the white (G) pixel is connected.

The DACb outputs the blue (B) pixel data DATA(B) as voltage data, and the output is output to the data line 14A to which the blue (B) pixel is connected.

As described above, in the first mode operation, each DAC (DACr, DACw, DACg, DACb) applies a data voltage to each pixel (R, W, G, B) connected to the corresponding data line (14Ar, 14Aw, 14Ag, 14Ab). Can be approved.

A circuit configuration in the second operation mode in the second operation mode of the driver IC according to the second embodiment of the present invention will be described with reference to FIGS. 9 to 12.

9 is a diagram illustrating a circuit operation of a source driver IC (SD-IC) in a second operation mode, and FIG. 10 is a diagram showing a control waveform diagram for switch control in a second operation mode.

9 and 10, the second mode is a sensing mode for sensing a current of a pixel. When a second mode selection signal is input to the switching unit 500, the first mode switches M1 are connected to the DACb. Everything except the switch is off. Any one of the second mode switches M2 from which current sensing is selected is turned on. When the second mode switch M2 is turned on, the DACb generating the reference data voltage for current sensing and the data line 14A of the selected pixel are connected.

The second mode may include a current integration period and a sampling and ADC operation period. In the second mode, the first switch SW1 is maintained in an off state, and the second switch SW2 is maintained in a turned-on state. The third switch SW3 is turned on in the current integration period and turned off in the sampling and ADC operation period. The fourth switch SW4 is maintained in a turned-on state. The fifth switch SW5 is turned off during the current integration period and turned on during the sampling and ADC operation period. The sixth switch SW6 and the seventh switch SW7 are maintained in an off state. The eighth switch SW8, the ninth switch SW9, and the tenth switch SW10 are turned off in the current integration period and turned on in the sampling and ADC operation periods.

In the second mode, DACr is a current integrator 510, DACw is a comparator 520, DACg is a feedback ADC 530, and DACb is a voltage generation DAC 540 that generates a reference data voltage for current sensing. do.

In the first step (①), the DACb of the voltage generating DAC 540 converts the reference data DATA_S for current sensing into an analog data voltage and outputs it. The data voltage output from the voltage generation DAC 540 is applied to the red (R) pixel on which the second mode switch M2 is turned on. The red (R) pixel is driven by receiving a data voltage, and a sensing current is applied to the sensing line 14B according to the sensing control signal SEN.

In the second step (②), the current integrator 510 integrates the sensing current flowing into the sensing line 14B and outputs a sensing voltage. The current integrator 510 integrates the sensing current during the current integration period in the second mode. Accordingly, the fifth to tenth switches SW5 to SW10 that are not related to the operation of the current integrator 510 are maintained in an off state during the current integration period.

In the current integrator 510, the first switch SW1, which is a reset switch, is maintained in an off state, and the second switch SW2 is maintained in a turned-on state, so that the feedback capacitor CFB is connected to the DACr. The third switch SW3 and the fourth switch SW4 are turned on during the current integration period to connect the sample and hold capacitor CSH to the output terminal of the DACr. Accordingly, the DACr of the current integrator 510 receives the sensing current flowing into the sensing line 14B through the inverting input terminal (-) and outputs a sensing voltage, and the output sensing voltage is stored in the sample and hold capacitor (CSH). .

In the third step (③), the sensing voltage stored in the sample and hold capacitor CSH of the integrator 510 is introduced into the comparator 520. The comparison value output from the DACw of the comparator 520 is fed back to the comparator 520 through the logic unit 550 and the feedback DAC 530. Accordingly, the third switch SW3 connecting the current integrator 510 is turned off. The fourth switch SW4 and the fifth switch SW5 are maintained in a turned-on state to connect the sample and hold capacitor CSH of the integrator 510 and the DACw of the comparator 520.

In the comparator 520, the sixth switch SW6 and the seventh switch SW7, which are initialization switches, are maintained in an off state. The eighth switch SW8 is turned on to connect the logic unit 550 to the output terminal of the DACw, and between the output of the logic unit 550 and the non-inverting input terminal (+) of the DACw, the ninth switch SW9 and the tenth switch (SW10) is turned on and the feedback ADC 530 is connected. Accordingly, the DACw of the comparator 520 receives the sensing voltage through the inverting input terminal (-) and feedback the comparison result through the non-inverting input terminal (+), and outputs the comparison result.

The logic unit 550 outputs the comparison result of the comparator 520 as a digital value, and the feedback ADC 530 converts the comparison result output as a digital value into an analog voltage and feeds it back to the non-inverting input terminal (+).

In the fourth step (④), when it is determined that the sensing voltage input to the inverting input terminal (-) of the comparator 520 and the output terminal voltage fed back to the non-inverting input terminal (+) are the same, the logic unit 550 displays the digital sensing voltage. Print the value.

11 is a diagram illustrating an equivalent circuit in the second operation mode of FIG. 9.

Referring to FIG. 11, in order to output current sensing data in the second operation mode, DACr may function as a current integrator 510, DACw may function as a comparator 520, and DACg may function as a feedback ADC 530.

The current integrator 510 is connected to the sensing line 14B to the inverting input terminal (-), and the DACr to which the reference voltage (Vpre) is applied to the non-inverting input terminal (+), and the inverting input terminal (-) of the DACr. It includes an integrating capacitor CFB connected between the output terminals, and a reset switch RST connected in parallel with the integrating capacitor CFB.

When the reset switch RST of the current integrator 510 is turned on, both the input terminals (+, -) and the output terminals of the DACr are initialized to the same voltage. When the reset switch RST is turned off, the DACr operates as a current integrator. Accordingly, the potential difference between both ends of the integrating capacitor CFB due to the sensing current flowing into the inverting input terminal (-) of the DACr increases as the sensing time elapses, that is, as the accumulated sensing current IPXL increases. However, due to the characteristics of the amplifier (AMP), the inverting input terminal (-) and the non-inverting input terminal (+) are shorted through a virtual ground and the potential difference between them is 0, so the potential of the inverting input terminal (-) is integrated. The integrator reference voltage VREF is maintained regardless of an increase in the potential difference of the capacitor CFB. Instead, the potential at the output terminal of the DACr is lowered in response to the potential difference between both ends of the integrating capacitor CFB. With this principle, the current integrator 510 outputs a sensing voltage according to the sensing current input to the sensing line 14B.

A sample and hold unit 515 is connected to the output terminal of the current integrator 510. The sample and hold unit 515 is connected to a sample and hold unit 515 including a sampling switch SAM, a sample and hold capacitor CSH, and a holding switch HOLD. When the sampling switch SAM is turned on, the sensing voltage output from the current integrator 510 is stored in the sample and hold capacitor CSH. When the holding switch HOLD is turned on, the sensing voltage stored in the sample and hold capacitor CSH is applied to the comparator 520.

The comparator 520 includes a DACw that compares the sensing voltage input through the inverting input terminal (-) and the feedback voltage inputted through the non-inverting input terminal (+) and outputs a comparison result. The DACw compares the sensing voltage of the sample-and-hold unit 515 input to the inverting input terminal (-) and the feedback voltage input to the non-inverting input terminal (+). The output of the DACw is fed back to the non-inverting input terminal (+) of the DACw through the logic unit 550 and the feedback DAC 530.

The DACw operating as the comparator 520 compares the sensing voltage of the sample-and-hold unit 515 input through the inverting input terminal (-) with the input voltage of the non-inverting input terminal (+) and outputs a comparison result. A feedback DAC 530 that converts the output results of the logic unit 550 and the logic unit 550 into analog voltage values and feeds them back to the non-inverting input terminal (+) of the DACw is provided at the output terminal of the DACw operating as the comparator 520. Connected.

The logic unit 550 sequentially determines a digital output bit value from the most significant bit (MSB) in response to the comparison result of the comparator 520. The digital output bit value output from the logic unit 550 is converted into a voltage value by the feedback DAC 530 and is input to the non-inverting input terminal (+) of the comparator 520.

The logic unit 550 sets the variable c for counting the bits of the logic unit 550 to "1" in step 1, initializes the logic unit 550 to "0", and then initializes the logic unit 550 to "0". "1" is allocated to the I bit of the sub 550. Therefore, the logic unit 550 has 1000... 000 is set. Thereafter, in step 3, the feedback DAC 530 converts the value of the logic unit 550 into an analog voltage and inputs it to the non-inverting input terminal (+) of the comparator 520.

The comparator 520 compares the sensing voltage input from the sample and hold unit 515 with the feedback voltage input from the feedback DAC 530. As a result of the comparison, if the sensing voltage is less than the feedback voltage, the I bit of the logic unit 550 is cleared to "0" and the logic unit 550 displays 0000... 000 is set. On the other hand, if the sensing voltage is greater than or equal to the reference voltage in the above process, the value of the logic unit 550 is maintained as it is, and as a next step, the variable c and the logic unit for counting the bits of the logic unit 550 It is compared with the variable (N) representing the size of (550). As a result of the comparison, if the variable (c) is smaller than the variable (N) representing the size of the logic unit 550, feedback is performed to the second step, and if the variable (c) is equal to or greater than the variable (N), the comparison operation Will end. As such, the comparator 520 sets a value of “1” when the sensing voltage input from the sample and hold unit 515 is greater than or equal to the value of the logic unit 550, and a value of “0” when the sensing voltage is smaller than the value of the logic unit 550. Print it out.

The value finally stored in the logic unit 550 after repeating the above process up to the N-th bit is output as digital data of the sensing voltage input from the sample and hold unit 515.

As described above, in the second embodiment of the present invention, a separate current sensing unit is provided by controlling the DACs supplying the data voltage to operate as a current integrator, a comparator, a feedback DAC, and a DAC for generating a reference voltage for measuring a sensing current. Current sensing function can be performed without the need.

12 is a diagram illustrating an operation flow of a driver IC in a second operation mode according to the second embodiment of the present invention.

In the first step (①), the voltage generating DAC 540 converts reference data for current sensing into an analog data voltage and outputs it. The pixel receiving the data voltage applies a sensing current according to the input data voltage to the sensing line.

In the second step (②), the current integrator 510 integrates the sensing current flowing into the sensing line 14B and outputs a sensing voltage.

In the third step (③), the comparator 520 that receives the sensing voltage of the integrator 510 and the comparison result of the comparator 520 are output as digital values, and the output of the logic unit 550 is a comparator. The sensing voltage is converted into digital data using the feedback DAC 530 that feeds back to 520.

In the fourth step (④), if the sensing voltage input to the inverting input terminal (-) of the comparator 520 and the output terminal voltage fed back to the non-inverting input terminal (+) are determined to be the same, the digital sensing voltage of the logic unit 550 Print the value.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above is in other specific forms without changing the technical spirit or essential features of the present invention by those skilled in the art. It will be appreciated that it can be implemented. Therefore, the embodiments described above are illustrative in all respects and should be understood as non-limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

10: display panel 11: timing control unit
12: data driving unit 13: scan driving unit
14A: data line 14B: sensing line
123: DAC unit 500: switching unit
510: current integrator 515: sample and hold unit
520: comparator 530: feedback DAC
540: sensing voltage output DAC 550: logic unit

Claims (15)

A plurality of DAC-AMPs are included, and in a first mode, the plurality of DAC-AMPs respectively generate an image data voltage to supply data voltages to data lines connected to a pixel, and in a second mode, the plurality of DAC-AMPs Each AMP operates in a configuration for current sensing, supplies a sensing data voltage to any one of the pixels, and includes a plurality of DAC-AMPs for sensing a sensing current of any one pixel input through a sensing line. DAC unit; And
A switching unit connecting the plurality of DAC-AMPs to the data lines in the first mode, and connecting any one of the plurality of DAC-AMPs to any one of the data lines in the second mode;
Driver integrated circuit comprising a. The method of claim 1,
The plurality of DAC-AMPs include a DAC-AMP that operates as a current integrator in the second mode, a DAC-AMP that operates as a comparator, and a feedback DAC that feeds a voltage back to the comparator. The method of claim 2,
The DAC-AMP operating as the current integrator includes an inverting input terminal to which the sensing current is input, a non-inverting input terminal connected to a reference voltage, and an output terminal to output an integral value of the sensing current,
An integrating capacitor connected between the non-inverting input terminal and the output terminal; And
An initialization switch connected in parallel to the integrating capacitor;
Driver integrated circuit comprising a. The method of claim 3,
A driver integrated circuit further comprising a sampling and hold unit connected to the output terminal of the DAC-AMP operating as the integrator to store and output an integral value of the sensing current. The method of claim 2,
The DAC-AMP operating as the comparator includes an inverting input terminal to which the integrated value of the sensing current is input, a non-inverting input terminal connected to a feedback voltage, and an output terminal for outputting a comparison value of the integrated value of the sensing current and the feedback voltage. ,
A logic unit connected to the output terminal to output digital data according to an output value of the comparator;
Driver integrated circuit comprising a. The method of claim 5,
The feedback DAC,
A driver integrated circuit connected between the logic unit and the non-inverting input terminal of the comparator to convert the digital data output from the logic unit into an analog voltage to apply the feedback voltage. The method of claim 6,
The logic unit,
When the output value of the comparator is the same as the integral value of the sensing current and the feedback voltage, the driver integrated circuit outputs the digital data as sensing data of the sensing current. A display panel including a plurality of pixels and data lines and sensing lines connected to the pixels; And
And a source driver IC including a plurality of DAC-AMPs supplying an image data voltage to the data line,
The source driver IC,
In the first mode, the plurality of DAC-AMPs apply the image data voltage to the data line, and in the second mode, each of the plurality of DAC-AMPs operates in a configuration for current sensing. A display device that supplies a sensing data voltage to a pixel and senses a sensing current of any one pixel input through a sensing line. The method of claim 8,
The source driver IC,
And a switching unit for connecting the plurality of DAC-AMPs to each of the data lines in the first mode, and connecting any one of the plurality of DAC-AMPs to any one of the data lines in the second mode. Display device. The method of claim 8,
The display device further comprises a timing controller for controlling an operation of the source driver IC in the second mode to receive sensing data of the sensing current of the pixel according to the sensing data voltage. The method of claim 8,
The plurality of DAC-AMPs include a DAC-AMP that operates as a current integrator in the second mode, a DAC-AMP that operates as a comparator, and a feedback DAC that feeds a voltage back to the comparator. The method of claim 11,
The DAC-AMP operating as the current integrator includes an inverting input terminal to which the sensing current is input, a non-inverting input terminal connected to a reference voltage, and an output terminal to output an integral value of the sensing current,
An integrating capacitor connected between the non-inverting input terminal and the output terminal; And
An initialization switch connected in parallel to the integrating capacitor; And
A sampling and holding unit connected to an output terminal of the DAC-AMP operating as the integrator to store and output an integral value of the sensing current;
Display device comprising a. The method of claim 11,
The DAC-AMP operating as the comparator includes an inverting input terminal to which the integrated value of the sensing current is input, a non-inverting input terminal connected to a feedback voltage, and an output terminal for outputting a comparison value of the integrated value of the sensing current and the feedback voltage. ,
A logic unit connected to the output terminal to output digital data according to an output value of the comparator;
Display device comprising a. The method of claim 13,
The feedback DAC,
A display device connected between the logic unit and the non-inverting input terminal of the comparator to convert the digital data output from the logic unit into an analog voltage to apply the feedback voltage to the comparator. The method of claim 6,
The logic unit,
When the output value of the comparator is the same as the integral value of the sensing current and the feedback voltage, the display device outputs the digital data as sensing data of the sensing current.

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