KR20210050695A - Manufacturing Method of Socket Board for Semiconductor Test Using Build-up Board Manufacturing Technology - Google Patents

Abstract

Disclosed is a method for manufacturing a multilayer printed circuit board which is easy to implement a microcircuit, has excellent reliability, and can reduce manufacturing lead time and manufacturing cost. The method for manufacturing a multilayer printed circuit board comprises the steps of: preparing a plurality of circuit boards having at least one plated via hole and having circuit patterns formed on both surfaces thereof; preparing a plurality of prepreg having prepreg via holes formed thereon; alternately matching and stacking the plurality of circuit boards; and collectively bonding the plurality of circuit boards and the plurality of prepreg.

Description

Manufacturing Method of Socket Board for Semiconductor Test Using Build-up Board Manufacturing Technology}

The present invention relates to a method of manufacturing a socket board for semiconductor testing using a high-density small-sized manufacturing technology, and describes a high-density miniaturization process of a printed circuit board capable of constructing a multilayer universal circuit according to the development of technology.

Recently, as electronic devices have become high-density, high-speed, small-sized, light-weight, thin, and multifunctional, research on a highly integrated substrate (PCB) that mounts components for electronic devices is also being actively conducted. . Accordingly, in the PCB industry, various methods are required according to short lines and fine pitch strings, which are important factors in optimizing the properties of components. In addition, the design of the board for the heat dissipation part that protects from thermal damage by removing heat generated from the chip during operation of the mounted component is emerging as a very important task.

An object of the present invention is to provide a method for manufacturing a multilayer printed circuit board that is easy to implement microcircuits, has excellent reliability, and can reduce manufacturing lead time and manufacturing cost. In addition, it is an object of the present invention to provide a method of manufacturing a multilayer printed circuit board capable of strengthening upper and lower conduction during interlayer connection. In addition, it is an object of the present invention to provide a method of manufacturing a multilayer printed circuit board capable of increasing interlayer adhesion by preventing adhesive deformation during a process.

According to embodiments of the present invention for achieving the object of the present invention described above, a method of manufacturing a multilayer printed circuit board includes preparing a plurality of circuit boards having at least one plated via hole and having circuit patterns formed on both surfaces thereof; Preparing a plurality of pre-flags having pre-flag via holes formed therein, alternately matching and laminating the plurality of circuit boards and the plurality of pre-flags, and collectively bonding the plurality of circuit boards and the plurality of pre-flags Consists of including. The circuit board includes preparing a base substrate having copper foil layers formed on both sides thereof, forming at least one via hole in the base substrate, filling the via hole and forming a plating layer to cover the surfaces of both copper foil layers, and the It may be configured including the step of forming a circuit pattern on the plating layer. The via hole may be formed to form the base substrate using a laser drill or a mechanical drill bit, and penetrate both the base layer and the copper foil layer on both sides. In addition, the fill plating layer may be formed using a plating solution formed mainly of copper (Cu), chlorine (Cl), sulfuric acid, trivalent iron (Fe3+), and the like and including a leveler and a brightener. The thickness of the plating layer may be determined by a current density flowing through the plating solution and a process time. In addition, the circuit pattern may be formed such that the base layer is exposed by etching the plating layer and the copper foil layer using a resist having a pattern formed on the plating layer. For example, the circuit pattern may be formed to include a plating layer filled in the via hole, a plating layer around the via hole, and a portion of a copper foil layer. The pre-flag is inserted between the two circuit boards, and the thickness may be equal to or thicker than the sum of the thicknesses of the circuit patterns of the two circuit boards. The pre-flag via hole may be formed using a laser drill or a mechanical drill bit. In addition, the diameter of the prepreg via hole may be larger than the diameter of the via hole.

Various embodiments of the present invention may have one or more of the following effects. As described above, according to the embodiments of the present invention, by collectively bonding a plurality of circuit boards plated on vias using pre-flags, the via holes of all layers can be filled with plating, and the upper and lower conduction can be strengthened when connecting between layers. have. In addition, by using the prefrag, it is possible to prevent the deformation of the adhesive during the process, thereby improving the interlayer adhesion.

1 is a cross-sectional view of a method of manufacturing a socket board for semiconductor testing using Build-Up manufacturing technology.
2 is a 6-layer exemplary configuration diagram of a method for manufacturing a socket board for semiconductor testing using Build-Up manufacturing technology.

A method of manufacturing a multilayer printed circuit board according to embodiments of the present invention will be described in detail. A base substrate with copper foil layers formed on both sides of the base layer is prepared. Then, a via hole is formed in the base substrate. Here, the via hole can be processed using a laser drill or a mechanical drill bit according to its diameter and operation convenience. In addition, the via hole is formed to penetrate both the base layer and the copper foil layer on both sides. Meanwhile, one or a plurality of via holes may be formed in the base substrate, and the positions of the via holes may be substantially changed in various ways. Next, the via hole is plated to form a plated layer. Here, the plating layer is formed to cover not only the inside of the via hole but also the surface of the copper foil layer on both sides of the base substrate. In addition, the plating layer is copper (Cu), chlorine (Cl), sulfuric acid, and trivalent iron in Reverse Pulse Plating. (Fe3+) is the main component, and copper (Cu) is filled inside the via hole by using a plating solution that maximizes the plating inhibitory action of the additive leveler (inhibitor) and the promotion action of the brightner (accelerator). In addition, the thickness of the plating layer applied to the surface of the copper foil layer of the base substrate is the thickness planned during the design of the multilayer printed circuit board, but it is adjusted in consideration of the current density flowing through the plating solution and the processing time. Next, a circuit pattern is formed on the base substrate on which the plating layer is formed. Coating a resist containing a dry film or liquid photoresist on the surface of the plating layer, irradiating ultraviolet rays using a photomask to form a circuit pattern, and then developing the resist pattern to form a resist pattern and etching the plating layer and the copper foil layer according to the resist pattern. A predetermined circuit pattern is formed on the substrate 100. After the circuit pattern is formed, the resist is removed from the base substrate to form a circuit board on which the circuit pattern is formed. Here, the circuit pattern consists of lands and lines by removing the plating layer and the copper foil layer by the resist. For example, in the circuit pattern, the plating layer and the copper foil layer are etched to expose the base layer, but the via hole and the plating layer around it and a part of the copper foil layer remain. Next, prepare the prefrag. For example, prepreg is a glass fiber impregnated with epoxy resin and has resin flow and semi-curing properties. In addition, since the thickness of the pre-flag is inserted between the two circuit boards, it is set equal to or greater than the sum of the thicknesses of the circuit patterns of both circuit boards, and it is preferable to select it in consideration of the final thickness of the final multilayer printed circuit board.

Claims (3)

Preparing a plurality of circuit boards having at least one fill-plated via hole and having circuit patterns formed on both surfaces thereof; preparing a plurality of pre-flags having pre-flag via holes formed; and the plurality of circuit boards and the plurality of pre-preps A method of manufacturing a socket board for semiconductor testing using a high-density and compact manufacturing technology comprising the steps of alternately matching and stacking lags, and collectively bonding the plurality of circuit boards and the plurality of pre-flags. The method of claim 1, wherein the circuit board comprises: preparing a base substrate having copper foil layers formed on both surfaces thereof; forming at least one via hole in the base substrate; filling the via hole and forming a plating layer to cover the surfaces of the copper foil layers. A method of manufacturing a socket board for semiconductor testing using a high-density and compact manufacturing technology, comprising the step of forming and forming a circuit pattern on the plating layer. The method of claim 2, wherein the via hole is formed by forming the base substrate by using a laser drill or a mechanical drill bit, and is formed to penetrate both the base layer and the copper foil layer on both sides, and the plating layer is copper (Cu), chlorine (Cl). ), sulfuric acid, trivalent iron (Fe3+), etc. as a main component, and a plating solution formed including a leveler and a polisher is used.

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