KR20210022982A - Neuromorphic system for multiple multiplication and accumulation operations and method thereof - Google Patents

Abstract

The present invention relates to a neuromorphic system for performing a multi-MAC operation and a method for performing a multi-MAC operation. The neuromorphic system according to one embodiment of the present invention comprises: a synapse array outputting at least one weight value corresponding to synaptic circuits receiving a spike signal among a plurality of synaptic circuits connected to one bit line among a plurality of bit lines; and a weight operation unit including a plurality of sense amplifiers receiving at least one weight value as an input through one bit line and performing a multiplication and accumulation (MAC) operation on the plurality of weight values by using the plurality of sense amplifiers.

Description

Neuromorphic system performing multi-MAC operation and its method {NEUROMORPHIC SYSTEM FOR MULTIPLE MULTIPLICATION AND ACCUMULATION OPERATIONS AND METHOD THEREOF}

It relates to a neuromorphic system, and more particularly, to a technical idea of performing a multi-MAC operation in a neuromorphic system.

The SNN (spiking neural network) system has been studied in a way that mimics the structure of the biological brain in order to obtain high energy efficiency that appears in the biological brain.

The basic operation of SNN system neurons is composed of MAC operation, and effectively implementing MAC operation is one of the ways to increase energy efficiency.

In the existing convolutional neural network (CNN), methods of processing many MAC operations at once using computation-in-memory (CIM) have been studied. However, applying CIM, which has been studied in CNN, to the SNN system as it is, acts as a factor that lowers energy efficiency.

Meanwhile, since the current sum method applied to the existing SNN system accumulates analog currents at once, an ADC (analog-digital converter) is required after the MAC operation, and the ADC used at this time is space There is a problem in that (area), energy, and delay overhead are very large.

In addition, when processing multi-weight through the current summing method, an additional configuration such as a multiplier or charge sharing is required in order to process the analog value at the bit line position as the correct value. Additionally, there is a problem that space, energy and delay overhead are increased.

Korean Patent Laid-Open Publication No. 10-2014-0144130, "Synaptic Array, Pulse Shaper Circuit and Neuromorphic System Containing These"

An object of the present invention is to provide a neuromorphic system and method capable of performing multiple-MAC operations using a plurality of sense amplifiers of SRAM, not analog type multiple-MAC operations requiring a conventional ADC.

In addition, the present invention is a neuromorphic system that can increase overall energy efficiency by minimizing losses due to space, energy, and delay overhead by performing multiple-MAC operations without an ADC, and I want to provide a way.

In addition, the present invention is to provide a neuromorphic system and method capable of reducing energy overhead caused by using a plurality of sense amplifiers by controlling the operation of a sense amplifier based on a plurality of flip-flop outputs.

The neuromorphic system according to an embodiment includes at least one weight corresponding to synaptic circuits for receiving spikes signals among a plurality of synaptic circuits connected to any one of a plurality of bit lines. ) A synapse array for outputting a value and a plurality of sense amplifiers receiving at least one weight value as an input through any one bit line, and a plurality of weight values using a plurality of sense amplifiers. It may include a weight calculator that performs a multiplication and accumulation (MAC) operation.

According to one side, the plurality of synaptic circuits may be circuits based on the SRAM memory cell structure.

According to one side, the neuromorphic system further includes a signal providing unit for selecting at least one word line among a plurality of word lines provided in the synapse array at the same timing and providing a spike signal through the word lines selected at the same timing. can do.

According to one side, the signal providing unit includes pre-neurons connected to each of a plurality of word lines, and may provide a spike signal to synaptic circuits corresponding to each of the plurality of word lines through the free neurons. .

According to one side, in each of the plurality of sense amplifiers, any one bit line and a reference voltage line for applying one reference voltage may be connected as inputs.

According to one side, each of the plurality of sense amplifiers may detect a time point when a bit line voltage applied through any one bit line becomes lower than a reference voltage, and output a MAC operation result corresponding to the sensed time point.

According to one side, each of the plurality of sense amplifiers receives a first output signal and a second output signal of each of the plurality of sense amplifiers as inputs to generate a control clock and a logic gate and a first output signal and a generated control clock as inputs. It may be connected to a receiving flip-flop.

According to one side, each of the plurality of sense amplifiers receives the output signals of the flip-flops from the flip-flops corresponding to each of the plurality of sense amplifiers, and enables an amplifier to control the operation of at least one sense amplifier among the plurality of sense amplifiers. An amplifier enable signal generated from a sense amplifier controller generating a signal may be received as an input.

A method of performing a multi-MAC operation using a neuromorphic system according to an embodiment is a synapse in which a spike signal is received from among a plurality of synaptic circuits connected to any one of a plurality of bit lines in a synapse array. Outputting at least one weight value corresponding to the circuits, and using a plurality of sense amplifiers that receive at least one weight value as an input through any one bit line in the weight calculator. Thus, it may include performing a multiplication and accumulation (MAC) operation on a plurality of weight values.

According to one side, in the method of performing a multi-MAC operation, the signal providing unit selects at least one word line from among a plurality of word lines provided in the synapse array at the same timing, and provides a spike signal through the word lines selected at the same timing. It may further include the step of.

According to one side, each of the plurality of sense amplifiers receives a first output signal and a second output signal of each of the plurality of sense amplifiers as inputs to generate a control clock and a logic gate and a first output signal and a generated control clock as inputs. It may be connected to a receiving flip-flop.

According to one side, each of the plurality of sense amplifiers receives the output signals of the flip-flops from the flip-flops corresponding to each of the plurality of sense amplifiers, and enables an amplifier to control the operation of at least one sense amplifier among the plurality of sense amplifiers. An amplifier enable signal generated from a sense amplifier controller generating a signal may be received.

According to an embodiment, a multiple-MAC operation may be performed using a plurality of sense amplifiers of an SRAM, rather than an analog multiple-MAC operation requiring an existing ADC.

According to an embodiment, a multiple-MAC operation is performed without an ADC to minimize loss due to space, energy, and delay overhead, thereby improving overall energy efficiency.

According to an embodiment, by controlling the operation of the sense amplifier based on a plurality of flip-flop outputs, it is possible to reduce energy overhead due to the use of a plurality of sense amplifiers.

1A to 1D are diagrams for describing a neuromorphic system according to an embodiment.
FIG. 2 is a diagram for describing an example of processing a plurality of spike signals simultaneously input in a neuromorphic system according to an embodiment.
3A to 3B are diagrams for explaining an implementation example of a weight calculating unit provided in a neuromorphic system according to an embodiment.
4A to 4B are diagrams for explaining implementation examples of a plurality of sense amplifiers included in a neuromorphic system according to an embodiment.
5A to 5D are diagrams for explaining simulation results of a neuromorphic system according to an embodiment.
6A to 6B are diagrams for explaining an example of processing a multi-bit weight value in a neuromorphic system according to an embodiment.
7 is a diagram illustrating a method of performing a multi-MAC operation using a neuromorphic system according to an embodiment.

Hereinafter, various embodiments of the present document will be described with reference to the accompanying drawings.

The embodiments and terms used therein are not intended to limit the technology described in this document to a specific embodiment, and should be understood to include various changes, equivalents, and/or substitutes for the corresponding embodiment.

In the following description of various embodiments, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the invention, a detailed description thereof will be omitted.

In addition, terms to be described later are terms defined in consideration of functions in various embodiments, which may vary according to the intention or custom of users or operators. Therefore, the definition should be made based on the contents throughout the present specification.

In connection with the description of the drawings, similar reference numerals may be used for similar elements.

Singular expressions may include plural expressions unless the context clearly indicates otherwise.

In this document, expressions such as "A or B" or "at least one of A and/or B" may include all possible combinations of items listed together.

Expressions such as "first," "second," "first," or "second," can modify the corresponding elements regardless of their order or importance, and to distinguish one element from another It is used only and does not limit the corresponding components.

When any (eg, first) component is referred to as being “(functionally or communicatively) connected” or “connected” to another (eg, second) component, a component is referred to as the other component. It may be directly connected to the element, or may be connected through another element (eg, a third element).

In the present specification, "configured to" (configured to)" is changed to "suitable to," "having the ability to," "to," "to," "suitable for" in hardware or software according to the situation, for example, ," "made to," "can do," or "designed to" can be used interchangeably.

In some situations, the expression "a device configured to" may mean that the device "can" along with other devices or parts.

For example, the phrase “a processor configured (or configured) to perform A, B, and C” means a dedicated processor (eg, an embedded processor) for performing the operation, or by executing one or more software programs stored in a memory device. , May mean a general-purpose processor (eg, a CPU or an application processor) capable of performing the corresponding operations.

In addition, the term'or' means an inclusive OR'inclusive or' rather than an exclusive OR'exclusive or'.

That is, unless stated otherwise or unless clear from context, the expression'x uses a or b'means any one of natural inclusive permutations.

In the above-described specific embodiments, constituent elements included in the invention are expressed in the singular or plural according to the presented specific embodiments.

However, the singular or plural expression is selected appropriately for the situation presented for convenience of description, and the above-described embodiments are not limited to the singular or plural constituent elements, and even constituent elements expressed in plural are composed of the singular or However, even if it is a component expressed in a singular number, it can be composed of pluralities.

Meanwhile, although specific embodiments have been described in the description of the present invention, various modifications are possible without departing from the scope of the technical idea included in the various embodiments.

Therefore, the scope of the present invention is limited to the described embodiments and should not be defined, and should be defined by the claims and equivalents as well as the claims to be described later.

1A to 1D are diagrams for describing a neuromorphic system according to an embodiment.

1A to 1D, reference numeral 110 denotes a neuromorphic system according to an embodiment, and reference numeral 120 denotes a plurality of sense amplifiers used for MAC operation in a neuromorphic system according to an embodiment. Show.

Further, reference numeral 130 denotes a result of a MAC operation using a plurality of sense amplifiers, and reference numeral 140 denotes a timing diagram according to an operation of a neuromorphic system according to an embodiment.

According to reference numeral 110, the neuromorphic system 110 according to an embodiment performs a multiple-MAC operation using a plurality of sense amplifiers of SRAM, not an analog multiple-MAC operation requiring an existing ADC. can do.

In addition, the neuromorphic system 110 performs a multiple-MAC operation without an ADC to minimize loss due to space, energy, and delay overhead, thereby increasing overall energy efficiency.

In addition, the neuromorphic system 110 controls the operation of the sense amplifiers based on a plurality of flip-flop outputs, thereby reducing energy overhead due to the use of a plurality of sense amplifiers.

To this end, the neuromorphic system 110 according to an embodiment may include a synapse array 111, a weight calculating unit 112, and a signal providing unit 113. In addition, the neuromorphic system 110 may further include a neuron processor 114.

For example, the neuron processor 114 functions as an adder for summing values output from a plurality of weight calculation units 112 connected to each of a plurality of bit lines BL0 to BLn; where n is a positive integer. You can do it.

For example, the neuromorphic system 110 according to an embodiment may be a spiking neural network (SNN) system.

The synaptic array 111 according to an embodiment corresponds to synaptic circuits for receiving spikes signals among a plurality of synaptic circuits connected to any one of a plurality of bit lines BL0 to BLn. At least one weight value may be output.

Specifically, the synaptic array 111 may include a plurality of synaptic circuits formed at intersections of a plurality of word lines WL0 to WLn and a plurality of bit lines BL0 to BLn.

According to one side, the plurality of synaptic circuits may be circuits based on the SRAM memory cell structure. In other words, the plurality of synaptic circuits may be memory cells of the SRAM memory.

According to one side, any one bit line may be a bit line selected through a separate column decoder.

The weight operation unit 112 according to an embodiment includes a plurality of sense amplifiers that receive at least one weight value as an input through any one bit line, and uses a plurality of sense amplifiers to perform a plurality of weights. A multiplication and accumulation (MAC) operation may be performed on a value.

Specifically, when any one bit line is'BL0', the plurality of sense amplifiers of the weight operation unit 112 are a plurality of synaptic circuits located at the intersection of the bit line'BL0' and the word lines'WL0' to'WLn'. Among them, at least one weight value corresponding to the synaptic circuits receiving a spike signal through word lines'WL0' to'WLn' is received as an input, and a multiple-MAC operation is performed based on the received at least one weight value. You can do it.

According to reference numeral 120, each of the plurality of sense amplifiers SA1 and SA2 is connected to one bit line and one reference voltage line _{, and receives the bit line voltage V BL} and the reference voltage V _REF as inputs. You can receive it.

That is, a plurality of sense amplifiers according to an embodiment may share the same bit line and the same reference voltage line, through which one bit line voltage (V _BL ) and one reference voltage (V _REF ) can be shared with each other. I can.

According to reference numeral 130, the MAC operation on any one bit line may be performed through Equation 1 below.

[Equation 1]

는 복수의 워드라인 각각으로 입력되는 스파이크 신호 값을 의미할 수 있고,

는 입력되는 스파이크 신호 각각에 대응되는 시냅스 회로들의 웨이트 값일 수 있다. here,

May mean a spike signal value input to each of a plurality of word lines,

May be a weight value of synaptic circuits corresponding to each input spike signal.

In addition, in reference numeral 130, tn (where n is a positive integer) indicates a time when the result value of Equation 1 is n, which _{is smaller than the reference voltage V REF} and the output of the sense amplifier becomes 1. I can.

For example, t3 may be a time when the yield of '3' and '2', which are the result values of Equation 1, are the same, and the value becomes the maximum, and t2 is the result of Equation 1, '2' and While the yield of '1' is the same, it may be a time when the value becomes the maximum, and t1 may be a time determined by the target yield of '1', which is a result of Equation 1.

Specifically, each of the plurality of sense amplifiers according to an exemplary embodiment detects a time point (t1, t2, t3) at _{which the bit line voltage (V BL} ) applied through any one bit line is lower than the reference voltage (V _{REF ).} And, it is possible to output the MAC operation result corresponding to the sensed time (t1, t2, t3).

_{That is, the bit line voltage (V BL} ) is lower than the reference voltage (V _REF ) according to the result values ('0', '1', '2', '3') of the MAC operation calculated through Equation 1 Since the time points t1, t2, and t3 are different, a plurality of sense amplifiers according to an embodiment may output the MAC operation result through a sensing operation for the time points t1, t2, and t3.

According to one side, each of the plurality of sense amplifiers uses one reference voltage (V _REF ) to distinguish between '3' and '2' which are the result values of Equation 1 at t3, and the result of Equation 1 at t2. '2' and '1' are distinguished, and in the case of t1, '1' and '0', which are the result values of Equation 1, can be distinguished.

Specifically, when a total of N spike signals (here, N is a positive integer) are simultaneously input, the minimum value of the result value of Equation 1 may be '0' and the maximum value may be'N'. In addition, the rate at which the bit line voltage V _BL is discharged may vary according to the result of Equation 1.

In theory, in order to perform a total of N MAC operations at the same time, enable the sense amplifiers up to N times sequentially from t1 to tn, and calculate the output value of the MAC operation when the first sense amplifier finds the time at which it becomes '1'. can do.

For example, if the sense amplifier is enabled at t3 and the output value of the sense amplifier is '1', the result value of Equation 1 may be '3!'.

However, when the result value of Equation 1 is greater than or equal to '4', the rate at which the bit line is discharged is very large, and the interval of tn may be very small.

In addition, the Considering the change (variation) of the bit line voltage (V _BL), bit line voltage (V _BL) distribution (distribution) is not less than the "4" results in the expression (1) through a large, the sense amplifier of There is a problem that it is difficult to distinguish.

Accordingly, the neuromorphic system 110 according to an embodiment may simultaneously enable a total of three word lines to simultaneously perform up to three MAC operations.

When a sense amplifier of an actual SRAM is designed, it may take at least 500ps or more for the output to be '0' or '1'. However, since the interval between t3 and t2 is smaller than that, the neuromorphic system 110 according to an embodiment may use two sense amplifiers for each bit line.

According to reference numerals 110 and 140, T _1OP may indicate a period until a result value is output through the neuron processor 114, PRE may indicate a precharge voltage, and WL may indicate a word line voltage. In addition, SAE1 and SAE2 may represent enable signals of each of the first sense amplifier and the second sense amplifier among the plurality of sense amplifiers, and ADD may indicate an enable signal for the operation of the neuron processor 114.

That is, it can be seen that the first sense amplifier is enabled only at t1 and t3, and the second sense amplifier is enabled only at t2.

Again, according to reference numeral 110, the signal providing unit 130 according to an embodiment selects at least one word line among a plurality of word lines WL0 to WLn provided in the synapse array at the same timing, and at the same timing. A spike signal may be provided through the selected word lines.

For example, the signal providing unit 113 may select up to three word lines from among the plurality of word lines WL0 to WLn at the same timing and provide spike signals corresponding to the selected three word lines.

According to one side, the signal providing unit 113 includes pre-neurons connected to each of the plurality of word lines WL0 to WLn, and a synaptic circuit corresponding to each of the plurality of word lines through the free neurons. It can provide spike signals to people.

In addition, the signal providing unit 113 may be implemented as a row decoder to provide spike signals corresponding to synaptic circuits.

2 is a diagram illustrating an example of processing a plurality of spike signals simultaneously input in a neuromorphic system according to an embodiment.

In other words, FIG. 2 is a diagram for explaining an example of a neuromorphic system according to an embodiment described with reference to FIGS. 1A to 1D, and a neuromorphic system according to an embodiment of the contents described with reference to FIG. 2 hereinafter. Descriptions that are overlapping with those described through will be omitted.

Referring to FIG. 2, as described above, when the result value of Equation 1 is '4' or more, the rate at which the bit line is discharged is very large, and the interval of tn may be very small, and the bit line voltage (V _BL ) is changed. When (variation) is considered, there is a problem that it is difficult to distinguish a case in which the result value of Equation 1 is '4' or more through the sense amplifier because the distribution of the _{bit line voltage V BL is increased.}

Thus, the neuromorphic system according to an embodiment, as shown in reference numeral 200, when four spike signals are input at the same time, performs MAC operation on only three spike signals of the four spike signals at the same time, and the remaining one The two spike signals may perform MAC operations in the next period.

_{That is, the neuromorphic} system according to an embodiment may output a result value by performing a MAC operation for 2*T 1OP when four spike signals are received.

In other words, when the neuromorphic system according to an embodiment receives M or more spike signals at the same time (here, M is a positive integer of 4 or more), the received M spike signals are divided and grouped by three, and the grouped The MAC operation may be performed on the spike signals included in each of the plurality of groups at the same timing (T _{1OP ).}

For example, the grouping operation of the spike signals may be performed through the weight calculator of the neuromorphic system according to an embodiment.

As a result, the present invention can perform MAC operation processing at a speed of about three times faster than that of the existing SNN system by simultaneously performing MAC operation on up to three spike signals.

3A to 3B are diagrams for explaining an implementation example of a weight calculation unit provided in a neuromorphic system according to an embodiment.

In other words, FIGS. 3A to 3B are views for explaining an example of a neuromorphic system according to an embodiment described with reference to FIGS. 1A to 2, and an embodiment of the contents described with reference to FIGS. 3A to 3B hereinafter Descriptions that are overlapping with those described through the neuromorphic system according to will be omitted.

3A to 3B, reference numeral 310 denotes a detailed structure of a weight operation unit according to an embodiment, and reference numeral 320 denotes a timing diagram according to an operation of the weight operation unit according to an embodiment.

According to reference numeral 310, the weight calculating unit according to an embodiment is a first sense amplifier 311, a second sense amplifier 312, a first logic gate 313, a second logic gate 314, a first flip-flop. 315 and a second flip-flop 316 may be included.

In addition, the weight calculation unit according to an embodiment may further include a sense amplifier controller 317, and the sense amplifier controller 317 may include an AND gate.

For example, the first logic gate 313 and the second logic gate 314 may include at least one of a NAND gate and an OR gate. Also, the first logic gate 313 and the second logic gate 314 may include a plurality of inverters connected to an output terminal of at least one of the NAND gate and the OR gate.

According to one side, each of the plurality of sense amplifiers 311 and 312 receives the first output signals SO1 and SO2 and the second output signals SOb1 and SOb2 of each of the plurality of sense amplifiers 311 and 312 as inputs. First to second logic gates 313 and 314 for generating control clocks CLK1 and CLK2, and first to second logic gates 313 and 314 for receiving first output signals SO1 and SO2 and generated control clocks CLK1 and CLK2 as inputs. It may be connected to the second flip-flops 315 and 316, respectively.

For example, the second output signals SOb1 and SOb2 may be inverted signals of the first output signals SO1 and SO2.

In other words, the first sense amplifier 311 receives the first output signal SO1 and the second output signal SOb1 of the first sense amplifier 311 as inputs and generates a control clock CLK1. The gate 313 and the first output signal SO1 of the first sense amplifier 311 and the first flip-flop 315 receiving the control clock CLK1 generated by the first logic gate 313 as inputs. I can.

In addition, the second sense amplifier 312 receives the first output signal SO2 and the second output signal SOb2 of the second sense amplifier 312 as inputs, and generates a control clock CLK2. 314 and the first output signal SO2 of the second sense amplifier 312 and the second flip-flop 316 receiving the control clock CLK2 generated by the second logic gate 314 as inputs. have.

More specifically, when the first to second sense amplifiers 311 and 312 are enabled by receiving the first to second enable signals SA1_EN and SA2_EN, the first output signals SO1 and SO2 and the second output The signals SOb1 and SOb2 are respectively raised to the power supply voltage level V _DD or the 0V level, and when the enable is terminated, all of the signals SOb1 and SOb2 may return to the 0V level.

In the first to second sense amplifiers 311 and 312 according to an embodiment, when the first to second logic gates 313 and 314 are OR gates, the first output signals SO1 and SO2 and the second output signals (SOb1, SOb2) can be transferred to the inputs of the first to second logic gates 313 and 314, and the first to second logic gates 313 and 314 are controlled clocks CLK1 and CLK2 based on the input signals. ) Can be created.

In addition, the first to second sense amplifiers 311 and 312 provide first output signals SO1 and SO2 to the first to second flip-flops 315 and 316 based on the generated control clocks CLK1 and CLK2. Can be delivered.

For example, when the first to second sense amplifiers 311 and 312 are enabled, they output the first output signals SO1 and SO2 of 0V, and the second output signals SOb1 of the _{power supply voltage level V DD} , SOb2), and the first to second logic gates 313 and 314 receive the first output signals SO1 and SO2 and the second output signals SOb1 and SOb2 as inputs, and the value is '1. 'In control clocks CLK1 and CLK2 can be generated.

In addition, when the first to second sense amplifiers 311 and 312 are disabled, they can output 0V first output signals SO1 and SO2 and second output signals SOb1 and SOb2, 2 The logic gates 313 and 314 receive the first output signals SO1 and SO2 and the second output signals SOb1 and SOb2 as inputs to generate control clocks CLK1 and CLK2 having a value of '0'. have.

In other words, since the control clocks CLK1 and CLK2 are always generated after the outputs of the first to second sense amplifiers 311 and 312 _{are changed to 0V or the power supply voltage level (V DD} ), the correct output values can always be delivered. have.

According to one side, each of the plurality of sense amplifiers 311 and 312 is an output signal OUT of the flip-flops 315 and 316 from the flip-flops 315 and 316 corresponding to each of the plurality of sense amplifiers 311 and 312. [0], OUT[1]) generated from the sense amplifier controller 317 generating an amplifier enable signal for controlling the operation of at least one sense amplifier among the plurality of sense amplifiers 311 and 312 The amplifier enable signal can be received as an input.

More specifically, the sense amplifier controller 317 includes an output signal OUT[0] of the first flip-flop 315, an output signal OUT[1] of the second flip-flop 316, and a first row enable. A first enable signal SA1_EN may be generated by receiving the signal SA1_EN_raw as an input.

Also, the first sense amplifier 311 may receive and enable the first enable signal SA1_EN, and the second sense amplifier 312 may receive and enable the second enable signal SA2_EN.

For example, the first row enable signal SA1_EN_raw and the second enable signal SA2_EN may be received from a separate control means provided outside, and the separate control means is a neuromorphic signal according to an embodiment. It may be the controller of the system.

According to reference numeral 320, when the result values of Equation 1 are '0', '1', '2', and '3', the output signal OUT[0] of the first flip-flop 315 and , The value of the output signal OUT[1] of the second flip-flop 316 may be expressed as shown in Table 1 below.

[Table 1]

According to Table 1 and reference numeral 320, when the output signal of the flip-flop becomes '1' at t3 or t2, since '3' or '2' is detected, in order to distinguish between '1' and '0', At t1, the first sense amplifier 311 does not need to be enabled.

That is, the sense amplifier controller 317 does not provide the first enable signal SA1_EN for enabling the first sense amplifier 311 at t3 to the first sense amplifier 311, so that the sense amplifier compared to the existing technology It is possible to reduce the energy overhead generated by using one more.

4A to 4B are diagrams for explaining implementation examples of a plurality of sense amplifiers included in a neuromorphic system according to an embodiment.

In other words, FIGS. 4A to 4B are views for explaining an example of a neuromorphic system according to an embodiment described with reference to FIGS. 1A to 3B, and an embodiment of the contents described with reference to FIGS. 4A to 4B hereinafter Descriptions that are overlapping with those described through the neuromorphic system according to will be omitted.

4A to 4B, reference numeral 410 denotes a detailed structure of a sense amplifier included in a neuromorphic system according to an embodiment, and reference numeral 420 denotes a signal input to the sense amplifier according to an embodiment. .

According to reference numerals 410 to 420, SAE denotes a first enable signal, SAEb denotes an inverted first enable signal, SAE2 denotes a second enable signal, and SAE2b denotes an inverted second enable signal. Can be indicated.

The plurality of sense amplifiers provided in the neuromorphic system according to the embodiment differs from the read operation of the conventional SRAM, which ends when the sense amplifier is enabled once at a specific time, while the bit line voltage changes over time. It may be designed in a structure in which the sense amplifier is enabled up to three times, and may be designed as 410 in order to prevent the bit line voltage from being changed due to the operation of the sense amplifier.

More specifically, the sense amplifier of reference numeral 410 is connected to the bit line when the sense amplifier is not enabled, and may generate an output through comparison with the _{reference voltage V REF at times t1, t2 and t3.} .

5A to 5D are diagrams for explaining simulation results of a neuromorphic system according to an embodiment.

5A to 5D, reference numeral 510 denotes a simulation result when the result value of Equation 1 is '3', and reference numeral 520 denotes a simulation result when the result value of Equation 1 is '2'. A simulation result is denoted, and reference numeral 530 denotes a simulation result when the result value of Equation 1 is '1', and 540 denotes a simulation result when the result value of Equation 1 is '0'.

According to reference numeral 510, since the values of the output signal OUT[0] of the first flip-flop and the output signal OUT[1] of the second flip-flop are both '1', the result of Equation 1 is' 3!', and since the output signal OUT[0] of the first flip-flop has already become '1', the first enable signal SA1_EN can be enabled only once.

Further, according to reference numeral 520, since the value of the output signal OUT[0] of the first flip-flop is '0' and the value of the output signal OUT[1] of the second flip-flop is '1', The result value of Equation 1 can be derived as '2!', and since the output signal OUT[1] of the second flip-flop has already become '1', the first enable signal SA1_EN will be enabled only once. I can.

In addition, according to reference numeral 530, the value of the output signal OUT[0] of the first flip-flop is '1' and the value of the output signal OUT[1] of the second flip-flop is '0'. The result of Equation 1 can be derived as '1!', and since the output signal OUT[1] of the second flip-flop has already become '1', the first enable signal SA1_EN is enabled twice. Can be.

Further, according to reference numeral 540, since the values of the output signal OUT[0] of the first flip-flop and the output signal OUT[1] of the second flip-flop are both '0', the result of Equation 1 May be derived as '0', and the first enable signal SA1_EN may be enabled twice. Reference numeral 540 may be generated when the weight value is '0'.

6A to 6B are diagrams for explaining an example of processing a multi-bit weight value in a neuromorphic system according to an embodiment.

In other words, FIGS. 6A to 6B are diagrams for explaining an example of a neuromorphic system according to an embodiment described with reference to FIGS. 1A to 5D, and an embodiment of the contents described with reference to FIGS. 6A to 6B hereinafter Descriptions that are overlapping with those described through the neuromorphic system according to will be omitted.

6A to 6B, reference numeral 610 denotes an example of an 8-bit weight and a 16-bit neuron membrane voltage, and 620 denotes a detailed structure of a neuron processor according to an embodiment.

According to reference numerals 610 to 620, the neuron processor of the neuromorphic system according to an embodiment includes a result value of a MAC operation and a membrane value (N) of a neuron corresponding to the MAC operation value, as shown in Equation 2 below. Can be summed up.

[Equation 2]

Since the neuromorphic system according to an embodiment has two outputs for each bit line, a case in which three values are added as shown by reference numeral 610 may occur.

In general, the output obtained by summing the outputs of each bit line with a (n+1) bit adder can be summed with the membrane voltage of a neuron, but in this case, the delay of the (n+1) bit adder compared to the existing SNN network ( delay) can be added.

In order to reduce the delay for this, the neuron processor of the neuromorphic system according to an embodiment is implemented by a combination of a bit carry save adder (CSA) and a carry ripple adder (CRA). It can handle multi-bit weights.

Specifically, the neuron processor can add up only carry over 9 bits in the intervals of reference numerals 611 and 621, and operate as a 9-bit adder that sums three values in the intervals of reference numerals 612 and 622. I can.

According to one side, the operation period T _adder of the neuron processor may be expressed as Equation 3 below.

[Equation 3]

Here, T _FA may represent a full-adder delay, and T _CRA may represent a CRA delay.

7 is a diagram illustrating a method of performing a multi-MAC operation using a neuromorphic system according to an embodiment.

In other words, FIG. 7 is a diagram for explaining a method of operating a neuromorphic system according to an embodiment described with reference to FIGS. 1A to 6B, and contents described with reference to FIGS. 1A to 6B among the contents described later with reference to FIG. 7 A description overlapping with will be omitted.

Specifically, in step 710, in the method of performing a multi-MAC operation according to an embodiment, the signal providing unit selects at least one word line from among a plurality of word lines provided in the synapse array at the same timing, and selects the word selected at the same timing. It is possible to provide a spike signal through the lines.

Next, in step 720, a method of performing a multi-MAC operation according to an embodiment is a synapse of receiving a spike signal from among a plurality of synaptic circuits connected to any one of a plurality of bit lines in a synapse array. At least one weight value corresponding to the circuits may be output.

Next, in step 730, a method of performing a multi-MAC operation according to an embodiment is performed by using a plurality of sense amplifiers receiving at least one weight value as an input through any one bit line in the weight calculation unit. A multiplication and accumulation (MAC) operation may be performed on the weight value of.

According to one side, each of the plurality of sense amplifiers receives a first output signal and a second output signal of each of the plurality of sense amplifiers as inputs to generate a control clock and a logic gate and a first output signal and a generated control clock as inputs. It may be connected to a receiving flip-flop.

In addition, each of the plurality of sense amplifiers receives the output signals of the flip-flops from the flip-flops corresponding to each of the plurality of sense amplifiers, and provides an amplifier enable signal for controlling the operation of at least one sense amplifier among the plurality of sense amplifiers. The generated amplifier enable signal may be received from the generated sense amplifier controller.

Consequently, using the present invention, it is possible to perform a multiple-MAC operation using a plurality of sense amplifiers of SRAM rather than an analog multiple-MAC operation requiring a conventional ADC.

In addition, the present invention can increase overall energy efficiency by minimizing loss due to space, energy, and delay overhead by performing a multiple-MAC operation without an ADC.

In addition, according to the present invention, by controlling the operation of the sense amplifiers based on a plurality of flip-flop outputs, energy overhead due to the use of a plurality of sense amplifiers can be reduced.

As described above, although the embodiments have been described by the limited drawings, various modifications and variations can be made from the above description to those of ordinary skill in the art. For example, the described techniques are performed in a different order from the described method, and/or components such as systems, structures, devices, circuits, etc. described are combined or combined in a form different from the described method, or other components Alternatively, even if substituted or substituted by an equivalent, an appropriate result can be achieved.

Therefore, other implementations, other embodiments, and those equivalent to the claims also fall within the scope of the claims to be described later.

110: neuromorphic system 111: synaptic array
112: weight calculating unit 113: signal providing unit
114: neuron processor

Claims (12)

A synapse array that outputs at least one weight value corresponding to synaptic circuits that receive a spikes signal from among a plurality of synaptic circuits connected to any one of a plurality of bit lines, and
And a plurality of sense amplifiers receiving the at least one weight value as an input through the one bit line, and MAC (multiplication and processing) for the plurality of weight values using the plurality of sense amplifiers. Weight calculation unit that performs accumulation) operation
Neuromorphic system comprising a. The method of claim 1,
The plurality of synaptic circuits are circuits based on the SRAM memory cell structure.
Neuromorphic system. The method of claim 1,
A signal providing unit for selecting at least one word line among a plurality of word lines provided in the synapse array at the same timing and providing the spike signal through the selected word lines at the same timing
Neuromorphic system further comprising a. The method of claim 3,
The signal providing unit
Including pre-neurons connected to each of the plurality of word lines, and providing the spike signal to synaptic circuits corresponding to each of the plurality of word lines through the free neurons
Neuromorphic system. The method of claim 1,
Each of the plurality of sense amplifiers
Any one of the bit lines and a reference voltage line for applying one reference voltage are connected as inputs.
Neuromorphic system. The method of claim 5,
Each of the plurality of sense amplifiers
Detecting a point in time when the bit line voltage applied through any one of the bit lines becomes lower than the reference voltage, and outputting the MAC operation result corresponding to the sensed point in time.
Neuromorphic system. The method of claim 1,
Each of the plurality of sense amplifiers
A logic gate receiving a first output signal and a second output signal of each of the plurality of sense amplifiers as inputs to generate a control clock, and a flip-flop receiving the first output signal and the generated control clock as inputs. flop) and connected
Neuromorphic system. The method of claim 7,
Each of the plurality of sense amplifiers
A sense amplifier controller that receives output signals of the flip-flops from flip-flops corresponding to each of the plurality of sense amplifiers, and generates an amplifier enable signal for controlling the operation of at least one sense amplifier among the plurality of sense amplifiers Receiving the generated amplifier enable signal as an input from
Neuromorphic system. In the synapse array, outputting at least one weight value corresponding to synaptic circuits receiving spikes signals from among a plurality of synaptic circuits connected to any one of a plurality of bit lines And
A weight calculator performs a multiplication and accumulation (MAC) operation on the plurality of weight values using a plurality of sense amplifiers that receive the at least one weight value as an input through the one bit line. Steps to do
A method of performing a multi-MAC operation using a neuromorphic system comprising a. The method of claim 9,
In a signal providing unit, selecting at least one word line among a plurality of word lines provided in the synapse array at the same timing, and providing the spike signal through the selected word lines at the same timing.
Method for performing a multi-MAC operation using a neuromorphic system further comprising a. The method of claim 9,
Each of the plurality of sense amplifiers
A logic gate receiving a first output signal and a second output signal of each of the plurality of sense amplifiers as inputs to generate a control clock, and a flip-flop receiving the first output signal and the generated control clock as inputs. flop) and connected
A method of performing multi-MAC operation using a neuromorphic system. The method of claim 11,
Each of the plurality of sense amplifiers
A sense amplifier controller that receives output signals of the flip-flops from flip-flops corresponding to each of the plurality of sense amplifiers, and generates an amplifier enable signal for controlling the operation of at least one sense amplifier among the plurality of sense amplifiers Receiving the generated amplifier enable signal from
A method of performing multi-MAC operation using a neuromorphic system.

Images