KR20210019188A - Memory system and operation method of memory system - Google Patents

Abstract

Provided is a memory system, which includes a memory device and a memory controller. The memory device includes a table for managing rows requiring an additional refresh operation. The memory controller may include: a replica table managed in the same manner as the memory table; an error history storage circuit for storing an error history of the memory device; and a determination circuit determining whether an active operation related to a row to be evicted is performed using the error history when the row to be evicted occurs in the replica table without the additional refresh operation. According to the present invention, rows which need to be refreshed by row hammering are efficiently selected.

Description

Memory system and its operation method {MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEM}

This patent document relates to a memory system.

As the density of the memory increases, the spacing between a plurality of word lines included in the memory is decreasing. As the spacing between word lines decreases, the coupling effect between adjacent word lines increases.

On the other hand, whenever data is input or output to a memory cell, the word line is toggled between the active (active) state and the inactive state. As described above, as the coupling effect between adjacent word lines increases, the word line adjacent to the frequently activated word line Data in the memory cell connected to the device is damaged. This phenomenon is called row hammering, and a phenomenon in which data of a memory cell is damaged before the memory cell is refreshed due to word line disturbance has been a problem.

FIG. 1 is a diagram illustrating a row hammering phenomenon and is a diagram illustrating a part of a cell array included in a memory device.

In FIG. 1,'WLL' corresponds to a word line with a large number of activations, and'WLL-1' and'WLL+1' are word lines disposed adjacent to'WLL', that is, word lines with the number of activations adjacent to the word line. Corresponds to. In addition,'CL' denotes a memory cell connected to'WLL','CL-1' denotes a memory cell connected to'WLL-1', and'CL+1' denotes a memory cell connected to'WLL+1'. Each memory cell includes cell transistors TL, TL-1, and TL+1 and cell capacitors CAPL, CAPL-1, and CAPL+1.

In FIG. 1, when'WLL' is activated or deactivated, the voltage of'WLL-1' and'WLL+1' rises due to the coupling phenomenon occurring between'WLL' and'WLL-1' and'WLL+1'. The amount of charge in the cell capacitors CL-1 and CL+1 is also affected while falling or falling. Therefore, if'WLL' is frequently activated and'WLL' toggles between the activated and deactivated states, the cell capacitors (CAPL-1, CAPL+1) included in'CL-1' and'CL+1' The change in the amount of stored charge increases and data in the memory cell may be deteriorated.

In addition, the electromagnetic wave generated while the word line toggles between the active and inactive states damages data by introducing electrons into the cell capacitor of a memory cell connected to the adjacent word line or releasing electrons from the cell capacitor.

As a method for solving row hammering, a method of finding a row that has been active multiple times and refreshing the surrounding rows of the row that has been active multiple times is mainly used. As a method of finding a row that has been active multiple times, a method of counting the number of actives of all active rows for a certain period of time is mainly used, and in this case, there is a problem that the overhead is excessively large.

Embodiments of the present invention can provide a technique for efficiently selecting rows that need to be refreshed by row hammering.

A memory system according to an embodiment of the present invention includes a memory device and a memory controller, wherein the memory device includes a table for managing rows requiring an additional refresh operation, and the memory controller is the same as the table of the memory. A replica table that is easily managed; An error history storage circuit for storing an error history of the memory device; And a determination circuit that determines whether or not an active operation related to the row to be eviction is performed using the error history when a row to be eviction is generated in the replica table without the additional refresh operation.

A method of operating a memory system according to an embodiment of the present invention includes the steps of: managing, by a memory device, a table storing rows requiring a plurality of additional refresh operations; Managing, by a memory controller, the same replica table as the table with the same rules as the table; Selecting, by the memory controller, a row to be removed without the additional refresh operation from the replica table and eviction; Checking, by the memory controller, an error history of the ejected row; In response to the memory controller confirming that an error history of the eviction row exists, determining to perform an active operation on the eviction row.

According to the embodiments of the present invention, rows requiring refreshing can be efficiently selected by row hammering.

1 is a view for explaining a row hammering phenomenon and showing a part of a cell array included in a memory device.
2 is a block diagram of a memory system 200 according to an embodiment of the present invention.
3 is a configuration diagram of an embodiment of a refresh target row selection circuit 214;
4 is a diagram for explaining the operation of the refresh target row selection circuit 214;
5 is a block diagram of a memory system 500 according to another embodiment of the present invention.
6 is a configuration diagram of a memory system 600 according to another embodiment of the present invention.
7 is a configuration diagram of a replica refresh target row selection circuit 618 according to an embodiment.

Hereinafter, in order to describe in detail so that those of ordinary skill in the art can easily implement the technical idea of the present invention, a most preferred embodiment of the present invention will be described with reference to the accompanying drawings. In describing the present invention, known configurations irrelevant to the gist of the present invention may be omitted. In adding reference numerals to elements of each drawing, it should be noted that only the same elements have the same number as possible, even if they are indicated on different drawings.

2 is a block diagram of a memory system 200 according to an embodiment of the present invention.

Referring to FIG. 2, the memory system 200 may include a memory controller 210 and a memory device 220.

The memory controller 210 may control the operation of the memory device 220 according to a request from a host (HOST). The host may include a central processing unit (CPU), a graphical processing unit (GPU), and an application processor (AP). The memory controller 210 may include a host interface 211, a scheduler 212, a command generator 213, a refresh target row selection circuit 214, and a memory interface 215.

The host interface 211 may be for an interface between the memory controller 210 and the host HOST. Requests from the host may be received through the host interface 211, and results of processing the request may be transmitted to the host.

The scheduler 212 may determine an order of requests to be directed to the memory device 220 among requests from a host (HOST). The scheduler 212 may change the order in which requests are received from the host and the order of operations to be directed to the memory device 220 in order to improve the performance of the memory device 220. For example, even if the host (HOST) requests a read operation of the memory device 220 first and then requests a write operation, the order may be adjusted so that the write operation is performed before the read operation.

The scheduler 212 may schedule a refresh operation between operations requested from the host in order to prevent data in the memory device 220 from being lost. Whenever a refresh command is applied from the memory controller 210 to the memory device 220 by scheduling of the scheduler 212, the memory device 220 sequentially activates internal rows (that is, word lines). I can.

Meanwhile, the scheduler 212 may schedule an additional refresh operation to prevent data loss due to row hammering in addition to the general refresh operation. The additional refresh operation may be performed not by sequentially refreshing the rows of the memory devices 220, but by activating a row determined to have a high possibility of data loss due to row hammering. That is, during the additional refresh operation, an address of a row determined to have a high probability of data loss due to row hammering together with an active command may be applied from the memory controller 210 to the memory device 220. Rows with a high possibility of data loss due to row hammering may be selected by the refresh target row selection circuit 214. The scheduler 212 may periodically schedule an additional refresh operation. For example, an additional refresh operation may be performed once every 10 times the refresh operation is performed, or an additional refresh operation may be performed once every 100 times the refresh operation is performed.

The refresh target row selection circuit 214 monitors an active command and an address applied from the memory controller 210 to the memory device 220, selects a row with a high possibility of data loss due to row hammering, and selects a row with a high probability of losing data. 212) can be provided to perform an additional refresh operation for a row in which data is likely to be lost due to row hammering.

The command generator 213 may generate a command to be applied to the memory device 220 in accordance with the order of operations determined by the scheduler 212.

The memory interface 215 may be for an interface between the memory controller 210 and the memory device 220. A command CMD and an address ADD may be transmitted from the memory controller 210 to the memory device 220 through the memory interface 215, and data DATA may be transmitted/received. The memory interface 215 is also referred to as a PHY interface.

The memory device 220 may perform an operation indicated by the memory controller 210. The memory device 220 may be a memory device 220 requiring a refresh operation. For example, the memory device 220 may be a DRAM, or another type of memory device requiring a refresh operation.

3 is a configuration diagram of a refresh target row selection circuit 214 according to an embodiment.

Referring to FIG. 3, the refresh target row selection circuit 214 may include a cold table 311, a hot table 312, an input unit 320, a promotion unit 330, and an eviction unit 340.

The cold table 311 may store a plurality of cold rows. Here, the cold rows may mean rows that have not been stored in the cold table 311 and the hot table 312 among the rows selected as hammered rows. A rank may be assigned to cold rows stored in the cold table 311.

The hot table 312 may store a plurality of hot rows. Here, the hot rows may refer to rows stored in the cold table 311 or the hot table 312 among rows selected as hammered rows. A rank may be assigned to the hot rows stored in the hot table 312. During the additional refresh operation, one of the hot rows may be refreshed, and one of two methods of (1) and (2) may be used. (1) During the additional refresh operation, a hot row of the highest rank of the hot table 312, that is, a hot row of rank 0, may be an additional refresh target. If the highest rank of the hot table 312 is empty, that is, if rank 0 is empty, an additional refresh operation may not be performed. (2) During the additional refresh operation, the hot row of the highest rank among the hot rows of the hot table 312 may be an additional refresh target. For example, when rank 0 is empty and there is a rank 1 hot row, an additional refresh operation for the rank 1 hot row may be performed. If the hot row does not exist at all in the hot table 312, the additional refresh operation may not be performed.

The insertion unit 320 may select a hammered row and insert the selected hammered row into the cold table 311. One of the two methods (A) and (B) may be used as a method for the input unit 320 to select a hammered row. (A) The input unit 320 may select all adjacent rows of the active row as hammered rows. For example, when row 3 is active, row 2 may be selected as a hammered row and row 4 may be selected as a hammered row. (B) The input unit 320 may select only randomly selected rows among adjacent rows of the active row as hammered rows. For example, only rows selected with a 10% probability among rows adjacent to the active row may be selected as hammered rows. In detail, the input unit 320 may select row 2 and row 4, which are adjacent rows of row 3, as hammered rows when row 3 is selected with a 10% probability when row 3 is active. have. If row 3 is not selected with a 10% probability, row 2 and row 4 may not be selected as hammered rows. Here, selecting the active row 3 with a 10% probability is to use a random number generator to generate a random number from 1 to 100, and if the generated random number is in the range of 1 to 10, select it with a 10% probability. Otherwise, it can be performed in the same way as non-selection. Data loss due to row hammering occurs when a specific row is activated at least 1000 times for a short period of time, so even if only 10% of the rows adjacent to the active row are selected as hammered rows, data is not There may be no problem figuring out which rows are likely to be lost. Rather than selecting all adjacent rows of the active row as hammered rows as in (A), as in (B), selecting adjacent rows of randomly selected rows as hammered rows. On, it is possible to reduce the size of the cold table and hot table.

When the selected hammered row is a row that has not been stored in the cold table 311 and the hot table 312, the input unit 320 assigns the selected hammered row to the highest rank of the cold table 311, that is, rank 0. , Can be stored as a cold row of. When the selected hammered row is stored as the highest rank of the cold table 311, the ranks of the cold rows already stored in the cold table 311 may be lowered by one step.

When the hammered row selected by the input unit 320 is one of the cold rows stored in the cold table 311, the promotion unit 330 deletes the row from the cold table 312 , It can be promoted to the lowest rank hot row of the hot table 312. At this time, the hot row that has already been in the lowest rank of the hot table 312 may be moved to the highest rank of the cold table 311. Also, when the hammered row selected by the input unit 320 is one of the hot rows stored in the hot table 312, the promotion unit 330 may increase the rank of the hot row by one step. As the rank of the hot row increases by one level, the rank of the hot row that was in the higher rank by one level may decrease by one level. For example, as the hot row of rank 2 increases to rank 1, the rank of the hot row of rank 1 may be lowered to rank 2.

The eviction unit 340 may delete from the hot table 312 a hot row for which an additional refresh operation has been performed among the hot rows of the hot table 312. In addition, when a new cold row is stored in the cold table 311, the eviction unit 340 may delete one of the cold rows of the cold table 311 when the cold table 311 is full. One of two methods of (I) and (II) may be used as a method for the extraction unit 340 to delete one of the cold rows of the cold table 311. (I) When a new cold row is stored in the cold table 311, the (I) extraction unit 340 may delete the cold row of the lowest rank from the cold table 311 when the cold table 311 is full. (II) When a new cold row is stored in the cold table 311, the eviction unit 340 may delete one cold row selected according to an eviction probability given for each rank of the cold rows. For example, there are 4 cold rows with a rank of 0 to 3 in the cold table 311, and each of them has a 10%, 20%, 20%, 50% eviction probability, and according to this probability One selected cold row may be deleted. Here, selecting according to probability is to generate one random number from 1 to 100 using the random number generator, and if the generated random number is in the range of 1 to 10, the cold row of rank 0 is deleted, and if the generated random number is 11 to 30, rank 1 If the generated random number is 31 to 50, the cold row of rank 2 is deleted, and if the generated random number is 51 to 100, the cold row of rank 3 is deleted. The reason that the ejection unit 340 uses the same method as in (II) is to impart some unexpectedness to the refresh target row selection method.

The refresh target row selection circuit 214 may select a row with a high possibility of data loss due to row hammering based on a history of active rows with a simple configuration and method.

4 is a diagram for explaining the operation of the refresh target row selection circuit 214. For convenience of explanation, the method (1) is used to refresh one of the hot rows of the hot table 312, and the method (A) is used to select the hammered row by the input unit 320 It will be exemplified that the method of (I) is used as a method for the extraction unit 340 to delete the cold row. In addition, the cold table 311 stores 4 cold rows, and the hot table 312 stores 3 hot rows. In addition, it is exemplified that there are 256 rows from 0 to 255.

Referring to FIG. 4, while the hot table 312 and the cold table 311 are recorded as shown in (a), row 11 may be active. Rows 10 and 12 adjacent to row 11 may be selected as hammered rows by the activation of row 11. Since row 10 has already been stored as a hot row in the hot table 312, the rank of row 10 increases from 1 to 0 so that the hot table 312 and the cold table 311 can be in the same state as (b). have. Since row 12 is not recorded in the hot table 312 and cold table 311, row 12 enters rank 0, which is the highest rank of the cold table 311, and rows 107 and 4 are ranked. When is lowered, row 89 is deleted from the cold table 311 so that the hot table 312 and the cold table 311 may be in the same state as (c).

When an additional refresh operation is performed in the state of the hot table 312 and the cold table 311 as shown in (c), an additional refresh operation for row 10, which is rank 0, of the hot table 312 may be performed. That is, the memory device 220 may perform an additional refresh operation for row 10. After the additional refresh operation is performed, row 10 is deleted from the hot table 312 so that the hot table 312 and the cold table 311 may be in the same state as (d).

In the state of the hot table 312 and the cold table 311 as shown in (d), row 25 may be activated. Rows 24 and 26 adjacent to row 25 may be selected as hammered rows by the active of row 25. Since row 24 is already stored in the cold table 311, row 24 may be moved to rank 2, which is the lowest rank of the hot table 312. In addition, row 216 in rank 2 of the hot table 312 may be moved to rank 0 of the cold table. Accordingly, the hot table 312 and the cold table 311 may be in the same state as (e). Since row 26 is a row that did not exist in the hot table 312 and cold table 311, row 26 is stored in rank 0 of the cold table 311, and the hot table 312 and the cold table 311 are ( It can be in the same state as f).

When the hot table 312 and the cold table 311 are in the same state as (f), row 0 may be activated. Row 1 adjacent to row 0 may be selected as the hammered row by the active of row 0. Since the first row is already stored in the hot table 311, the rank of the first row increases from 1 to 0, and the hot table 311 may be in the same state as (g).

When the hot table 312 and the cold table 311 are in the same state as (g), row 25 may be activated. Rows 24 and 26 adjacent to row 25 may be selected as hammered rows by the active of row 25. Since row 24 is already stored in the hot table 311, the rank of row 24 is increased from 2 to 1, so that the hot table 311 may be in the same state as (h). Since row 26 already exists in the cold table 311, row 26 is moved to rank 3 of the hot table 312 and deleted from the cold table 311, so that the hot table and the cold table are in the same state as (i). Can be.

In the state of the hot table 312 and the cold table 311 as shown in (i), row 255 may be activated. Row 254 adjacent to row 255 may be selected as a hammered row by the active of row 255. Row 254 is a row that did not exist in the hot table 312 and the cold table 311, so row 254 is stored in rank 0 of the cold table 311, and the hot table 312 and the cold table 311 It can be in the same state as (j).

Referring to FIG. 4, as adjacent rows of rows that are active several times are stored in a higher rank in the hot table 312, the rank of adjacent rows of rows that have passed a long time after being activated gradually decreases in the cold table 311. You can see that it is deleted.

5 is a block diagram of a memory system 500 according to another embodiment of the present invention.

Referring to FIG. 5, the memory system 500 may include a memory controller 510 and a memory device 520. In the memory system 500 of FIG. 5, the refresh target row selection circuit 522 may be included in the memory device 520 rather than the memory controller 510.

The memory controller 510 may control the operation of the memory device 520 according to a request from a host (HOST). The host may include a central processing unit (CPU), a graphical processing unit (GPU), and an application processor (AP). The memory controller 510 may include a host interface 511, a scheduler 512, a command generator 513, and a memory interface 515.

The host interface 511 may be for an interface between the memory controller 510 and a host (HOST). Requests from the host may be received through the host interface 511, and results of processing of the request may be transmitted to the host.

The scheduler 512 may determine an order of requests to be directed to the memory device 520 among requests from a host (HOST). The scheduler 512 may change the order in which requests are received from the host and the order of operations to be directed to the memory device 520 in order to improve the performance of the memory device 520. For example, even if the host (HOST) first requests the read operation of the memory device 520 and then requests the write operation, the order may be adjusted so that the write operation is performed before the read operation.

The scheduler 512 may schedule a refresh operation between operations requested from the host in order to prevent data in the memory device 520 from being lost. Whenever a refresh command is applied from the memory controller 510 to the memory device 520 due to scheduling of the scheduler 512, the memory device 520 sequentially activates internal rows (that is, word lines). I can.

Meanwhile, the scheduler 512 may schedule an additional refresh operation to prevent data loss due to row hammering in addition to the general refresh operation. In the embodiment of FIG. 5, since the memory device 520 includes a refresh target row selection circuit 522 that selects a row for which an additional refresh operation is to be performed, the memory controller 510 sends an additional refresh command to the memory device 520. It is possible to instruct an additional refresh operation by applying to. The scheduler 512 may periodically schedule an additional refresh operation. For example, an additional refresh operation may be performed once every 10 times the refresh operation is performed, or an additional refresh operation may be performed once every 100 times the refresh operation is performed.

The command generator 513 may generate a command to be applied to the memory device 520 according to the order of operations determined by the scheduler 512.

The memory interface 515 may be for an interface between the memory controller 510 and the memory device 520. A command CMD and an address ADD may be transmitted from the memory controller 510 to the memory device 520 through the memory interface 515, and data DATA may be transmitted/received. The memory interface 515 is also referred to as a PHY interface.

The memory device 520 may perform an operation indicated by the memory controller 510. The memory device 520 may include a command decoder 521, a refresh target row selection circuit 522, an address counter 523, and a memory array 524.

The command decoder 521 may decode the command CMD transmitted from the memory controller 510 to generate internal command signals ACT, PCG, RD, WT, REF, and ADD_REF. The internal command signals may include an active signal ACT, a precharge signal PCG, a read signal RF, a write signal WT, a refresh signal REF, and an additional refresh signal ADD_REF.

The refresh target row selection circuit 522 uses the active signal ACT and the address ADD transmitted to the memory array 524 to select adjacent rows of the rows that are activated several times, that is, a row for which an additional refresh operation is to be performed. I can. The refresh target row selection circuit 522 may be configured and operated in the same manner as the refresh target row selection circuit 214 described in FIGS. 3 to 4. The additional refresh address ADD_REF_ADD output from the refresh target row selection circuit 522 may be an address indicating a row to which an additional refresh operation is to be performed, and may be an address indicating a row of the highest rank of the hot table 312.

The address counter 523 may change the refresh address REF_ADD whenever the refresh signal REF is activated. The refresh address REF_ADD generated by the address counter 523 may be used in a normal refresh operation rather than an additional refresh operation.

The memory array 524 may perform an operation indicated by the internal command signals ACT, PCG, RD, WT, REF, and ADD_REF. During an additional refresh operation in which the additional refresh signal ADD_REF is activated, the memory array 524 may perform a refresh operation on a row selected by the additional refresh address ADD_REF_ADD. In addition, during a refresh operation in which the refresh signal REF is activated, the memory array 524 may perform a refresh operation on a row selected by the refresh address REF_ADD. In addition, the address ADD transferred from the memory controller 510 may be used during active, read, and write operations of the memory array 524. The memory array 524 includes active, precharge, read, write, refresh and additional refresh such as a cell array, a row circuit for activating/deactivating a row of the cell array, and a column circuit for inputting/outputting data from the cell array. Components for operation may be included.

In the embodiment of FIG. 2, it is illustrated that the refresh target row selection circuit 214 is included in the memory controller 210, and in the embodiment of FIG. 5, the refresh target row selection circuit 522 is included in the memory device 520. However, this is only an example, and the refresh target row selection circuit may be located in a different location than the memory device and the memory controller. For example, the refresh target row selection circuit may be configured as a separate chip and exist between the memory device and the memory controller.

6 is a block diagram of a memory system 600 according to another embodiment of the present invention.

Referring to FIG. 6, the memory system 600 may include a memory controller 610 and a memory device 620. In the memory system 600 of FIG. 6, as in FIG. 5, a refresh target row selection circuit 622 is included in the memory device 620 and may be used to select a row requiring an additional refresh operation. In addition, the memory controller 610 may also include a replica of the refresh target row selection circuit 622 and a refresh target row selection circuit 618.

The memory device 620 may perform an operation indicated by the memory controller 610. The memory device 620 may include a command decoder 621, a refresh target row selection circuit 622, an address counter 623, and a memory array 624.

The command decoder 621 may decode the command CMD transmitted from the memory controller 610 to generate internal command signals ACT, PCG, RD, WT, REF, and ADD_REF. The internal command signals may include an active signal ACT, a precharge signal PCG, a read signal RF, a write signal WT, a refresh signal REF, and an additional refresh signal ADD_REF.

The refresh target row selection circuit 622 uses the active signal ACT and the address ADD delivered to the memory array 624 to select adjacent rows of the rows that are activated several times, that is, a row for which an additional refresh operation is to be performed. I can. The refresh target row selection circuit 522 may be configured and operated in the same manner as the refresh target row selection circuit 214 described in FIGS. 3 to 4. The additional refresh address ADD_REF_ADD output from the refresh target row selection circuit 622 may be an address indicating a row to which the additional refresh operation is to be performed, and may be an address indicating a row of the highest rank of the hot table 312.

The address counter 623 may change the refresh address REF_ADD whenever the refresh signal REF is activated. The refresh address REF_ADD generated by the address counter 623 may be used in a normal refresh operation rather than an additional refresh operation.

The memory array 624 may perform an operation indicated by the internal command signals ACT, PCG, RD, WT, REF, and ADD_REF. During an additional refresh operation in which the additional refresh signal ADD_REF is activated, the memory array 624 may perform a refresh operation on a row selected by the additional refresh address ADD_REF_ADD. In addition, during the refresh operation in which the refresh signal REF is activated, the memory array 624 may perform a refresh operation on the row selected by the refresh address REF_ADD. In addition, the address ADD transferred from the memory controller 610 may be used during active, read, and write operations of the memory array 624. The memory array 624 includes active, precharge, read, write, refresh and additional refresh such as a cell array, a row circuit for activating/deactivating a row of the cell array, and a column circuit for inputting/outputting data from the cell array. Components for operation may be included.

The memory controller 610 may control the operation of the memory device 620 according to a request from a host (HOST). The host may include a central processing unit (CPU), a graphical processing unit (GPU), and an application processor (AP). The memory controller 610 includes a host interface 611, a scheduler 612, a command generator 613, a memory interface 615, an ECC circuit 616, an error history storage circuit 617, a replica refresh target row selection circuit ( 618) and a determination circuit 619 may be included.

The host interface 611 may be for an interface between the memory controller 610 and a host (HOST). Requests from a host may be received through the host interface 611, and results of processing of the request may be transmitted to the host.

The scheduler 612 may determine an order of requests to be directed to the memory device 620 among requests from a host (HOST). The scheduler 612 may change the order in which requests are received from the host and the order of operations to be directed to the memory device 620 to improve performance of the memory device 620. For example, even if the host (HOST) first requests the read operation of the memory device 620 and then requests the write operation, the order may be adjusted so that the write operation is performed before the read operation.

The scheduler 612 may schedule a refresh operation between operations requested from the host in order to prevent data from the memory device 620 from being lost. Whenever a refresh command is applied from the memory controller 610 to the memory device 620 by scheduling of the scheduler 612, the memory device 620 sequentially activates internal rows (that is, word lines). I can.

Meanwhile, the scheduler 612 may schedule an additional refresh operation to prevent data loss by row hammering in addition to the general refresh operation. In the embodiment of FIG. 6, since the memory device 620 includes a refresh target row selection circuit 622 that selects a row for which an additional refresh operation is to be performed, the memory controller 610 sends an additional refresh command to the memory device 620. It is possible to instruct an additional refresh operation by applying to. The scheduler 612 may periodically schedule an additional refresh operation. For example, an additional refresh operation may be performed once every 10 times the refresh operation is performed, or an additional refresh operation may be performed once every 100 times the refresh operation is performed.

The command generator 613 may generate a command to be applied to the memory device 620 in accordance with the order of operations determined by the scheduler 612.

The memory interface 615 may be for an interface between the memory controller 610 and the memory device 620. The command CMD and the address ADD may be transmitted from the memory controller 610 to the memory device 620 through the memory interface 615, and data DATA may be transmitted/received. The memory interface 615 is also referred to as a PHY interface.

The ECC (Error Correcting Code) circuit 616 may generate an error correction code using data during a write operation. During the write operation, the error correction code may be transferred to and stored in the memory device 620 together with data. The data DATA of FIG. 6 may represent data obtained by combining raw data and an error correction code. In addition, during a read operation, an error of data read from the memory device 620 may be corrected using an error correction code read from the memory device 620.

The error history storage circuit 617 may store an error history in which an error has been found by the ECC circuit 616, that is, an error has been corrected. For example, the error history storage circuit 617 may store information about rows in which errors are found as an error history.

The replica refresh target row selection circuit 618 is a circuit that simulates the refresh target row selection circuit 622 and may be configured and operated in the same manner as the refresh target row selection circuit 622. 7 illustrates a replica refresh target row selection circuit 618, the replica refresh target row selection circuit 618 includes a replica table 710, an input unit 720, a promotion unit 730, and an eviction unit 740 can do. The replica table 710 may include a cold table 711 and a hot table 712 like the table of the refresh target row selection circuit 622. The input unit 720, the promotion unit 730, and the eviction unit 740 of the replica refresh target row selection circuit 618 are the input unit 320, the promotion unit 330, and the eviction unit 340 of the row selection 622 to be refreshed. ) Can be operated in the same way. Accordingly, the replica table 710 may be managed in the same manner as the table of the refresh target row selection circuit 622, that is, the cold table 311 and the hot table 312.

The determination circuit 619 generates an error history storage circuit 617 when a row to be deleted (extracted) from the replica table 710 is generated without an additional refresh operation, for example, a row is deleted from the cold table 711. ), you can check whether there is an error history of the row to be evicted. For example, when row 4 is deleted (extracted) from the replica table 710 without an additional refresh operation, it can be checked whether an error history for row 4 exists in the error history storage circuit 617. When there is an error history of the row to be ejected, the determination circuit 619 may notify the scheduler 612 so that an active operation for the row to be ejected (eg, row 4) can be performed. Then, the scheduler 612 may schedule an active operation for the row to be evicted. If there is no error history of the row to be ejected, the determination circuit 619 may not be scheduled for an active operation on the row to be ejected.

Now, the operation of the memory system 600 will be described.

First, the refresh target row selection circuit 622 of the memory device 620 may manage rows requiring an additional refresh operation. A row determined to require an additional refresh operation by the refresh target row selection circuit 622, eg, a row of the highest rank of the hot table 312, is from the hot table 312 together with the execution of the additional refresh operation for the row. It can be deleted. In addition, a row determined that an additional refresh operation is not required by the refresh target row selection circuit 622, for example, a row of the lowest rank of the cold table 311, is the cold table 312 without performing an additional refresh operation for the corresponding row. Can be deleted from

The replica refresh target row selection circuit 618 of the memory controller 610 may manage the replica table 710 in the same manner as the table of the refresh target row selection circuit 622 of the memory device 620. For example, when the refresh target row selection circuit 622 deletes row 45 from the hot table 312 along with an additional refresh operation for row 45 stored in the hot table 312, a replica refresh target row is selected. The circuit 618 may also delete row 45 from the hot table 712 of the replica table 710. Further, for example, when the refresh target row selection circuit 622 deletes the fourth row from the cold table 311, the replica refresh target row selection circuit 618 also transfers the fourth row to the replica table 710. It can be deleted from the cold table 711.

The replica refresh target row selection circuit 618 may notify the determination circuit 619 when a row to be deleted from the replica table 710, example 4 row, occurs without an additional refresh operation. The determination circuit 619 may use the error history storage circuit 617 to determine whether an error history for the row deleted from the replica table 710, Example 4, row, is present without an additional refresh operation.

When there is no error history for the fourth row, the determination circuit 619 may determine that it is safe to delete from the replica table 710 without an additional refresh operation for the fourth row.

However, when there is an error history for the fourth row, the determination circuit 619 may determine that it is not safe to delete from the replica table 710 without an additional refresh operation for the fourth row. That is, although an additional refresh operation is required for row 4, the replica refresh target row selection circuit 618 and the refresh target row selection circuit 622 erroneously determine this, and thus, row 4 is performed without an additional refresh operation for row 4. It can be judged to be deleted. Accordingly, the determination circuit 619 notifies this to the scheduler 612, and the scheduler 612 may schedule an active operation for row 4. When the active operation for row 4 is scheduled by the scheduler 612, an address corresponding to row 4 along with an active command is transmitted from the memory controller 610 to the memory device 620, and the memory device 620 Row 4 may be active. Since the effect of the active operation is the same as the effect of the refresh operation, in the end, the same effect as the additional refresh operation for row 4 may occur.

In the memory system 600 of FIG. 6, the memory controller 610 uses the replica refresh target row selection circuit 618, and the row to be deleted from the table by the refresh target row selection circuit 622 of the memory device 620 does not require an additional refresh operation. You can monitor what happens. In addition, the row deleted from the table without an additional refresh operation is verified using the error history storage circuit 617 and the determination circuit 619, and if it is determined that it is not safe to delete the row, the active operation for the row is performed. Risk can be eliminated by scheduling.

In the memory system 600 of FIG. 6, the memory controller 610 schedules an additional refresh operation of the memory device 620. That is, it is illustrated that the memory device 620 performs an additional refresh operation when there is an instruction from the memory controller 610. However, according to an exemplary embodiment, there may be a case in which the memory device 620 itself performs an additional refresh operation without an instruction from the memory controller 610. For example, there may be a case in which the memory device 620 performs an additional refresh operation in a spare time in a hidden manner without the memory controller 610 knowing. In this case, since the replica refresh target row selection circuit 618 of the memory controller 610 cannot know whether the additional refresh operation has been performed, the memory device 620 will notify the memory controller 610 that the additional refresh operation has been performed. In addition, when there is a notification that the additional refresh operation has been performed, the row of the highest rank of the hot table 712 of the replica refresh target row selection circuit 618 may be deleted.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiments, it should be noted that the above embodiments are for the purpose of explanation and not limitation. In addition, any expert in the technical field of the present invention will recognize that various embodiments are possible within the scope of the technical idea of the present invention.

600: memory system
610: memory controller
620: memory device

Claims (16)

A memory system comprising a memory device and a memory controller,
The memory device is
Includes a table for managing rows that need additional refresh operations,
The memory controller is
A replica table managed in the same way as the memory table;
An error history storage circuit for storing an error history of the memory device; And
In the case where a row to be ejected without the additional refresh operation occurs in the replica table, a determination circuit for determining whether or not an active operation related to the row to be ejected is performed using the error history
Memory system.
The method of claim 1,
The table above is
Store a number of additional refresh candidate rows,
Among the candidate rows, a row determined to require an additional refresh operation is deleted from the table together with the execution of the additional refresh operation for the corresponding row,
Among the candidate rows, a row determined that an additional refresh operation is not necessary is deleted from the table without the additional refresh operation.
Memory system.
The method of claim 2,
The memory device notifies the memory controller when the additional refresh operation is performed.
Memory system.
The method of claim 3,
The memory controller is
When notified of the execution of the additional refresh operation from the memory device, a row determined to require an additional refresh operation is deleted from the replica table.
Memory system.
The method of claim 1,
When it is determined by the determination circuit to perform an active operation on the row to be ejected, the memory controller transmits an active command and an address corresponding to the row to be ejected to the memory.
Memory system.
The method of claim 1,
The table above is
The cold table for storing the row selected as the hammered row as a cold row when the row selected as the hammered row is not one of the cold rows stored in the cold table and the hot rows stored in the hot table ; And
And the hot table for storing the row selected as the hammered row as a hot row when the row selected as the hammered row is one of the cold rows stored in the cold table.
Memory system.
The method of claim 6,
When the row selected as the hammered row is one of the cold rows, the row transferred to the hammered row is deleted from the cold table.
Memory system.
The method of claim 7,
A rank is assigned to the hot rows stored in the hot table,
The lowest rank is given to the hot row newly stored in the hot table,
When the row selected as the hammered row is one of the hot rows, the rank of the row selected as the hammered row is increased.
Memory system.
The method of claim 8,
A rank is assigned to the cold rows stored in the cold table,
The highest rank is given to a cold row newly stored in the cold table.
Memory system.
The method of claim 9,
When a new hot row is stored in the hot table, an existing hot row of the lowest rank is stored as a cold row of the highest rank in the cold table, and a cold row corresponding to the new hot row is deleted from the cold table.
Memory system.
The method of claim 10,
When a new cold row is stored in the cold table, if the cold table is full, the cold row of the lowest rank of the cold table is deleted without the additional refresh operation.
Memory system.
The method of claim 6,
A row adjacent to the active row is selected as the hammered row.
Memory system.
The method of claim 6,
Among the active rows, a row adjacent to the row selected with a certain probability is selected as the hammered row.
Memory system.
Managing, by the memory device, a table storing rows requiring a plurality of additional refresh operations;
Managing, by a memory controller, the same replica table as the table with the same rules as the table;
Selecting, by the memory controller, a row to be removed without the additional refresh operation from the replica table and eviction;
Checking, by the memory controller, an error history of the ejected row;
In response to the memory controller confirming that the error history of the eviction row exists, determining to perform an active operation on the eviction row
A method of operating a memory system comprising a.
The method of claim 14,
Selecting, by the memory controller, another row to be ejected without the additional refresh operation from the replica table and ejecting it;
Checking, by the memory controller, an error history of the ejected another row; And
In response to the memory controller confirming that the error history of the other evited row does not exist, confirming that an active operation for the eviction other row is not required.
The method of operating a memory system further comprising.
The method of claim 14,
Notifying the memory controller when the memory device performs the additional refresh operation; And
Deleting, by the memory controller, a row determined to require the additional refresh operation from the replica table in response to the notification
The method of operating a memory system further comprising.

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