KR20220082730A - Memory system - Google Patents

Abstract

The memory system includes: a normal area for storing normal data; a secure area for storage of secure data; a first row hammer detection circuit for sampling and counting a portion of rows that are active in the normal region to select first rows that need to be refreshed; and a second row hammer detection circuit for selecting second rows requiring refresh by counting all of the rows activated in the security area.

Description

memory system {MEMORY SYSTEM}

This patent document relates to a memory system.

As the density of the memory increases, the spacing between a plurality of word lines included in the memory is decreasing. As the spacing between word lines decreases, a coupling effect between adjacent word lines increases.

Meanwhile, whenever data is input/output to/from the memory cell, the word line toggles between an active (active) state and an inactive state. There is a phenomenon in which data in the memory cell connected to the is damaged. This phenomenon is called row hammering, and data in the memory cell is damaged before the memory cell is refreshed due to word line disturbance, which is a problem.

1 is a diagram for explaining row hammering, and is a diagram illustrating a part of a cell array included in a memory device.

In FIG. 1, 'WLL' corresponds to a word line with a large number of activations, and 'WLL-1' and 'WLL+1' are respectively a word line disposed adjacent to 'WLL', that is, a word line adjacent to the word line having an activation count. corresponds to In addition, 'CL' denotes a memory cell connected to 'WLL', 'CL-1' denotes a memory cell connected to 'WLL-1', and 'CL+1' denotes a memory cell connected to 'WLL+1'. Each memory cell includes cell transistors TL, TL-1, and TL+1 and cell capacitors CAPL, CAPL-1, and CAPL+1.

In FIG. 1, when 'WLL' is activated or deactivated, the voltages of 'WLL-1' and 'WLL+1' increase due to a coupling phenomenon occurring between 'WLL' and 'WLL-1' and 'WLL+1'. It also affects the amount of charge in the cell capacitors CL-1 and CL+1 as it goes down. Therefore, when the activation of 'WLL' occurs frequently and the 'WLL' toggles between the active state and the inactive state, the cell capacitors (CAPL-1, CAPL+1) included in 'CL-1' and 'CL+1' A change in the amount of stored charge may increase and data in the memory cell may deteriorate.

In addition, electromagnetic waves generated while a word line toggles an active state and an inactive state causes electrons to flow into or outflow electrons from the cell capacitor of a memory cell connected to an adjacent word line, thereby damaging data.

As a method for solving row hammering, a method of finding a row (word line) that has been activated several times and refreshing adjacent rows of a row that has been activated multiple times is mainly used.

According to the embodiments of the present invention, it is possible to increase the defense capability of the memory system against the row hammering attack.

A memory system according to an embodiment of the present invention includes a normal area for storing normal data; a secure area for storage of secure data; a first row hammer detection circuit for sampling and counting a portion of rows that are active in the normal region to select first rows that need to be refreshed; and a second row hammer detection circuit for selecting second rows requiring refresh by counting all of the rows activated in the security area.

A memory system according to another embodiment of the present invention includes: a memory including a normal area for storing normal data and a security area for storing secure data; and an error correction code storage area for storing an error correction code corresponding to the security data and an error correction circuit for correcting an error of data read from the security area using the error correction code stored in the error correction code storage area It can include hosts.

A memory system according to another embodiment of the present invention includes a normal area for storing normal data; a secure area for storage of secure data; It may include a cache memory and allow access to the normal area bypassing the cache memory, but may not allow access to the security area bypassing the cache memory.

A memory system according to another embodiment of the present invention includes a normal area for storing normal data; a secure area for storage of secure data; a first row hammer detection circuit for sampling and counting a portion of rows that are active in the normal region to select first rows that need to be refreshed; a second row hammer detection circuit for selecting second rows that need refresh by counting all of the rows that are active in the security area; a cache memory storing an error correction code corresponding to the security data; and an error correction circuit configured to correct an error of data read from the secure area using an error correction code stored in the cache memory.

According to the embodiments of the present invention, it is possible to increase the defense capability of the memory system against the row hammering attack.

1 is a view for explaining row hammering;
2 is a block diagram of a memory system 200 according to an embodiment of the present invention.
FIG. 3 is a configuration diagram of the memory 250 of FIG. 2 according to an embodiment;
FIG. 4 is a configuration diagram of the memory controller 221 of FIG. 2 according to an embodiment;
5 is a diagram showing an example of a counting result stored in the cache memory 219 of the last level.

Hereinafter, the most preferred embodiment of the present invention will be described with reference to the accompanying drawings in order to describe in detail so that those of ordinary skill in the art to which the present invention pertains can easily implement the technical idea of the present invention. In describing the present invention, well-known components that are not related to the gist of the present invention may be omitted. In adding reference numbers to the components of each drawing, it should be noted that only the same components are given the same number as possible even though they are indicated on different drawings.

2 is a block diagram of a memory system 200 according to an embodiment of the present invention.

Referring to FIG. 2 , the memory system 200 may include a processor 210 and a memory 250 .

The processor 210 may include a processor core 211 , a cache controller 213 , various levels of cache memories 215 , 217 , 219 , and a memory controller 221 . Components inside the processor 210 may communicate via a memory bus 223 . The processor 210 may be an entity that processes data or signals. Examples of the processor 210 include a microprocessor, a central processing unit (CPU), a graphic processing unit (GPU), an application processor (AP), and a digital signal processor (DSP, Digital Signal). Processor) and the like.

The processor core 211 may include circuits that process instructions of the computing system. The processor core 211 may be single or multi-core. The processor core 211 may use various levels of cache memories 215 , 217 , and 219 to access data in the memory 250 .

The cache memories 215 , 217 , and 219 may be divided into several levels. The lower the level, the faster the operation speed may be, but the capacity may be small. The cache controller 213 manages the cache memories 215 , 217 , and 219 and determines from which cache memory among the cache memories 215 , 217 , and 219 to obtain data required by the processor core 211 or the memory ( 250) can be controlled. The processor core 211 preferentially obtains necessary data from the cache memories 215 , 217 , and 219 , and when data necessary for the cache memories 215 , 217 , and 219 is not cached, through the memory controller 221 . It can be obtained from memory 250 .

The memory controller 221 may control the memory 250 . The processor 210 may access the memory 250 through the memory controller 221 . That is, the processor 210 may write data to the memory 250 and read data stored in the memory 250 through the memory controller 221 . The memory controller 221 may transmit a command and an address CA to the memory 250 to control an operation of the memory 250 , and may transmit/receive data DATA to and from the memory 250 .

Here, although the memory controller 221 is illustrated as being included in the processor 210 , the memory controller 221 may exist outside the processor 210 . A device including the memory controller 221 in the memory system 200 is generally referred to as a host. Accordingly, in FIG. 2 , the processor 210 may be a host.

The memory 250 may perform an operation indicated by the memory controller 221 . The memory 250 may be one of random access memories such as dynamic random access memory (DRAM), static RAM (SRAM), phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. It may also be another type of memory that requires operation. For example, memories in which data is likely to be lost due to a row hammering attack may be the memory 250 .

3 is a configuration diagram of the memory 250 of FIG. 2 according to an embodiment.

Referring to FIG. 3 , the memory 250 may include a control circuit 310 , a first row hammer detection circuit 320 , and a cell array 330 .

The control circuit 310 may control the overall operation of the memory 250 . The control circuit 310 performs operations indicated by a command and an address CA, for example, an active operation, a precharge operation, a read operation, a write operation, and a refresh operation. refresh) operation, it is possible to control the internal components of the memory 250 so that the memory can perform.

The cell array 330 may include a plurality of memory cells arranged in a plurality of rows and a plurality of columns. The cell array 330 may include a normal area 331 and a security area 333 . The normal area 331 may be an area for storing general data, and the security area 333 may be an area for storing security-important data. Since the normal area 331 and the security area 333 are distinguished for applying different policies, they may be distinguished by an address. For example, if the number of rows in the cell array is N+1, rows 0 to K may be the normal area 331 , and rows K+1 to N may be the security area 333 . Since the security area 333 is an area for storing only a part of data for which security is important, the size of the security area 333 may be much smaller than the size of the normal area 331 . For example, the size of the normal area 331 may be several tens to several thousand times the size of the security area 333 .

The first row hammer detection circuit 320 may select rows requiring refresh by sampling and counting a portion of rows that are active in the cell array 330 . In detail, there may be innumerable rows that are active in the cell array 330 , and the first row hammer sensing circuit 320 randomly samples some of the numerous rows that are active in the cell array 330 , By counting rows, excessively active rows can be identified. In addition, adjacent rows of overactive rows, that is, rows with a risk of data loss due to a row hammering attack, may be classified as rows requiring refresh.

It is difficult for the first row hammer sensing circuit 320 to count all of the active rows in the cell array 330 without counting all of the rows active in the cell array 330, but to sample and count only some rows. This is because the burden in terms of area and current consumption is too great for the implementation of . Rows classified as rows requiring refresh by the first row hammer detection circuit 320 are preferentially or additionally refreshed during a normal refresh operation, or a command (eg, refresh management (RFM) ) may be refreshed upon application of the command).

In the cell array 330 , rows with a risk of data loss due to a row hammering attack in the secure area 333 are classified as rows requiring refresh by the second row hammer detection circuit 407 of the memory controller 221 . can be Therefore, the first row hammer detection circuit 320 excludes the security region 333 from management and samples and counts a portion of rows that are active only in the normal region 231 , and may select rows requiring refresh. have.

4 is a configuration diagram of the memory controller 221 of FIG. 2 according to an embodiment.

Referring to FIG. 4 , the memory controller 221 includes a host interface 401 , a scheduler 403 , a command generator 405 , a second row hammer detection circuit 407 , an error correction circuit 409 , and a memory interface 411 . ) may be included.

The host interface 401 may be for an interface between the memory controller 221 and the remaining components of the processor 210 . The memory controller 221 may be connected to the memory bus 223 by the host interface 401 .

The scheduler 403 may schedule an operation of the memory 250 . The scheduler 403 may determine the order of the requests to be indicated to the memory 250 among the requests transmitted through the memory bus 223 . The scheduler 403 may change the order in which requests are received through the memory bus 223 and the order of operations to be directed to the memory 250 in order to improve performance. For example, even if the read operation of the memory 250 is requested first and the write operation is requested later through the memory bus 223, the operation order may be adjusted so that the write operation of the memory 250 is performed before the read operation. have.

The command generator 405 may generate a command to be applied to the memory 250 according to the order of operations determined by the scheduler 403 .

The memory interface 411 may be for an interface between the memory controller 221 and the memory 250 . A command and an address CA may be transmitted from the memory controller 221 to the memory 250 through the memory interface 411 , and data DATA may be transmitted/received. The memory interface 411 is also referred to as a PHY interface.

The second row hammer detection circuit 407 counts all of the rows activated in the security area 333 of the memory 250 and selects rows requiring refresh. The second row hammer detection circuit 407 may detect excessively active rows by counting the active number of all rows activated in the security area. In addition, adjacent rows of overactive rows, that is, rows with a risk of data loss due to a row hammering attack, may be classified as rows requiring refresh. Since the active operation of the memory 250 is performed according to the instruction of the memory controller 221 , the second row hammer detection circuit 407 of the memory controller 221 detects which row in the security area 333 of the memory 250 . You can see if it's active. For the rows classified as rows requiring refresh by the second row hammer detection circuit 407 , the memory controller 221 sends an active operation to the memory 250 (data loss can also be prevented by the active operation) Alternatively, a refresh operation may be instructed, and thus, loss of data of rows requiring refresh may be prevented.

Since the second row hammer detection circuit 407 counts the number of active times of all rows of the security area 333 in a full counting manner, there may be a lot of burden in operation, but since the size of the security area 333 is relatively small, Such an operation may be possible. The second row hammer detection circuit 407 requires a storage circuit for counting, and one of the cache memories 215 , 217 , and 219 of the processor 210 may be used as a storage circuit for storing the counting result. . Since the cache memory 219 of the last level among the cache memories 215 , 217 , and 219 has the largest capacity, the second row hammer detection circuit 407 uses the cache memory 219 as a storage circuit. It may be desirable to Of course, a storage circuit for storing the counting result may be provided in the second row hammer detection circuit 407 . 5 illustrates an example of a counting result stored in the cache memory 219 of the last level. Referring to FIG. 5 , it can be seen that the number of active times is counted for every row of the security area 333 .

The error correction circuit 409 may be a circuit for error correction of the security area 333 . The error correction circuit 409 generates an error correction code for correcting an error in write data during a write operation of the secure area 333 , and applies the error correction code to the cache memories 215 , 217 , and 219 . ) can be stored in one of the It may be desirable to store the error correction code in the cache memory 219 of the last level among the cache memories 215 , 217 , and 219 . The error correction circuit 409 may correct an error in data read from the security region 333 using an error correction code stored in the cache memory 219 during a read operation of the security region 333 . That is, the error correction circuit 409 stores an error correction code for error correction of data stored in the security area 333 during a write operation in the cache memory 219 , and stores it in the cache memory 219 during a read operation. An error in data read from the secure area can be corrected using the stored error correction code.

The memory system 200 can protect the security data stored in the security area 333 by differentiating the normal area 331 and the security area 333 in the following three aspects.

1. Counting of active rows

Rows activated in the normal region 331 are counted by the first row hammer detection circuit 320 in a random counting manner. Since not all of the active rows are counted, but only some rows are randomly selected and counted, this counting method tends to be less reliable. That is, in the normal region 331 , the reliability in the method of selecting the row attacked by the row hammering attack cannot be 100%.

On the other hand, the rows activated in the security area 333 are counted in a full-counting manner by the second row hammer detection circuit 407 . That is, since all rows active in the security area 333 are counted, a row attacked by the row hammering attack can be selected with almost 100% reliability. Accordingly, data stored in the security area 333 may be more protected than data stored in the normal area 331 .

2. Error correction method

The error correction circuit 409 performs an error correction operation only on data stored in the security area 333 . Accordingly, data stored in the security area 333 may be more protected than data stored in the normal area 331 . An additional error correction circuit may be further provided in the memory system 200 in addition to the error correction circuit 409 , but the error correction circuit protects both the data of the security region 333 and the normal region 331 , and thus the security region There is no change in the fact that the data of 333 is more protected than the data of the normal area 331 .

3. Access method

Memory 250 is generally accessed via cache memories 215 , 217 , and 219 . That is, the processor core 211 does not directly access the memory 250 to obtain data, and data is transferred from the memory 250 to the cache memories 215 , 217 , and 219 , and the processor core 211 caches the cache. The memories 215, 217, and 219 are accessed to obtain data. However, when the processor core 211 needs to directly access the memory 250 due to a cache flush situation or other circumstances, the processor core 211 directly accesses the memory 250 . can be accessed

Indirect access to memory 250 and direct access to memory 250 through these cache memories 215, 217, 219 may be controlled by a cache controller 213, which Direct access of the processor core 211 to the normal region 331 of the 250 may be allowed, but direct access by the processor core 211 to the secure region 333 of the memory 250 may be prohibited.

If direct access of the processor core 211 to the memory 250 is allowed, an attack by hackers may be easier, where the cache controller 213 has the processor core 211 over the secure area 333 . ), since direct access is prohibited, an attack on the security area 333 may be difficult. That is, data in the security area 333 may be protected.

Although the technical idea of the present invention has been specifically described according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of explanation and not for limitation thereof. In addition, an expert in the technical field of the present invention will know that various embodiments are possible within the scope of the technical idea of the present invention.

200: memory system
210: processor 250: memory
211: processor core 213: cache controller
215, 217, 219: cache memories
221: memory controller

Claims (17)

a normal area for storing normal data;
a secure area for storage of secure data;
a first row hammer detection circuit for selecting first rows requiring refresh by sampling and counting a portion of rows that are active in the normal region; and
A second row hammer detection circuit that counts all rows that are active in the security area and selects second rows that need refresh
A memory system comprising a.
The method of claim 1,
the memory system
Further including different levels of cache memories,
and the second row hammer detection circuit stores a counting result of rows activated in the security area in one of the cache memories of the different levels.
memory system.
3. The method of claim 2,
The cache memory used by the second row hammer detection circuit is a last-level cache memory among the cache memories of the different levels.
memory system.
3. The method of claim 2,
the normal region, the security region, and the first low hammer detection circuit are included in a memory;
The second row hammer detection circuit is included in the memory controller for controlling the memory.
memory system.
5. The method of claim 4,
The different levels of cache memories are included in the processor including the memory controller.
memory system.
a memory including a normal area for storing normal data and a security area for storing secure data; and
a host comprising: an error correction code storage region for storing an error correction code corresponding to the security data; and an error correction circuit for correcting an error in data read from the security region using the error correction code stored in the error correction code storage region;
A memory system comprising a.
7. The method of claim 6,
the host is a processor;
The processor further includes different levels of cache memories,
The error correction code storage area is included in one of the cache memories of the different levels.
memory system.
8. The method of claim 7,
The error correction circuit is
included in the memory controller of the processor
memory system.
8. The method of claim 7,
The error correction code storage area is included in a last-level cache memory among the different-level cache memories.
memory system.
a normal area for storing normal data;
a secure area for storage of secure data;
including cache memory;
Access to the normal area bypassing the cache memory is permitted, but access to the security area bypassing the cache memory is not permitted.
memory system.
11. The method of claim 10,
The normal area and the security area are included in a memory,
The cache memory is included in the processor.
memory system.
a normal area for storing normal data;
a secure area for storage of secure data;
a first row hammer detection circuit for selecting first rows requiring refresh by sampling and counting a portion of rows that are active in the normal region;
a second row hammer detection circuit for selecting second rows that need refresh by counting all of the rows that are active in the security area;
a cache memory storing an error correction code corresponding to the security data; and
An error correction circuit for correcting an error in data read from the secure area using an error correction code stored in the cache memory
A memory system comprising a.
13. The method of claim 12,
the normal region, the security region, and the first row hammer detection circuit are included in a memory;
The cache memory is included in the processor;
The second row hammer detection circuit is included in the memory controller of the processor.
memory system.
14. The method of claim 13,
Access to the normal area bypassing the cache memory is permitted, but access to the security area bypassing the cache memory is not permitted.
memory system.
14. The method of claim 13,
and the second row hammer detection circuit stores a counting result of rows activated in the security area in the cache memory.
memory system.
14. The method of claim 13,
the processor is
A processor core that processes the instructions and accesses the memory through the cache memory.
memory system.
17. The method of claim 16,
the memory controller
a host interface for communication with a host;
a scheduler for scheduling operations of the memory;
a command generator for generating a command to be applied to the memory; and
Further comprising a memory interface for communication with the memory
memory system.

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