KR20210017085A - Display device - Google Patents

Abstract

According to the present invention, a display device includes: a display panel including a plurality of pixels; a gate driving circuit for supplying a scan signal to a gate line connected to the pixels of each horizontal line of the display panel; a data driving circuit which converts pixel data into data voltages based on gamma reference voltages and supplies different gamma reference voltages to three or more consecutive channels including a plurality of channels for supplying the data voltages to a plurality of pixels; and a gamma reference voltage generating unit generating the gamma reference voltage. The present invention provides the display device for compensating for the difference in characteristics between channels of a driver IC.

Description

Display device {DISPLAY DEVICE}

This specification relates to a display device, and more particularly, to a display device that compensates a data voltage by reflecting a drop in a driving voltage.

Flat panel displays include a liquid crystal display (LCD), an electroluminescence display, a field emission display (FED), and a quantum dot display panel (QD). . Electroluminescent display devices are classified into inorganic light emitting display devices and organic light emitting display devices according to the material of the emission layer. The pixels of the organic light emitting diode display include organic light emitting diodes (OLEDs), which are self-luminous devices, to emit light to display an image.

The driving circuit of the flat panel display includes a data driving circuit that converts digital data corresponding to an input image into a data voltage for driving a pixel to supply data lines, and a scan signal (or gate signal) synchronized with the data voltage to the gate lines. And a gate driving circuit that outputs to. The data driving circuit converts digital data into a data voltage using a digital to analog converter (DAC). The DAC converts digital data into a gamma voltage and outputs a data voltage.

A data voltage and a scan gate signal are supplied to the pixels, and a pixel driving power supply for driving the pixels is supplied. For example, in pixels of an organic light emitting diode, pixel driving power such as an upper limit pixel driving voltage (Vdd) and a low potential power supply voltage (Vss) are common through a power line so that current flows through the OLED, which is a light emitting element. Is supplied.

However, since the voltage drop of the driving voltage in the power line is different according to the position of the pixel in the display panel, different pixel driving voltages may be actually supplied to the pixels. Accordingly, even if the data voltage of the same size is supplied to the pixel, the luminance of light emitted by the OLED varies according to the position of the pixel, so that an input image to be reproduced with the same luminance may be expressed differently according to the pixel position.

In addition, it is important to maintain uniformity in the process of forming a light emitting layer by depositing an organic material on a display panel or forming a driving element that drives a light emitting element on the display panel, but variations (in-plane deviations) for each position of the display panel It is difficult to avoid what happens. When an in-plane deviation occurs between the driving characteristic and the light emitting characteristic in the display panel, the light emitting element does not emit light with the same luminance even when the same pixel driving voltage and the same data voltage are applied to the pixels.

The embodiments disclosed in this specification take this situation into account, and the purpose of this specification is to enable pixels to emit light corresponding to input data regardless of position.

Another object of this specification is to provide a display device that compensates for difference in characteristics between channels of a driver IC.

Another object of this specification is to provide a configuration that three-dimensionally compensates for in-plane deviations in a display panel in a horizontal direction and a vertical direction.

A display device according to an exemplary embodiment includes: a display panel including a plurality of pixels; A gate driving circuit that supplies a scan signal to a gate line connected to pixels of each horizontal line of the display panel; A data driving circuit including a plurality of channels for converting pixel data into a data voltage based on a gamma reference voltage and supplying it to a plurality of pixels, and supplying different gamma reference voltages to three or more consecutive channels; And a gamma reference voltage generator that generates a gamma reference voltage.

In the display device according to an exemplary embodiment, the gamma reference voltage generator further includes first and second gamma reference voltage generators for generating first and second gamma reference voltage sets each comprising first to kth gamma reference voltages. The data driving circuit includes first to k-th gamma reference voltages and first to n-th gamma reference voltages included in the first gamma reference voltage set, in which an output terminal is disposed on a first channel side among successive first to n-th channels. The first to kth gamma reference voltages included in the second gamma reference voltage set, wherein the output terminal is disposed on the n-th channel side of the channels, respectively, include first to k-th conductors for connecting the corresponding gamma reference voltages to each other, , Each of the first to nth channels may receive a gamma reference voltage by connecting to the first to kth conductors at corresponding positions.

When the gamma reference voltage is supplied to a plurality of DACs in the driver IC, the difference between the driver ICs or the in-plane variation of the display panel can be compensated by gradually differently supplying the gamma reference voltage for each DAC in an analog manner.

In addition, by changing the gamma reference voltage in real time while performing the scan operation, it is possible to minimize luminance fluctuation due to a drop in the pixel driving voltage.

In addition, it is possible to emit light with the same luminance for the same data input regardless of the position of the pixel, thereby enabling predictable and normal image display.

In addition, by changing the analog gamma compensation voltage to correct the in-plane deviation inside the panel, it is possible to improve the uniformity of image display without loss of digital input data.

1 illustrates an organic light emitting display device as a functional block,
2 shows a specific configuration of the data driver,
3 shows a gamma reference voltage generator,
4 shows an example of a pixel circuit,
5 shows signals related to driving the pixel circuit of FIG. 4,
6 is a diagram illustrating a path of a power line supplied from a host system to a display panel for a mobile terminal,
7 conceptually illustrates an embodiment in which the gamma compensation voltage is supplied differently in the X direction,
8 shows a configuration in which a gamma reference voltage is continuously and gradually changed and supplied to DACs in a driver IC.
9 shows an example in which a different gamma reference voltage is gradually applied to each channel,
FIG. 10 shows an example in which a gamma compensation voltage is applied to each channel inside one driver IC in a parabolic form of a quadratic equation,
11 illustrates an example in which a gamma compensation voltage is applied in a complex form to each channel across a plurality of driver ICs,
12 shows an example of changing the gamma reference voltage while performing a scan,
13 shows a configuration for generating a lower/upper gamma reference voltage supplied to a gamma reference voltage generator by reflecting a pixel driving voltage that changes while scanning is performed,
14 is a diagram illustrating a specific circuit implementing FIG. 13.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals throughout the specification mean substantially the same constituent elements. In the following description, when it is determined that a detailed description of a well-known function or configuration related to the content of this specification may unnecessarily obscure or obstruct understanding of the content, the detailed description thereof will be omitted.

In a display device, the pixel circuit and the gate driving circuit may include at least one of an N-channel transistor (NMOS) and a P-channel transistor (PMOS). The transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit from the transistor. In the transistor, the flow of carriers flows from the source to the drain. In the case of the N-channel transistor, since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In the N-channel transistor, the direction of current flows from the drain to the source. In the case of a P-channel transistor, since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. Since holes flow from the source to the drain in the P-channel transistor, current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may be changed according to the applied voltage. Therefore, the invention is not limited due to the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

A scan signal (or gate signal) applied to the pixels swings between a gate on voltage and a gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage, while it is turned off in response to the gate-off voltage. In the case of an N-channel transistor, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of a P-channel transistor, the gate-on voltage may be the gate low voltage VGL, and the gate-off voltage may be the gate high voltage VGH.

Each of the pixels of the organic light-emitting display device includes an OLED, which is a light-emitting element, and a driving element for driving the OLED by supplying a current to the OLED according to a gate-source voltage (Vgs). The OLED includes an anode, a cathode, and an organic compound layer formed between the electrodes. The organic compound layer is a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer, EIL) and the like may be included, but are not limited thereto. When current flows through the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emission layer (EML) to form excitons, and as a result, the emission layer (EML) can emit visible light. have.

The driving element may be implemented as a transistor such as a metal oxide semiconductor field effect transistor (MOSFET). The driving element must have uniform electrical characteristics between pixels, but there may be differences between pixels due to process variations and variations in device characteristics, and may change with the passage of display driving time. In order to compensate for the electric characteristic deviation of the driving element, an internal compensation method and/or an external compensation method may be applied to the organic light emitting display device.

The internal compensation method compensates the pixel data voltage by the electrical characteristics of the pixels within the pixel by sampling electrical characteristics between pixels in each of the pixels (subpixels) in real time. The electrical characteristics of the pixel include a threshold voltage or mobility of a driving element.

The external compensation method senses the current or voltage of a pixel that changes according to the electrical characteristics of the pixel in real time, and modulates the pixel data (digital data) of the input image in an external circuit based on the electrical characteristics sensed for each pixel. Compensate for changes or deviations in electrical characteristics.

The contents disclosed in this specification may be applied to an organic light emitting diode display to which an internal compensation method and/or an external compensation method is applied. In the following embodiments, a pixel circuit to which an internal compensation method is applied is exemplified, but is not limited thereto. Compared to the internal compensation method, the external compensation method can reduce the number of transistors and pixel power supplies required in the pixel circuit.

1 illustrates an organic light emitting display device as a block. The display device of FIG. 1 includes a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, a power supply unit 16, and two or more gamma reference voltage generation units 17. can do.

6 is a representation of a display device for a mobile terminal based on an implementation shape. The display device includes a display panel 10, a flexible printed circuit (FPC) 20, and a drive integrated circuit (IC) 30. It may be configured to include, the drive IC 30 may be mounted on the FPC (20).

The timing controller 11, the data driving circuit 12, the gate driving circuit 13, the power supply unit 16, and the gamma reference voltage generation unit 17 of FIG. 1 are all or part of the drive IC 30 of FIG. Can be integrated.

On the screen AA on which the input image is displayed on the display panel 10, a plurality of data lines 14 are arranged in a column direction (or vertical direction) and a row direction (or horizontal direction) A plurality of gate lines 15 cross each other, and pixels PXL are arranged in a matrix form for each crossing region to form a pixel array. The gate line 15 supplies a first gate line 15_1 for supplying a scan signal for applying a data voltage supplied to the data line 14 to a pixel, and a light emitting signal for emitting a pixel to which the data voltage is written. A second gate line 15_2 may be included.

The display panel 100 includes a first power line 101 for supplying a pixel driving voltage (or a high potential power voltage) Vdd to the pixels PXL, and a low potential power voltage Vss to the pixels PXL. A second power line 102 for supplying to ), an initialization voltage line 103 for supplying an initialization voltage Vini for initializing the pixel circuit, and the like may be further included. The first and second power lines 101 and 102 and the initialization voltage line 103 are connected to the power supply unit 16. The second power line 102 may be formed in the form of a transparent electrode covering a plurality of pixels PXL.

Touch sensors may be disposed on the pixel array of the display panel 10. The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors are on-cell type or add-on type, and are arranged on the screen AA of the display panel PXL or are embedded in a pixel array. It can be implemented with sensors.

In the pixel array, a pixel PXL arranged on the same horizontal line is one of the data lines 14 and one of the gate lines 15 (or any one of the first gate lines 15_1 and the second One of the gate lines 15_2) is connected to form a pixel line. The pixel PXL is electrically connected to the data line 14 in response to a scan signal and a light emission signal applied through the gate line 15, receives a data voltage, and emits an OLED with a current corresponding to the data voltage. The pixels PXL arranged on the same pixel line operate simultaneously according to the scan signal and the emission signal applied from the same gate line 15.

One pixel unit may be composed of three subpixels including a red subpixel, a green subpixel, and a blue subpixel or four subpixels including a red subpixel, a green subpixel, a blue subpixel, and a white subpixel. , Not limited to that. Each subpixel may be implemented as a pixel circuit including an internal compensation circuit. Hereinafter, a pixel means a subpixel.

The pixel PXL receives a pixel driving voltage Vdd, an initialization voltage Vini, and a low potential power voltage Vss from the power supply unit 16, and may include a driving transistor, an OLED, and an internal compensation circuit. The compensation circuit may include a plurality of switch transistors and one or more capacitors as shown in FIG. 4 to be described below.

The timing controller 11 supplies image data RGB transmitted from an external host system (not shown) to the data driving circuit 12. The timing controller 11 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a dot clock (DCLK) from the host system, and the data driving circuit 12 and the Control signals for controlling the operation timing of the gate driving circuit 13 are generated. The control signals include a gate control signal GCS for controlling an operation timing of the gate driving circuit 13 and a data control signal DCS for controlling an operation timing of the data driving circuit 12.

The data driving circuit 12 converts digital video data RGB input from the timing controller 11 into an analog data voltage based on the data control signal DCS, and converts the data voltage to the data line 14. It is supplied to the pixels PXL. The data voltage may be a value corresponding to a gray scale to be expressed by a pixel. The data driving circuit 12 may be composed of a plurality of driver ICs.

The gate driving circuit 13 generates a scan signal and a light emission signal based on the gate control signal GCS, but generates the scan signal and the light emission signal in a row-sequential manner in the active period, and the gate line 15 connected to each pixel line It is provided sequentially. The scan signal and the emission signal of the gate line 15 are synchronized with the supply of the data voltage of the data line 14. The scan signal and the emission signal swing between the gate-on voltage VGL and the gate-off voltage VGH. The gate-on voltage VGL and the gate-off voltage VGH may be set as VGH = 8V and VGL = -7V, but are not limited thereto.

The gate driving circuit 13 may be composed of a plurality of gate drive integrated circuits each including a shift register, a level shifter and an output buffer for converting an output signal of the shift register into a swing width suitable for driving a TFT of a pixel. have. Alternatively, the gate driving circuit 13 may be directly formed on the lower substrate of the display panel 10 in a GIP (Gate Drive IC in Panel) method. In the case of the GIP method, the level shifter may be mounted on a printed circuit board (PCB), and the shift register may be formed on a lower substrate of the display panel 10.

The power supply unit 16 uses a DC-DC converter to adjust the DC input voltage provided from the host to provide a gate-on voltage required for the operation of the data driving circuit 12 and the gate driving circuit 13. (VGL). A gate-off voltage (VGH) or the like is generated, and a pixel driving voltage (Vdd), an initialization voltage (Vini), and a low-potential power supply voltage (Vss) required for driving the pixel array are generated.

The power supply unit 16 receives a measured value or an estimated value of the pixel driving voltage Vdd supplied to the PXL at the corresponding location while driving the pixel, and based on this, the lower/upper gamma input voltage Vgam_l/Vgam_h May be generated and provided to the gamma reference voltage generator 17.

Also, the power supply unit 16 may generate two or more sets of lower/upper gamma input voltages Vgam_l/Vgam_h and provide them to other gamma reference voltage generators 17_1 and 17_2.

The gamma reference voltage generator 17 generates gamma reference voltages GMA1 to GMA8 in a range determined by the lower/upper gamma input voltages (Vgam_l/Vgam_h), so the lower/upper gamma input voltages (Vgam_l/Vgam_h) are based on gamma. The voltage generation range, that is, the upper and lower limits of the gamma reference voltage can be determined.

Two or more gamma reference voltage generators 17 are provided, and at least one of them generates different gamma reference voltages based on different lower/upper gamma input voltages (Vgam_l/Vgam_h) to output data voltages. Different gamma compensation voltages can be applied for each channel.

The host system may be an application processor (AP) in mobile devices, wearable devices, and virtual/augmented reality devices. Alternatively, the host system may be a main board such as a television system, a set-top box, a navigation system, a personal computer, and a home theater system, but is not limited thereto.

2 shows a specific configuration of a data driving circuit.

Referring to FIG. 2, the data driving circuit 12 includes a shift register 121, a first latch 122, a second latch 123, a level shifter 124, a DAC 125, and It includes a buffer 126.

The shift register 121 shifts the clock input from the timing controller 11 and sequentially outputs the clock for sampling. The first latch 122 samples and latches the pixel data RGB of the input image at a sampling clock timing sequentially input from the shift register 121, and simultaneously outputs the sampled pixel data RGB. The second latch 123 simultaneously outputs the pixel data RGB input from the first latch 122.

The level shifter 124 shifts the voltage of the pixel data RGB input from the second latch 123 into the input voltage range of the DAC 125. The DAC 125 converts the pixel data RGB from the level shifter 124 into a data voltage based on the gamma compensation voltage and outputs the converted data voltage. The data voltage output from the DAC 125 is supplied to the data line 14 through the buffer 126.

3 shows a gamma reference voltage generator.

Although the gamma reference voltage generator 17 of FIG. 3 is shown to output eight gamma reference voltages GMA1 to GMA8, the number of gamma reference voltages output by the gamma reference voltage generator is not limited thereto.

3, the gamma reference voltage generator 17 includes a first divider RS1, first to third divider circuits GC1, GC2, and GC3, and includes the highest gamma reference voltage (hereinafter, 1 gamma reference voltage) GMA1 and second to eighth gamma reference voltages GMA2 to GMA8 are generated.

The first divider circuit GC1 generates a first gamma reference voltage GMA1 based on the voltage distributed by the first divider RS1. To this end, the first divider circuit GC1 includes a first multiplexer MUX1 and a first buffer BUF1.

The first divider RS1 may be formed of a plurality of resistors connected in series between the input terminal of the upper gamma reference voltage Vgam_h and the input terminal of the lower gamma reference voltage Vgam_l (GND). The first multiplexer MUX1 receives the voltage distributed from the first divider RS1 and outputs a voltage selected according to the highest gamma register value REG1. The first buffer BUF1 prevents current flow from reversing and allows the first gamma reference voltage GMA1 to be smoothly transmitted.

The second divider circuit GC2 distributes the upper limit gamma reference voltage Vgam_h to generate second to eighth gamma reference voltages GMA2 to GMA8. The second voltage divider circuit GC2 includes second to eighth voltage dividers RS2 to RS8, second to eighth multiplexers MUX2 to MUX8, and second to eighth buffers BUF2 to BUF8.

The second to seventh dividing units RS2 to RS7 respectively receive an upper limit gamma reference voltage Vgam_h and a later gamma reference voltage, and distribute the upper limit gamma reference voltage Vgam_h. The eighth divider RS8 receives the upper limit gamma reference voltage Vgam_h and the lower limit gamma reference voltage Vgam_l, and distributes the upper limit gamma reference voltage Vgam_h. Each of the second to eighth voltage dividers RS2 to RS8 may be formed of a variable resistor.

Each of the eighth to eighth multiplexers MUX2 to MUX8 uses a gamma reference voltage among voltages distributed by the second to eighth dividers RS2 to RS8 according to preset gamma register values REG2 to REG8. Select by The second to seventh dividing units RS2 to RS7 receive the upper gamma reference voltage Vgam_h and the gamma reference voltage of the rear end and distribute the upper gamma reference voltage Vgam_h, and the eighth dividing unit RS8 is the upper gamma reference voltage. The reference voltage Vgam_h and the lower limit gamma reference voltage Vgam_l are received and the upper limit gamma reference voltage Vgam_h is distributed. The second to eighth buffers BUF2 to BUF8 prevent reverse current flow and allow the second to eighth gamma reference voltages GMA2 to GMA8 to be smoothly output.

Specifically, the second divider RS2 receives the upper limit gamma reference voltage Vgam_h and the third gamma reference voltage GMA3, and distributes the upper limit gamma reference voltage Vgam_h. The second multiplexer MUX2 selects one of the voltages distributed by the second voltage divider RS2 according to the second gamma register value REG2, and applies the selected voltage to the second gamma through the second buffer BUF2. Output as the reference voltage (GMA2).

The third divider RS3 receives the upper limit gamma reference voltage Vgam_h and the fourth gamma reference voltage GMA4 and distributes the upper limit gamma reference voltage Vgam_h. The third multiplexer MUX3 selects any one of voltages distributed by the third divider RS3 according to the third gamma register value REG3, and applies the selected voltage to the third gamma through the third buffer BUF3. Output as the reference voltage (GMA3).

The fourth divider RS4 receives the upper limit gamma reference voltage Vgam_h and the fifth gamma reference voltage GMA5, and distributes the upper limit gamma reference voltage Vgam_h. The fourth multiplexer MUX4 selects any one of voltages distributed by the fourth divider RS4 according to the fourth gamma register value REG4, and applies the selected voltage to the fourth gamma through the fourth buffer BUF4. Output as compensation voltage (GMA4).

The fifth divider RS5 receives the upper limit gamma reference voltage Vgam_h and the sixth gamma reference voltage GMA6 and distributes the upper limit gamma reference voltage Vgam_h. The fifth multiplexer MUX5 selects any one of voltages distributed by the fifth divider RS5 according to the fifth gamma register value REG5, and applies the selected voltage to the fifth gamma through the fifth buffer BUF5. Output as the reference voltage (GMA5).

The sixth divider RS6 receives the upper limit gamma reference voltage Vgam_h and the seventh gamma reference voltage GMA7 and distributes the upper limit gamma reference voltage Vgam_h. The sixth multiplexer MUX6 selects any one of voltages distributed by the sixth voltage divider RS6 according to the sixth gamma register value REG6, and applies the selected voltage to the sixth gamma through the sixth buffer BUF6. Output as the reference voltage (GMA6).

The seventh dividing unit RS7 receives the upper limit gamma reference voltage Vgam_h and the eighth gamma reference voltage GMA8 and distributes the upper limit gamma reference voltage Vgam_h. The seventh multiplexer MUX7 selects any one of voltages distributed by the seventh voltage divider RS7 according to the seventh gamma register value REG7, and applies the selected voltage to the seventh gamma through the seventh buffer BUF7. Output as voltage (GMA7).

The eighth divider RS8 receives the upper limit gamma reference voltage Vgam_h and the lower limit gamma reference voltage Vgam_l and distributes the upper limit gamma reference voltage Vgam_h. The eighth multiplexer MUX8 selects any one of voltages distributed by the eighth divider RS8 according to the eighth gamma register value REG8, and applies the selected voltage to the eighth gamma through the eighth buffer BUF8. Output as the reference voltage (GMA8).

The third voltage divider circuit GC3 includes first to seventh resistors R1 to R7, and the first to seventh resistors are taps tap1 to outputting the second to eighth gamma reference voltages GMA2 to GMA8. It is placed between tap8). For example, the first resistor R1 is disposed between the first and second tabs tap1 and tap2, and the seventh resistor R7 is disposed between the seventh and eighth tabs tap8. do. The third divider circuit GC3 maintains the voltage levels of the second to eighth gamma reference voltages GMA2 to GMA8 output through the taps tap1 to tap7 stably.

The data driving circuit 12 includes a DAC 125 that converts pixel data RGB of an input image into an analog data voltage Vdata, as shown in FIG. 2. In order to convert the pixel data RGB into different analog data voltages Vdata of V0 to V255, 255 gamma compensation voltages are required. To this end, a predetermined number of gamma reference voltages output by the gamma reference voltage generator 17 between the gamma reference voltage generator 17 and the DAC 125 are converted into 255 gamma compensation voltages. A compensation voltage generator may be added.

Alternatively, the DAC 125, in order to convert 8-bit pixel data (RGB) into different analog data voltages (Vdata) of V0 to V255, instead of receiving all 256 gamma compensation voltages, a predetermined number, for example, For example, only 4 or 8 gamma reference voltages may be input, and 256 different data voltages may be generated from pixel data using this.

When the timing controller 11, the data driving circuit 12, the gate driving circuit 13, the power supply unit 16, and the gamma reference voltage generation unit 17 are integrated into one drive IC, the gamma reference voltage generation unit 17 ) And the gamma compensation voltage generator in front of the DAC 125 may be integrated into one block to generate a gamma compensation voltage.

The gamma compensation voltage for generating the data voltage may be implemented as a positive gamma or a negative gamma according to a pixel circuit structure. For example, when a light-emitting element of a pixel, for example, a driving transistor driving an OLED is implemented as a P-channel MOSFET and a data voltage is applied to the gate electrode of the transistor, a gamma compensation voltage is generated with an inverse gamma, resulting in pixel data The higher the gray scale of (RGB), the lower the gamma compensation voltage. The driving transistor that drives the light emitting elements of the pixels is implemented as an N-channel MOSFET, and when a data voltage is applied to the gate of the transistor, a gamma compensation voltage is generated with positive gamma, and the gamma compensation voltage increases as the gray level of the pixel data (RGB) increases. It becomes higher.

4 shows an example of a pixel circuit, and FIG. 5 shows signals related to driving in the pixel circuit of FIG. 4. The pixel circuit of FIG. 4 is only an example, and the pixel circuit to which the embodiment of this specification is applied is not limited to FIG. 4.

The pixel circuit of FIG. 4 is an internal compensation circuit composed of a light emitting element (OLED), a driving element (DT) supplying current to the light emitting element (OLED), a plurality of switch transistors (T1 to T6), and a storage capacitor (Cst). Including, the gate voltage of the driving element DT may be compensated by the threshold voltage Vth of the driving element DT by sampling the threshold voltage Vth of the driving element DT. Each of the driving element DT and the switch transistors T1 to T6 may be implemented as a P-channel transistor, but is not limited thereto.

The pixel circuit of FIG. 4 is for pixels disposed on an n-th horizontal line (or pixel line). The operation of the pixel circuit of Fig. 4 is largely divided into an initialization period (t1), a sampling period (t3), a data writing period (t4), and a light emission period (t5).

In the initialization period t1, the (n-1)th scan signal SCAN(n-1) for supplying the data voltage to the pixels of the (n-1)-th horizontal line is applied as the gate-on voltage VGL Thus, the fifth and sixth switch transistors T5 and T6 are turned on, thereby initializing the pixel circuit. After the initialization period t1, before the n-th scan signal SCAN(n) for controlling the supply of data to the current horizontal line is applied as the gate-on voltage VGL, the (n-1)th scan signal SCAN(n- The hold period t2 in which 1)) changes from the gate-on voltage VGL to the gate-off voltage VGH is arranged, but the hold period t2 corresponding to the second period may be omitted.

In the sampling period t3, the n-th scan signal SCAN(n) for controlling the supply of data to the current horizontal line is applied as the gate-on voltage VGL so that the first and second switch transistors T1 and T2 are When turned on, the threshold voltage of the driving element (or driving transistor) DT is sampled and stored in the storage capacitor Cst.

In the data writing period t4, the n-th scan signal SCAN(n) is applied as the gate-off voltage VGH to turn off the first and second switch transistors T1 and T2, and the remaining switch transistors T3 All of to T6) are also turned off, and the voltage of the gate electrode of the driving transistor DT increases due to the current flowing through the driving transistor DT.

In the light-emitting period t5, the n-th light-emitting signal EM(n) is applied as a gate-on voltage VGL, and the third and fourth switch transistors T3 and T4 are turned on, and the light-emitting element OLED is turned on. Glow.

In order to accurately express the low gradation luminance by the duty ratio of the emission signal EM(n), the emission signal EM(n) is applied to the gate-on voltage VGL and the gate during the emission period t5. The third and fourth switch transistors T3 and T4 may be repeatedly turned on/off by swinging at a predetermined duty ratio between the off voltages VGH.

The anode electrode of the light emitting device OLED is connected to the fourth node n4 between the fourth and sixth switch transistors T4 and T6. The fourth node n4 is connected to the anode electrode of the light emitting device OLED, the second electrode of the fourth switch transistor T4, and the second electrode of the sixth switch transistor T6. The cathode electrode of the light-emitting element OLED is connected to the second power line 102 to which the low-potential power voltage Vss is applied. The light emitting element OLED emits light with a current flowing according to the gate-source voltage Vgs of the driving element DT. The current flow of the light emitting device OLED is switched by the third and fourth switch transistors T3 and T4.

The storage capacitor Cst is connected between the first power line 101 and the second node n2. The data voltage Vdata compensated by the threshold voltage Vth of the driving element DT is charged in the storage capacitor Cst. Since the data voltage Vdata in each of the pixels is compensated by the threshold voltage Vth of the driving element DT, variation in characteristics of the driving element DT may be compensated for in the pixels.

The first switch transistor T1 is turned on in response to the gate-on voltage VGL of the n-th scan signal SCAN(n) to connect the second node n2 and the third node n3. The second node n2 is connected to the gate electrode of the driving element DT, the first electrode of the storage capacitor Cst, and the first electrode of the first switch transistor T1. The third node n3 is connected to the second electrode of the driving element DT, the second electrode of the first switch transistor T1, and the first electrode of the fourth switch transistor T4. The gate electrode of the first switch transistor T1 is connected to the first gate line 15_1 to receive the n-th scan signal SCAN(n). The first electrode of the first switch transistor T1 is connected to the second node n2, and the second electrode of the first switch transistor T1 is connected to the third node n3.

The second switch transistor T2 is turned on in response to the gate-on voltage VGL of the n-th scan signal SCAN(n) to supply the data voltage Vdata to the first node n1. The gate electrode of the second switch transistor T2 is connected to the first gate line 31 to receive the n-th scan signal SCAN(n). The first electrode of the second switch transistor T2 is connected to the data line DL to which the data voltage Vdata is applied. The second electrode of the second switch transistor T2 is connected to the first node n1. The first node n1 is connected to the second electrode of the second switch transistor T2, the second electrode of the third switch transistor T3, and the first electrode of the driving element DT.

The third switch transistor T3 is turned on in response to the gate-on voltage VGL of the emission signal EM(n) to connect the first power line 101 to the first node n1. The gate electrode of the third switch transistor T3 is connected to the second gate line 15_2 to receive the emission signal EM(n). The first electrode of the third switch transistor T3 is connected to the first power line 101. The second electrode of the third switch transistor T3 is connected to the first node n1.

The fourth switch transistor T4 is turned on in response to the gate-on voltage VGL of the light emitting signal EM(n), and connects the third node n3 to the anode electrode of the light emitting device OLED. The gate electrode of the fourth switch transistor T4 is connected to the second gate line 15_2 to receive the emission signal EM(n). The first electrode of the fourth switch transistor T4 is connected to the third node n3, and the second electrode is connected to the fourth node n4.

The light emitting signal EM(n) controls the on/off of the third and fourth switch transistors T3 and T4 to switch the current flow of the light emitting element OLED. Controls the lighting and lighting time.

The fifth switch transistor T5 is turned on in response to the gate-on voltage VGL of the (n-1)th scan signal SCAN(n-1) to set the second node n2 to an initialization voltage line 103 ). The gate electrode of the fifth switch transistor T5 is connected to the first gate line 15_1 that supplies a scan signal that controls the supply of a data voltage to the pixels of the (n-1)-th horizontal line, 1) Receive scan signal (SCAN(n-1)). The first electrode of the fifth switch transistor T5 is connected to the second node n2 and the second electrode is connected to the initialization voltage line 103.

The sixth switch transistor T6 is turned on in response to the gate-on voltage VGL of the (n-1)th scan signal SCAN(n-1), thereby connecting the initialization voltage line 103 to the fourth node n4. ). The gate electrode of the sixth switch transistor T6 is connected to the first gate line 15_1 with respect to the (n-1)th horizontal line to receive the (n-1)th scan signal SCAN(n-1). . The first electrode of the sixth switch transistor T6 is connected to the initialization voltage line 103 and the second electrode is connected to the fourth node n4.

The driving element DT drives the light emitting element OLED by controlling the current flowing through the light emitting element OLED according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

During the initialization period t1, the (n-1)th scan signal SCAN(n-1) is input as the gate-on voltage VGL. The n-th scan signal SCAN(n) and the emission signal EM(n) maintain the gate-off voltage VGH during the initialization period t1. Accordingly, during the initialization period t1, the fifth and sixth switch transistors T5 and T6 are turned on, so that the second and fourth nodes n2 and n4 are initialized to the initialization voltage Vini. A hold period t2 may be set between the initialization period t1 and the sampling period t3. In the hold period t2, the (n-1)th scan signal SCAN(n-1) is changed from the gate-on voltage VGL to the gate-off voltage VGH, and the n-th scan signal SCAN(n)) And the light emission signal EM(n) maintain the previous state.

During the sampling period t3, the n-th scan signal SCAN(n) is input as the gate-on voltage VGL. The pulse of the nth scan signal SCAN(n) is synchronized with the data voltage Vdata to be supplied to the nth pixel line. The (n-1)th scan signal SCAN(n-1) and the emission signal EM(n) maintain the gate-off voltage VGH during the sampling period t3. Accordingly, the first and second switch transistors T1 and T2 are turned on during the sampling period t3.

During the sampling period t3, the voltage of the gate terminal of the driving element DT, that is, the second node n2 is increased by the current flowing through the first and second switch transistors T1 and T2. When the driving element DT is turned off, the voltage Vn2 of the second node n2 is (Vdata-|Vth|). At this time, the voltage of the first node n1 is also (Vdata-|Vth|). In the sampling period t3, the gate-source voltage Vgs of the driving element DT is |Vgs|=Vdata-(Vdata-|Vth|)=|Vth|.

During the data writing period t4, the n-th scan signal SCAN(n) is inverted to the gate-off voltage VGH. The (n-1)th scan signal SCAN(n-1) and the emission signal EM(n) maintain the gate-off voltage VGH during the data write period t4. Accordingly, all the switch transistors T1 to T6 are maintained in the off state during the data writing period t4.

During the light emission period t5, the light emission signal EM(n) continuously maintains the gate-on voltage VGL or is turned on/off at a predetermined duty ratio and swings between the gate-on voltage VGL and the gate-off voltage VGH. can do. During the light emission period t5, the (n-1)th and nth scan signals SCAN(n-1) and SCAN(n) maintain the gate-off voltage VGH. During the emission period t5, the third and fourth switch transistors T3 and T4 may repeatedly turn on/off according to the voltage of the emission signal EM. When the light-emitting signal EM(n) is the gate-on voltage VGL, the third and fourth switch transistors T3 and T4 are turned on, so that a current flows through the light-emitting element OLED. At this time, the gate-source voltage Vgs of the driving element DT is |Vgs|=Vdd-(Vdata-|Vth|), and the current flowing through the light emitting element OLED is K(Vdd-Vdata) ² . K is a proportional constant determined by charge mobility, parasitic capacitance, channel capacity, and the like of the driving element DT.

The luminance of light emitted by the light-emitting device (OLED) is proportional to the current flowing through the light-emitting device, and the pixel driving voltage (Vdd) supplied through the first power line 101 changes depending on the load or the pattern of the input image, but the input When the data voltage Vdata is maintained unchanged, the luminance emitted from the light emitting device OLED varies according to the pixel driving voltage Vdd for the same data voltage Vdata.

6 is a diagram illustrating a path of a power line supplied from a host system to a display panel for a mobile terminal.

The pixel driving voltage (Vdd) directly supplied from the host system or the pixel driving voltage (Vdd) generated by the power supply 16 included in the drive IC 30 using the input power supplied from the host system is applied to the FPC 20. It is supplied to the display panel 10 through the formed power wiring 21. The first power line 101 formed in a mesh shape on the display panel 10 is connected to the power line 21 of the FPC 20 to supply the pixel driving voltage Vdd to the pixel PXL.

In the pixel driving voltage Vdd supplied to the display panel 10, a voltage drop (IR Drop) occurs according to the load of the display panel 10, and the voltage drop amount varies according to a load variation of the display panel 10. The load of the display panel 10 is determined by resistance (R) and capacity (Capacitance, C), and additionally, the pattern of the input image, that is, the luminance of the screen AA determined by the input data (for example, It can be changed by the average picture level (APL).

When the APL of the input image is high, the current consumed by the pixels PXL included in the display panel 10 increases, so the voltage drop of the pixel driving voltage Vdd increases, and when the APL of the input image is low, the display panel ( As the current consumed by 10) decreases, the amount of voltage drop of the pixel driving voltage Vdd decreases.

In order to compensate for the voltage drop of the pixel driving voltage Vdd according to the load of the display panel, the pixel driving voltage Vdd is measured at a specific point of the display panel 10, mainly at a point where the pixel driving voltage Vdd is applied. , Based on this, the data voltage can be varied.

In addition, in order to compensate for the voltage drop of the pixel driving voltage Vdd due to the pattern of the input image, the pixel driving voltage Vdd is increased as the light emission operation of each pixel line proceeds from the top to the bottom of the display panel 10. , The accumulated current value (or APL) up to the currently driven pixel line may be calculated, and a gain for raising the pixel driving voltage Vdd may be adjusted based on this. To compensate for the voltage drop of the pixel driving voltage Vdd, these two compensation algorithms can be used together.

7 conceptually illustrates an embodiment in which gamma compensation voltages are supplied differently in the X direction.

If an in-plane deviation occurs in the driving characteristic and the light emitting characteristic in the display panel, the luminance varies from position to position even when the same data voltage is supplied to the pixel. The in-plane deviation existing in the vertical direction (or Y direction) in which the data line travels may be compensated by changing the gamma compensation voltage over time as the scan operation proceeds.

However, since the channels in the same driver IC use the same gamma compensation voltage when converting pixel data, the in-plane deviation of the display panel existing in the horizontal direction (or X direction) in which the gate line travels is affected by the change of the gamma compensation voltage. It is difficult to compensate. Instead, the in-plane deviation can be compensated by changing the input digital pixel data, but in this case, one of the high gradation data or the low gradation data may be saturated and the gradation resolution may decrease.

In addition, even if the channels included in the driver IC convert the same pixel data into a data voltage by applying the same gamma compensation voltage and output it, the data voltages output for each channel are different depending on the characteristics of each channel (mainly, the DAC characteristics of the corresponding channel). can be different. Even in this case, digital pixel data input to each channel can be changed to compensate for characteristics according to the corresponding channel, but saturation may also occur in low or high gradations.

In consideration of this situation, in FIG. 7, the gamma compensation voltage is gradually supplied in the X direction at different values to compensate for the deviation in the X direction, that is, the in-plane deviation of the display panel and the output characteristic deviation between channels. For example, when the digital pixel data is 127 (Digital 127), a gamma compensation voltage of 2V is applied for data conversion in the leftmost channel and a gamma compensation voltage of 3V is applied for data conversion in the middle channel. A gamma compensation voltage of 4V is applied to the data conversion of.

In addition, a gamma compensation voltage that changes continuously and gradually is applied to the channels between the three channels listed above. For example, a gamma compensation voltage of 2.5V is applied to data conversion in the channel in the middle of the leftmost channel and the middle channel. And a gamma compensation voltage of 3.5V can be applied for data conversion in the middle channel and the channel in the middle of the rightmost channel.

8 shows a configuration in which the gamma reference voltage is continuously and gradually changed and supplied to DACs in the driver IC.

As described with reference to FIG. 2, the gamma reference voltage provided by the gamma reference voltage generator 17 is provided to the DAC 125, and the DAC 125 converts digital pixel data to an analog data voltage based on this. Convert.

In one driver IC, a plurality of channels are provided, and each channel has a DAC 125, in which a gamma reference voltage is supplied from one gamma reference voltage generator 17 (or a gamma compensation voltage is supplied from one gamma compensation voltage generator. ) If provided in common to a plurality of DACs 125, when the same data voltage is applied, each DAC 125 converts the same data voltage and outputs it to the corresponding channel, so that the in-plane deviation can be compensated in an analog manner with X echo. Can't.

In FIG. 8, the first and second gamma reference voltage generators 17_1 and 17_2 at both ends of the plurality of DACs 125 constituting the driver IC have different gamma reference voltages, that is, the first gamma reference voltage set GMA1 ~GMAk) and the second gamma reference voltage set (GMA1'~GMAk') are output, but the corresponding gamma reference voltages are connected to each other through conductors S1~Sk having resistance components.

8, the first and second gamma reference voltage generators 17_1 and 17_2 are located at both ends of the continuous channels CH1 to CH5 (outside the first channel CH1 and outside the fifth channel CH5). Although shown as being disposed, the first and second gamma reference voltage generators 17_1 and 17_2 are disposed outside the driver IC or separately from the data driving circuit 12 on the power supply unit 16, and are not limited thereto. Output terminals connected to the 1/second gamma reference voltage generators 17_1 and 17_2 and outputting k gamma reference voltages may be disposed at both ends of the channels.

Assuming that the internal resistance of each conductor is uniformly distributed, for example, the i-th conductor Si is the i-th gamma reference voltage GMAi supplied by the first gamma reference voltage generator 17_1 on the left and the right The ith gamma reference voltage GMAi' supplied by the second gamma reference voltage generator 17_2 of is uniformly distributed, and the gamma reference voltage continues from GMAi to GMAi' while progressing along the X direction from left to right. It changes gradually.

Each DAC 125 is connected to each of the conductive lines S1 to Sk at a corresponding position to receive a gamma reference voltage. The leftmost DAC (DAC1 in FIG. 8) converts pixel data into a data voltage by applying the gamma reference voltage of the first gamma reference voltage set (GMA1 to GMAk) provided by the first gamma reference voltage generator 17_1. And, the rightmost DAC (DAC5 in FIG. 8) applies the gamma reference voltage of the second gamma reference voltage set GMA1' to GMAk' provided by the second gamma reference voltage generator 17_2 to generate pixel data. Convert to data voltage.

On the other hand, the DAC in the middle (DAC3 in FIG. 8) is the first gamma reference voltage set GMA1 to GMAk provided by the first gamma reference voltage generator 17_1 and the second gamma reference voltage generator 17_2. Pixel data is converted into a data voltage based on an intermediate value of the second gamma reference voltage set GMA1' to GMAk'. In FIG. 8, DAC2 applies an intermediate value of a gamma reference voltage set used by DAC1 and DAC3, and DAC4 applies an intermediate value of a gamma reference voltage set used by DAC3 and DAC5.

That is, each DAC is a first gamma reference voltage generator based on the ratio of the first distance from the position where the corresponding channel is placed to the position where the leftmost channel is placed and the second distance from the position where the corresponding channel is placed to the position where the rightmost channel is placed. The gamma reference voltage of the first gamma reference voltage set (GMA1 to GMAk) provided by (17_1) and the second gamma reference voltage set (GMA1' to GMAk') provided by the second gamma reference voltage generation unit 17_2 is internally divided. The pixel data is converted into a data voltage using the obtained gamma reference voltage.

The driver IC is responsible for the first and second gamma reference voltage sets (GMA1 to GMAk/GMA1' to GMAk') provided by the first and second gamma reference voltage generators 17_1 and 17_2 on both sides of the driver IC. The value may be determined by reflecting the in-plane deviation in the area of the display panel (a region in which pixels connected to a data line supplying a data voltage of the corresponding driver IC are arranged) and taking into account characteristics of each channel of the corresponding driver IC.

The characteristics of each channel of the driver IC may not have a certain tendency, but the in-plane variation of the display panel may have some directionality in relation to a process of depositing a light emitting material or a process of forming a driving transistor. Accordingly, by providing different gamma reference voltages from both sides of the driver IC and connecting them to supply the gradually changing gamma reference voltage to the DAC of each channel, the deviation in the X direction can be compensated.

If there is a tendency in each channel characteristic of the driver IC, this can be reflected additionally to prepare a pair of gamma reference voltage sets supplied from both sides of the driver IC. Alternatively, the driver IC may have characteristics in the form of offsets from other driver ICs. For example, when the same reference voltage is applied to the same pixel data, the data voltage output from each channel of the first driver IC is It may be higher or lower than the data voltage output by each channel. In this case, a different gamma reference voltage of two sets of gamma reference voltages may be provided for each driver IC by reflecting these characteristics.

These X-direction in-plane deviation characteristics, channel characteristics of driver ICs, or deviation characteristics between driver ICs are measured in advance at the time of product shipment, stored in a memory, and used when generating a gamma reference voltage.

FIG. 9 shows an example in which different gamma reference voltages are gradually applied to each channel. For convenience of explanation, a case in which four gamma reference voltage sets are configured, such as GMA1 to GMA4, will be described.

On the left, each of the gamma reference voltages GMA1 to GMA4 is supplied at 4V, 3V, 2V, and 1V, and on the right, each of the gamma reference voltages GMA1' to GMA4' is supplied at 4.2V, 3.2V, 2.2V, 1.2V, and the left Each of the corresponding gamma reference voltages (GMA1 to GMA4/GMA1' to GMA4') on the right and to the right is connected through conductors (S1 to S4) to supply different gamma reference voltages to each channel, so the gamma reference voltage proceeds through the channel. It changes linearly while doing.

For example, the first gamma reference voltage GMA1 corresponding to the white gray scale (eg, pixel data 255) is provided as 4.0V to the leftmost channel 1 (CH1), and the rightmost channel 5 (CH5). 4.2V is provided, and 4.05V, 4.10V, and 4.15V are provided to channels 2 to 4 (CH2 to CH4), respectively, with 4.0V and 4.2V divided at regular intervals.

Meanwhile, in FIG. 8, so that the first gamma reference voltage generator 17_1 and the second gamma reference voltage generator 17_2 can output different gamma reference voltage sets, the power supply unit 16 is Two voltage pairs may be differently generated and provided to the first gamma reference voltage generator 17_1 and the second gamma reference voltage generator 17_2.

In FIG. 8, the power supply unit 16 supplies a first lower/upper gamma reference voltage pair (Vgma_l1(y)/Vgma_h1(y)) to the first gamma reference voltage generator 17_1, and generates a second gamma reference voltage. A second lower/upper gamma reference voltage pair Vgma_l2(y)/Vgma_h2(y) may be supplied to the unit 17_2.

Here, y means that the value changes in the Y direction, that is, the direction in which the data line proceeds or the direction in which the scan operation proceeds, and will be described in detail with reference to FIGS. 12 to 14 below.

The first lower/upper gamma reference voltage pair and the second lower/upper gamma reference voltage pair are generated not only by reflecting the in-plane deviation of the panel area covered by the corresponding driver IC, but also by reflecting the difference in characteristics between the corresponding driver IC and other driver ICs. Can be.

FIG. 10 shows an example in which a gamma compensation voltage is applied to each channel in one driver IC in the form of a quadratic equation, and FIG. 11 is a complex gamma compensation voltage for each channel across a plurality of driver ICs. It shows an example applied.

As shown in FIG. 10, a numerical expression of the deviation characteristic in the X direction inside one driver IC may not have the same shape as a straight line of a linear equation, but may be a parabolic shape of a quadratic equation. In this case, it is not possible to compensate for this parabolic deviation characteristic by supplying different gamma reference voltages only at both sides of the driver IC.

In this case, a gamma reference voltage can be provided at three locations within one driver IC to compensate for a parabolic deviation characteristic. In FIG. 10, the deviation feature is convex upward and has the highest value at the center and similar values at both ends. In this case, a gamma reference voltage having the same first value (AV) is provided to both sides of the driver IC, and a gamma reference having a second value (BV) formed in a range higher than the first value (AV) at the center of the driver IC By providing a voltage and connecting them with a conductive line, the gamma compensation voltage may be formed high in the center portion of the driver IC and the gamma compensation voltage may be formed low in both portions as shown in FIG. 10.

When including the first to n-th channels included in the driver IC, a gamma reference voltage having a first value (AV) is provided on the first channel side and the n-th channel side, which are both ends of the continuous first to n-th channels, and , The gamma reference voltage having the second value BV may be an arbitrary position between the first to nth channels.

11 shows a case where the deviation characteristic in the X direction is gradual in the first and second driver ICs (Driver IC #1, Driver IC #2), and there is no deviation in the X direction in the third driver IC (Driver IC #3) to be.

The numerical expression of the deviation characteristic gradually increases as it progresses from left to right in the first driver IC (Driver IC #1), and gradually decreases as it proceeds from left to right in the second driver IC (Driver IC #2). Accordingly, a gamma reference voltage of the first value AV is provided at the left end of the first driver IC #1 and the right end of the second driver IC #2, and the first driver IC A gamma reference voltage having a second value (BV) higher than the first value (AV) is provided at the right end of #1) and the left end of the second driver IC (Driver IC #2), and the first/second driver IC It is possible to compensate for deviation characteristics in (Driver IC#1, Driver IC#2).

Since there is no deviation in the X direction in the third driver IC #3, a gamma reference voltage having the same first value AV can be provided at both ends of the third driver IC #3. Alternatively, a gamma reference voltage having a first value AV may be provided to the third driver IC (Driver IC#3) only at one end instead of at both ends.

In FIG. 10, three gamma reference voltage generators 17 may be provided in the driver IC, and in FIG. 11, one gamma reference voltage generator 17 is provided for each driver IC, but the first driver IC or the last driver IC One more reference voltage generator 17 may be provided. That is, as shown in FIG. 11, when the gamma reference voltage generator 17 provides the gamma reference voltage to two neighboring driver ICs, at least one of them may be the same.

If only one set of gamma reference voltages is provided for each driver IC, channels within the corresponding driver IC use the same gamma reference voltage. If you provide a different set of gamma reference voltages to the neighboring driver ICs, the two neighboring channels at the boundary of the two driver ICs use different gamma reference voltages.

However, when two different sets of gamma reference voltages are provided to one driver IC, since one driver IC has a large number of channels, at least three or more consecutive channels use different gamma reference voltages to store pixel data. Convert to voltage.

FIG. 12 shows an example of changing the gamma reference voltage while performing a scan. In FIG. 12, a gamma compensation voltage or a gamma compensation voltage is performed while the display operation proceeds in the Y direction from the first horizontal period 1H to the 2880 horizontal period 2880H. The gamma reference voltage is changing.

In addition to the in-plane deviation in the X direction in which the gate line travels, the in-plane deviation in the manufacturing process of the display panel also occurs in the Y direction in which the data line travels, so that even if the same data voltage is written to the pixel, the emission luminance may be different.

In addition, as described with reference to FIG. 6, the voltage drop increases as the power line that supplies the pixel driving voltage Vdd for driving the pixel is further away from the power source depending on the load. Also, as the data scan and light emission proceed in the Y direction, the current consumed by the pixels of the previous horizontal line gradually increases due to the input screen pattern, thereby increasing the voltage drop of the pixel driving voltage. In this case, since the pixel driving voltage supplied to the pixel is different for each location, even if the same data voltage is applied, the light emission luminance may vary.

In order to compensate for the difference in the in-plane deviation characteristic and the amount of drop in the pixel driving voltage from the viewpoint of the Y-direction using an analog method instead of correcting the pixel data, the horizontal synchronization signal is applied while the data writing operation and the light emission operation are performed (as the horizontal period progresses). The gamma compensation (or reference) voltage can be changed synchronously. Whenever the horizontal synchronization signal is generated, the gamma reference voltage may be compensated, or when a predetermined number of horizontal synchronization signals are generated, the gamma reference voltage may be compensated once.

From the point of view of the Y direction, the in-plane deviation characteristic can be detected in advance when the product is shipped, stored in a memory, and compensated by changing the gamma reference voltage based on the value stored in the memory while the display operation proceeds.

In addition, a drop characteristic of the pixel driving voltage Vdd due to a load of the display panel may be detected or calculated in advance according to the position of the pixel, and then stored in a memory for compensation.

Since the in-plane deviation characteristic and the voltage drop characteristic due to the load vary according to the Y direction, the Y value (the panel position, the number of counts of the horizontal synchronization signal, or the progress time after the vertical synchronization signal) can be managed as a variable.

In addition, by analyzing the input image while driving the display, the APL is obtained until the current horizontal period, and based on this, the amount of current applied to drive the pixels up to the current horizontal line and the corresponding drop in the pixel driving voltage are obtained, and the pixel driving voltage The range of the gamma reference voltage can be adjusted so that the data voltage can be lowered according to the amount of drop in.

That is, when performing the display operation along the Y direction, the power supply unit 16 reflects a predetermined in-plane deviation characteristic, a voltage drop characteristic due to its own load, and a voltage drop characteristic due to an input image pattern calculated in real time. The gamma compensation voltage or the gamma reference voltage used to convert the data voltage to be supplied may be adjusted in synchronization with the horizontal synchronization signal.

FIG. 13 is a diagram illustrating a configuration of generating a lower limit/upper limit gamma reference voltage supplied to a gamma reference voltage generator by reflecting a pixel driving voltage that changes while scanning is performed, and FIG. 14 is a diagram illustrating a specific circuit implementing FIG. will be.

The power supply unit 16 is a gamma reference voltage adjusting unit 161 that changes a lower limit gamma reference voltage Vgam_l and an upper gamma reference voltage Vgam_h that define a range of the gamma reference voltage to be generated by the gamma reference voltage generator 17 It may include.

When there is one driver IC, two gamma reference voltage adjustment units 161 and two gamma reference voltage generation units 17 may be provided. In order to correct in-plane deviation of a complex shape as shown in FIG. 10, three or more A gamma reference voltage adjusting unit 161 and a gamma reference voltage generating unit 17 may be provided.

The gamma reference voltage adjusting unit 161 not only adjusts the lower limit/upper limit gamma reference voltage that defines the range of the gamma reference (or compensation) voltage by reflecting the deviation characteristic in the X direction, but also adjusts the Y that changes in real time while simultaneously performing a scan operation. An additional lower/upper gamma reference voltage can be adjusted to compensate for the voltage drop in the direction.

The gamma reference voltage adjusting unit 161 is configured to compensate for a voltage drop occurring in the Y direction, and the pixel driving voltage estimated (or measured) at a plurality of positions in the Y direction of the display panel 10 through a comparator. A lower limit gamma defining the upper and lower limits of the gamma reference voltage based on the comparison of the estimated value (Vdd_e(y)) and the reference value (Vdd_r) of the pixel driving voltage generated by the power supply unit 16 and supplied to the display panel 10 The reference voltage Vgam_l and the upper gamma reference voltage Vgam_h can be adjusted.

Estimation of the pixel driving voltage can be calculated in real time based on the voltage drop caused by the power line's own load and the voltage drop caused by the data input pattern input.The estimated pixel driving voltage (Vdd_e) is the position at which the display is driven (y ) Can be calculated as a variable, and the Y-direction position can be obtained by counting the horizontal synchronization signal. The estimated value Vdd_e of the pixel driving voltage may be calculated for each horizontal synchronization signal or may be calculated only once for a predetermined number of horizontal synchronization signals.

In addition, the gamma reference voltage adjusting unit 161 separately manages the internal lower/upper limit voltages (Vgma_10/Vgma_h0) in order to determine the upper and lower limits of the gamma reference voltage, apart from considering the voltage drop. The internal low/high voltage (Vgma_l0/Vgma_h0) is a value that reflects the in-plane deviation, the channel characteristic deviation of the driver IC, or the characteristic deviation between the driver ICs.The deviation of the channel characteristic of the driver IC and the characteristic deviation between the driver IC is only in the X direction. It changes and is fixed in the Y direction, but the in-plane deviation can vary in the X and Y directions, i.e. at (x, y) positions.

Since two or more sets of gamma reference voltages are supplied to a single driver IC, and the internal low/high voltage (Vgma_l0/Vgma_h0) is used to determine the gamma reference voltage, the internal low/high voltage (Vgma_l0/Vgma_h0) is the driver in the X direction. It is managed by the number corresponding to the number of ICs (refer to the description of FIGS. 10 and 11), and the number to be managed may be changed in the Y direction according to the degree of in-plane deviation in the Y direction. That is, the internal lower and upper limit voltages Vgma_10/Vgma_h0 to be stored in the memory may be stored in the memory as many as the number of times the number in the X direction and the number in the Y direction.

Referring to FIG. 14, the gamma reference voltage adjusting unit 161 compares the pixel driving voltage reference value Vdd_r with the pixel driving voltage estimated value Vdd_e, amplifies and outputs the difference value (drop amount of the pixel driving voltage). Including an amplifier and second and third differential amplifiers that respectively generate an upper gamma reference voltage Vgam_h and a lower gamma reference voltage Vgam_l based on the amplified voltage drop and the internal lower/upper voltage (Vgma_l0/Vgma_h0). Can be configured.

The first differential amplifier receives a pixel driving voltage estimation value Vdd_e(y) estimated in real time in synchronization with a horizontal synchronization signal to an inverting terminal through a resistor R1, and receives the pixel driving voltage reference value Vdd_r as a resistance R1. ) To the non-inverting terminal, connect the inverting terminal and the output terminal through a resistor (R2), and connect the non-inverting terminal to the ground through a resistor (R2).

Therefore, the first differential amplifier amplifies the difference (the amount of voltage drop of the pixel driving voltage) between the pixel driving voltage reference value Vdd_r and the pixel driving voltage estimated value Vdd_e(y) at the ratio R2/R1, so that the output of the first differential amplifier Vo is Vo=R2/R1*(Vdd_e(y)-Vdd_s). If the resistances R1 and R2 are the same and the amplification ratio of the first differential amplifier is 1, the output of the first differential amplifier becomes Vo=Vdd_r-Vdd_e(y).

Estimation of the pixel driving voltage and adjustment of the data voltage using the gamma reference voltage changed based on this may cause a predetermined time difference, so the ratio of the resistors R1 and R2 is adjusted in the first differential amplifier, for example, R2/ It is also possible to compensate for the time interval between estimation of the pixel driving voltage and adjustment of the data voltage by making R1 larger than 1.

The second differential amplifier that outputs the upper limit gamma reference voltage Vgam_h(x, y) receives the output Vo of the first differential amplifier through the resistor R1 to the inverting terminal, and receives the internal upper limit voltage Vgam_h0(x , y)) is input to the non-inverting terminal through the resistor R1, the inverting terminal and the output terminal are connected through the resistor R1, and the non-inverting terminal is connected to the ground through the resistor R1.

Therefore, in the second differential amplifier, the amplification ratio is 1, and the value obtained by subtracting the output Vo of the first differential amplifier from the internal upper limit voltage Vgam_h0(x, y) is the upper limit gamma reference voltage Vgam_h(x, y). ), the upper limit gamma reference voltage becomes Vgam_h(x, y) = Vgam_h0(x, y) + R2/R1*(Vdd_e(y)-Vdd_r).

Similarly, a third differential amplifier that outputs a lower limit gamma reference voltage (Vgam_l(x, y)) receives the output (Vo) of the first differential amplifier through a resistor (R1) to an inverting terminal, and receives an internal lower limit voltage (Vgam_l0). (x, y)) is input to the non-inverting terminal through the resistor R1, the inverting terminal and the output terminal are connected through the resistor R1, and the non-inverting terminal is connected to the ground through the resistor R1.

Therefore, in the third differential amplifier, the amplification ratio is 1, and the value obtained by subtracting the output Vo of the first differential amplifier from the internal lower limit voltage Vgam_l0(x, y) is the lower limit gamma reference voltage Vgam_l(x, y) ), the lower limit gamma reference voltage becomes Vgam_l(x, y) = Vgam_l0(x, y) + R2/R1*(Vdd_e(y)-Vdd_r).

The amplification ratio of the first differential amplifier can be set to 1 or more.For example, if the amplification ratio is set to 1, the upper limit gamma reference voltage Vgam_h = Vgam_h0 + (Vdd_e-Vdd_r), which is the output of the second differential amplifier, becomes The lower limit gamma reference voltage, which is the output of the differential amplifier, becomes Vgam_l = Vgam_l0 + (Vdd_e-Vdd_r).

The lower/upper gamma reference voltage (Vgam_l/Vgam_h) is changed in conjunction with the change in the estimated value (Vdd_e) of the pixel driving voltage, and the estimated value (Vdd_e) of the pixel driving voltage is the reference value (Vdd_r) of the pixel driving voltage output from the power supply unit 16. ), the lower/upper gamma reference voltage (Vgam_l/Vgam_h) is lowered as the estimated value (Vdd_e) of the pixel driving voltage decreases.

The gamma compensation voltage or gamma reference voltage, which is a reference for converting pixel data into a data voltage (Vdata), is determined by the lower/upper gamma reference voltage (Vgam_l/Vgam_h), and the lower/upper gamma reference voltage (Vgam_l/ Since Vgam_h is changed according to the estimated pixel driving voltage Vdd_e, the data voltage Vdata applied to the pixel may be changed in response to the fluctuation of the estimated pixel driving voltage Vdd_e.

When the estimated value (Vdd_e) of the pixel driving voltage is the same as the reference value (Vdd_r) of the pixel driving voltage output from the power supply unit 16, the lower/upper gamma reference voltage (Vgam_l/Vgam_h) is the internal lower/upper voltage (Vgam_l0/Vgam_h0). Keep it as it is. In this case, the data voltage is determined by a gamma compensation voltage formed between the internal upper limit voltage Vgam_h0 and the internal lower limit voltage Vgam_10.

However, when a voltage drop occurs in the pixel driving voltage Vdd and the estimated value (Vdd_s) of the pixel driving voltage is lower than the pixel driving voltage reference value Vdd output from the power supply unit 16 by a drop (Vdd_d), that is, Vdd_r-Vdd_s When =Vdd_d, the lower/upper gamma reference voltage (Vgam_l/Vgam_h) is lower than the internal lower/upper voltage (Vgam_l0/Vgam_h0) by the amount of drop (Vdd_d), and the upper gamma reference voltage (Vgam_h) becomes Vgam_h0-Vdd_d and the lower gamma reference The voltage Vgam_l becomes Vgam_l0-Vdd_d.

In this case, the data voltage is determined by a gamma compensation voltage formed between the upper limit gamma reference voltage Vgam_h and the lower limit gamma reference voltage Vgam_l lowered by the drop amount Vdd_d from the internal lower/upper voltage Vgam_l0/Vgam_h0.

Therefore, even if the same pixel data is applied to pixels of different horizontal lines, when it is estimated that the pixel driving voltage estimation value Vdd_s lowered by the drop amount Vdd_d from the pixel driving voltage reference value Vdd_r is supplied to the pixel, the drop amount Vdd_d The lowered data voltage is applied to the pixel.

In addition, the internal lower/upper limit voltage (Vgam_l0/Vgam_h0) reflects the deviation according to the position (x) in the X direction or the position (y) in the Y direction, and the lower/upper gamma reference voltage (Vgam_l/Vgam_h) is the internal lower limit/ Since the upper limit voltage Vgam_10/Vgam_h0 is reflected as it is, the data voltage can also reflect a deviation according to the position (x) in the X direction or the position (y) in the Y direction.

In the state where the position in the Y direction is fixed, the lower/upper gamma reference of two pairs generated with different values by reflecting the positions of both sides of the driver IC (positions in the X direction) by the gamma reference voltage adjusting unit 161 of FIG. 14 The voltages Vgam_l/Vgam_h are supplied to one and the other of the first and second gamma reference voltage generators 17_1 and 17_2, respectively, and a predetermined number of first and second gamma reference voltage generators 17_1 and 17_2 When a first/second gamma reference voltage set consisting of the gamma reference voltages of is generated and supplied to both sides of the driver IC, the first and second gamma reference voltages are connected to each channel by a conductor connecting each corresponding gamma reference voltage inside the driver IC. The gamma reference voltage may be distributed and supplied.

Accordingly, by distributing the gamma reference voltage in the X direction and continuously supplying a different value for each channel to the DAC, it is possible to compensate for the deviation of the display panel, the channel of the driver IC, or the difference between the driver ICs in the X direction.

In addition, it is possible to emit pixels with the same luminance for the same pixel data by reflecting the deviation in the amount of drop in the pixel driving voltage supplied to the pixel according to the position in the Y direction in the display panel and the in-plane deviation in the Y direction of the display panel. do.

In addition, since pixel data is converted into a data voltage by changing a gamma reference voltage or a gamma compensation voltage, it is possible to compensate for a deviation of a display panel or a voltage drop of a driving voltage without loss of a digital value.

The display device described in the specification may be described as follows.

A display device according to an exemplary embodiment includes: a display panel including a plurality of pixels; A gate driving circuit that supplies a scan signal to a gate line connected to pixels of each horizontal line of the display panel; A data driving circuit including a plurality of channels for converting pixel data into a data voltage based on a gamma reference voltage and supplying it to a plurality of pixels, and supplying different gamma reference voltages to three or more consecutive channels; And a gamma reference voltage generator that generates a gamma reference voltage.

In an embodiment, the gamma reference voltage generator may change the gamma reference voltage in synchronization with the horizontal synchronization signal.

In an embodiment, the gamma reference voltage generator may further include first and second gamma reference voltage generators that respectively generate first and second gamma reference voltage sets composed of first to kth gamma reference voltages. .

In an embodiment, the data driving circuit includes first to kth gamma reference voltages and first to kth gamma reference voltages included in the first gamma reference voltage set, in which the output terminal is disposed on the first channel side among successive first to nth channels. Among the n-th channels, first through k-th conductors connecting the first through k-th gamma reference voltages included in the second gamma reference voltage set to the n-th channel side to each other, respectively. And each of the first to nth channels may be supplied with a gamma reference voltage by connecting to the first to kth conductors at corresponding positions.

In one embodiment, the gamma reference voltage generator further comprises a third gamma reference voltage generator for generating a third gamma reference voltage set consisting of first to kth gamma reference voltages, and included in the third gamma reference voltage set The output terminals of the first through k-th gamma reference voltages are disposed between the i-th channel and the (i+1)-th channel among the first through n-th channels and are respectively connected to the conductors of the corresponding gamma reference voltages, where i is 1 It may be a natural number equal to or greater than 1 and less than n.

In one embodiment, the data driving circuit includes a plurality of driver ICs, and the gamma reference voltage generator provides at least one set of gamma reference voltages to each driver IC, but at least one set of the same gamma reference voltage is provided to two neighboring driver ICs. Can provide.

In an embodiment, the display device includes: a power supply unit supplying a pixel driving voltage to a plurality of pixels through a power line; And a gamma reference voltage adjusting unit configured to adjust a lower limit gamma reference voltage and an upper gamma reference voltage that limit a range of the gamma reference voltage based on a characteristic of the display panel and a voltage drop of the pixel driving voltage, wherein the gamma voltage generator The gamma reference voltage may be generated based on the lower limit gamma reference voltage and the upper limit gamma reference voltage provided by the voltage adjuster.

In one embodiment, the gamma reference voltage adjuster compares a reference value of the pixel driving voltage output from the power supply unit to an estimated value of the pixel driving voltage estimated at a plurality of positions of the display panel in synchronization with the horizontal synchronization signal, and compares the lower limit and the upper limit gamma reference value. The voltage can be adjusted.

In an embodiment, the gamma reference voltage adjusting unit includes a first differential amplifier that outputs a first signal corresponding to a difference between a reference value and an estimated value, and a difference between a predetermined internal lower limit voltage and the first signal by reflecting characteristics of the display panel. A second differential amplifier that outputs a lower limit gamma reference voltage and a third differential amplifier that outputs a difference between a predetermined internal upper limit voltage and the first signal by reflecting characteristics of the display panel as an upper limit gamma reference voltage.

In an embodiment, the internal lower limit voltage and the internal upper limit voltage may be managed in the memory by a number determined by the number of driver ICs included in the data driving circuit and the number of positions for calculating the estimated value.

In an embodiment, the estimated value may be calculated in real time in synchronization with a horizontal synchronization signal based on a voltage drop due to a power line's own load and a voltage drop due to a data input pattern.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14: data line 15: gate line
16: power supply unit 17: gamma reference voltage generation unit

Claims (10)

A display panel including a plurality of pixels;
A gate driving circuit for supplying a scan signal to a gate line connected to pixels of each horizontal line of the display panel;
A data driving circuit including a plurality of channels for converting pixel data into a data voltage based on a gamma reference voltage and supplying the plurality of pixels to the plurality of pixels, and supplying different gamma reference voltages to three or more consecutive channels; And
A display device comprising a gamma reference voltage generator that generates the gamma reference voltage. The method of claim 1,
And the gamma reference voltage generator to change the gamma reference voltage in synchronization with a horizontal synchronization signal. The method of claim 1 or 2,
The gamma reference voltage generator further includes first and second gamma reference voltage generators respectively generating first and second gamma reference voltage sets consisting of first to kth gamma reference voltages,
The data driving circuit includes first to k-th gamma reference voltages included in the first gamma reference voltage set, and the first to n-th gamma reference voltages, in which an output terminal is disposed on a first channel side among successive first to n-th channels. Including first to k-th conducting wires for connecting the first to k-th gamma reference voltages included in the second gamma reference voltage set to each of the corresponding gamma reference voltages, the output terminal disposed on the n-th channel side among the channels and,
Each of the first to nth channels is connected to the first to kth conductors at corresponding positions to receive the gamma reference voltage. The method of claim 3,
The gamma reference voltage generator further includes a third gamma reference voltage generator for generating a third gamma reference voltage set consisting of the first to kth gamma reference voltages,
The output terminals of the first to kth gamma reference voltages included in the third gamma reference voltage set are disposed between the i-th channel and the (i+1)-th channel among the first to n-th channels, respectively, with corresponding gamma reference voltages. A display device, characterized in that it is connected to a voltage conductor, and i is a natural number equal to or greater than 1 and smaller than n. The method of claim 3,
The data driving circuit includes a plurality of driver ICs, and the gamma reference voltage generator provides at least one set of gamma reference voltages to each driver IC, but provides at least one set of the same gamma reference voltage to two neighboring driver ICs. The display device characterized by the above-mentioned. The method of claim 2,
A power supply unit supplying a pixel driving voltage to the plurality of pixels through a power line; And
Further comprising a gamma reference voltage adjusting unit for adjusting a lower limit gamma reference voltage and an upper limit gamma reference voltage for defining a range of the gamma reference voltage based on a characteristic of the display panel and a voltage drop of the pixel driving voltage,
And the gamma voltage generator generates the gamma reference voltage based on a lower limit gamma reference voltage and an upper limit gamma reference voltage provided by the gamma reference voltage adjusting unit. The method of claim 6,
The gamma reference voltage adjuster may compare the estimated values of the pixel driving voltages estimated at a plurality of positions of the display panel with a reference value of the pixel driving voltage output from the power supply in synchronization with the horizontal synchronization signal, and the lower limit and the upper limit A display device, characterized in that the gamma reference voltage is adjusted. The method of claim 7,
The gamma reference voltage adjusting unit may include a first differential amplifier for outputting a first signal corresponding to a difference between the reference value and the estimated value, and a difference between the first signal and an internal lower limit voltage determined in advance by reflecting characteristics of the display panel. A second differential amplifier that outputs a lower limit gamma reference voltage, and a third differential amplifier that outputs a difference between the first signal and an internal upper limit voltage predetermined by reflecting characteristics of the display panel as the upper limit gamma reference voltage. The display device characterized by the above-mentioned. The method of claim 8,
And the internal lower limit voltage and the internal upper limit voltage are managed in a memory by a number determined by the number of driver ICs included in the data driving circuit and the number of positions in which the estimated value is to be calculated. The method of claim 7,
And the estimated value is calculated in real time in synchronization with the horizontal synchronization signal based on a voltage drop due to a load of the power line itself and a voltage drop due to a data input pattern.

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