KR20190059625A - Gamma voltage generater and display device using the same - Google Patents

Abstract

The present invention relates to a gamma voltage generator and a display device using the same. The gamma voltage generator comprises: a luminance control unit generating a reference voltage selected among voltages distributed from a first input voltage; a gamma voltage generating unit generating gamma compensation voltages corresponding to a gradation voltage of pixel data based on voltages distributed from the reference voltage in a first driving mode and generating the gamma compensation voltages based on voltages distributed from a second input voltage in a second driving mode; and a switch circuit blocking the first input voltage inputted to the luminance control unit in the second driving mode and the reference voltage inputted to the gamma voltage generating unit.

Description

TECHNICAL FIELD [0001] The present invention relates to a gamma voltage generating apparatus and a display apparatus using the gamma voltage generating apparatus.

The present invention relates to a gamma voltage generator and a display using the same.

The flat panel display device includes a liquid crystal display (LCD), an electroluminescence display, a field emission display (FED), and a plasma display panel (PDP). The electroluminescent display is divided into an inorganic light emitting display and an organic light emitting display depending on the material of the light emitting layer. The pixels of the OLED display display an image using an OLED (Organic Light Emitting Diode).

The driving circuit of the flat panel display device includes a data driver for converting digital data of an input video signal into a data voltage for driving a pixel to drive data lines and a scan driver for outputting a scan signal synchronized with a data voltage to scan lines . The data driver converts the digital data into a data voltage using a digital-to-analog converter (DAC). The DAC converts the digital data into the gamma voltage from the gamma voltage generator and outputs the data voltage.

The flat panel display can be operated in a low luminance mode according to the user's selection or according to the illuminance of the surrounding environment. Various methods have been tried to reduce the power consumption in the low brightness mode, but there has been a limit in reducing the power consumption.

The present invention provides a gamma voltage generator capable of minimizing power consumption in a low luminance mode and a display using the same.

A gamma voltage generator according to the present invention includes a luminance controller for generating a reference voltage selected from voltages distributed from a first input voltage, a voltage controller for generating a reference voltage corresponding to a gradation voltage of pixel data based on voltages distributed from the reference voltage in a first driving mode A gamma voltage generator for generating gamma compensation voltages based on the voltages divided from the second input voltage in the second drive mode and a gamma correction voltage generator for generating the gamma compensation voltages based on the voltages distributed from the second input voltage in the second drive mode, 1 input voltage, and a switch circuit for interrupting the reference voltage input to the gamma voltage generator.

The gamma voltage generating apparatus of the present invention includes a data driver for converting pixel data of an input image to gamma compensation voltages to generate a data voltage and outputting the data voltage to the data lines.

The present invention generates gamma compensation voltages by driving only the minimum circuit in the gamma voltage generator in a state in which the entire circuit of the luminance controller and some circuits of the gamma voltage generator are not driven in the low luminance mode. As a result, the present invention can minimize the power consumption of the gamma voltage generator in the low brightness mode.

1 is a view showing a reference voltage selected in a normal mode and a low brightness mode.
FIG. 2 is a view showing gamma voltage and gradation expression ranges in the normal mode and the low luminance mode. FIG.
3 is a block diagram briefly showing a gamma voltage generator according to an embodiment of the present invention.
4 is a circuit diagram showing the luminance controller shown in FIG. 3 in detail.
5A and 5B are circuit diagrams illustrating the gamma voltage generator shown in FIG. 4 in detail.
6A to 6C are circuit diagrams showing the operation of the gamma voltage generator according to the first embodiment of the present invention.
7A to 7C are circuit diagrams illustrating the operation of the gamma voltage generator according to the second embodiment of the present invention.
8 is a block diagram showing an example of a display device according to an embodiment of the present invention.
9 is a diagram showing an example of the AoD screen.
10 is a circuit diagram showing an example of a pixel circuit.
11 is a waveform diagram showing a driving signal of the pixel circuit shown in FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art. To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the description of the embodiments, the first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or wholly and technically various interlocking and driving are possible and that the embodiments may be practiced independently of each other, It is possible.

The display device of the present invention can be driven with brightness desired by the user. The present invention minimizes power consumption by driving only the minimum circuit in the gamma voltage generating circuit when the user selects a dark screen.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following embodiments, the display device of the present invention will be described mainly with reference to an organic light emitting display, but is not limited thereto. The display device of the present invention is applicable to any display device requiring a gamma voltage generator.

In the display device of the present invention, a normal mode in which data is displayed at a high luminance and a low luminance mode in which data is displayed at a low luminance are set. The user can select the low brightness mode through the user interface. The low luminance mode includes a low brightness mode in which the maximum brightness of the screen is lower than the normal mode, such as Always On Display (AoD) mode, Idle Mode, Low Power Mode, and Sleep In Mode.

The low brightness mode can control the maximum brightness of pixels in the entire screen to a low value or control some pixels defined in the partial mode to a predetermined brightness. The partial mode is a driving mode in which only a part of pixels in the pixel array of the display panel 100 is driven and the remaining pixels are kept in an off state. In the always on mode and the virtual reality mode (VR), the screen can be driven in the partial mode.

In the normal mode, the first reference voltage BC_VREF1 is selected as shown in Fig. The first reference voltage BC_VREF1 may be set to a voltage for expressing a high luminance. The first reference voltage BC_VREF1 increases the gamma voltages GMA1 to GMA9 as shown in FIG. 2 in the normal mode. In the normal mode, since the voltage difference between the lowest gamma voltage GM9 and the highest gamma voltage GMA1 increases, the gradation expression range GR1 is wide.

In the low luminance mode, the second reference voltage BC_VREF2 is selected as shown in Fig. The second reference voltage BC_VREF2 may be set to a relatively low voltage. The second reference voltage BC_VREF2 lowers the gamma voltages GMA1 to GMA9 as shown in Fig. 2 in the low luminance mode. In the low luminance mode, the voltage difference between the lowermost gamma voltage GM9 and the highest gamma voltage GMA1 becomes small, so that the gradation expression range GR2 becomes narrow.

3 is a block diagram briefly showing a gamma voltage generator according to an embodiment of the present invention.

Referring to FIG. 3, the gamma voltage generator of the present invention includes a luminance controller 10 for generating a reference voltage VREF and a gamma voltage generator 20 for outputting gamma voltages GMA1 to GMA9.

The luminance controller 10 receives the first high potential input voltage VH1 and the first low potential input voltage VL1 in the normal mode in the normal mode and divides the first high potential input voltage VH1 to generate the reference voltage VREF ). In the normal mode, the reference voltage VREF output from the luminance controller 10 is supplied to the gamma voltage generator 20. The input voltage VH1 of the luminance controller 10 is cut off in the low luminance mode. Therefore, in the low luminance mode, the luminance controller 10 does not operate and does not generate power consumption.

The gamma voltage generator 20 generates the gamma reference voltages GMA1 to GMA9 by dividing the reference voltage VREF from the luminance controller 10 in the normal mode by using the voltage dividing circuit and the voltage selecting circuit, Divides the voltages GMA1 to GMA9 and outputs the gamma compensation voltage of the entire gradation of the pixel data. The gamma voltage generator 20 does not generate the reference voltage VREF because the luminance controller 10 does not operate in the low luminance mode. The gamma voltage generator 20 receives the separate input voltages VH2 and VL2 in the low luminance mode. In the low luminance mode, the gamma voltage generator 20 divides the second high potential input voltage VH2 to generate the gamma voltages GMA1 to GMA9. The second high potential input voltage VH2 may be set to a voltage lower than the first high potential input voltage VH1. The second low potential input voltage VL2 may be set to the same voltage as the first low potential input voltage VL1. The low potential input voltages VL1 and VL2 can be set to the base low voltage (GND).

The gamma voltage generator 20 divides the reference voltage VREF through the voltage divider circuit as shown in FIGS. 5A and 5B, and generates a gamma reference voltage (hereinafter, referred to as " gamma reference voltage ") including the highest gamma reference voltage and the lowest gamma reference voltage A first circuit portion 51 for selecting one of the plurality of reference voltages GMA1, GMA8 and GMA9, distributing some of the depression reference voltages GMA1, GMA8 and GMA9 and selecting the remaining gamma reference voltages GMA2 to GMA7 from the divided voltages And a third circuit part 53 for dividing the gamma reference voltages GMA1 to GMA9 output from the first and second circuit parts 51 and 52 and outputting the gamma compensation voltages .

The gamma voltages GMA1 to GMA9 output from the gamma voltage generator 20 are input to the data driver 30. [ The DAC of the data driver 30 converts the pixel data (digital data) of the input image into gamma compensation voltages from the gamma voltage generator to output the data voltage Vdata. The data voltage (Vdata) is output to the data lines of the pixel array. 6C and 7C while supplying the gamma compensation voltage of the entire gradation to the data driver 30 in the low luminance mode, the entire luminance controller 10 and some circuits of the gamma voltage generator 20 So that the power consumption of the gamma voltage generator is minimized.

FIG. 4 is a circuit diagram showing the detail of the luminance controller 10 shown in FIG.

4, the luminance controller 10 includes power switch circuits SW01 and SW02 for blocking the input voltages VH1 and VH2 in the low luminance mode, a first voltage divider for dividing the first high voltage input voltage VH1, Circuit RS1, first voltage selectors MUX01 to MUX04, a plurality of buffers BUF01 to BUF04, and a second voltage dividing circuit RS2.

The luminance controller 10 selects one of the divided voltages of the first low-potential power supply voltage VH1 as the reference voltage VREF in the normal mode and supplies it to the gamma voltage generator 20. On the other hand, the luminance controller 10 does not operate because the input voltages VH1 and VL1 are cut off by the switch circuits SW01 and SW02 in the low luminance mode. Therefore, the luminance controller 10 does not generate current consumption in the low luminance mode.

The power switch circuits SW01 and SW02 include a switch element SW01 to which the first high potential input voltage VH1 is supplied and a switch element SW02 to which the first low potential input voltage VL1 is supplied. The switch element SW01 is turned on in accordance with the first logic value of the low brightness enable signal LLM in the normal mode to turn on the first high potential input voltage VH1 to the first voltage dividing circuit RS1, Off signal according to the second logic value of the low-luminance enable signal LLM in the low-luminance mode, and supplies the first high-potential input RS1 to one end of the first voltage dividing circuit RS1, The voltage VH1 is cut off. The switch element SW02 is turned on in accordance with the first logic value of the low brightness enable signal LLM in the normal mode to supply the first low potential input voltage VL1 to the other terminal of the first voltage dividing circuit RS1 On the other hand, in the low luminance mode, the first low potential input voltage VL1 is turned off according to the second logic value of the low luminance enable signal LLM to block the first low potential input voltage VL1 supplied to the first voltage dividing circuit RS1. The luminance controller 10 operates in the normal mode in which the first high potential input voltage VH1 and the first low potential input voltage VL1 are supplied to divide the first high potential input voltage VH1 to generate the reference voltage VREF, .

Each of the input voltages VH1 and VL1 can be adjusted in voltage level according to a register setting value.

The first voltage divider circuit RS1 divides the input voltages VH1 and VL1 using an R string circuit including resistors connected in series, and outputs the result through a node between the resistors. Since the input voltages VH1 and VL1 are supplied to the first voltage division circuit RS1 only in the normal mode, the current consumption of the first voltage division circuit RS1 occurs only in the normal mode and not in the low luminance mode.

The first voltage selectors MUX01 to MUX04 select the voltages distributed by the first voltage dividing circuit RS1. The first voltage selectors MUX01 to MUX04 select the first reference voltage BC_REF1 from the voltages distributed by the first voltage dividing circuit RS1 according to the register set value REF1, A multiplexer MUX02 for selecting the second reference voltage BC_REF2 from the voltages distributed by the first voltage dividing circuit RS1 in accordance with the second register set value REF2, The first to third multiplexers MUX03 and MUX03 select the third reference voltage BC_REF3 from the voltages distributed by the first voltage dividing circuit RS1 according to the set value REF3. A fourth 1-4 multiplexer MUX04 for selecting the fourth reference voltage BC_REF4 from the voltages distributed by the first divider circuit RS1 and a buffer BUF01 connected to the output of each of the multiplexers MUX01 through MUX04, To BUF04). Each of the reference voltages BC_REF1 to BC_REF4 output from the multiplexers MUX01 to MUX04 is supplied to the second voltage dividing circuit RS2 through buffers BUF01 to BUF04. The voltage selection units (MUX01 to MUX04) have current consumption only in the normal mode and not in the low-luminance mode.

The second voltage divider circuit RS2 divides the input voltages VH1, BC_REF1 to BC_REF4, VL1 using an R string circuit including resistors connected in series, and outputs the result through a node between the resistors. Since the input voltages VH1, BC_REF1 to BC_REF4 and VL1 are supplied to the second voltage dividing circuit RS2 only in the normal mode, the current consumption of the second voltage dividing circuit RS2 occurs only in the normal mode and not in the low luminance mode.

The different voltages output from the second voltage dividing circuit RS2 are supplied to the 1-5th multiplexer MUX05. The 1-5 multiplexer MUX05 selects one of the voltages distributed by the second voltage dividing circuit RS2 according to the register setting value BC for determining the reference voltage VREF. The reference voltage VREF output from the 1-5 multiplexer MUX05 is supplied to the gamma voltage generator 20 through the buffer BUF05. The multiplexer (MUX05) and buffer (BUF05) only draw current in normal mode and not in low-brightness mode.

The user can select the low brightness mode through the user interface. In order to generate the gamma compensation voltage optimized for each of the various driving modes of the display apparatus, the gamma voltage generator sets a gamma band corresponding to each of the driving modes. The voltage of each gamma band is defined by register settings. The register set value includes a register set value for controlling each of the multiplexers, which is a register for adjusting the input voltages VH1 and VL1. Accordingly, when the user selects the drive mode, the register set value of the gamma band is selected and the reference voltage VREF can be adjusted according to the drive mode.

5A and 5B are circuit diagrams showing the gamma voltage generator 20 shown in FIG. 4 in detail. The gamma voltage generator 20 divides the input voltage to generate first to n-th (n is a positive integer of 4 or more) gamma reference voltages. In the embodiment, n is assumed to be 9, but the present invention is not limited thereto.

5A, the gamma voltage generator 20 according to the first embodiment of the present invention includes a first circuit unit 51 for receiving a reference voltage VREF and generating some gamma reference voltages GMA1, GMA8, and GMA9, A second circuit section 52 for generating gamma reference voltages GMA2 to GMA7 other than the gamma reference voltages GMA1, GMA8 and GMA9 selected by the first circuit section 51, Switch circuits SW11 to SW13 for supplying the first and second input voltages VH2 and VL2 to the second and third circuit portions 52 and 53 and the first and second circuit portions 51 and 52, To generate a gamma compensation voltage of the entire gradation.

The gamma voltage generator 20 according to the first embodiment of the present invention generates gamma reference voltages GMA1 to GMA9 by dividing the reference voltage VREF from the luminance controller 10 in the normal mode, Divides the reference voltages GMA1 to GMA9 to generate gamma compensation voltages of the full gradation. The gamma voltage generator 20 generates the gamma compensation voltages of the entire gradation by only the second and third circuit portions 52 and 53 without operating the first circuit portion 51 in the low luminance mode. Therefore, the consumption current of the gamma voltage generator 20 in the low luminance mode is greatly reduced.

The output terminal of the first circuit portion 51 is connected to the second circuit portion 52 only in the normal mode through the switch circuits SW11 to SW12. In the low luminance mode, the output terminal of the first circuit portion 51 is separated from the second circuit portion 51 by the switch circuits SW11 to SW13. Therefore, the first circuit portion 51 does not consume current in the low luminance mode.

The first circuit portion 51 distributes the reference voltage VREF input from the luminance controller 10 and determines first, eighth and ninth gamma reference voltages GMA1, GMA8, and GMA9 from the divided voltages do. The voltage levels of the gamma reference voltages GMA1, GMA8 and GMA9 can be adjusted in accordance with the register set values RGMA1, RGMA8 and RGMA9. The first circuit unit 51 includes a third voltage divider circuit RS3, second voltage selectors MUX11 to MUX13, and a plurality of buffers BUF11 to BUF13.

The third voltage divider circuit RS3 outputs the reference voltage VREF through the node between the resistors by using an R string circuit including resistors connected in series. The second voltage selectors MUX11 to MUX13 select the voltages distributed by the third voltage dividing circuit RS3 and output some gamma reference voltages GMA1, GMA8 and GM9 including the highest and lowest gamma reference voltages. The second voltage selectors MUX11 to MUX13 include a multiplexer MUX11 for selecting the first gamma reference voltage GMA1 from the voltages distributed by the third voltage dividing circuit RS3 in accordance with the register set value RGMA1, A multiplexer MUX13 for selecting the eighth gamma reference voltage GMA8 from the voltages distributed by the third voltage dividing circuit RS3 in accordance with the set value RGMA8, And a multiplexer (MUX12) for selecting the ninth gamma reference voltage (GMA9) from the voltages distributed by the third transistor (RS3). The first gamma reference voltage GMA1 is the highest gamma reference voltage. The ninth gamma reference voltage (GMA9) is the lowest gamma reference voltage. The eighth gamma reference voltage GM8 is higher than the ninth gamma reference voltage GMA9.

Each of the gamma reference voltages GMA1, GMA8 and GMA9 outputted from the multiplexers MUX11 to MUX13 is supplied to the switch circuits SW11 to SW13 through the buffers BUF11 to BUF13.

The switch circuits SW11 to SW13 supply the gamma reference voltages GMA1, GMA8 and GMA9 outputted from the first circuit portion 51 to the second and third circuit portions 52 in the normal mode, And supplies the separate input voltages VH2 and VL2 to the second and third circuit portions 52 and 53. [ The switch circuits SW11 to SW13 electrically isolate the first circuit portion 51 and the second circuit portion 52 in the low luminance mode to drive only the circuit portions 52 and 53 of the gamma voltage generating portion 20 .

The switch circuits SW11 to SW13 are provided with switch elements SW11 and SW21 to which the first gamma reference voltage GMA1 and the second high potential input voltage VH2 are inputted and a switch element SW13 And a switch element SW12 to which the ninth gamma reference voltage GMA9 and the second low potential input voltage VL2 are input.

The switch element SW11 selects the first gamma reference voltage GMA1 in accordance with the first logic value of the low brightness enable signal LLM in the normal mode and outputs this voltage GMA1 to the second and third circuit portions 52, 53). On the other hand, the switch element SW11 selects the second high-potential input voltage VH2 in accordance with the second logic value of the low-luminance enable signal LLM in the low-luminance mode and outputs the voltage VH2 to the second and 3 circuit portions 52 and 53, respectively.

The switch element SW13 is turned on in accordance with the first logic value of the low brightness enable signal LLM in the normal mode to supply the eighth gamma reference voltage GMA8 to the second and third circuit portions 52 and 53 While the eighth gamma reference voltage GMA8 supplied to the second and third circuit portions 52 and 53 is turned off according to the second logic value of the low luminance enable signal LLM in the low luminance mode do.

The switch element SW12 selects the ninth gamma reference voltage GMA9 in accordance with the first logic value of the low brightness enable signal LLM in the normal mode and supplies this voltage GMA9 to the third circuit portion 53 . On the other hand, the switch element SW12 selects the second low-potential input voltage VL2 in accordance with the second logic value of the low-luminance enable signal LLM in the low-luminance mode and outputs this voltage VL2 to the third circuit part 53).

The second circuit unit 52 receives the first and eighth gamma reference voltages GMA1 and GMA8 input from the first circuit unit 51 in the normal mode and distributes the first gamma reference voltage GMA1, 8 gamma reference voltages (GMA2 to GMA8). The voltage level of the gamma reference voltages GMA2 to GMA7 can be adjusted according to the register set values RGMA2 to RGMA7.

The second circuit unit 52 receives the second high-potential input voltage VH2 and the eighth gamma reference voltage GMA8 determined by the voltage division circuit of the third circuit unit 52 in the low-luminance mode. The second circuit portion 52 divides the second high potential input voltage VH2 to determine the second to eighth gamma reference voltages GMA2 to GMA8.

The second circuit unit 52 includes a fourth voltage divider circuit RS2, third voltage selectors MUX21 to MUX27, and a plurality of buffers BUF21 to BUF27.

The fourth voltage dividing circuit RS4 is divided into fourth to seventh voltage dividing circuits RS41 to RS46. Each of the 4-1 to 4-6 voltage dividing circuits RS41 to RS46 distributes the input voltage using an R string circuit including resistors connected in series. The third voltage selectors MUX21 to MUX26 include a 3-1 multiplexer MUX21 and a 4-2 voltage dividing circuit R542 connected between the 4-1 voltage divider circuit R541 and the 2-1 buffer BUF21, A third -3 multiplexer MUX22 connected between the 2-2 buffer BUF22 and a 3-3 multiplexer MUX23 connected between the 4-3 voltage divider circuit R543 and the 2-3 buffer BUF23, The third 4-4 multiplexer MUX24 connected between the fourth 4-4 voltage divider circuit R544 and the second 2-4 buffer BUF24, the fourth 4-5 voltage divider circuit R545 and the second -1 buffer BUF25 And a third 3-6 multiplexer MUX26 connected between the 4-6 voltage divider circuit R546 and the 2-1 buffer BUF26.

The 4-1 voltage dividing circuit RS41 receives the first gamma reference voltage GMA1 and the eighth gamma reference voltage GMA8 in the normal mode and distributes the first gamma reference voltage GMA1 to a node between the resistors And outputs a different voltage through the resistor. The 4-2 voltage divider circuit RS42 receives the second high potential input voltage VH2 and the eighth gamma reference voltage GMA8 in the low luminance mode and distributes the second high potential input voltage VH2, Lt; RTI ID = 0.0 > node < / RTI > The 3-1 multiplexer MUX21 selects any one of the voltages distributed by the 4-1 voltage dividing circuit RS41 as the second gamma reference voltage GMA2 in accordance with the register set value RGMA2. The 3-1 buffer BUF21 supplies the second gamma reference voltage GMA2 input from the 3-1 multiplexer MUX21 to the third circuit unit 53. [

The 4-2 voltage dividing circuit RS42 receives the second gamma reference voltage GMA2 and the eighth gamma reference voltage GMA8 in the normal mode and the low luminance mode to divide the second gamma reference voltage GMA2, And outputs a different voltage through the node between them. The 3-2 multiplexer MUX22 selects any one of the voltages distributed by the 4-2 voltage dividing circuit RS42 as the third gamma reference voltage GMA3 in accordance with the register set value RGMA3. The 3-2 buffer BUF22 supplies the third gamma reference voltage GMA3 input from the 3-2 multiplexer MUX22 to the third circuit portion 53. [

The 4-3 voltage dividing circuit RS43 receives the third gamma reference voltage GMA3 and the eighth gamma reference voltage GMA8 in the normal mode and the low brightness mode and distributes the third gamma reference voltage GMA3, And outputs a different voltage through the node between them. The 3-3 multiplexer MUX23 selects any one of the voltages distributed by the 4-3 voltage dividing circuit RS43 as the fourth gamma reference voltage GMA4 in accordance with the register set value RGMA4. The third 3-3 buffer BUF23 supplies the fourth gamma reference voltage GMA4 input from the third 3-3 multiplexer MUX23 to the third circuit portion 53. [

The fourth 4-4 voltage dividing circuit RS44 receives the fourth gamma reference voltage GMA4 and the eighth gamma reference voltage GMA8 in the normal mode and the low brightness mode to divide the fourth gamma reference voltage GMA4, And outputs a different voltage through the node between them. The 3-4 multiplexer MUX24 selects any one of the voltages distributed by the 4-4 voltage dividing circuit RS44 as the fifth gamma reference voltage GMA5 according to the register set value RGMA5. The 3-4 buffer BUF24 supplies the fifth gamma reference voltage GMA5 input from the 3-4 multiplexer MUX24 to the third circuit portion 53. [

The fourth 4-5 voltage dividing circuit RS45 receives the fifth gamma reference voltage GMA5 and the eighth gamma reference voltage GMA8 in the normal mode and the low brightness mode and distributes the fifth gamma reference voltage GMA5, And outputs a different voltage through the node between them. The 3-5 multiplexer MUX 25 selects any one of the voltages distributed by the 4-5 voltage dividing circuit RS45 as the sixth gamma reference voltage GMA6 according to the register set value RGMA6. The 3-5 buffer BUF25 supplies the sixth gamma reference voltage GMA6 input from the 3-5 multiplexer MUX25 to the third circuit portion 53. [

The 4-6 voltage dividing circuit RS46 receives the sixth gamma reference voltage GMA6 and the eighth gamma reference voltage GMA8 in the normal mode and the low luminance mode to divide the sixth gamma reference voltage GMA6, And outputs a different voltage through the node between them. The 3-6 multiplexer MUX 26 selects any one of the voltages distributed by the 4-6 voltage dividing circuit RS46 as the seventh gamma reference voltage GMA7 according to the register set value RGMA7. The 3-6 buffer BUF26 supplies the seventh gamma reference voltage GMA7 input from the 3-6 multiplexer MUX26 to the third circuit portion 53. [

The third circuit unit 53 receives the gamma reference voltages GMA1 to GMA9 using the voltage dividing circuit in the normal mode and the low luminance mode, divides the gamma reference voltages GMA1 to GMA9, And outputs the gamma compensation voltages of the full gradation that can be expressed.

The voltage dividing circuit of the third circuit part 53 is divided into 5-1 to 5-8 voltage dividing circuits RS51 to RS58. Each of the 5-1 to 5-8 voltage dividing circuits RS51 to RS58 distributes the input voltage using an R-string circuit including resistors connected in series. The 5-1 voltage dividing circuit RS51 divides the first gamma reference voltage GMA1 and the second gamma reference voltage GMA2 to divide the voltage between the first gamma reference voltage GMA1 and the second gamma reference voltage GMA2 And outputs the gamma compensation voltages of the gradations expressed by the following equation. The 5-2 voltage dividing circuit RS52 divides the second gamma reference voltage GMA2 and the third gamma reference voltage GMA3 and outputs a voltage between the second gamma reference voltage GMA2 and the third gamma reference voltage GMA3 And outputs the gamma compensation voltages of the gradations expressed by the following equation. The fifth to third voltage dividing circuit RS53 divides the third gamma reference voltage GMA3 and the fourth gamma reference voltage GMA4 to generate a voltage between the third gamma reference voltage GMA3 and the fourth gamma reference voltage GMA4 And outputs the gamma compensation voltages of the gradations expressed by the following equation. The fifth to fourth voltage dividing circuit RS54 divides the fourth gamma reference voltage GMA4 and the fifth gamma reference voltage GMA5 to generate a voltage between the fourth gamma reference voltage GMA4 and the fifth gamma reference voltage GMA5 And outputs the gamma compensation voltages of the gradations expressed by the following equation. The fifth to fifth voltage divider circuit RS56 divides the fifth gamma reference voltage GMA5 and the sixth gamma reference voltage GMA6 to generate a voltage between the fifth gamma reference voltage GMA5 and the sixth gamma reference voltage GMA6 And outputs the gamma compensation voltages of the gradations expressed by the following equation. The fifth to sixth voltage divider circuit RS56 divides the sixth gamma reference voltage GMA6 and the seventh gamma reference voltage GMA7 to generate a voltage between the sixth gamma reference voltage GMA6 and the seventh gamma reference voltage GMA7 And outputs the gamma compensation voltages of the gradations expressed by the following equation. The fifth-seventh voltage divider circuit RS57 divides the seventh gamma reference voltage GMA7 and the eighth gamma reference voltage GMA8 to generate a voltage between the seventh gamma reference voltage GMA7 and the eighth gamma reference voltage GMA8 And outputs the gamma compensation voltages of the gradations expressed by the following equation. The fifth to eighth voltage dividing circuit RS58 divides the eighth gamma reference voltage GMA8 and the ninth gamma reference voltage GMA9 to generate a voltage between the eighth gamma reference voltage GMA8 and the seventh gamma reference voltage GMA9 And outputs the gamma compensation voltages of the gradations expressed by the following equation.

5B shows a gamma voltage generator 20 according to a second embodiment of the present invention.

In the gamma voltage generator 20 according to the second embodiment of the present invention, substantially the same components as those of the first embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. The circuit configurations of the first, second and third circuit portions 51 to 53 are substantially the same as those of the first embodiment described above.

Referring to FIG. 5B, the gamma voltage generating unit 20 according to the second embodiment of the present invention includes a first circuit unit 51 for receiving a reference voltage VREF and generating some gamma reference voltages GMA1, GMA8, and GMA9, A second circuit section 52 for selecting the gamma reference voltages GMA2 to GMA7 other than the gamma reference voltages GMA1, GMA8 and GMA9 selected by the first circuit section 51, The switch circuits SW31 to SW33 for supplying the two input voltages VH2 and VL2 to the third circuit portion 53 and the gamma reference voltages GMA1 to GMA9 from the first and second circuit portions 51 and 52, And a switch circuit SW41 to SW46 for separating the second circuit portion 52 and the third circuit portion 53 in the low luminance mode.

The gamma voltage generator 20 according to the second embodiment of the present invention generates the gamma reference voltages GMA1 to GMA9 by dividing the reference voltage VREF from the luminance controller 10 in the normal mode, Divides the reference voltages GMA1 to GMA9 to generate gamma compensation voltages of the entire gradation. The gamma voltage generating unit 20 generates the gamma compensation voltages of the entire gradation by only the third circuit unit 53 without operating the first and second circuit units 51 and 52 in the low luminance mode. Therefore, this embodiment can further reduce the consumption current of the gamma voltage generator 20 in the low luminance mode than the first embodiment.

The first circuit portion 51 and the second circuit portion 52 are directly connected without a switch element. Therefore, the gamma reference voltages GMA1, GMA8, and GMA9 output from the first circuit portion 51 are supplied to the second circuit portion 52 in the normal mode and the low brightness mode.

The gamma reference voltages GMA2 to GMA7 output from the second circuit portion 52 are supplied to the third circuit portion 53 via the switch elements SW41 to SW46 in the normal mode. The output terminal of the second circuit part 52 is electrically separated from the third circuit part 53 due to the switch elements SW31 to SW33 in the low luminance mode. Because of this, the second circuit portion 52 does not operate in the low luminance mode, and therefore, there is no current consumption of the second circuit portion 52.

The switch circuits SW31 to SW33 supply the gamma reference voltages GMA1, GMA8 and GMA9 outputted from the first circuit portion 51 to the third circuit portion 53 in the normal mode, And supplies the voltages VH2 and VL2 to the third circuit portion 53. [ The switch circuits SW31 to SW33 electrically isolate the third circuit portion 53 from the first and second circuit portions 51 and 52 in the low luminance mode and are connected to the third circuit portion 53 in the gamma voltage generating portion 20, .

The switch circuits SW31 to SW33 are respectively connected to the switch elements SW31 and SW33 to which the first gamma reference voltage GMA1 and the second high potential input voltage VH2 are input, And a switch element SW32 to which the ninth gamma reference voltage GMA9 and the second low potential input voltage VL2 are input.

The switch element SW31 selects the first gamma reference voltage GMA1 in accordance with the first logic value of the low brightness enable signal LLM in the normal mode and supplies this voltage GMA1 to the third circuit portion 53 . On the other hand, the switch element SW31 selects the second high-potential input voltage VH2 in accordance with the second logic value of the low-luminance enable signal LLM in the low-luminance mode and outputs this voltage VH2 to the third circuit portion 53).

The switch element SW33 is turned on in accordance with the first logic value of the low luminance enable signal LLM in the normal mode to supply the eighth gamma reference voltage GMA8 to the third circuit portion 53, Mode to turn off the eighth gamma reference voltage GMA8 supplied to the third circuit portion 52 in accordance with the second logic value of the low brightness enable signal LLM.

The switch element SW32 selects the ninth gamma reference voltage GMA9 in accordance with the first logic value of the low brightness enable signal LLM in the normal mode and supplies this voltage GMA9 to the third circuit portion 53 . On the other hand, the switch element SW32 selects the second low-potential input voltage VL2 in accordance with the second logic value of the low-luminance enable signal LLM in the low-luminance mode and outputs this voltage VL2 to the third circuit portion 53).

The switch circuits SW41 to SW46 supply the gamma reference voltages GMA2 to GMA7 output from the second circuit portion 52 to the third circuit portion 53 in the normal mode while the second circuit portion 52 And the third circuit part 53 are electrically separated from each other. The switch circuits SW41 to SW46 switch elements SW41 for switching the second gamma reference voltage GMA2 from the second circuit portion 52 and the third gamma reference voltage GMA3 from the second circuit portion 52 A switching element SW42 for switching the fourth gamma reference voltage GMA4 from the second circuit portion 52 and a fifth element GMA4 for switching the fifth gamma reference voltage GMA5 from the second circuit portion 52 to A switch element SW45 for switching the sixth gamma reference voltage GMA6 from the second circuit portion 52 and a seventh gamma reference voltage GMA7 from the second circuit portion 52, And a switching element SW46 for switching the switching element SW46. Each of the switch elements SW41 to SW46 is turned on in accordance with the first logic value of the low brightness enable signal LLM in the normal mode to turn on the gamma reference voltage node of the second circuit part 52 to the third circuit part 53 ) To the corresponding gamma reference voltage node. On the other hand, each of the switch elements SW41 to SW46 is turned off in accordance with the second logic value of the low brightness enable signal LLM in the low brightness mode, so that the gamma reference voltage node of the third circuit part 52 and the third And electrically isolates the corresponding gamma reference voltage node in the circuitry 52.

6A to 6C are circuit diagrams showing the operation of the gamma voltage generator according to the first embodiment of the present invention. 6A to 6C, reference numeral 61 denotes a voltage generator for generating a first high-potential input voltage VH1, and 62 denotes a voltage generator for generating a first low-potential input voltage VL1. 6A is a diagram showing a circuit configuration of a gamma voltage generator. 6B is a view showing the operation of the gamma voltage generator in the normal mode. 6C is a diagram showing the operation of the gamma voltage generator in the low luminance mode.

6B, the first voltage dividing circuit RS1 of the luminance controller 10 divides the first high potential input voltage VH1 to generate the first high potential input voltage VH1 and the second low potential input voltage VL1 ). ≪ / RTI > The first voltage selectors MUX01 to MUX04 select the voltages indicated by the register set values REF1 to REF4 among the voltages distributed by the first voltage dividing circuit RS1 to output the first to fourth reference voltages REF1 to REF4, REF4. The second voltage dividing circuit RS2 distributes the first to fourth reference voltages REF1 to REF4 to generate a plurality of voltages having different voltage levels. The multiplexer MUX05 selects, as the reference voltage VREF, the voltage indicated by the register set value BC among the voltages distributed by the second voltage dividing circuit RS2.

The gamma voltage generating unit 20 generates the first, eighth, and ninth gamma reference voltages Vgs using the third voltage dividing circuit RS3 and the second voltage selecting units MUX11 to MUX13, to which the reference voltage VREF is input in the normal mode, To generate voltages (GMA1, GMA8, GMA9). The fourth voltage dividing circuits RS41 to RS46 receive the first, eighth, and ninth gamma reference voltages GMA1, GMA8, and GMA9 in the normal mode, and generate a plurality of voltages having different voltage levels. The third voltage selectors MUX21 to MUX26 select the voltages indicated by the register set values RGMA2 to RGMA7 and output the second to seventh gamma reference voltages GMA2 to GMA7. The fourth voltage dividing circuit RS2 divides the gamma reference voltages GMA1 to GMA9 to generate gamma compensation voltages of the entire gradation.

6C, the input power supplies VH1 and VL1 of the luminance controller 10 are cut off by the switch circuits SW01 and SW02 in the low luminance mode. The switch circuits SW11 to SW13 electrically isolate the second and third circuit portions 52 and 53 from the first circuit portion 51 of the gamma voltage generating portion 20 in the low luminance mode. The switch circuits SW11 to SW13 supply the second high potential voltage VH2 to the second and third circuit portions 52 and 53 in the low luminance mode and the second low potential input voltage VL2). At this time, the eighth gamma reference voltage GMA8 is determined according to the resistance value of the voltage dividing circuit RS58. The third circuit unit 53 divides the second high potential input voltage VH2 in the low brightness mode and outputs the gamma compensation voltage VH2 of the full gray level between the second high potential input voltage VH2 and the second low potential input voltage VL2 .

6C, the gamma voltage generator can generate the gamma compensation voltages of the entire gradation by only the second and third circuit portions 52 and 53 of the gamma voltage generator 20. [

In Fig. 6C, a blurred portion represents a circuit without current consumption because it does not operate in the low-luminance mode. The unoperated circuit is the entirety of the luminance control section 10 and the first circuit section 51 of the gamma voltage generating section 20.

7A to 7C are circuit diagrams illustrating the operation of the gamma voltage generator according to the second embodiment of the present invention. 7A is a diagram showing a circuit configuration of a gamma voltage generator. 7B is a diagram showing the operation of the gamma voltage generator in the normal mode. The operation of the normal mode is substantially the same as that of the first embodiment described above. 7C is a diagram showing the operation of the gamma voltage generator in the low luminance mode.

Referring to Fig. 7C, in the low luminance mode, the input power supplies VH1 and VL1 of the luminance controller 10 are cut off by the switch circuits SW01 and SW02. The switch circuits SW31 to SW33 electrically isolate the third circuit portion 53 from the first and second circuit portions 51 and 52 of the gamma voltage generating portion 20 in the low luminance mode. The switch circuits SW31 to SW33 supply the second high potential voltage VH2 and the second low potential input voltage VL2 to the third circuit portion 52 in the low luminance mode. The third circuit unit 53 divides the second high potential input voltage VH2 in the low brightness mode and outputs the gamma compensation voltage VH2 of the full gray level between the second high potential input voltage VH2 and the second low potential input voltage VL2 .

As shown in FIG. 7C, the gamma voltage generator can generate gamma compensation voltages of the entire gradation by only the third circuit portions 52 and 53 of the gamma voltage generator 20. This embodiment can further reduce the power consumption than the first embodiment described above.

8 is a block diagram showing an example of a display device according to an embodiment of the present invention. 9 is a diagram showing an example of the AoD screen. 10 is a circuit diagram showing an example of a pixel circuit. 11 is a waveform diagram showing a driving signal of the pixel circuit shown in FIG. 8 to 11 illustrate an organic light emitting display device, but it should be noted that the display device of the present invention is not limited thereto.

An OLED of an organic light emitting display includes an anode electrode and a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a power source voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons. As a result, the light emitting layer (EML) Thereby generating visible light.

The compensation circuit for compensating the difference in driving characteristics of the pixels in the organic light emitting display may be divided into an internal compensation circuit and an external compensation circuit. The internal compensation circuit samples the threshold voltage of the driving element using an internal compensation circuit disposed in each of the pixels, adds a threshold voltage to the data voltage of the pixel data, drives the pixels, Automatically compensate. The external compensation circuit senses the electrical characteristics of the driving elements, and modulates the pixel data of the input image based on the sensed result, thereby compensating for the driving characteristic change of each of the pixels. The driving element is implemented as a transistor.

It should be noted that the compensation circuit of the present invention is described, but not limited to, the internal compensation circuit in the following embodiments.

8 to 11, a display device of the present invention includes a display panel 100, a drive IC (Integrated Circuit) 300 for writing pixel data of an input image to pixels of the display panel 100, System 200, and the like.

The input image is reproduced on the screen AA of the display panel 100. [ The screen AA of the display panel 100 includes data lines 102, gate lines 103 that intersect the data lines 102, and a pixel array in which pixels are arranged in a matrix. The data lines 102 supply the data voltages from the drive IC 300 to the pixels. The gate lines 103 supply the gate signals from the gate driver 40 to the pixels. The gate signal may be divided into a scan signal (SCAN), a light emission control signal (EM signal), and the like as shown in FIG.

Each of the pixels includes sub-pixels 101 of different colors for color implementation. The subpixels 101 may include red, green, and blue subpixels 101. Further, each of the pixels may further include a white subpixel. Each of the subpixels may be implemented with the pixel circuit shown in FIG. 10, but is not limited thereto. It should be noted that the pixel circuit may be implemented as a pixel circuit of various known structures.

The display panel 100 may further include a VDD line 104 as a pixel drive voltage VDD and a Vini line 105 as shown in Figure 10 for supplying the initialization voltage Vini to the pixels have. These power supply lines are connected to a power supply circuit not shown. The power supply circuit generates a DC power required for driving the display panel by using a DC-DC converter. The DC-DC converter includes a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply circuit outputs a power source necessary for driving the pixels P of the display panel, for example, ELVDD, VGH, VGL, Vref, an analog gamma voltage, and the like. VGH is the gate high voltage, and VGL is the gate low voltage. Such a power supply circuit can be integrated in the drive IC 300. Fig.

The gate driver 40 may be formed on the substrate of the display panel 100 together with the TFT array of the pixel array. Each of the pixel circuit and the gate driver 40 is implemented with a plurality of transistors. The transistors include TFTs including oxide semiconductor, thin film transistors (TFT), amorphous silicon (a-Si), and low temperature polysilicon (LTPS) Or more. The TFT may be implemented by a metal oxide semiconductor field effect transistor (MOSFET) structure. The TFT may be implemented as one of an n-type transistor (NMOS) or a p-type transistor (PMOS) or a combination thereof.

The gate signal outputted from the gate driver 40 is a gate-on voltage between the gate on voltage on which the TFT can be turned on and a gate off voltage on which the TFT can be turned off . In the n-channel MOSFET (NMOS), the gate-on voltage is VGH and the gate-off voltage is VGL. In the p-channel MOSFET (PMOS), the gate-on voltage is VGL and the gate-off voltage is VGH.

The gate driver 40 includes a shift register. The shift register includes a plurality of stages connected in a dependent manner and sequentially supplies the gate signal to the gate lines 103 by shifting the output voltage in accordance with the gate shift clock timing.

The driver IC 300 includes a timing controller 50, a data driver 30, a gamma voltage generator 120, a resistor 60, and the like.

The timing controller 50 uses the timing signals received from the host system 200 such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock CLK, and the data enable signal DE And generates timing control signals for controlling the operation timings of the gate driver 40 and the data driver 30. The host system 200 may be any one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile system, a wearable system, and a virtual reality system.

The data driver 30 converts the pixel data (digital data) of the input image into gamma compensation voltages from the gamma voltage generator 120 to generate a data voltage. The data voltage output from the data driver 30 is supplied to the pixels through the data lines 102. [ The gamma voltage generator 120 generates only gamma compensation voltages by operating at least a circuit in the low luminance mode as described above.

Register settings for adjusting the output voltage of the gamma voltage generator 120 are stored in the memory of the register 60 according to the gamma band. The gamma band can be selected according to the luminance value DBV input to the host system 200. [ Register setting values are set separately for each gamma band. The luminance value DBV indicates the maximum gradation value of the pixel data, for example, the brightness corresponding to the gradation 255 in the case of 8-bit data. The brightness value DBV may be determined by the host system 200 by a user command inputted from a user through a user interface connected to the host system 200 or by various sensors such as an illuminance sensor.

The AoD mode which drives only some pixels of the screen AA in the low brightness mode can be activated. As shown in the example of FIG. 9, the AoD screen is driven by low power consumption of only a few pixels, and can display AOD information that can be set by a user as shown in a clock, a message, and a picture.

10 and 11, a pixel circuit includes a light emitting device OLED, a plurality of transistors T1 through T6, a capacitor DT, a capacitor Cst, and the like. The transistors T1 to T6 and DT are illustrated as TFTs of a p-channel MOSFET (PMOS) structure in FIG. 10, but are not limited thereto.

The pixel circuit is supplied with the power supply voltage such as the pixel drive voltage VDD, the low potential power supply voltage VSS, and the initialization voltage Vini. The power supply voltage may be VDD = 5V, VSS = -5V, Vini = 1V to -1V, but is not limited thereto. The gate signal swings between the gate high voltage (VGH) and the gate low voltage (VGL). VGH and VGL may be, but are not limited to, VGH = 10V and VGL = -5V. The data voltage Vdata may be a voltage between 5V and 1V, but is not limited thereto. This voltage may vary depending on the driving characteristics of the display panel 100 and the product model.

The pixel circuit is initialized in the initialization step t01 and then charges the capacitor Cst with the data voltage Vdata compensated by the threshold voltage by sampling the threshold voltage of the driving element DT in the sampling step t02. The pixel circuit emits light in the light emitting step t04 after the holding step. In the initialization step t01, the fifth switch TFT T5 is turned on in response to the (N-1) th scan signal SCAN (N-1). In the sampling step t02, the first, second and sixth switch TFTs T1, T2 and T6 are turned on in response to the Nth scan signal SCAN (N) synchronized with the data voltage Vdata do. In the hold step t03, the switch TFTs T1 to T6 maintain the off state, and the main nodes n1, n3, n4 and n6 of the pixel circuit are floating and remain in the previous state. In the light emitting step t04, the third and fourth switch TFTs T3 and T4 are turned on.

The light emitting device OLED includes an organic compound layer formed between the anode and the cathode. The organic compound layer may include, but not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED is connected to the fourth and sixth switch TFTs T4 and T6 through the sixth node n6. The cathode of the OLED is connected to the VSS wiring to which the low potential supply voltage VSS is applied. The OLED emits light with a current supplied through the driving TFT DT. The current path of the OLED is switched by the third and fourth switch TFTs T3 and T4.

The capacitor Cst is connected between the first node n1 and the second node n2. The data voltage Vdata compensated by the threshold voltage Vth of the driving TFT DT is charged in the capacitor Cst. Since the data voltage Vdata in each of the subpixels 101 is compensated by the threshold voltage Vth of the driving TFT DT, the characteristic deviation of the driving TFT DT in the subpixels 101 is compensated for, And can be driven by driving characteristics.

The first switch TFT T1 is turned on in response to the N scan signal SCAN (N) in the sampling step t02. When the first switch TFT (T1) is turned on, the first node (n1) and the fourth node (n4) are connected. One node n1 is connected to the gate of the driving TFT DT, the first electrode of the capacitor Cst, and the first electrode of the first switch TFT T1. The fourth node n4 is connected to the second electrode of the drive TFT DT, the second electrode of the first switch TFT T1, and the first electrode of the fourth switch TFT T4. The gate of the first switch TFT T1 is supplied with the Nth scan signal SCAN (N). The first electrode of the first switch TFT (T) is connected to the first node (n1), and the second electrode of the first switch TFT (T1) is connected to the fourth node (n4).

The second switch TFT T2 is turned on in response to the Nth scan signal SCAN1 in the sampling step t02. When the second switch TFT T2 is turned on, the data voltage Vdata is supplied to the third node n3. And the gate of the second switch TFT T2 is supplied with the Nth scan signal SCAN (N). And the first electrode of the second switch TFT T2 is connected to the third node n3. The second electrode of the second switch TFT (T2) is supplied with the data voltage (Vdata) through the data line. The third node n3 is connected to the first electrode of the second switch TFT T20, the second electrode of the third TFT T3, and the second electrode of the drive TFT DT.

The third switch TFT T3 is turned on in response to the EM signal EM (N) in the light emitting step t04. And the second node n2 is connected to the third node n3 when the third switch TFT T3 is turned on. The gate of the third switch TFT T3 is supplied with the EM signal EM (N). The first electrode of the third switch TFT (T3) is connected to the second node (n2). And the second electrode of the third switch TFT T3 is connected to the third node n3. The second node n2 is connected to the VDD line 104 to which the pixel driving voltage VDD is supplied and the second electrode of the capacitor Cst.

The fourth switch TFT (T4) is turned on in response to the EM signal EM (N) in the light emitting step t04. And the fourth node n4 is connected to the sixth node n6 when the fourth switch TFT T4 is turned on. The fifth node n5 is connected to the second electrode of the fourth switch TFT (T4), the second electrode of the sixth switch TFT (T6), and the anode of the light emitting element (EL). The gate of the fourth switch TFT (T4) is supplied with the EM signal EM (N). The first electrode of the fourth switch TFT (T4) is connected to the fourth node (n4), and the second electrode is connected to the sixth node (n6). The sixth node n6 is connected to the second electrode of the fourth switch TFT T4, the second electrode of the sixth switch TFT T6, and the anode of the light emitting element EL.

The fifth switch TFT T5 is turned on in response to the (N-1) th scan signal SCAN (N-1) in the initialization step t01. When the fifth switch TFT (T5) is turned on, the first node (n1) is connected to the fifth node (n5). The fifth node n5 is connected to the Vini line to which the initializing voltage Vini is supplied, the second electrode of the fifth switch TFT T5, and the first electrode of the sixth switch TFT T6. The gate of the fifth switch TFT T5 is supplied with the (N-1) th scan signal SCAN (N-1). The first electrode of the fifth switch TFT (T5) is connected to the first node (n1), and the second electrode is connected to the Vini line (105) through the fifth node (n5).

The sixth switch TFT T6 is turned on in response to the N scan signal SCAN (N) in the sampling step t02. And the fifth node n5 is connected to the sixth node n6 when the sixth switch TFT T6 is turned on. And the gate of the sixth switch TFT T6 is supplied with the Nth scan signal SCAN (N). The first electrode of the sixth switch TFT (T6) is connected to the fifth node (n5), and the second electrode is connected to the sixth node (n6).

The driving TFT DT is a driving element for adjusting the current flowing in the light emitting element EL. The driving TFT DT includes a gate connected to the first node n1, a first electrode connected to the third node n3, and a third electrode connected to the second node n2.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: luminance controller 20: gamma voltage generator
30: Data driver 40: Gate driver
50: timing control section 51: first circuit section
52: second circuit part 53: third circuit part
60: Register 100: Display panel
120: gamma voltage generator 200: host system
300: Driver IC SW01 to SW46: Switch circuit

Claims (9)

A luminance controller for generating a reference voltage selected from voltages distributed from the first input voltage;
Generating gamma compensation voltages corresponding to the gradation voltages of the pixel data based on the voltages distributed from the reference voltage in the first drive mode and generating the gamma compensation voltages based on the voltages distributed from the second input voltage in the second drive mode, A gamma voltage generator for generating a gamma voltage; And
And a switch circuit for interrupting the first input voltage input to the brightness controller in the second drive mode and the reference voltage input to the gamma voltage generator. The method according to claim 1,
And the gamma voltage generating unit drives only a part of the gamma voltage generating unit in the second driving mode to generate the gamma compensation voltages. The method according to claim 1,
The gamma-
A first circuit portion for distributing the reference voltage through a voltage divider circuit and selecting some gamma reference voltages including a highest gamma reference voltage and a lowest gamma reference voltage from the distributed voltages;
A second circuitry for distributing the some of the depletion reference voltages and selecting the remaining gamma reference voltages from the distributed voltages; And
And a third circuit unit for dividing the gamma reference voltages output from the first and second circuit units and outputting the gamma compensation voltages. The method of claim 3,
Wherein the first input voltage comprises:
A first high potential input voltage and a first low potential input voltage lower than the first high potential input voltage,
Wherein the second input voltage comprises:
A second high potential input voltage and a second low potential input voltage that is lower than the second high potential input voltage,
Wherein the second high potential input voltage is lower than the first high potential input voltage. 5. The method of claim 4,
The switch circuit
And a first switch circuit for interrupting the first high-potential input voltage and the second high-potential input voltage supplied to the luminance controller in the second drive mode. 6. The method of claim 5,
The switch circuit includes:
Gamma reference voltage output from the first circuit section in the first drive mode to the second and third circuit sections and supplies the second high potential input voltage to the second and third circuit sections in the second drive mode, A second-1 < / RTI >
And supplies the lowermost gamma reference voltage outputted from the first circuit section to the second and third circuit sections in the first drive mode and supplies the second low potential input voltage to the second and third circuit sections in the second drive mode, A second-2 switch circuit for supplying to the circuit part; And
And supplies a lower gamma reference voltage higher than the lowest gamma reference voltage among the gamma reference voltages in the first drive mode to the second and third circuit portions in the second drive mode, And a second 2-3 switch circuit for blocking the supplied lower gamma reference voltage. 6. The method of claim 5,
The switch circuit includes:
And a second driving circuit for supplying the highest gamma reference voltage output from the first circuit section to the third circuit section in the first driving mode and for supplying the second high potential input voltage to the third circuit section in the second driving mode, -1 switch circuit;
And supplies the lowermost gamma reference voltage outputted from the first circuit section to the third circuit section in the first drive mode and supplies the second low potential input voltage to the third circuit section in the second drive mode, -2 switch circuit; And
And supplies the sub-gamma reference voltage higher than the lowest gamma reference voltage among the gamma reference voltages in the first drive mode to the third circuit portion, and supplies the sub-gamma reference voltage to the third circuit portion in the second drive mode, And a second-third switch circuit for blocking the voltage. A display panel on which data lines, gate lines intersecting with the data lines, and pixels are arranged;
A gamma voltage generator for outputting gamma compensation voltages that can be changed by a user; And
And a data driver for converting the pixel data of the input image into the gamma compensation voltages to generate a data voltage and outputting the data voltage to the data lines,
The gamma voltage generator
A luminance controller for generating a reference voltage selected from voltages distributed from the first input voltage;
Generating gamma compensation voltages corresponding to the gradation voltages of the pixel data on the basis of voltages distributed from the reference voltage in a first drive mode and generating gamma compensation voltages based on voltages distributed from the second input voltage in a second drive mode, A gamma voltage generator for generating voltages; And
And a switch circuit for interrupting the first input voltage input to the brightness controller in the second drive mode and the reference voltage input to the gamma voltage generator. 9. The method of claim 8,
Wherein only a part of the circuits of the gamma voltage generator is driven in the second drive mode to generate the gamma compensation voltages.

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