KR20210016091A - Integrated CMOS Source Drain Formation Using Advanced Control - Google Patents

Abstract

The FinFET device includes a doped source and/or drain extension disposed between the bulk semiconductor portion of the semiconductor substrate and the gate spacer of the FinFET device, such n-doped or p-doped source or drain extension It is disposed on the semiconductor part. The doped source or drain extension is formed in a cavity formed close to the gate spacer by a selective epitaxial growth (SEG) process. After formation of the cavity, advanced processing controls (APC) (ie, integrated metrology) are used to determine the distance of the recess without exposing the substrate to an oxidizing environment. The isotropic etching process, metrology and selective epitaxial growth can be performed on the same platform.

Description

Integrated CMOS Source Drain Formation Using Advanced Control

[0001] Embodiments of the present disclosure generally relate to fabrication of integrated circuits, and in particular, an apparatus for forming source drain extensions in a finFET using selective epitaxial growth (SEG). And a method.

[0002] Transistors are a key component of most integrated circuits. Faster transistors generally require a larger gate width because the drive current and hence the speed of the transistor is proportional to the gate width of the transistor. Thus, there is a trade-off between transistor size and speed, and “fin” field-effect transistors (finFETs) to address the conflicting targets of transistors with maximum drive current and minimum size. field-effect transistors) were developed. FinFETs feature a fin-shaped channel region that significantly increases the size of the transistor without significantly increasing the transistor's footprint, and is currently being applied in many integrated circuits. However, finFETs have their own drawbacks.

[0003] In the case of narrow and high finFETs, the formation of horizontal source/drain extensions becomes increasingly difficult because the fin-shaped channel region is easily amorphized or otherwise damaged by conventional ion implantation techniques such as beamline ion implantation. Because it can be. Specifically, in some finFET architectures (eg, h-GAA (horizontal Gate-All-Around)), ion implantation can cause severe mixing between the silicon channel and the adjacent silicon-germanium (SiGe) sacrificial layer. Such mixing is highly undesirable, since the ability to selectively remove the sacrificial SiGe layer is then compromised. In addition, repairing such implant damage through thermal annealing increases the thermal budget of the finFET device.

[0004] Additionally, the precise placement of the desired dopant in the horizontal source/drain extension region of the finFET is very difficult at best, since the source/drain extension in the finFET can be covered by other structures. For example, (inner) sidewall spacers on a sacrificial SiGe superlattice (SL) layer typically cover the source/drain extension regions when doping is performed. As a result, conventional line-of-sight ion implantation techniques cannot directly deposit dopants uniformly in the finFET source/drain extension region.

[0005] In addition, the time the substrate is exposed to the atmosphere (also referred to as Q-time) can significantly affect the defectivity of the epitaxial film. Accordingly, there is a need for processing apparatus and techniques for precisely doping source/drain regions in finFET devices currently available or under development.

[0006] One or more embodiments of the present disclosure relate to methods of forming a semiconductor device. An anisotropic etching process is performed on the semiconductor material to expose the surface of the semiconductor material on the semiconductor substrate. This surface is disposed between the bulk semiconductor portion of the semiconductor substrate and the existing structure of the semiconductor device, the semiconductor material being formed on the bulk semiconductor portion of the semiconductor substrate. An isotropic etching process is performed on the exposed sidewalls to form a cavity by concave the semiconductor material disposed between the bulk semiconductor portion of the semiconductor substrate and the existing structure by a predetermined distance. A layer of evaporation material is formed on the surface of the cavity through a selective epitaxial growth (SEG) process. The substrate does not undergo a pre-clean process between the formation of the cavity and the SEG.

[0007] Additional embodiments of the present disclosure relate to methods of forming a semiconductor device. A semiconductor substrate is positioned within a semiconductor material on the semiconductor substrate in a first processing chamber. An anisotropic etching process is performed on the semiconductor material to expose the surface of the semiconductor material. This surface is disposed between the bulk semiconductor portion of the semiconductor substrate and the existing structure of the semiconductor device, the semiconductor material being formed on the bulk semiconductor portion of the semiconductor substrate. An isotropic etching process is performed on the exposed sidewalls to form a cavity by concave the semiconductor material disposed between the bulk semiconductor portion of the semiconductor substrate and the existing structure by a predetermined distance. Without exposing the semiconductor substrate to oxidative conditions, the semiconductor substrate is moved from the first processing chamber to the second processing chamber. The distance at which the semiconductor material becomes concave after isotropic etching is determined. A layer of deposition material is formed on the surface of the cavity using a selective epitaxial growth (SEG) process in a second processing chamber. The semiconductor substrate does not undergo a pre-clean process between the formation of the cavity and the SEG. The SEG process takes into account the distance the semiconductor material has become concave after isotropic etching.

[0008] Additional embodiments of the present disclosure relate to processing tools for forming a semiconductor device. The central transfer station has a plurality of processing chambers disposed around the central transfer station. The robot is within the central transfer station and is configured to move the substrate between a plurality of processing chambers. The first processing chamber is connected to the central transfer station. The first processing chamber is configured to perform an isotropic etching process. A metrology station accessible to the robot is in the processing tool. The metrology station is configured to determine the distance of a recess in the semiconductor material on the substrate by an isotropic etching process. A second processing chamber is connected to the central transfer station. The second processing chamber is configured to perform a selective epitaxial growth (SEG) process. A controller is connected to one or more of the central transfer station, robot, first processing chamber, metrology station or second processing chamber. The controller includes: a first configuration for moving a substrate on the robot between a plurality of processing chambers and a metrology station; A second configuration for performing an isotropic etching process on the substrate in the first processing chamber; A third configuration for performing an analysis to determine a recess in the semiconductor material at the measurement station; Or a fourth configuration for performing the selective epitaxial growth process in the second processing chamber, wherein the selective epitaxial growth process is adapted for the recess of the semiconductor material.

[0009] In such a way that the above-mentioned features of the present disclosure can be understood in detail, a more detailed description of the present disclosure briefly summarized above may be made by reference to examples, some of which are Illustrated in the drawings. However, it should be noted that the appended drawings illustrate only typical embodiments of the present disclosure and should not be regarded as limiting the scope of the present disclosure accordingly, as this disclosure describes other equally effective embodiments. Because it is acceptable.
1 is a perspective view of a fin-field-effect transistor (finFET), in accordance with one or more embodiments of the present disclosure;
[0011] Figure 2 is a cross-sectional view of the finFET of Figure 1, in accordance with one or more embodiments of the present disclosure;
3 is a flow diagram of a manufacturing process for forming a finFET, in accordance with one or more embodiments of the present disclosure;
4A-4E show schematic cross-sectional views of a semiconductor device, corresponding to various stages of the process of FIG. 3, in accordance with one or more embodiments of the present disclosure;
5 is a schematic cross-sectional view of the finFET of FIG. 1 after formation of cavities, in accordance with one or more embodiments of the present disclosure;
6 is a flow diagram of a manufacturing process for forming a nanowire structure, in accordance with one or more embodiments of the present disclosure;
7A-7G are schematic cross-sectional views of the nanowire/nanosheet structure of FIG. 7, corresponding to various stages of the process of FIG. 6, in accordance with one or more embodiments of the present disclosure;
8 is a flow diagram of a manufacturing process for forming a semiconductor device, in accordance with one or more embodiments of the present disclosure; And
9 shows a schematic diagram of a processing system for performing the methods of any of the embodiments of the present disclosure.

[0019] Before describing various exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the construction or process steps presented in the following description. Other embodiments of the present disclosure are possible, and may be performed or practiced in various ways.

[0020] As used herein and in the appended claims, the term “substrate” refers to a surface or portion of a surface on which a process acts. Further, it will be understood by those skilled in the art that unless the context clearly indicates otherwise, reference to a substrate may also refer to only a portion of the substrate. Additionally, reference to depositing on a substrate may mean both a bare substrate and a substrate having or having one or more films or features deposited thereon.

[0021] As used herein, “substrate” refers to any substrate or material surface formed on a substrate on which film processing is performed during the manufacturing process. For example, the substrate surface on which processing can be performed is silicon, silicon oxide, strained silicon, SOI (silicon on insulator), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, depending on the application. , Materials such as gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydrate, anneal, UV cure, e-beam cure and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps also includes an underlayer formed on the substrate as disclosed in more detail below. As the context indicates, the term “substrate surface” is intended to include such sublayers. Thus, for example, when a film/layer or partial film/layer is deposited on the substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.

[0022] Embodiments of the present disclosure relate to semiconductor devices, processing tools and processing methods, including a doped semiconductor material formed in a region disposed between a bulk semiconductor portion of a semiconductor substrate and an existing structure of the semiconductor device. In one or more embodiments, the semiconductor device includes a finFET device. In such embodiments, the n-doped silicon-containing material forms an n-doped source or drain extension disposed between the bulk semiconductor portion of the semiconductor substrate and the gate spacer of the finFET, such an n-doped source or drain. The extension is disposed on the bulk semiconductor portion of the semiconductor substrate. While embodiments of the present disclosure are described for the formation of n-type metal oxide semiconductor (nMOS) and n-doped films, those skilled in the art will recognize that p-doped films can also be formed by similar processes. will be. References to “nMOS” or “n-doped” throughout this disclosure are for convenience of description only and should not be considered as limiting the disclosure to nMOS or n-doped structures. In some embodiments, the methods relate to the formation of p-type metal oxide semiconductor (pMOS) or p-doped films. Some embodiments of the present disclosure relate to processes for forming pMOS devices in which a Source/Drain (SD) includes multiple SiGe and boron layers. In one or more embodiments, SD materials provide compressive stress to pMOS devices, which increases hole mobility. With epitaxial SD layer formation, control of the amount of lateral push can affect the overall performance.

[0023] 1 is a perspective view of a fin-field-effect transistor (finFET) 100, according to an embodiment of the present disclosure. The finFET 100 includes a semiconductor substrate 101, insulating regions 102 formed on the surface of the semiconductor substrate 101, a fin structure 120 formed on the surface of the semiconductor substrate 101, and insulating regions 102. ) And a gate electrode structure 130 formed on the fin structure 120. The uppermost portion of the fin structure 120 is exposed and electrically coupled to the source contact (not shown) of the finFET 100, and the other uppermost portion of the fin structure 120 is exposed to the drain contact (not shown) of the finFET 100. And the central portion of the semiconductor fin 121 includes the channel region of the finFET 100. The gate electrode structure 130 serves as a gate of the finFET 100.

The semiconductor substrate 101 may be a bulk silicon (Si) substrate, a bulk germanium (Ge) substrate, a bulk silicon-germanium (SiGe) substrate, or the like. Insulation regions 102, alternatively referred to as shallow trench isolation (STI), may comprise one or more dielectric materials such as silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or multiple layers thereof. I can. The insulating regions 102 may be formed by high-density plasma (HDP), flowable chemical vapor deposition (FCVD), or the like.

[0025] The fin structure 120 includes a semiconductor fin 121 and fin spacers (not shown for clarity) formed on sidewalls of the semiconductor fin 121. The semiconductor fins 121 may be formed from the semiconductor substrate 101 or from a different semiconductor material deposited on the semiconductor substrate 101. In the latter case, the different semiconductor materials may include silicon-germanium, group III-V compound semiconductor materials, and the like.

[0026] The gate electrode structure 130 includes a gate electrode layer 131, a gate dielectric layer 132, gate spacers 133, and a mask layer 136. In some embodiments, the gate electrode layer 131 includes a polysilicon layer, or a metal layer capped with a polysilicon layer. In other embodiments, the gate electrode layer 131 may include metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), and molybdenum nitride (MoN _x ))), metal carbides ( For example, tantalum carbide (TaC) and hafnium carbide (HfC)), metal-nitride-carbides (such as TaCN), metal oxides (such as molybdenum oxide (MoO _x )), metal oxynitrides. (Such as molybdenum oxynitride (MoO _x N _y )), metal silicides (such as nickel silicide), and combinations thereof. The gate electrode layer 131 may also be a metal layer capped with a polysilicon layer.

The gate dielectric layer 132 may include silicon oxide (SiOx), which may be formed by thermal oxidation of the semiconductor fins 121. In other embodiments, the gate dielectric layer 132 is formed by a deposition process. Suitable materials for forming the gate dielectric layer 132 are silicon oxide, silicon nitrides, oxynitrides, metal oxides, such as HfO ₂ , HfZrO _x , HfSiO _x , HfTiO _x , HfAlO _x and combinations thereof. And multiple layers. The gate spacers 133 are formed on sidewalls of the gate electrode layer 131, and each of the gate spacers 133 may include a nitride portion 134 and/or an oxide portion 135 as shown. I can. In some embodiments, the mask layer 136 may be formed on the gate electrode layer 131 as shown, and may include silicon nitride.

[0028] 2 is a cross-sectional view of finFET 100, according to an embodiment of the present disclosure. The cross-sectional view illustrated in FIG. 2 is taken in section A-A of FIG. 1. As shown, the finFET 100 includes a semiconductor fin 121 having heavily doped regions 201, doped extension regions 202 and channel regions 205. While embodiments herein are described for the formation of nMOS, one of ordinary skill in the art will recognize that the heavily doped region 201 and the doped extension region 202 may be p-doped regions.

The heavily doped regions 201 form the source and drain regions of the finFET 100, and relatively high concentrations of n-dopants (eg, phosphorus (P), arsenic (As), antimony ( Sb), bismuth (Bi), lithium (Li)) or p-dopants (eg, boron (B), aluminum (Al), gallium (Ga) or indium (In)). While zone 201 may be referred to as being n-doped at a high concentration, one of ordinary skill in the art knows that this zone can be a p-doped zone and may contain relatively high concentrations of p-dopants such as boron (B). Will recognize. For example, in some embodiments, the concentration of dopants in heavily doped regions 201 may be as high as 5×10 ²¹ atoms/cm ³ . In some embodiments, the heavily doped region 201 has a dopant concentration ranging from about 1× ^{10 20} atoms/cm ³ to about 1×10 ²² atoms/cm ³ . The heavily doped regions 201 can be created by any suitable doping technique. Since the heavily doped regions 201 are generally not covered by the intervening structure of the finFET 100 upon doping, a linear doping technique such as beamline ion implantation may be used. Alternatively, a conformal doping technique, such as plasma doping (PLA), may be used to form highly doped regions 201, because each highly doped region 201 This is because a significant portion of) is usually exposed during doping.

[0030] Doped extension regions 202 form the source and drain extensions of finFET 100 and include one or more n-dopants. One of skill in the art will recognize that the extension region may be a p-doped region. According to embodiments of the present disclosure, the doped extension regions 202 may contain one or more n-dopants that serve as a diffusion barrier for n-dopants located in the heavily doped regions 201. Include. Thus, since the doped extension regions 202 are disposed between the channel region 205 and the heavily doped regions 201, the n-dopant located in the heavily doped regions 201, such as phosphorus. They cannot spread into the channel region 205. With the small geometries associated with modern finFET devices, the width 133A of the gate spacers 133-this width 133A is also approximately the distance between the heavily doped regions 201-is only a few nanometers. It can be a meter. Therefore, such n-dopant diffusion can be a serious challenge in nMOS devices such as finFET 100. In some embodiments, the doped extended regions 202 include one or more heavier mass atoms (eg, Ge, Sn, etc.) that increase the compressive stress in the channel region 205.

[0031] In some embodiments, n-dopants located in heavily doped regions 201 may include phosphorus. In such embodiments, the n-dopants included in the doped extension regions 202 may include arsenic (As), which is a significant diffusion barrier to phosphorus diffusion, or simply spatial (geometric ) Can serve as an offset. Alternatively or additionally, in such embodiments, the n-dopants included in the doped expansion regions 202 may include antimony (Sb), which antimony (Sb) is also It can serve as a partial barrier to diffusion. In some embodiments, the p-dopants included in zone 201 and zone 202 independently comprise one or more of boron (B), aluminum (Al), gallium (Ga), or indium (In). I can.

[0032] In some embodiments, the doped extension regions 202 are formed with a thickness 202A that is less than the width 133A of the gate spacers 133. For example, in such embodiments, the thickness 202A of the doped extension regions 202 may be approximately 1 nanometer less than the width 133A. Consequently, in such embodiments, the doped extension regions 202 do not extend into the channel region 205.

[0033] Further, according to embodiments of the present disclosure, the doped extension regions 202 are formed through a (SEG) process. Specifically, a cavity is formed in a portion of the semiconductor fin 121, which is disposed between the bulk semiconductor portion of the semiconductor substrate 101 and the gate spacers 133. The cavity is then an n-doped or p-doped semiconductor material, such as an arsenic (As) doped silicon material (e.g., also referred to herein as Si:As) or boron (B) doped silicon. Material (eg, also referred to herein as Si:B). Accordingly, source-drain extensions for finFET 100 are formed in the region of semiconductor fin 121, between the bulk semiconductor portion of semiconductor substrate 101 and the existing structure of semiconductor fin 121. Further, the n-dopants included in the doped extension regions 202 may be selected to serve as a diffusion barrier for n-dopants located in the heavily doped regions 201. It is noted that due to the presence of the gate spacers 133, the doped extension regions 202 cannot be formed by beamline ion implantation or PLAD. Various embodiments that allow doped extension regions 202 to be formed in finFET 100 are described below in conjunction with FIGS. 3 and 4A-4E.

[0034] 3 is a flow diagram of a fabrication process 300 for forming an nMOS finFET, in accordance with various embodiments of the present disclosure. Those of skill in the art will recognize that pMOS finFETs can be formed by similar manufacturing processes. 4A-4E are schematic cross-sectional views of a semiconductor device, such as finFET 100 of FIG. 1, corresponding to various stages of process 300, in accordance with various embodiments of the present disclosure. While a process 300 for forming a doped extension region is illustrated, the process 300 can also be used to form other structures on a substrate.

[0035] Process 300 begins in operation 301, in which operation 301, gate electrode structure 130 and gate spacers 133 are formed on semiconductor fin 121 as shown in FIG. 4A. . In the embodiment illustrated in FIG. 4A, the semiconductor fins 121 are formed as part of the semiconductor substrate 101.

[0036] In operation 302, an anisotropic etching process is performed on a portion of the semiconductor fin 121, which is disposed between the bulk semiconductor portion of the semiconductor substrate 101 and the gate spacers 133. As a result, as illustrated in FIG. 4B, one or more sidewall surfaces 401 of the semiconductor material of the semiconductor fin 121 are exposed. As shown, the sidewall surface 401 is disposed between the bulk semiconductor portion of the semiconductor substrate 101 and the existing structure of the finFET 100. That is, the sidewall surface 401 is disposed between the semiconductor substrate 101 and the gate spacers 133. As a result, the sidewall surface 401 is in the region of the semiconductor fin 121, which is inaccessible to conventional surface-normal line-of-sight ion implantation techniques.

[0037] The anisotropic etching process of operation 302 may be selected to remove sufficient material from semiconductor fins 121 such that sidewall surface 401 has any suitable target length 401A. For example, in some embodiments, the anisotropic etching process of operation 302 is performed such that the sidewall surface 401 has a target length 401A of about 5 nm to about 10 nm. In other embodiments, the sidewall surface 401 is characterized by the geometry of the gate spacers 133, the concentration of n-dopants in the heavily doped regions 201, the dimensions of the channel region 205 and other factors. Depending on the case, it may have a target length 401A of more than 10 nm or less than 5 nm. The anisotropic etch process of operation 302 may be, for example, a deep reactive-ion etch (DRIE) process, and during this deep reactive-ion etch (DRIE) process, the gate spacers 133 and other parts of the finFET 100 Are masked.

[0038] In operation 303, an isotropic etching process is performed on the sidewall surface 401 to form one or more cavities 402 in the material of the semiconductor fin 121, as illustrated in FIG. 4C. As shown, each cavity 402 has a surface 403. In addition, each cavity 402 is disposed between the bulk semiconductor portion of the semiconductor substrate 101 and the existing structure of the finFET 100 (ie, one of the gate spacers 133 ). As a result, portions of the cavities 402 are each in a region of the semiconductor fin 121 that is inaccessible to the linear ion implantation technique.

[0039] The isotropic etching process of operation 303 may be selected to remove sufficient material from semiconductor fins 121 such that cavity 402 has any suitable target width 402A. For example, in some embodiments, the isotropic etching process of operation 303 is performed such that the cavity 402 has a target width 402A of about 2 nm to about 10 nm. In other embodiments, the sidewall surface 401 depends on the geometry of the gate spacers 133, the concentration of n-dopants or p-dopants in the heavily doped regions 201 and other factors, It may have a target width 402A greater than 10 nm or less than 2 nm. For example, in some embodiments, the target width 402A may be selected such that the cavities 402 have a target width 402A that is less than the width 133A of the gate spacers 133 by about 1 nm or less. have.

The isotropic etching process of operation 303 may include any suitable etching process selective to the semiconductor material of the semiconductor fin 121. For example, when the semiconductor fin 121 comprises silicon (Si), the isotropic etching process of operation 303 may be a HCl-based chemical vapor etch (CVE) process, an HCl-based and GeH ₄ -based CVE process and/or It may include one or more of the Cl ₂ -based CVE processes. In some embodiments, the isotropic etching process of operation 303 includes one or more of a wet etching process or a dry etching process. In some embodiments, the isotropic etching process of operation 303 includes a dry etching process.

[0041] In some embodiments, an optional operation 304 is performed, in which operation 304 a pre-deposition cleaning process or other surface preparation process is performed on the surfaces 403 of the cavities 402. The surface preparation process may be performed to remove the native oxide on the surface 403 and to prepare the surface 403 in a different way prior to the (SEG) process performed in operation 305. The surface preparation process may include a dry etch process, a wet etch process, or a combination of both.

[0042] In such embodiments, the dry etch process may include a conventional plasma etch or a remote plasma-assisted dry etch process, such as a SiCoNi ^™ etch process available from Applied Materials, Inc. located in Santa Clara, CA. I can. In the SiCoNi ^™ etching process, the surfaces 403 are exposed to H ₂ , NF ₃ and/or NH ₃ plasma species, such as plasma-excited hydrogen and fluorine species. For example, in some embodiments, surfaces 403 may experience simultaneous exposure to H ₂ , NF ₃ and NH ₃ plasma. The SiCoNi ^TM etching process of operation 304 can be performed in a SiCoNi Preclean chamber, which SiCoNi Preclean chambers are available from Applied Materials, including Centura ^TM , Dual ACP, Producer ^TM GT and Endura platforms, including various multi-processing platforms. Can be incorporated into either. The wet etching process may comprise a hydrofluoric acid last process (HF), i.e., a so-called "HF final" process, wherein the surfaces 403 are subjected to hydrogen-termination. HF etching is performed. Alternatively, in operation 304, any other liquid-based pre-epitaxial pre-clean process may be used. In some embodiments, the process includes sublimation etching for natural oxide removal. The etching process can be plasma or heat based. Plasma processes can be any suitable plasma (eg, conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0043] In some embodiments, the apparatus or process tool is configured to hold the substrate under vacuum conditions to prevent formation of an oxide layer, and a pre-epitaxial pre-clean process is not used. In this kind of embodiments, the process tool is configured to move the substrate from the etch process chamber to the epitaxy chamber without exposing the substrate to atmospheric conditions.

[0044] In operation 305, as illustrated in FIG. 4D, a selective epitaxial growth (SEG) process is performed on the surfaces 403 to grow a layer of deposition material 406, such that the doped extension region Forms 202. Specifically, the deposition material includes a semiconductor material such as silicon, and an n-type dopant. For example, in some embodiments, the deposition material 406 includes Si:As, where the arsenic concentration in the deposition material 406 is selected based on the electrical requirements of the finFET 100. It is noted that Si:As can be deposited via (SEG) at an electroactive dopant concentration of arsenic as high as about 5x10 ²¹ atoms/cm ³ . However, such high arsenic concentrations present in the doped expansion regions 202 will cause an increase in resistivity due to undesired formation of As V (arsenic-vacancy) complexes and arsenic diffusion into the channel region 205. I can. In addition, arsenic-phosphorous-vacancy (AsP V) complexes may be formed in the doped expansion regions 202, resulting in increased diffusion of phosphorus into the channel region 205. Consequently, in some embodiments, the deposition material 406 comprises an electroactive dopant concentration of arsenic of no more than about 5x10 ²⁰ atoms/cm ³ .

[0045] In some embodiments, the deposition material 406 can have a deposition thickness 406A of about 2 nm to about 10 nm. In other embodiments, the deposition material 406 may have a deposition thickness 406A that is greater than 10 nm for certain configurations of the finFET 100. In some embodiments, the deposition thickness 406A is selected such that the deposition material 406 completely fills the cavity 402 as shown in FIG. 4D. In other embodiments, the deposition thickness 406A is selected to cover the exposed surface of the semiconductor fin 121, where the deposition material 406 partially fills the cavity 402 and forms the cavity 402. do.

[0046] A suitable SEG process in operation 305 may include specific process temperatures and pressures, process gases and gas flows selected to enable selective growth of a particular n-doped or p-doped semiconductor material. Can include. In embodiments where the specific n-doped semiconductor material comprises Si:As, the doping gas used in the SEG process of operation 305 is AsH ₃ , As(SiH ₃ ) ₃ , AsCl _3, or tertiary butylarsine. (TBA) may be included. Other gases used in the SEG process may include dichlorosilane (DCS), HCl, SiH ₄ , Si ₂ H ₆ and/or Si ₄ H ₁₀ . In such embodiments, the SEG process of operation 305 may be performed in an atmospheric or high sub-atmospheric pressure chamber with a low H ₂ carrier gas flow. For example, in such embodiments, the process pressure in the processing chamber performing the SEG process may be on the order of 20-700 T. In such embodiments, high reactor pressure and low dilution (due to low carrier gas flow) yields high arsenic and high dichlorosilane (H ₂ SiCl ₂ or DCS) partial pressures from surface 403 during the SEG process. It can promote the removal of chlorine (Cl) and excess arsenic. As a result, high film growth rates and associated high arsenic incorporation rates are realized, and good crystal quality can be achieved. In some embodiments, the doping gas used provides a p-doped semiconductor material. In some embodiments, the p-doped semiconductor material includes one or more of boron (B), aluminum (Al), gallium (Ga), or indium (In). In some embodiments, the doping precursor includes one or more of borane, diborane, or plasmas thereof.

[0047] The SEG process of operation 305 is in any suitable processing chamber, such as a processing chamber integrated into one of a variety of multi-processing platforms including Producer ^TM GT, Centura ^TM AP and Endura platforms available from Applied Materials. Can be done. In such embodiments, the SiCoNi ^™ etch process of operation 304 may be performed in another chamber of the same multi-processing platform.

[0048] In operation 306, a second SEG process is performed in which heavily doped regions 201 are formed, as illustrated in FIG. 4E. The heavily doped regions 201 are formed on the doped expansion regions 202. The heavily doped regions 201 may be formed of any suitable semiconductor material including doped silicon, doped silicon germanium, doped silicon carbon, and the like. The dopant or dopants may include any suitable n-dopant such as phosphorus. For example, in some embodiments, heavily doped regions 201 may include phosphorus-doped silicon (Si:P). Any suitable SEG process can be used to form heavily doped regions 201. The thickness of the heavily doped regions 201 and other film properties may be selected based on the electrical requirements of the finFET 100, the size of the finFET 100, and other factors.

[0049] In some embodiments, the second SEG process is performed in the same process chamber as the SEG process of operation 305. Thus, the doped extension regions 202 may be formed in a step that is in fact a pre-deposition step during the formation of the heavily doped regions 201. As a result, in such embodiments, a dedicated process chamber for forming the doped expansion regions 202 is not required, and from the first process chamber (to perform the SEG of the doped expansion regions 202). The additional time to transfer the substrate to the second process chamber (for performing the SEG of heavily doped regions 201) is avoided. In addition, the deposition material 406 is not exposed to air in such embodiments. Alternatively, in some embodiments, the second SEG process is performed in a different process chamber than the SEG process of operation 305 to reduce the number of process chambers exposed to dangerous dopants such as arsenic. In such embodiments, both chambers are integrated into the same multi-processing platform, so that vacuum breakdown and exposure of the deposition material 406 to air can be avoided.

[0050] After operation 306, the remaining components of finFET 100 can be completed using conventional fabrication techniques.

[0051] The implementation of the process 300 allows the formation of doped extension regions 202 at precisely defined locations, ie in the region of the semiconductor fin 121 that is difficult to access with conventional ion implantation techniques. In addition, the process by which the doped extension region 202 is formed is incorporated into the existing selective epitaxial growth step already used in the fabrication of the finFET, so that disturbances to the process flow to form the finFET will be minimized or eliminated. I can. In addition, implantation damage, i.e. defects due to heavy mass ion implantation, such as silicon fissures, or even silicon amorphization, as well as between such crystal defects and high concentrations of arsenic and/or phosphorus. Any harmful interactions are avoided. Therefore, there is no need for post implant anneal or the associated additional thermal budget to affect the processes. In addition, when the SEG process of operation 305 is performed in the same process chamber as the SEG process of operation 306 or in different process chambers on the same multi-processing platform, additional pre-clean-related material losses are also This is avoided because vacuum breakdown does not occur between the deposition of the doped extension regions 202 and the heavily doped regions 201.

[0052] As is well known in the art, the introduction of tensile strain into the channel region of the nMOS finFET can increase the charge mobility in the nMOS finFET. Also, as described herein, the formation of an epitaxially grown Si:As material adjacent to the channel region 205 of the semiconductor fin 121 can introduce significant tensile strain to the channel region 205. For example, in accordance with some embodiments of the present disclosure, n-doped expansion regions may be deposited at a concentration of arsenic sufficient to cause a target tensile strain within the doped expansion regions 202. Thus, in embodiments where the deposition material 406 comprises epitaxially grown Si:As, an additional advantage of the formation of doped extension regions 202 in finFET 100 is channel region 205 The formation of these n-doped extension regions allows for improved charge mobility as a result of the tensile strain introduced into this channel region 205. In some embodiments, for example germanium (Ge), antimony (Sb) and/or tin (Sn) are doped with a p-doped extension region to provide compressive stress to the channel.

[0053] In some embodiments, an optional carbon-containing layer is formed in the cavities 402. In such embodiments, the carbon-containing layer may be a liner between the doped expansion region 202 and the heavily n-doped region 201. One such embodiment is illustrated in FIG. 5.

5 is a schematic cross-sectional view of finFET 100 after formation of cavities 402, according to various embodiments of the present disclosure. As shown, a carbon-containing layer 501 is deposited on the surface 407 of the deposition material 406. The presence of carbon (C) can increase the diffusion of arsenic while reducing the diffusion of phosphorus. Thus, in some embodiments, the carbon-containing layer 501 includes about 0.5% to about 1.0% carbon. In such embodiments, the carbon-containing layer 501 may further include phosphorus of, for example, about 1x10 ²⁰ atoms/cm ³ to about 5x10 ²⁰ atoms/cm ³ . Such a carbon-containing layer can be grown at a process temperature of about 650° C.±50° C. in an atmospheric or near atmospheric SEG chamber. Thus, in embodiments where the carbon-containing layer 501 comprises Si:C:P, Si:P (highly n-doped region 201), Si:C:P (carbon-containing layer ( 501)) and Si:As (doped expansion regions 202). Such a triple layer structure can cause diffusion of arsenic away from the channel region 205 and towards the highly n-doped region 201.

[0055] In some embodiments, as part of the nanowire structure, an n-doped semiconductor material may be formed in regions of the nanowire structure that are not accessible through conventional ion implantation techniques. The formation of one such embodiment is described below in conjunction with FIGS. 6 and 7A-E.

[0056] 6 is a flow diagram of a manufacturing process 600 for forming a nanowire structure 700, in accordance with various embodiments of the present disclosure. 7A-7E are schematic cross-sectional views of nanowire structure 700, corresponding to various stages of process 600, according to embodiments of the present disclosure. Although a process 600 for forming n-doped regions in a nanowire structure is depicted, process 600 can also be used to form other structures on a substrate.

[0057] Process 600 begins at operation 601, at which operation 601, alternating silicon layers 710 and silicon-germanium (SiGe) layers on the bulk semiconductor substrate 701 as illustrated in FIG. 7A. Are formed. The bulk semiconductor substrate 701 may be formed of silicon, silicon germanium, or any other suitable bulk crystalline semiconductor material. The silicon layers 710 and the silicon-germanium layers 720 may each be formed through an SEG process, and may typically include a crystalline semiconductor material.

[0058] In operation 602, silicon layers 710 and silicon-germanium layers 720 are vertical sidewalls 711 on silicon layers 710 and vertical sidewalls on silicon-germanium layers 720 as illustrated in FIG. 7B. Patterned and etched to expose s 721. In some embodiments, operation 602 includes a DRIE process.

[0059] In operation 603, silicon-germanium layers 720 are selectively etched inward from vertical sidewalls 721 to form cavities 706 as illustrated in FIG. 7C. In some embodiments, a chemical vapor etching (CVE) process is used to selectively remove the silicon-germanium layers 720 over the silicon layers 710. For example, a gaseous hydrochloric acid selective etching of SiGe to Si in a reduced pressure-chemical vapor deposition reactor has been demonstrated. Alternatively, in operation 603, after ex-situ HF-dip, a GeH4-reinforced Si etching performed in-situ in an epi reactor. Can be used.

[0060] Then, in operation 604, a low-k material 704 is conformally deposited on the bulk semiconductor substrate 701 as illustrated in FIG. 7D. Low-k material 704 fills at least a portion of cavities 706.

[0061] In operation 605, the low-k material 704 fills the vertical sidewalls 711 on the silicon layers 710 and filled cavities 706 on the silicon-germanium layers 720 as illustrated in FIG. 7E. Patterned and etched to expose. In some embodiments, operation 605 includes a DRIE process. Filled cavities 706 form spacers 702, where each spacer 702 is formed in the edge region 705 of the silicon-germanium layer 720.

In operation 606, portions of silicon layers 710 are selectively removed from edge regions 705 to form cavities 706 as shown in FIG. 7F. Silicon may be removed from edge regions 705 through a CVE process, such as a CVE process selective to silicon over spacers 702. In some embodiments, the CVE process may include one or more of an HCl-based CVE process, an HCl-based and GeH ₄ -based CVE process, and/or a Cl ₂ -based CVE process.

[0063] In operation 607, n-doped silicon material 718 is grown in the cavities 706 through the SEG process as illustrated in FIG. 7G. In some embodiments, the n dopant is arsenic and the n-doped silicon material includes Si:As. In such embodiments, the SEG process of operation 605 may be substantially similar to the SEG process of operation 305 in process 300 presented above.

[0064] In alternative embodiments, the spacers 702 are not selectively etching portions of the silicon-germanium layers 720-then these portions are then filled with low-k material 704- , May be formed by selectively oxidizing portions of the silicon-germanium layers 720.

[0065] Implementation of process 600 enables formation of nanowire structure 700 comprising doped regions, ie cavities 706 filled with n-doped silicon material 708. Because the cavities 706 are disposed between the bulk semiconductor portion of the semiconductor substrate 701 and the existing structure of the nanowire structure 700, it is noted that the doped regions described above are not accessible by linear ion implantation techniques. Noted. As a result, such doped regions cannot be formed through conventional techniques.

[0066] 8 illustrates another embodiment of the present disclosure. Those of skill in the art will recognize that the method 800 illustrated in FIG. 8 may be combined with the process 300 or 600. 8 and 4A-4E, the method 800 begins at 801, where a semiconductor substrate is provided for processing. The semiconductor substrate has a semiconductor material on this semiconductor substrate. As used in this specification and the appended claims, the term “provided” means that the substrate is placed in a position for processing. For example, the substrate may be placed in a first processing chamber for processing.

[0067] In operation 802, an anisotropic etching process is performed on the semiconductor material on the semiconductor substrate. The anisotropic etching process exposes the surface of the semiconductor material. In some embodiments, operation 802 is not performed. The exposed surface of some embodiments is disposed between the bulk semiconductor portion of the semiconductor substrate and the existing structure of the semiconductor device, the semiconductor material being formed on the bulk semiconductor portion of the semiconductor substrate.

[0068] In operation 803, an isotropic etching process is performed on the exposed sidewalls to concave the semiconductor material disposed between the bulk semiconductor portion of the substrate and the existing structure. The side walls are concave by a certain distance, and a cavity is formed. The amount by which the sidewall becomes concave can be varied based on, for example, isotropic etching conditions.

[0069] In operation 804, the distance at which the semiconductor material has been concave by the isotropic etching process is determined. The recess distance can be measured by any suitable technique known to a person skilled in the art. In some embodiments, the recess distance is determined by refractometry.

[0070] In operation 805, a layer of deposition material is formed on the surface of the cavity through a selective epitaxial growth (SEG) process. The substrate of some embodiments does not undergo a pre-clean process between the formation of the cavity and the SEG. In some embodiments, the substrate is not exposed to atmospheric conditions or oxidation conditions between the formation of the cavity and the SEG process.

[0071] The SEG process of some embodiments is adjusted from a predetermined method, based on the distance of the recess. For example, if the predetermined method is configured for a depression depth of 5 Å and the actual measured depression depth is 6 Å, the SEG conditions can be changed to grow a film sufficient to compensate for the difference. In some embodiments, the SEG process is tuned to perform more than one type of growth. For example, if the depth of the depression exceeds a predetermined limit, the SEG process can begin by depositing silicon prior to formation of the doped deposition material.

[0072] In one or more embodiments, operation 803, operation 804, and operation 805 are integrated by using advanced process controls (APC). As used herein, the term “integrated” means that lateral push and epitaxial growth are performed on the same platform (under vacuum processing). In operation 804, an integrated metric may be used to determine the amount of recess distance. In some embodiments, the integrated metrology is performed in situ. Once the concave distance has been determined by integrated metrology, the measurements will be fed to the epitaxial tool, so compensation can be performed (e.g., the thickness/composition of the first epitaxial layer can be adjusted accordingly. ). In some embodiments, the APC includes one or more of scatterometry (ie, optical critical dimension (OCD) measurement), refractometry, ellipsmetry, or e-beam.

[0073] Referring to FIG. 9, additional embodiments of the present disclosure relate to processing tools 900 for performing the methods described herein. 9 illustrates a system 900 that may be used to process a substrate, in accordance with one or more embodiments of the present disclosure. System 900 may be referred to as a cluster tool. The system 900 includes a central transfer station 910, which has a robot 912 therein. The robot 912 is illustrated as a single blade robot; Those of skill in the art will recognize that other robot 912 configurations are within the scope of the present disclosure. The robot 912 is configured to move one or more substrates between chambers connected to the central transfer station 910.

[0074] At least one pre-clean/buffer chamber 920 is connected to the central transfer station 910. The pre-clean/buffer chamber 920 may include one or more of a heater, a radical source, or a plasma source. The pre-clean/buffer chamber 920 may be used as a holding area for an individual semiconductor substrate or a cassette of wafers for processing. The pre-clean/buffer chamber 920 may perform pre-clean processes, or may preheat a substrate for processing, or may simply be a staging area for a process sequence. In some embodiments, there are two pre-clean/buffer chambers 920 connected to the central transfer station 910.

[0075] In the embodiment shown in FIG. 9, the pre-clean chambers 920 may serve as pass through chambers between the factory interface 905 and the central transfer station 910. Factory interface 905 may include one or more robots 906 for moving the substrate from the cassette to the pre-clean/buffer chamber 920. The robot 912 can then move the substrate from the pre-clean/buffer chamber 920 to other chambers in the system 900.

[0076] The first processing chamber 930 may be connected to the central transfer station 910. The first processing chamber 930 may be configured as an anisotropic etch chamber and may be in fluid communication with one or more reactive gas sources for providing one or more flows of reactive gases to the first processing chamber 930. The substrate can be moved to and from the deposition chamber 930 by the robot 912 passing through the isolation valve 914.

[0077] The processing chamber 940 can also be connected to the central transfer station 910. In some embodiments, the processing chamber 940 includes an isotropic etch chamber and is in fluid communication with one or more reactive gas sources to provide flows of reactive gas to the processing chamber 940 to perform the isotropic etch process. do. The substrate can be moved to and from the deposition chamber 940 by the robot 912 passing through the isolation valve 914.

[0078] The processing chamber 945 can also be connected to the central transfer station 910. In some embodiments, processing chamber 945 is the same type of processing chamber 940 configured to perform the same process as processing chamber 940. If the process taking place in the processing chamber 940 takes much longer than the process in the processing chamber 930, this arrangement may be useful.

[0079] In some embodiments, the processing chamber 960 is connected to the central transfer station 910 and is configured to serve as an optional epitaxial growth chamber. The processing chamber 960 may be configured to perform one or more different epitaxial growth processes.

[0080] In some embodiments, the anisotropic etching process occurs in the same processing chamber as the isotropic etching process. In this kind of embodiments, processing chamber 930 and processing chamber 960 may be configured to perform etching processes on two substrates at the same time, and processing chamber 940 and processing chamber 945 are optional. It can be configured to perform epitaxial growth processes.

[0081] In some embodiments, each of the processing chambers 930, 940, 945 and 960 is configured to perform different portions of the processing method. For example, the processing chamber 930 may be configured to perform an anisotropic etching process, the processing chamber 940 may be configured to perform an isotropic etching process, and the processing chamber 945 may be configured as a metrology station or Can be configured to perform one selective epitaxial growth process, and processing chamber 960 can be configured to perform a second epitaxial growth process. One of ordinary skill in the art will recognize that the number and arrangement of individual processing chambers on the tool may be varied and that the embodiment illustrated in FIG. 9 is representative of only one possible configuration.

[0082] In some embodiments, processing system 900 includes one or more metrology stations. For example, metrology stations may be located within the pre-clean/buffer chamber 920, within the central transfer station 910, or within any of the individual processing chambers. The metrology station can be any position within system 900 that allows the distance of the recess to be measured without exposing the substrate to an oxidizing environment.

[0083] At least one controller 950 is coupled to one or more of the central transfer station 910, pre-clean/buffer chamber 920, and processing chambers 930, 940, 945 or 960. In some embodiments, there is more than one controller 950 connected to individual chambers or stations, and a primary control processor is coupled to each of the separate processors to control the system 900. The controller 950 may be any type of general purpose computer processor, microcontroller, microprocessor, or the like that can be used in an industrial field to control various chambers and sub-processors.

[0084] At least one controller 950 includes a processor 952, a memory 954 coupled to the processor 952, input/output devices 956 coupled to the processor 952, and between different electronic components. May have support circuits 958 for communicating in Memory 954 may include one or more of temporary memory (eg, random access memory) and non-transitory memory (eg, storage).

[0085] The processor's memory 954 or computer-readable medium can be easily used, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of digital storage (local or remote). It may be one or more of the available memory. Memory 954 may hold a set of instructions operable by processor 952 to control parameters and components of system 900. Support circuits 958 are coupled to the processor 952 to support the processor in a conventional manner. Circuits may include, for example, cache, power supplies, clock circuits, input/output circuitry, subsystems, and the like.

[0086] Processes may generally be stored in memory as software routines that when executed by a processor cause the process chamber to perform the processes of the present disclosure. The software routine may also be stored and/or executed by a second processor (not shown) located remotely from hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the process may be implemented in software, for example as a custom integrated circuit or other type of hardware implementation, or as a combination of software and hardware, using a computer system in hardware. The software routine, when executed by the processor, converts a general purpose computer into a special purpose computer (controller) that controls chamber operation so that processes are performed.

[0087] In some embodiments, controller 950 has one or more configurations for executing individual processes or sub-processes to perform a method. Controller 950 may be connected to and configured to operate intermediate components to perform the functions of the methods. For example, the controller 950 may be connected to and configured to control one or more of gas valves, actuators, motors, slit valves, vacuum controller, and the like.

[0088] The controller 950 of some embodiments includes a configuration for moving a substrate on a robot between a plurality of processing chambers and a metrology station; A configuration for performing an anisotropic etching process on the substrate; A configuration for performing an isotropic etching process on the substrate in the processing chamber; A configuration for performing an analysis to determine a recess in the semiconductor material at the measurement station; A configuration for performing a selective epitaxial growth process in the epitaxy chamber; A configuration for adjusting a selective epitaxial growth process recipe to account for recesses in the semiconductor material; A configuration for performing a bulk selective epitaxial growth process; It has one or more configurations selected from configurations for loading and/or unloading substrates from the system.

[0089] In summary, one or more embodiments of the present disclosure include regions of doped semiconductor material disposed between the bulk semiconductor portion of the semiconductor substrate and the existing structure of the semiconductor device-the doped silicon-containing material is the bulk semiconductor portion of the semiconductor substrate. Formed on-provides systems and techniques for forming. In embodiments in which the semiconductor device comprises a finFET device, the doped semiconductor material forms a doped source and/or drain extension disposed between the bulk semiconductor portion of the semiconductor substrate and the gate spacer of the finFET, such a doped source or The drain extension is disposed on the bulk semiconductor portion of the semiconductor substrate.

[0090] Reference throughout this specification to “one embodiment”, “specific embodiments”, “one or more embodiments” or “an embodiment” refers to a particular feature, structure, material, or characteristic described in connection with the embodiment. It is meant to be included in at least one embodiment of the present disclosure. Accordingly, appearances of phrases such as "in one or more embodiments", "in certain embodiments", "in one embodiment" or "in an embodiment" in various places throughout this specification are necessarily included in the Not referring to the same embodiment. Further, certain features, structures, materials or properties may be combined in any suitable manner in one or more embodiments.

[0091] While the disclosure herein has been described with reference to specific embodiments, those skilled in the art will understand that the described embodiments merely illustrate the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, this disclosure may include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims (15)

As a method of forming a semiconductor device,
Performing an anisotropic etching process on the semiconductor material to expose the surface of the semiconductor material on the semiconductor substrate, the surface being disposed between the bulk semiconductor portion of the semiconductor substrate and the existing structure of the semiconductor device, the semiconductor material Is formed on the bulk semiconductor portion of the semiconductor substrate;
Performing an isotropic etching process on the exposed sidewalls to form a cavity by concave the semiconductor material disposed between the bulk semiconductor portion of the semiconductor substrate and the existing structure by a predetermined distance; And
Forming a layer of a deposition material on the surface of the cavity through a selective epitaxial growth (SEG) process
Including,
The substrate does not undergo a pre-clean process between the formation of the cavity and the SEG,
A method of forming a semiconductor device. The method of claim 1,
The isotropic etching occurs in a first process chamber, and the method further comprises moving the substrate from the first process chamber to a second process chamber for the SEG process,
A method of forming a semiconductor device. The method of claim 2,
Determining a distance at which the semiconductor material has become concave after the isotropic etching and prior to the SEG process,
A method of forming a semiconductor device. The method of claim 3,
Adjusting the SEG process based on the distance the semiconductor material has become concave,
A method of forming a semiconductor device. The method of claim 4,
Further comprising epitaxially growing a portion of the semiconductor material prior to forming the layer of the deposition material,
A method of forming a semiconductor device. The method of claim 3,
The distance at which the semiconductor material is concave includes refractometry,
A method of forming a semiconductor device. The method of claim 3,
The isotropic etching process comprises an etching process selective to the semiconductor material,
A method of forming a semiconductor device. The method of claim 3,
The step of forming the layer of the deposition material comprises filling the cavity with the deposition material,
A method of forming a semiconductor device. The method of claim 3,
Prior to forming the layer of the deposition material, further comprising depositing a carbon-containing material on the surface of the cavity, the carbon-containing material comprising a silicon-carbon-phosphorus (SiCP) material,
A method of forming a semiconductor device. The method of claim 3,
To form a cavity in the semiconductor material, performing an isotropic etching process on the exposed sidewall includes removing the semiconductor material until a portion of the semiconductor material comprising phosphorus-doped bulk semiconductor material is exposed. Including the step of,
A method of forming a semiconductor device. The method of claim 3,
The deposition material includes an n-type dopant containing arsenic (As), and the SEG (selective epitaxial growth) process includes at least one of AsCl ₃ , TBA or AsH ₃ , and dichlorosilane (DCS), HCl, SiH ₄ , Si ₂ H ₆ or Si ₄ H ₁₀ comprising exposing the surface of the cavity to at least one,
A method of forming a semiconductor device. The method of claim 3,
The deposition material includes a p-type dopant comprising boron (B), and the selective epitaxial growth (SEG) process includes exposing the surface of the cavity to one or more of borane, diborane, or plasmas thereof. doing,
A method of forming a semiconductor device. The method of claim 3,
Forming a layer of an additional deposition material on a portion of the semiconductor material where the anisotropic etching process is not performed through a selective epitaxial growth (SEG) process, wherein the additional deposition material is silicon (Si) and Containing phosphorus (P),
A method of forming a semiconductor device. The method of claim 1,
The isotropic etching process and the SEG process are performed on the same platform under vacuum processing,
A method of forming a semiconductor device. As a processing tool for forming a semiconductor device,
A central transfer station, the central transfer station having a plurality of processing chambers disposed around the central transfer station;
A robot in the central transfer station, configured to move a substrate between the plurality of processing chambers;
A first processing chamber connected to the central transfer station, the first processing chamber configured to perform an isotropic etching process;
A metrology station within the processing tool, accessible to the robot, the metrology station configured to determine a distance of a recess of semiconductor material on a substrate by the isotropic etching process;
A second processing chamber connected to the central transfer station, the second processing chamber configured to perform a selective epitaxial growth (SEG) process; And
A controller connected to at least one of the central transfer station, the robot, the first processing chamber, the metrology station, or the second process chamber
Including,
The controller includes: a first configuration for moving a substrate on the robot between the plurality of processing chambers and the metrology station; A second configuration for performing an isotropic etching process on a substrate in the first processing chamber; A third configuration for performing an analysis to determine a recess in a semiconductor material at the measurement station; Or a fourth configuration for performing a selective epitaxial growth process in the second processing chamber, wherein the selective epitaxial growth process is adapted for the recess of the semiconductor material,
A processing tool for forming semiconductor devices.

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