KR20210015258A - Electroluminescent Device - Google Patents

Abstract

According to the present invention, an electroluminescent display device comprises: a substrate on which first to third pixel regions are defined; a first electrode positioned in each of the first to third pixel regions of an upper portion of the substrate; a bank for covering an edge of the first electrode; a first hole auxiliary layer having at least one side surface surrounded by the bank on the upper portion of the first electrode; a first blocking layer on upper portions of the first hole auxiliary layer and the bank; a light emitting material layer having at least one side surface surrounded by the bank on an upper portion of the first blocking layer; a second blocking layer on upper portions of the light emitting material layer and the first blocking layer; a first electron auxiliary layer on an upper portion of the second blocking layer; and a second electrode on an upper portion of the first electron auxiliary layer. The first hole auxiliary layer has the height increasing as close to the bank, and the first hole auxiliary layers of the first to third pixel regions have different thicknesses from each other. Accordingly, a micro-cavity effect is realized, thereby increasing the light efficiency, and improving the lifespan of the electroluminescent display device.

Description

Electroluminescent device {Electroluminescent Device}

The present invention relates to an electroluminescent display device, and more particularly, to an electroluminescent display device including a light-emitting diode having improved light efficiency.

Electroluminescent Display Device, one of the flat panel display devices, is self-luminous, so it has superior viewing angles compared to Liquid Crystal Display Devices, and it does not require a backlight, so it can be lightweight and thin. , It is also advantageous in terms of power consumption.

In addition, the electroluminescent display device is capable of low-voltage direct current driving, has a fast response speed, and is resistant to external shock because it is all solid, has a wide operating temperature range, and has an advantage of being inexpensive in terms of manufacturing cost.

Such an electroluminescent display device includes a plurality of pixels including red, green, and blue sub-pixels, and selectively emits red, green, and blue sub-pixels to display various color images.

Red, green, and blue subpixels are provided with red, green, and blue light emitting diodes, respectively, and red, green, and blue light emitting diodes include red, green, and blue light emitting materials, respectively.

However, red, green, and blue light emitting materials have characteristics of each other. Accordingly, the red, green, and blue light emitting diodes have different light efficiencies under the same conditions, which reduces the lifespan of the electroluminescent display device.

The present invention has been presented in order to solve the above problems, and is to provide an electroluminescent display device including a light emitting diode having improved light efficiency.

In order to achieve the above object, an electroluminescent display device of the present invention includes: a substrate having first, second, and third pixel regions defined; A first electrode positioned in each of the first, second, and third pixel regions on the substrate; A bank covering an edge of the first electrode; A first hole auxiliary layer on the first electrode, at least one side of which is surrounded by the bank; A first blocking layer over the first hole auxiliary layer and the bank; A light-emitting material layer over the first blocking layer, at least one side of which is surrounded by the bank; A second blocking layer over the light-emitting material layer and the first blocking layer; A first electron auxiliary layer over the second blocking layer; In addition, a second electrode on the first electron auxiliary layer is included, and the first hole auxiliary layer has a height that increases as it approaches the bank.

The bank includes a hydrophilic first bank and a hydrophobic second bank.

The first hole auxiliary layer contacts the top and side surfaces of the first bank and the side surfaces of the second bank.

The first blocking layer contacts the top and side surfaces of the second bank.

A second hole auxiliary layer is further included between the first hole auxiliary layer and the first blocking layer, and the second hole auxiliary layer contacts an upper surface and a side surface of the second bank.

The first bank and the second bank may be formed integrally.

The thickness of the first hole auxiliary layer in the center of the second pixel area is smaller than the thickness of the first hole auxiliary layer in the center of the first pixel area and is greater than the thickness of the first hole auxiliary layer in the center of the third pixel area .

The thickness of the light emitting material layer is less than or equal to the thickness of the first hole auxiliary layer in the center of the third pixel area.

A second electron auxiliary layer may be further included between the first electron auxiliary layer and the second electrode.

At least one thin film transistor is further included between the substrate and the first electrode, and the first electrode is connected to the at least one thin film transistor.

In the present invention, by varying the thickness of the light emitting layer in each pixel region, more specifically, the thickness of the first hole auxiliary layer, the light emitting diodes in each pixel region have a device thickness corresponding to the microcavity effect corresponding to the wavelength of the emitted light. Can have. Accordingly, it is possible to increase the light efficiency and improve the life of the electroluminescent display device.

Since the first hole auxiliary layer is formed through a solution process, it is possible to minimize the number of layers to be laminated and/or the micrometal mask, thereby reducing manufacturing cost and manufacturing process.

In addition, since the first hole auxiliary layer is formed separately for each pixel region, leakage current may be prevented between adjacent pixel regions and crosstalk may be prevented.

In addition, by forming the light emitting material layer through a thermal evaporation process, optical efficiency can be further increased by forming a thinner thickness than the light emitting material layer formed through a solution process.

1 is a schematic diagram of one pixel of an electroluminescent display device according to a first exemplary embodiment of the present invention.
2 is a diagram illustrating energy levels of an electroluminescent display device according to a first exemplary embodiment of the present invention.
3 is a schematic cross-sectional view of an electroluminescent display device according to a first embodiment of the present invention.
4 is an equivalent circuit diagram of one subpixel of the electroluminescent display device according to the first embodiment of the present invention.
5 is a timing diagram schematically illustrating a plurality of signals applied to one subpixel of the electroluminescent display device according to the first embodiment of the present invention.
6 is a schematic plan view of one subpixel of the electroluminescent display device according to the first embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view of one subpixel of the electroluminescent display device according to the first embodiment of the present invention, and illustrates a cross-section corresponding to line VI-VI' of FIG.
8 is a schematic diagram of one pixel of an electroluminescent display device according to a second exemplary embodiment of the present invention.
9 is a schematic cross-sectional view of an electroluminescent display device according to a second exemplary embodiment of the present invention.

Hereinafter, an electroluminescent display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The electroluminescent display according to an exemplary embodiment of the present invention includes red, green, and blue light emitting diodes, and the red, green, and blue light emitting diodes each have a structure to which a microcavity effect is applied. Accordingly, light efficiency can be increased.

In more detail, the light-emitting diode emits a narrow color spectrum by selectively amplifying the wavelength by using the micro-cavity effect that causes interference between the two electrodes, thereby obtaining light of high color purity and It can be made to have high efficiency. In order to implement such a micro-cavity effect, red, green, and blue light emitting diodes have different device thicknesses. Here, the device thickness may be defined as a distance from the lower surface of the first electrode to the lower surface of the second electrode, and the device thickness of the light emitting diode can be implemented by adjusting the distance between the two electrodes, that is, the thickness of the light emitting layer.

<First Example>

1 is a schematic diagram of one pixel of an electroluminescent display device according to a first exemplary embodiment of the present invention.

As shown in FIG. 1, first, second, and third pixel regions P1, P2, and P3 are defined on the substrate 100, and light emitting diodes De are formed in each of the pixel regions P1, P1, and P3. ) Is formed.

Each light-emitting diode De includes a first electrode 162, a light-emitting layer 180, and a second electrode 190, and the light-emitting layer 180 includes a first hole auxiliary layer 182 and a second hole auxiliary layer 183 ), a first blocking layer 184, a light emitting material layer 185, a second blocking layer 186, a first electron auxiliary layer 187, and a second electron auxiliary layer 188.

Here, the first, second, and third pixel regions P1, P2, and P3 may correspond to red, green, and blue subpixels, respectively, and the first, second, and third pixel regions P1, P1, P3 The light emitting diodes De of) may be red, green, and blue light emitting diodes, respectively, but are not limited thereto.

In more detail, a first electrode 162 is formed in each of the first, second, and third pixel regions P1, P2, and P3 on the substrate 100. The first electrode 162 is an anode that supplies holes, and may be made of a conductive material having a relatively high work function. For example, the first electrode 162 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Meanwhile, the electroluminescent display device of the present invention may be of a top emission type in which light from the emission layer 180 is output to the outside through the second electrode 190. In this case, a reflective electrode or a reflective layer may be further formed under the first electrode 162. For example, the reflective electrode or the reflective layer may be made of silver (Ag) or aluminum-palladium-copper (APC) alloy.

Alternatively, the first electrode 162 may include a reflective electrode. In this case, the first electrode 162 may have a stacked structure of ITO/Ag/ITO or ITO/APC/ITO, and the thickness of ITO may be about 10 nm, and the thickness of Ag or APC may be about 100 nm.

The first electrode 162 is formed separately for each of the first, second, and third pixel regions P1, P2, and P3.

Subsequently, a light emitting layer 180 is formed on the first electrode 162 of each of the pixel regions P1, P2, and P3.

The light emitting layer 180 includes a first hole auxiliary layer 182 and a second hole auxiliary layer 183, a first blocking layer 184, a light emitting material layer 185, which are sequentially positioned from the top of the first electrode 162, A second blocking layer 186, a first electron assisting layer 187, and a second electron assisting layer 188 are included.

The first hole auxiliary layer 182 is a hole injection layer (HIL) and serves to smoothly inject holes from the first electrode 162 into the light emitting material layer 185.

The first hole auxiliary layer 182 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a solution process. The first, second, and third pixel regions ( Each P1, P2, P3) has different thickness and is formed separately.

That is, the first hole auxiliary layers 182a, 182b, 182c at the centers of the first, second, and third pixel regions P1, P2, and P3 have first, second, and third thicknesses t1, t2, t3), and the second thickness t2 is larger than the third thickness t3 and smaller than the first thickness t1. In this case, the first thickness t1 may be 100 nm to 150 nm, the second thickness t2 may be 60 nm to 110 nm, and the third thickness t3 may be 30 nm to 90 nm. However, the present invention is not limited thereto.

The first hole auxiliary layer 182 may be made of a material having relatively high electrical mobility, and the electrical mobility of the first hole auxiliary layer 182, that is, the hole mobility is 10 ^-3 cm ² /V·s or more. It is desirable. The first hole auxiliary layer 182 is an aromatic compound including thiophene and/or sulfonate, or an aromatic compound including alkyl and/or alkoxy. amine) compound. For example, the first hole auxiliary layer 182 may be formed of PEDOT:PSS, but is not limited thereto.

The second hole auxiliary layer 183 above the first hole auxiliary layer 182 is a hole transport layer (HTL), and holes from the first electrode 162 are smoothly transferred to the light emitting material layer 185 Plays a role.

The second hole auxiliary layer 183 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the second hole auxiliary layers 183 in the first, second, and third pixel regions P1, P2, and P3 are connected to each other and have the same thickness.

In this case, the thickness of the second hole auxiliary layer 183 may be 50 nm to 100 nm. The thickness of the second hole auxiliary layer 183 may be larger than the third thickness t3 and smaller than the second thickness t2, but is not limited thereto.

The first blocking layer 184 on the second hole auxiliary layer 183 is an electron blocking layer (EBL), and electrons in the light emitting material layer 185 are the second hole auxiliary layer 183 Blocks from moving to.

The first blocking layer 184 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the first blocking layers 184 of the first, second, and third pixel regions P1, P2, and P3 are connected to each other and have the same thickness.

Here, the thickness of the first blocking layer 184 may be 5 nm to 10 nm, but is not limited thereto.

Each of the second hole auxiliary layer 183 and the first blocking layer 184 may be formed of an amine compound or a carbazole compound.

For example, each of the second hole auxiliary layer 183 and the first blocking layer 184 may be selected from compounds represented by Formula 1 below. At this time, the LUMO (lowest unoccupied molecular orbital) energy level of the first blocking layer 184 is preferably higher than the LUMO energy level of the second hole auxiliary layer 183 and the light emitting material layer 185, which will be described in detail later. do.

[Formula 1]

Next, the light emitting material layer 185 above the first blocking layer 184 is the first, second, and third light emitting material layers corresponding to the first, second, and third pixel regions P1, P2, and P3, respectively. (185a, 185b, 185c).

The first, second, and third light-emitting material layers 185a, 185b, and 185c are each of the first, second, and third pixels through a thermal evaporation process using a fine metal mask. It is formed separately for each of the regions P1, P2, and P3.

The first light-emitting material layer 185a is made of a red light-emitting material that emits red light, the second light-emitting material layer 185b is made of a green light-emitting material that emits green light, and the third light-emitting material layer 185c May be made of a blue light emitting material that emits blue light.

The red light-emitting material may be made of a carbazole derivative, a fluorene derivative, an imidazole derivative, or a naphthalene derivative, and the green light-emitting material may be made of a carbazole derivative or a fluorene derivative. In addition, the blue light-emitting material may be formed of a distyrylarylene derivative, an anthracene derivative, or a pyrene derivative.

Here, the thicknesses of the first, second, and third light emitting material layers 185a, 185b, and 185c may be less than or equal to the third thickness t3. In this case, the thickness of the first light-emitting material layer 185a and the second light-emitting material layer 185b is the same, and the thickness of the third light-emitting material layer 185c is that of the first and second light-emitting material layers 185a and 185b. May be less than the thickness. For example, the thickness of the first and second emission material layers 185a and 185b may be 25 nm to 35 nm, and the thickness of the third emission material layer 185c may be 15 nm to 25 nm. However, the present invention is not limited thereto.

The second blocking layer 186 on the top of the light emitting material layer 185 is a hole blocking layer (HBL), and blocks the movement of holes in the light emitting material layer 185 to the first electron auxiliary layer 187 do.

The second blocking layer 186 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the second blocking layers 186 of the first, second, and third pixel regions P1, P2, and P3 are connected to each other and have the same thickness.

In this case, the thickness of the second blocking layer 186 may be 5 nm to 10 nm, but is not limited thereto.

The first electron auxiliary layer 187 on the second blocking layer 186 is an electron transport layer (ETL), which smoothly transfers electrons from the second electrode 190 to the light emitting material layer 185 Plays a role.

The first electron auxiliary layer 187 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the first electron auxiliary layers 187 in the first, second, and third pixel regions P1, P2, and P3 are connected to each other and have the same thickness.

In this case, the thickness of the first electron auxiliary layer 187 may be 10 nm to 20 nm. The thickness of the first electron auxiliary layer 187 may be smaller than the third thickness t3, but is not limited thereto.

Each of the first electron auxiliary layer 187 and the second blocking layer 186 is Alq ₃ , a triazole derivative, a triazine derivative, an oxadiazole derivative, and a phenanthroline. ) Derivatives, quinoxaline derivatives, fluorene derivatives, and benzimidazole derivatives.

For example, each of the first electron auxiliary layer 187 and the second blocking layer 186 may be selected from compounds represented by Formula 2 below.

[Formula 2]

In this case, as shown in FIG. 2, the HOMO energy level of the second blocking layer 186 is lower than the HOMO energy level of the first electron assisting layer 187 and the light emitting material layer 185. desirable.

2 is a diagram illustrating energy levels of an electroluminescent display device according to a first exemplary embodiment of the present invention.

Here, the lower line of each layer is the highest energy level of the valence band through which holes can move, and is called the highest occupied molecular orbital (HOMO) energy level, and the upper line is the conductive band through which electrons can move ( conduction band), the lowest energy level, called LUMO (lowest unoccupied molecular orbital). The difference between the HOMO energy level and the LUMO energy level becomes a band gap.

For the movement of electrons and holes, it is preferable that the difference between the HOMO energy level and the difference between the LUMO energy level of adjacent layers be 0.5 eV or less.

For example, the HOMO energy level of the first hole auxiliary layer 182 may be -5.2 eV and the LUMO energy level may be -3.7 eV. The HOMO energy level of the second hole auxiliary layer 183 may be -5.7 eV, and the LUMO energy level may be -2.6 eV. The HOMO energy level of the first blocking layer 184 may be -5.7 eV and the LUMO energy level may be -2.3 eV. The HOMO energy level of the light emitting material layer 185 may be -6.0 eV and the LUMO energy level may be -2.9 eV. The HOMO energy level of the second blocking layer 186 may be -6.5 eV and the LUMO energy level may be -2.9 eV. The HOMO energy level of the first electron auxiliary layer 187 may be -5.9 eV, and the LUMO energy level may be -3.0 eV.

Meanwhile, the Fermi level of the first electrode 162 may be -4.8 eV, and the Fermi level of the second electron auxiliary layer 188 and the second electrode 192 may be -3.2 eV.

Referring back to FIG. 1, the second electron auxiliary layer 188 on the first electron auxiliary layer 187 is an electron injection layer (EIL), and electrons from the second electrode 190 are used as a light emitting material. It serves to smoothly inject into the layer 185.

The second electron auxiliary layer 188 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the second electron auxiliary layers 188 of the first, second, and third pixel regions P1, P2, and P3 are connected to each other and have the same thickness.

In this case, the thickness of the second electron auxiliary layer 188 may be 1 nm to 2 nm, but is not limited thereto.

For example, the second electron auxiliary layer 188 may be made of LiF, and the second electron auxiliary layer 188 may be omitted.

In the first embodiment of the present invention, the first hole auxiliary layer 182 is formed through a solution process, and the remaining layers of the light emitting layer 180 are formed through a thermal evaporation process. Only a metal mask is needed.

Next, a second electrode 190 is formed on the second electron auxiliary layer 188. The second electrode 190 is a cathode that supplies electrons, may be made of a conductive material having a relatively low work function, and substantially covers the first, second, and third pixel regions P1, P2, and P3. It may be formed on the entire surface of the containing substrate 100.

As mentioned above, the electroluminescent display device of the present invention may be of a top emission type, and in this case, the second electrode 190 may have a relatively thin thickness so that light is transmitted. For example, the thickness of the second electrode 190 may be 8 nm to 13 nm, but is not limited thereto.

The second electrode 190 may be made of aluminum (Al), magnesium (Mg), silver (Ag), or an alloy thereof. As an example, the second electrode 190 may be made of a magnesium and silver alloy. When the second electron auxiliary layer 188 is present, the silver content is greater than the magnesium content, and the second electron auxiliary layer 188 is omitted. In this case, the content of magnesium may be greater than the content of silver.

Meanwhile, a capping layer (CPL) 195 is formed on the second electrode 190. Like the second electrode 190, the capping layer 195 may be substantially formed on the entire surface of the substrate 100, and the capping layer 195 may have a thickness of 50 nm to 100 nm.

The capping layer 195 may be made of an organic material having a relatively high refractive index, and at this time, the wavelength of light traveling along the capping layer 195 is amplified by surface plasma resonance, thereby causing a peak. The intensity of) increases, so that the light efficiency in the top emission type electroluminescent display device can be improved. For example, the capping layer 195 may be made of an amine compound or a carbazole compound.

This capping layer 195 may be omitted.

As described above, in the first embodiment of the present invention, the thickness of the light emitting layer 180 in each pixel region P1, P2, P3, and more specifically, the thickness of the first hole auxiliary layer 182 is different, so that each pixel The light emitting diodes De in the regions P1, P2, and P3 may have a device thickness corresponding to a micro-cavity effect corresponding to the wavelength of the emitted light, thereby increasing light efficiency.

At this time, by forming the first hole auxiliary layer 182 through a solution process, the thickness of the first hole auxiliary layer 182 may be different for each of the first, second, and third pixel regions P1, P2, and P3. . Accordingly, compared to the case of forming the first hole auxiliary layer through the thermal evaporation process, the number of layers to be laminated and/or the micrometal mask can be minimized, and thus manufacturing cost and manufacturing process can be reduced.

In addition, since the first hole auxiliary layer 182 is formed separately for each of the first, second, and third pixel regions P1, P2, P3, the first hole auxiliary layer 182 having relatively high electric mobility A leakage current may be prevented between adjacent pixel regions P1, P2, and P3, and crosstalk may be prevented.

In addition, by forming the light emitting material layer 185 through a thermal evaporation process, the optical efficiency can be further increased by forming a thinner thickness than the light emitting material layer formed through a solution process.

Meanwhile, in the previous embodiment, the top emission type electroluminescent display device has been described, but the present invention is not limited thereto. In the present invention, the light from the emission layer 180 is output to the outside through the first electrode 162. It can also be applied to a bottom emission type electroluminescent display device.

A cross-sectional structure of the electroluminescent display device according to the first embodiment of the present invention will be described in more detail with reference to FIG. 3.

3 is a schematic cross-sectional view of an electroluminescent display device according to a first embodiment of the present invention.

As shown in FIG. 3, first, second, third, fourth, and fifth insulating films on the substrate 100 on which the first, second, and third pixel regions P1, P2, and P3 are defined ( 110, 120, 130, 140, 150) are sequentially formed. The first, second, and third pixel regions P1, P2, and P3 may be red, green, and blue subpixel regions, respectively.

Although not shown, at least one thin film transistor and at least one capacitor may be formed in each of the pixel regions P1, P2, and P3 between the substrate 100 and the fifth insulating layer 150.

The substrate 100 may be a glass substrate or a plastic substrate. As an example, polyimide may be used as a plastic substrate, but is not limited thereto.

Here, the first insulating layer 110 is a buffer layer, the second insulating layer 120 is a gate insulating layer, the third insulating layer 130 is a first interlayer insulating layer, and the fourth insulating layer 140 is a second interlayer insulating layer, and 5 The insulating layer 150 may be an overcoat layer. However, the present invention is not limited thereto, and the type and number of the insulating layers 110, 120, 130, 140, and 150 formed on the substrate 100 may be changed as necessary.

A first electrode 162 is formed in each of the pixel regions P1, P2, and P3 on the fifth insulating layer 150. The first electrode 162 is a conductive material having a relatively high work function, and is formed separately for each of the first, second, and third pixel regions P1, P2, and P3.

Although not shown, the first electrode 162 is electrically connected to the drain electrode of at least one thin film transistor.

A hydrophilic first bank 172 is formed on the first electrode 162. The first bank 172 overlaps the edge of the first electrode 162 and covers the edge of the first electrode 162. At this time, the first bank 172 makes contact with a part of the upper surface and the side surface of the first electrode 162.

The first bank 172 may be formed of a material having hydrophilic properties, for example, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx). Alternatively, the first bank 172 may be formed of polyimide.

In addition, a hydrophobic second bank 174 is formed on the first bank 172. At this time, at least an upper surface of the second bank 174 may be hydrophobic, and a side surface of the second bank 174 may be hydrophobic or hydrophilic.

The second bank 174 has a narrower width than the first bank 172 and exposes an edge of the first bank 172. For example, the width of the first bank 172 may be 13 μm to 15 μm, and the width of the second bank 174 may be 20 μm to 25 μm, but is not limited thereto.

The second bank 174 may overlap the edge of the first electrode 162. Alternatively, the second bank 174 may be spaced apart without overlapping with the first electrode 162.

In addition, the second bank 174 has a thickness thicker than that of the first bank 172. For example, the thickness of the first bank 172 may be 0.2 μm to 0.5 μm, and the thickness of the second bank 174 may be 1 μm to 1.5 μm, but is not limited thereto.

The second bank 174 may be formed of an organic insulating material having hydrophobic properties. Alternatively, the second bank 174 may be formed of an organic material having hydrophilic properties and then subjected to hydrophobic treatment.

Meanwhile, the hydrophilic first bank 172 and the hydrophobic second bank 174 are made of the same material and may be integrally formed. As an example, a first bank 172 having a different width and thickness is formed by forming an organic material layer having a hydrophobic upper surface on the entire surface of the substrate 100 and then patterning it using a mask including a transmissive portion, a blocking portion, and a semi-transmissive portion. And a second bank 174 may be formed.

The first bank 172 and the second bank 174 expose the central portion of the first electrode 162, and the emission layer 180 is formed on the exposed first electrode 162. The light emitting layer 180 includes a first hole auxiliary layer 182 and a second hole auxiliary layer 183, a first blocking layer 184, a light emitting material layer 185, which are sequentially positioned from the top of the first electrode 162, A second blocking layer 186, a first electron assisting layer 187, and a second electron assisting layer 188 are included. Here, the first hole auxiliary layer 182 is formed through a solution process, and the second hole auxiliary layer 183, the first blocking layer 184, the light emitting material layer 185, and the second blocking layer 186 , The first electron auxiliary layer 187 and the second electron auxiliary layer 188 are formed through a thermal evaporation process.

In more detail, a first hole auxiliary layer 182 is formed on the exposed first electrode 162. At least one side of the first hole auxiliary layer 182 is surrounded by the second bank 174, and contacts the top and side surfaces of the first bank 172 and the side surfaces of the second bank 174.

The first hole auxiliary layer 182 is formed by being separated and having different thicknesses for each of the first, second, and third pixel regions P1, P2, and P3. That is, the first hole auxiliary layers 182a, 182b, 182c at the centers of the first, second, and third pixel regions P1, P2, and P3 have first, second, and third thicknesses t1, t2, t3), and the second thickness t2 is larger than the third thickness t3 and smaller than the first thickness t1.

The first hole auxiliary layer 182 is formed through a solution process. At this time, a portion of the first hole auxiliary layer 182 in contact with the first electrode 162 has a uniform thickness and height, and the closer to the second bank 174 the height of the first hole auxiliary layer 182 is It gets higher. That is, when the solution is dried, due to the difference in the drying rate of the solvent in the portion adjacent to the second bank 174 and the other portion, the first hole auxiliary layer 182 in the portion adjacent to the second bank 174 is The closer to the bank 174, the higher its height.

The solution process may be a spin coating method, an inkjet printing method, or a screen printing method, but is not limited thereto.

A second hole auxiliary layer 183 is formed on the first hole auxiliary layer 182. The second hole auxiliary layer 183 may be formed substantially on the entire surface of the substrate 100.

The second hole auxiliary layer 183 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the second hole auxiliary layer 183 is located above the first electrode 162 and also on the side and upper surfaces of the second bank 174 and contacts the side and upper surfaces of the second bank 174. In addition, the second hole auxiliary layers 183 of the first, second, and third pixel regions P1, P2, and P3 are connected to each other to be integrally formed and have the same thickness.

A first blocking layer 184 is formed on the second hole auxiliary layer 183. The first blocking layer 184 may be formed substantially on the entire surface of the substrate 100.

The first blocking layer 184 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the first blocking layer 184 is located above the first electrode 162 and also on the side and upper surfaces of the second bank 174, and the first, second, and third pixel regions P1, P2, P3 The first blocking layers 184 of are connected to each other to be integrally formed, and have the same thickness.

Next, a light emitting material layer 185 is formed on the first blocking layer 184. The light-emitting material layer 185 includes first, second, and third light-emitting material layers 185a, 185b, and 185c respectively corresponding to the first, second, and third pixel regions P1, P2, and P3. Each of the first, second, and third light emitting material layers 185a, 185b, and 185c is surrounded by a second bank 174 and has a substantially uniform thickness in each of the pixel regions P1, P2, and P2. . Here, each of the first, second, and third light emitting material layers 185a, 185b, and 185c of the first, second, and third pixel regions P1, P2, and P3 is a lower first hole auxiliary layer 182 ), the height may increase as the portion adjacent to the second bank 174 gets closer to the second bank 174.

The first light-emitting material layer 185a is made of a red light-emitting material that emits red light, the second light-emitting material layer 185b is made of a green light-emitting material that emits green light, and the third light-emitting material layer 185c May be made of a blue light emitting material that emits blue light.

The first, second, and third light-emitting material layers 185a, 185b, and 185c are formed separately for each of the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process using a fine metal mask. do. That is, the first light-emitting material layer 185a is formed in the first pixel region P1 through a thermal evaporation process using a first micrometal mask, and the second light-emitting material layer 185b is formed using a second micrometal mask. It is formed in the second pixel region P2 through a thermal evaporation process, and the third light emitting material layer 185c is formed in the third pixel region P3 through a thermal evaporation process using a third micrometal mask.

A second blocking layer 186 is formed on the light emitting material layer 185. The second blocking layer 186 may be formed substantially on the entire surface of the substrate 100.

The second blocking layer 186 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the second blocking layer 186 is also located above the first electrode 162 and the side and upper surfaces of the second bank 174, and the second blocking layer 186 is disposed on the side and the upper surface of the second bank 174. It contacts the first blocking layer 184 located on the upper surface. In addition, the second blocking layers 186 of the first, second, and third pixel regions P1, P2, and P3 are connected to each other to be integrally formed, and have the same thickness.

A first electron auxiliary layer 187 is formed on the second blocking layer 186. The first electron auxiliary layer 187 may be formed substantially on the entire surface of the substrate 100.

The first electron auxiliary layer 187 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the first electron auxiliary layer 187 is also located on the first electrode 162 and on the side and upper surfaces of the second bank 174, and is formed in the first, second, and third pixel regions P1, P2, and P3. ) Of the first electron auxiliary layer 187 are connected to each other to form an integral, and have the same thickness.

A second electron assist layer 188 is formed on the first electron assist layer 187. The second electronic auxiliary layer 188 may be formed substantially on the entire surface of the substrate 100.

The second electron auxiliary layer 188 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the second electron auxiliary layer 188 is also located on the first electrode 162 and on the side surfaces and the upper surface of the second bank 174, and the first, second, and third pixel regions P1, P2, P3 ) Of the second electron auxiliary layer 188 are connected to each other to be integrally formed, and have the same thickness.

A second electrode 190 is formed on the second electron auxiliary layer 188. The second electrode 190 may be formed substantially on the entire surface of the substrate 100. Accordingly, the second electrode 190 is located above the first electrode 162 and also on the side and upper surfaces of the second bank 174, and The second electrodes 190 are connected to each other to be integrally formed, and have the same thickness.

The first electrode 162, the emission layer 180, and the second electrode 190 in each of the pixel regions P1, P2, and P3 form a light emitting diode De.

A capping layer 195 is formed on the second electrode 190. The capping layer 195 may be formed substantially on the entire surface of the substrate 100. Accordingly, the capping layer 195 is located above the first electrode 162 and also on the side surfaces and upper surfaces of the second bank 174, and the capping layer 195 is formed in the first, second, and third pixel regions P1, P2, and P3. The ping layers 195 are connected to each other to be integrally formed, and have the same thickness.

As described above, in the first embodiment of the present invention, a hydrophilic first bank 172 and a hydrophobic second bank 174 covering an edge of the first electrode 162 are formed, and on the first electrode 162 The first hole auxiliary layers 182a, 182b, and 183c separated for each of the pixel regions P1, P2, and P3 are formed through a solution process. Then, the second hole auxiliary layer 183, the first blocking layer 184, the light emitting material layers 185a, 185b, 185c, through a thermal evaporation process on the first hole auxiliary layers 182a, 182b, 183c, The second blocking layer 186, the first electron assisting layer 187, and the second electron assisting layer 188 are sequentially formed, and a fine metal mask is used only when forming the light emitting material layers 185a, 185b, and 185c.

Accordingly, since the number of micrometal masks and/or layers to be stacked can be minimized, manufacturing cost and manufacturing process can be reduced.

In addition, since the first hole auxiliary layers 182a, 182b, 183c are formed separately for each of the first, second, and third pixel regions P1, P2, P3, the first hole auxiliary layer with relatively high electric mobility ( A leakage current may be prevented between adjacent pixel regions P1, P2, and P3 through 182a, 182b, and 183c, and crosstalk may be prevented.

In addition, by varying the thickness of the first hole auxiliary layers 182a, 182b and 183c corresponding to the first, second, and third pixel regions P1, P2, and P3, respectively, the first, second, and third pixels By varying the thickness of the emission layers 180a, 180b, and 180c corresponding to the regions P1, P2, and P3, respectively, a micro-cavity effect may be implemented.

In addition, by forming the light emitting material layers 185a, 185b, and 185c through a thermal evaporation process, optical efficiency may be further increased by forming a thinner thickness compared to the light emitting material layer formed through a solution process.

Each of the subpixels of the electroluminescent display device has the same configuration except for the emission layer, and the configuration of such a subpixel will be described in more detail with reference to FIGS. 4 to 7.

4 is an equivalent circuit diagram of one subpixel of the electroluminescent display device according to the first embodiment of the present invention.

As shown in FIG. 4, one sub-pixel of the electroluminescent display device according to the first embodiment of the present invention includes a driving thin film transistor DTr, first to sixth thin film transistors T1 to T6, and a light emitting diode. De) and storage capacitor (Cst).

Here, the first to sixth thin film transistors T1 to T6 and the driving thin film transistor DTr are p-type thin film transistors in which holes are used as carriers for transferring charges. However, the present invention is not limited thereto, and the first to sixth thin film transistors T1 to T6 and the driving thin film transistor DTr may be n-type thin film transistors in which free electrons are used as carriers to transfer charges.

In more detail, the gate of the first thin film transistor T1 is connected to the n-th scan line that transmits the n-th (n is a natural number) scan signal Scan(n), and the source of the first thin film transistor T1 is It is connected to the first node N1, and the drain of the first thin film transistor T1 is connected to the second node N2. The gate of the second thin film transistor T2 is connected to the nth scan line, the source of the second thin film transistor T2 is connected to the data line supplying the data voltage Vdata, and the second thin film transistor T2 The drain is connected to the third node N3. The gate of the third thin film transistor T3 is connected to the light emission control wiring that transmits the light emission control signal EM(n), and the source of the third thin film transistor T3 is a high potential supplying a high potential voltage VDD. It is connected to the wiring, and the drain of the third thin film transistor T3 is connected to the third node N3. The gate of the fourth thin film transistor T4 is connected to the emission control line, the source of the fourth thin film transistor T4 is connected to the second node N2, and the drain of the fourth thin film transistor T4 is a fourth node. It is connected to (N4). The gate of the fifth thin film transistor T5 is connected to the (n-1)-th scan line that transmits the (n-1)-th scan signal (Scan(n-1)), and the source of the fifth thin film transistor T5 Is connected to the initialization line supplying the initialization voltage Vinit, and the drain of the fifth thin film transistor T5 is connected to the first node N1. The gate of the sixth thin film transistor T6 is connected to the (n-1)-th scan line, the source of the sixth thin film transistor T6 is connected to the initialization line, and the drain of the sixth thin film transistor T6 is connected to the fourth It is connected to node N4.

In addition, the gate of the driving thin film transistor DTr is connected to the first node N1, the source of the driving thin film transistor DTr is connected to the third node N3, and the drain of the driving thin film transistor DTr is zero. It is connected to the 2 node (N2).

Meanwhile, the first capacitor electrode of the storage capacitor Cst is connected to the first node N1, and the second capacitor electrode is connected to the high potential line. Further, the anode of the light emitting diode De is connected to the fourth node N4, and the cathode of the light emitting diode De is connected to the ground. Alternatively, the cathode of the light emitting diode De may be connected to a low-potential wiring supplying a low-potential voltage VSS.

Accordingly, the first node N1 includes the gate of the driving thin film transistor DTr, the source of the first thin film transistor T1, the drain of the fifth thin film transistor T5, and the first capacitor electrode of the storage capacitor Cst. Is connected, the drain of the driving thin film transistor DTr, the drain of the first thin film transistor T1, and the source of the fourth thin film transistor T4 are connected to the second node N2, and a third node N3 ) Is connected to the source of the driving thin film transistor (DTr), the drain of the second thin film transistor (T2), and the drain of the third thin film transistor (T3), and the fourth thin film transistor (T4) is connected to the fourth node (N4). The drain of, the drain of the sixth thin film transistor T6, and the anode of the light emitting diode De are connected.

The storage capacitor Cst stores and maintains the gate voltage and the threshold voltage Vth of the driving thin film transistor DTr until the next frame.

The driving of the subpixel of the electroluminescent display according to the first embodiment of the present invention will be described with reference to FIG. 5.

5 is a timing diagram schematically illustrating a plurality of signals applied to one subpixel of the electroluminescent display device according to the first exemplary embodiment of the present invention, and illustrates one frame.

As shown in FIG. 5, one frame F1 includes first, second, and third sections t11, t12, and t13. Here, the first period t11 is a sensing period, the second period t12 is a programming period, and the third period t13 is a light-emitting period. Here, the first section t11 may include an initialization step.

In the first period t11, the n-th scan signal Scan(n) and the emission control signal EM(n) have a high level. Accordingly, the first to fourth thin film transistors T1 to T4 are turned off.

On the other hand, in the first period t11, the (n-1)-th scan signal Scan(n-1) has a high level and then a low level, and the (n-1)-th scan signal Scan(n-1) When (n-1)) has a low level, the fifth and sixth thin film transistors T5 and T6 are turned on. Accordingly, the initialization voltage Vinit is applied to the first node N1 through the fifth thin film transistor T5 and to the fourth node N4 through the sixth thin film transistor T6, Four nodes (N1, N4) become the initialization voltage (Vinit). Subsequently, the (n-1)-th scan signal Scan(n-1) has a high level, so that the fifth and sixth thin film transistors T5 and T6 are turned off.

Next, in the second period t12, the emission control signal EM(n) has a high level, and the third and fourth thin film transistors T3 and T4 are maintained in a turned-off state.

On the other hand, in the second period t12, the (n-1)-th scan signal Scan(n-1) has a high level and then a low level, and the n-th scan signal Scan(n) has a low level. Have high level

In more detail, when the (n-1)-th scan signal Scan(n-1) has a high level, the fifth and sixth thin film transistors T5 and T6 are turned off, and the n-th scan signal Since (Scan(n)) has a low level, the first and second thin film transistors T1 and T2 are turned on. Accordingly, the data voltage Vdata is supplied to the third node N3 through the second thin film transistor T2 so that the third node N3 becomes the data voltage Vdata. In addition, the initialization voltage Vinit of the first node N1 is discharged through the first thin film transistor T1, and the voltage of the first node N1 is the same as the threshold voltage Vth of the driving thin film transistor DTr. It is discharged until dark, so that the first node N1 becomes a threshold voltage Vth. Subsequently, the n-th scan signal Scan(n) has a high level, so that the first and second thin film transistors T1 and T2 are turned off, and the threshold voltage Vth of the first node N1 is storage It is stored in the capacitor Cst.

Next, when the (n-1)-th scan signal Scan(n-1) goes to a low level, the fifth and sixth thin film transistors T5 and T6 are turned on, and the n-th scan signal Scan( n)) has a high level so that the first and second thin film transistors T1 and T2 are maintained in a turned-off state. In this case, the initialization voltage Vinit is applied to the first node N1 through the fifth thin film transistor T5 and to the fourth node N4 through the sixth thin film transistor T6. Accordingly, the first node N1 becomes the sum of the stored threshold voltage Vth and the applied initialization voltage Vinit, and the fourth node N4 becomes the initialization voltage Vinit.

Next, in the third period t13, the (n-1)-th scan signal Scan(n-1) has a high level, so that the fifth and sixth thin film transistors T5 and T6 are turned off.

On the other hand, the n-th scan signal Scan(n) has a low level and a high level, and the emission control signal EM(n) has a low level. When the n-th scan signal Scan(n) has a low level, the second thin film transistor T2 is turned on and the data voltage Vdata is applied to the third node N3, and the emission control signal EM Since (n)) has a low level, the third and fourth thin film transistors T3 and T4 are turned on, so that the light emitting diode De emits light in response to the data voltage Vdata.

The planar and cross-sectional structures of subpixels of the electroluminescent display device according to the first embodiment of the present invention will be described in more detail with reference to FIGS.

6 is a schematic plan view of one subpixel of the electroluminescent display device according to the first embodiment of the present invention.

As shown in FIG. 6, the scan wiring 122 extending along the first direction is formed. The scan wiring 122 includes first and second scan wirings 122a and 122b spaced apart from each other. The first scan wire 122a corresponds to the (n-1)-th scan wire, and the second scan wire 122b corresponds to the n-th scan wire. The scan wiring 122 may also be referred to as a gate wiring. Here, the second scan wiring 122b may have a protrusion extending along the second direction.

In addition, the emission control wiring 124 and the first capacitor electrode 128 are formed on the same layer of the scan wiring 122 and the same material. The light emission control wiring 124 is located adjacent to the second scan wiring 122b and is spaced apart from the second scan wiring 122b and extends along a first direction, and the first capacitor electrode 128 is a second scan wiring 122b. ) And the light emission control wiring 124.

Subsequently, the second capacitor electrode 132 and the initialization wiring 134 are formed on a layer different from the scan wiring 122. The second capacitor electrode 132 and the initialization wiring 134 may be made of the same material as the scan wiring 122.

The second capacitor electrode 132 is positioned between the second scan wire 122b and the emission control wire 124, overlaps the first capacitor electrode 128 to form a storage capacitor Cst, and the first capacitor electrode 128 ) It has a capacitor hole (132a) on the top. The initialization wiring 134 is positioned adjacent to the first scan wiring 122a and is spaced apart from the first scan wiring 122a and extends along the first direction.

Next, a data line 141 and a high potential line 142 extending along the second direction are formed. The data wiring 141 and the high potential wiring 142 are formed on a layer different from the scan wiring 122, the emission control wiring 124, and the initialization wiring 134, and the scan wiring 122 and the emission control wiring 124 And the initialization wiring 134. The high potential wiring 142 overlaps the first and second capacitor electrodes 128 and 132 and is electrically connected to the second capacitor electrode 132. The data line 141 may be spaced apart from the first capacitor electrode 128 and overlap the second capacitor electrode 132.

In addition, first, second, and third electrode patterns 144, 146, and 148 are formed on the same layer of the same material as the data line 141 and the high potential line 142. The first electrode pattern 144 overlaps and crosses the second scan line 122b, overlaps the first and second capacitor electrodes 128 and 132, and is electrically connected to the first capacitor electrode 128. The second electrode pattern 146 overlaps and crosses the light emission control line 124. The third electrode pattern 148 overlaps and crosses the first scan wiring 122a and also overlaps the initialization wiring 134.

Meanwhile, the semiconductor layer 112 includes first and second scan wirings 122a and 122b, emission control wiring 124, first and second capacitor electrodes 128 and 132, initialization wiring 134, and data wiring ( 141), the high potential wiring 142, and the first, second, and third electrode patterns 144, 146, and 148, respectively. The semiconductor layer 112 may be formed in a pattern in which a plurality of parts are integrally formed, and the first and second scan wires 122a and 122b, the emission control wire 124, the first and second capacitor electrodes 128, 132, the initialization line 134, the data line 141, the high potential line 142, and the first, second, and third electrode patterns 144, 146, and 148 overlap and/or cross. The semiconductor layer 112 becomes an active layer and source and drain regions of each of the first to sixth thin film transistors T1 to T6 and the driving thin film transistor DTr, and impurities may be doped corresponding to the source and drain regions. have.

Here, the first thin film transistor T1 and the second thin film transistor T2 are connected to the second scan wiring 122b to be turned on/off, and the light emission control wiring 124 includes a third thin film transistor T3 and a fourth The thin film transistor T4 is connected to be turned on/off, and the fifth thin film transistor T5 and the sixth thin film transistor T6 are connected to the first scan wiring 122a to be turned on/off. At this time, some of the first and second scan wirings 122a and 122b and the emission control wiring 124 become gate electrodes of the first to sixth thin film transistors T1 to T6, and a part of the emission control wiring 124 Reference numeral 126 becomes a gate electrode of the fourth thin film transistor T4.

In addition, the driving thin film transistor DTr is located between the second scan wiring 122b and the emission control wiring 124, and the driving thin film transistor DTr includes first to fifth thin film transistors T1 to T5 and a storage capacitor. It is connected with (Cst).

Meanwhile, the first electrode 162 is substantially formed on the entire sub-pixel area to cover the first to sixth thin film transistors T1 to T6, the driving thin film transistor DTr, and the storage capacitor Cst. The first electrode 162 is electrically connected to the driving thin film transistor DTr through the fourth thin film transistor T4. Further, the first electrode 162 is shown to be spaced apart from the data line 151, but is not limited thereto. That is, the first electrode 162 may partially overlap the data line 151. In this case, the first electrode 162 may overlap one of the first and second sides facing the data line 151 and may be spaced apart from the other. Alternatively, the first electrode 162 may overlap both the first and second sides facing the data line 151.

Next, a first bank 172 is formed along the first direction. The first bank 172 covers an edge of the first electrode 162 and has a first opening 172a exposing a central portion of the first electrode 162. This first bank 172 has a hydrophilic property.

In addition, a second bank 174 is formed on the first bank 172. The second bank 174 covers an edge of the first electrode 162 and has a second opening 174a exposing a central portion of the first electrode 162. Here, the second bank 174 overlaps with the first bank 172, and the second opening 174a of the second bank 174 has a wider width than the first opening 172a of the first bank 172. Have. Accordingly, the edge of the first bank 172 is exposed through the second opening 174a. This second bank 174 has a hydrophobic property.

Meanwhile, the hydrophilic first bank 172 and the hydrophobic second bank 174 are made of the same material and may be integrally formed.

A light emitting layer (not shown) is formed on the first electrode 162 exposed through the first and second banks 172 and 174.

Next, a second electrode (not shown) is formed substantially on the entire surface of the substrate on the emission layer and the second bank 174.

The first electrode 162, the light emitting layer, and the second electrode constitute a light emitting diode.

FIG. 7 is a schematic cross-sectional view of one subpixel of the electroluminescent display device according to the first embodiment of the present invention, and illustrates a cross-section corresponding to line VI-VI' of FIG. 6.

As shown in FIG. 7, the buffer layer 110 is substantially formed on the entire surface of the substrate 100. The substrate 100 may be a glass substrate or a plastic substrate. As an example, polyimide may be used as a plastic substrate, but is not limited thereto.

The buffer layer 110 may be formed of an inorganic material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), and may be formed of a single layer or multiple layers.

A patterned semiconductor layer 112 is formed on the buffer layer 110. The semiconductor layer 112 may be made of polycrystalline silicon, and the semiconductor layer 112 may be selectively doped with impurities. Alternatively, the semiconductor layer 112 may be made of an oxide semiconductor material.

A gate insulating layer 120 made of an insulating material is formed on the semiconductor layer 112 substantially over the entire surface of the substrate 100. The gate insulating layer 120 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx). Meanwhile, when the semiconductor layer 112 is made of an oxide semiconductor material, the gate insulating layer 120 is preferably made of silicon oxide (SiO ₂ ).

A gate electrode 126 made of a first conductive material such as metal, a light emission control line 124, and a first capacitor electrode 128 are formed on the gate insulating layer 120. Here, the gate electrode 126 is disposed on the semiconductor layer 112 and may be a part of the emission control line 124. In addition, the first capacitor electrode 128 partially overlaps the semiconductor layer 112.

Meanwhile, first and second scan lines 122a and 122b of FIG. 6 are further formed on the gate insulating layer 120 of a first conductive material.

In the electroluminescent display device according to the first embodiment of the present invention, the gate insulating layer 120 is formed on the entire surface of the substrate 100, but the gate insulating layer 120 may be patterned in the same shape as the gate electrode 126.

A first interlayer insulating layer 130 made of an insulating material is formed substantially on the entire surface of the substrate 100 on the gate electrode 126, the emission control line 124, and the first capacitor electrode 128. The first interlayer insulating layer 130 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx). Alternatively, the first interlayer insulating layer 130 may be formed of an organic insulating material such as photo acryl or benzocyclobutene.

A second capacitor electrode 132 made of a second conductive material such as metal is formed on the first interlayer insulating layer 130. The second capacitor electrode 132 overlaps the first capacitor electrode 128 and has a capacitor hole 132a corresponding to the first capacitor electrode 128. The first interlayer insulating layer 130 between the first and second capacitor electrodes 128 and 132 and the first and second capacitor electrodes 128 and 132 forms a storage capacitor Cst.

In addition, an initialization line (134 in FIG. 6) made of a second conductive material is further formed on the first interlayer insulating layer 130.

On the second capacitor electrode 132, a second interlayer insulating layer 140 made of an insulating material is substantially formed on the entire surface of the substrate 100. The second interlayer insulating layer 140 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx). Alternatively, the second interlayer insulating layer 140 may be formed of an organic insulating material such as photo acryl or benzocyclobutene.

The second interlayer insulating layer 140 has a plurality of contact holes. In this case, the plurality of contact holes may also be formed in the first interlayer insulating layer 130 and/or the gate insulating layer 120 under the second interlayer insulating layer 140.

As an example, the second interlayer insulating layer 140 has a first contact hole 140a exposing a part of the semiconductor layer 112 together with the first interlayer insulating layer 130 and the gate insulating layer 120, and the first interlayer insulating layer Together with 130, a second contact hole 140b exposing a part of the first capacitor electrode 128 is provided. In addition, the second interlayer insulating layer 140 has a third contact hole 140c exposing a portion of the lower second capacitor electrode 132. Here, the second contact hole 140b is located in the capacitor hole 132a of the second capacitor electrode 132.

Next, a high potential wiring 142 made of a third conductive material such as metal, a first electrode pattern 144 and a second electrode pattern 146 are formed on the second interlayer insulating layer 140. The high potential wiring 142 is in contact with the second capacitor electrode 132 through the third contact hole 140c, and the first electrode pattern 144 is in contact with the first capacitor electrode 128 through the second contact hole 140b. ), and the second electrode pattern 146 contacts the semiconductor layer 112 through the first contact hole 140a. Here, the second electrode pattern 146 corresponds to the drain electrode of the fourth thin film transistor (T4 in FIG. 6 ).

Further, a data line (141 in FIG. 6) and a third electrode pattern (148 in FIG. 6) are further formed on the second interlayer insulating layer 140 using a third conductive material.

Subsequently, an overcoat layer 150, which is a third insulating film made of an insulating material, is substantially formed on the entire surface of the substrate 100 on the high potential wiring 142 and the first electrode pattern 144 and the second electrode pattern 146. The overcoat layer 150 may have a flat upper surface by reducing a step difference caused by the lower layer. The overcoat layer 150 may be formed of an organic insulating material such as photo acrylic or benzocyclobutene.

The overcoat layer 150 has a drain contact hole 150a exposing a part of the second electrode pattern 156. The drain contact hole 150a may be formed to be spaced apart from the first contact hole 140a. However, the present invention is not limited thereto, and the drain contact hole 150a may be formed to overlap the first contact hole 140a.

Next, a first electrode 162 is formed on the overcoat layer 150 of a conductive material having a relatively high work function. The first electrode 162 contacts the second electrode pattern 146 through the drain contact hole 150a. For example, the first electrode 162 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto. .

Meanwhile, the electroluminescent display according to the first embodiment of the present invention may be a top light emitting type in which light from a light emitting diode is output in a direction opposite to the substrate 100. Accordingly, the first electrode 162 may further include a reflective electrode or a reflective layer formed of a metal material having a high reflectivity under the transparent conductive material. For example, the reflective electrode or the reflective layer may be made of an aluminum-palladium-copper (APC) alloy or silver (Ag). In this case, the first electrode 162 may have a triple layer structure of ITO/APC/ITO or ITO/Ag/ITO, but is not limited thereto.

A first bank 172 is formed on the first electrode 162 of an insulating material. The first bank 172 covers an edge of the first electrode 162 and has a first opening 172a exposing a central portion of the first electrode 162. This first bank 172 has a hydrophilic property.

The first bank 172 may be formed of a material having hydrophilic properties, for example, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx). Alternatively, the first bank 172 may be formed of polyimide.

A second bank 174 is formed on the first bank 172. The second bank 174 has a second opening 174a exposing the central portion of the first electrode 162. Here, the second bank 174 overlaps with the first bank 172, and the second opening 174a of the second bank 174 has a wider width than the first opening 172a of the first bank 172. Have. Accordingly, the width of the first bank 172 is wider than the width of the second bank 174, and the edge of the first bank 172 is exposed through the second opening 174a. In addition, the second bank 174 has a thickness thicker than that of the first bank 172.

The second bank 174 has hydrophobic properties. The second bank 174 may be formed of an organic insulating material having hydrophobic properties. Alternatively, the second bank 174 may be formed of an organic material having hydrophilic properties and then subjected to hydrophobic treatment.

Meanwhile, the hydrophilic first bank 172 and the hydrophobic second bank 174 are made of the same material and may be integrally formed.

The emission layer 180 is formed on the first electrode 162 exposed through the first and second openings 172a and 174a. The light emitting layer 180 includes a first hole auxiliary layer 182 and a second hole auxiliary layer 183, a first blocking layer 184, a light emitting material layer 185, which are sequentially positioned from the top of the first electrode 162, A second blocking layer 186, a first electron assisting layer 187, and a second electron assisting layer 188 are included.

Here, the first hole auxiliary layer 182 is formed through a solution process. At least one side of the first hole auxiliary layer 182 is surrounded by the second bank 174, and contacts the top and side surfaces of the first bank 172 and the side surfaces of the second bank 174. In addition, in a portion adjacent to the second bank 174, the height of the first hole auxiliary layer 182 increases as it approaches the second bank 174.

Meanwhile, the second hole auxiliary layer 183 and the first blocking layer 184, the light emitting material layer 185, the second blocking layer 186, the first electron auxiliary layer 187, and the second electron auxiliary layer 188 ) Is formed through a thermal evaporation process. At this time, the second hole auxiliary layer 183, the first blocking layer 184, the second blocking layer 186, the first electron auxiliary layer 187 and the second electron auxiliary layer 188 are substantially without a fine metal mask. Is formed on the entire surface of the substrate 100, and the light emitting material layer 185 is formed only in a region surrounded by the second bank 174 using a fine metal mask.

Accordingly, the second hole auxiliary layer 183, the first blocking layer 184, the second blocking layer 186, the first electron auxiliary layer 187 and the second electron auxiliary layer 188 are the first electrode ( 162) It is also located on the upper side and the side and upper surface of the second bank 174, the second hole auxiliary layer 183 is in contact with the side and upper surface of the second bank 174.

Here, the light emitting material layer 185 may be made of any one of red, green, and blue light emitting materials. Such a light emitting material may be an organic light emitting material such as a phosphorescent compound or a fluorescent compound, or an inorganic light emitting material such as a quantum dot.

Next, a second electrode 190 made of a conductive material having a relatively low work function is formed on the emission layer 180. The second electrode 190 may be formed substantially on the entire surface of the substrate 100. Accordingly, the second electrode 190 is also located above the first electrode 162 and also on the side and upper surfaces of the second bank 174.

For example, the second electrode 190 may be formed of aluminum, magnesium, silver, or an alloy thereof. In this case, the second electrode 190 has a relatively thin thickness so that light from the emission layer 180 can be transmitted. Alternatively, the second electrode 190 may be formed of a transparent conductive material such as indium-gallium-oxide (IGO), but is not limited thereto.

In addition, a capping layer 195 is formed on the second electrode 190. The capping layer 195 may be formed substantially on the entire surface of the substrate 100.

The first electrode 162, the light emitting layer 180, and the second electrode 190 form a light emitting diode De. Here, the first electrode 162 may serve as an anode, and the second electrode 190 may serve as a cathode, but is not limited thereto.

As mentioned above, in the electroluminescent display device according to the first embodiment of the present invention, light from the light emitting layer 180 of the light emitting diode De is opposite to the substrate 100, that is, the second electrode 190 The upper light emission method may be output to the outside through the light emitting method, and the upper light emission method may have a wider light emitting area than the lower light emission method of the same area, thereby improving luminance and lowering power consumption.

In this case, the light emitting diodes De of each subpixel may have a device thickness corresponding to the micro-cavity effect corresponding to the wavelength of the emitted light, thereby increasing light efficiency. That is, the light emitting diodes De of the red, green, and blue subpixels may have different device thicknesses. Here, the device thickness may be defined as a distance between the first electrode 162 and the second electrode 190, more specifically, the distance between the reflective electrode of the first electrode 162 and the second electrode 190. have.

On the other hand, a protective layer and/or an encapsulation layer (not shown) is formed substantially on the entire surface of the substrate 100 above the capping layer 195 to protect the light emitting diode De by blocking moisture or oxygen flowing from the outside. can do.

<Second Example>

Hereinafter, an electroluminescent display device according to a second embodiment of the present invention will be described with reference to the drawings. The electroluminescent display device according to the second exemplary embodiment of the present invention has a difference in configurations of the first and second hole auxiliary layers compared to the first exemplary embodiment, and descriptions of the same portions are omitted or simplified.

8 is a schematic diagram of one pixel of an electroluminescent display device according to a second exemplary embodiment of the present invention.

As shown in FIG. 8, first, second, and third pixel regions P1, P2, and P3 are defined on the substrate 200, and the light emitting diodes De are defined in each of the pixel regions P1, P1, and P3. ) Is formed.

Each light-emitting diode De includes a first electrode 262, a light-emitting layer 280, and a second electrode 290, and the light-emitting layer 280 includes a first hole auxiliary layer 282 and a first blocking layer 284. ), a light emitting material layer 285, a second blocking layer 286, a first electron assisting layer 287, and a second electron assisting layer 288.

In more detail, a first electrode 262 is formed in each of the first, second, and third pixel regions P1, P2, and P3 on the substrate 200. The first electrode 262 is formed separately for each of the first, second, and third pixel regions P1, P2, and P3.

The first electrode 262 is an anode that supplies holes, and may be made of a conductive material having a relatively high work function. In addition, the first electrode 262 and the first electrode 262 may include a reflective electrode. As an example, the first electrode 262 may be formed of a stacked structure of ITO/Ag/ITO or ITO/APC/ITO.

An emission layer 280 is formed on the first electrode 262 in each of the pixel areas P1, P2, and P3.

The light emitting layer 280 includes a first hole auxiliary layer 282 and a first blocking layer 284 sequentially positioned from the top of the first electrode 262, a light emitting material layer 285, a second blocking layer 286, and 1 electron auxiliary layer 287 and a second electron auxiliary layer 288 are included.

The first hole auxiliary layer 282 is a hole injection layer (HIL) and is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a solution process. The first hole auxiliary layer 282 is formed to have different thicknesses for each of the first, second, and third pixel regions P1, P2, and P3.

That is, the first hole auxiliary layers 282a, 282b, 282c of the first, second, and third pixel regions P1, P2, and P3 are respectively first, second, and third thicknesses t1, t2, and t3. And the second thickness t2 is larger than the third thickness t3 and smaller than the first thickness t1. In this case, the first thickness t1 may be 150 nm to 150 nm, the second thickness t2 may be 110 nm to 220 nm, and the third thickness t3 may be 80 nm to 190 nm. However, the present invention is not limited thereto.

The first hole auxiliary layer 282 may be made of a material having relatively high electrical mobility, and the electrical mobility of the first hole auxiliary layer 282, that is, the hole mobility is 10 ^-3 cm ² /V·s or more. It is desirable. The first hole auxiliary layer 282 is an aromatic compound containing thiophene and/or sulfonate, or an aromatic amine containing alkyl and/or alkoxy. amine) compound. For example, the first hole auxiliary layer 282 may be formed of PEDOT:PSS, but is not limited thereto.

The first blocking layer 284 above the first hole auxiliary layer 282 is an electron blocking layer (EBL), and is formed through a thermal evaporation process to form the first, second, and third pixel regions P1 and P2. It is formed simultaneously in P3). Accordingly, the first blocking layers 284 of the first, second, and third pixel regions P1, P2, and P3 are connected to each other and have the same thickness.

Here, the thickness of the first blocking layer 284 may be 5 nm to 10 nm, but is not limited thereto.

The first blocking layer 284 may be made of an amine compound or a carbazole compound. For example, the first blocking layer 284 may be selected from compounds represented by Formula 1 above.

Next, the light emitting material layer 285 above the first blocking layer 284 is a first, second, and third light emitting material layer corresponding to the first, second, and third pixel regions P1, P2, and P3, respectively. (285a, 285b, 285c).

The first, second, and third light-emitting material layers 285a, 285b, and 285c are separated for each of the first, second, and third pixel areas P1, P2, and P3 through a thermal evaporation process using respective micrometal masks. Is formed.

The first light-emitting material layer 285a is made of a red light-emitting material that emits red light, the second light-emitting material layer 285b is made of a green light-emitting material that emits green light, and the third light-emitting material layer 285c May be made of a blue light emitting material that emits blue light.

The red light-emitting material may be made of a carbazole derivative, a fluorene derivative, an imidazole derivative, or a naphthalene derivative, and the green light-emitting material may be made of a carbazole derivative or a fluorene derivative. In addition, the blue light-emitting material may be formed of a distyrylarylene derivative, an anthracene derivative, or a pyrene derivative.

Here, the thicknesses of the first, second, and third emission material layers 285a, 285b, and 285c may be smaller than the third thickness t3. At this time, the thickness of the first light-emitting material layer 285a and the second light-emitting material layer 285b is the same, and the thickness of the third light-emitting material layer 285c is that of the first and second light-emitting material layers 285a and 285b. May be less than the thickness. For example, the thickness of the first and second light-emitting material layers 285a and 285b may be 25 nm to 35 nm, and the thickness of the third light-emitting material layer 285c may be 15 nm to 25 nm. However, the present invention is not limited thereto.

The second blocking layer 286 on the light-emitting material layer 285 is a hole blocking layer (HBL), and the first, second, and third pixel regions P1, P2, and P3 are formed through a thermal evaporation process. Is formed at the same time. Accordingly, the second blocking layers 286 of the first, second, and third pixel regions P1, P2, and P3 are connected to each other and have the same thickness.

In this case, the thickness of the second blocking layer 286 may be 5 nm to 10 nm, but is not limited thereto.

The first electron-assisting layer 287 on the second blocking layer 286 is an electron transport layer (ETL). The first, second, and third pixel regions P1, P2, and P3 are formed through a thermal evaporation process. ) Is formed at the same time. Accordingly, the first electron auxiliary layers 287 in the first, second, and third pixel regions P1, P2, and P3 are connected to each other and have the same thickness.

In this case, the thickness of the first electron auxiliary layer 287 may be 10 nm to 20 nm. The thickness of the first electron auxiliary layer 287 may be smaller than the third thickness t3, but is not limited thereto.

Each of the first electron auxiliary layer 287 and the second blocking layer 286 is Alq ₃ , a triazole derivative, a triazine derivative, an oxadiazole derivative, and a phenanthroline. ) Derivatives, quinoxaline derivatives, fluorene derivatives, and benzimidazole derivatives.

For example, each of the first electron assistance layer 287 and the second blocking layer 286 may be selected from the compounds represented by Formula 2 above. In this case, the HOMO energy level of the second blocking layer 286 is preferably lower than the HOMO energy level of the first electron auxiliary layer 287 and the light emitting material layer 285.

The second electron assisting layer 288 on the first electron assisting layer 287 is an electron injection layer (EIL), and is used in the first, second, and third pixel regions P1 and P2 through a thermal evaporation process. , P3) are formed simultaneously. Accordingly, the second electron auxiliary layers 288 in the first, second, and third pixel regions P1, P2, and P3 are connected to each other and have the same thickness.

In this case, the thickness of the second electron auxiliary layer 288 may be 1 nm to 2 nm, but is not limited thereto.

For example, the second electron auxiliary layer 288 may be formed of LiF, and the second electron auxiliary layer 288 may be omitted.

In the second embodiment of the present invention, the first hole auxiliary layer 282 is formed through a solution process, and the remaining layers of the light emitting layer 280 are formed through a thermal evaporation process. Only a metal mask is needed.

Next, a second electrode 290 is formed on the second electron auxiliary layer 288. The second electrode 290 is a cathode that supplies electrons, may be made of a conductive material having a relatively low work function, and substantially covers the first, second, and third pixel regions P1, P2, and P3. It may be formed on the entire surface of the included substrate 200.

As mentioned above, the electroluminescent display device of the present invention may be a top emission type, and in this case, the second electrode 290 may have a relatively thin thickness so that light is transmitted. For example, the thickness of the second electrode 290 may be 8 nm to 13 nm, but is not limited thereto.

The second electrode 290 may be made of aluminum (Al), magnesium (Mg), silver (Ag), or an alloy thereof. As an example, the second electrode 290 may be made of a magnesium and silver alloy. If the second electron auxiliary layer 288 is present, the silver content is greater than the magnesium content, and the second electron auxiliary layer 288 is omitted. In this case, the content of magnesium may be greater than the content of silver.

Meanwhile, a capping layer (CPL) 295 is formed on the second electrode 290. Like the second electrode 290, the capping layer 295 may be substantially formed on the entire surface of the substrate 200, and the capping layer 295 may have a thickness of 50 nm to 100 nm.

The capping layer 295 may be made of an organic material having a relatively high refractive index. For example, the capping layer 295 may be made of an amine compound or a carbazole compound.

This capping layer 295 may be omitted.

As described above, in the second embodiment of the present invention, the thickness of the light emitting layer 280 of each pixel region (P1, P2, P3), more specifically, the thickness of the first hole auxiliary layer 282 is different, so that each pixel The light emitting diodes De in the regions P1, P2, and P3 may have a device thickness corresponding to a micro-cavity effect corresponding to the wavelength of the emitted light, thereby increasing light efficiency.

At this time, by forming the first hole auxiliary layer 282 through a solution process, the thickness of the first hole auxiliary layer 282 may be different for each of the first, second, and third pixel regions P1, P2, and P3. . Accordingly, compared to the case of forming the first hole auxiliary layer through the thermal evaporation process, the number of layers to be laminated and/or the micrometal mask can be minimized, and thus manufacturing cost and manufacturing process can be reduced.

In addition, since the first hole auxiliary layer 282 is formed separately for each of the first, second, and third pixel regions P1, P2, P3, the first hole auxiliary layer 282 having relatively high electric mobility A leakage current may be prevented between adjacent pixel regions P1, P2, and P3, and crosstalk may be prevented.

In addition, by forming the light emitting material layer 285 through the thermal evaporation process, the optical efficiency may be further increased by forming a thinner thickness than the light emitting material layer formed through the solution process.

Meanwhile, in the second embodiment of the present invention, the second hole auxiliary layer (183 in FIG. 1) of the first embodiment is omitted, and the thickness of the first hole auxiliary layer 282 is changed to the first hole auxiliary layer of the first embodiment. (182 in FIG. 1) and the thickness of the second hole auxiliary layer (183 in FIG. 1). Accordingly, by further reducing the number of layers to be stacked, manufacturing cost and manufacturing process can be further reduced, and since the first hole auxiliary layer 282 is formed through a solution process, thickness control is easy.

A cross-sectional structure of the electroluminescent display device according to the second embodiment of the present invention will be described in more detail with reference to FIG. 9.

9 is a schematic cross-sectional view of an electroluminescent display device according to a second exemplary embodiment of the present invention.

As shown in FIG. 9, first, second, third, fourth, and fifth insulating layers on the substrate 200 on which the first, second, and third pixel regions P1, P2, and P3 are defined ( 210, 220, 230, 240, 250) are sequentially formed. The first, second, and third pixel regions P1, P2, and P3 may be red, green, and blue subpixel regions, respectively.

Although not shown, at least one thin film transistor and at least one capacitor may be formed in each of the pixel regions P1, P2, and P3 between the substrate 200 and the fifth insulating layer 250.

The substrate 200 may be a glass substrate or a plastic substrate. As an example, polyimide may be used as a plastic substrate, but is not limited thereto.

Here, the first insulating layer 210 is a buffer layer, the second insulating layer 220 is a gate insulating layer, the third insulating layer 230 is a first interlayer insulating layer, and the fourth insulating layer 240 is a second interlayer insulating layer, 5 The insulating layer 250 may be an overcoat layer. However, the present invention is not limited thereto, and the type and number of the insulating layers 210, 220, 230, 240, 250 formed on the substrate 200 may be changed as necessary.

A first electrode 262 is formed in each of the pixel regions P1, P2, and P3 on the fifth insulating layer 250. The first electrode 262 is a conductive material having a relatively high work function, and is formed separately for each of the first, second, and third pixel regions P1, P2, and P3.

Although not shown, the first electrode 262 is electrically connected to the drain electrode of at least one thin film transistor.

A hydrophilic first bank 272 is formed on the first electrode 262. The first bank 272 overlaps the edge of the first electrode 262 and covers the edge of the first electrode 262. At this time, the first bank 272 contacts a portion of the upper surface and the side surface of the first electrode 262.

The first bank 272 may be formed of a material having hydrophilic properties, for example, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx). Alternatively, the first bank 272 may be formed of polyimide.

In addition, a hydrophobic second bank 274 is formed on the first bank 272. At this time, at least an upper surface of the second bank 274 may be hydrophobic, and a side surface of the second bank 274 may be hydrophobic or hydrophilic.

The second bank 274 has a narrower width than the first bank 272 and exposes an edge of the first bank 272. For example, the width of the first bank 272 may be 13 μm to 15 μm, and the width of the second bank 274 may be 20 μm to 25 μm, but is not limited thereto.

The second bank 274 may overlap the edge of the first electrode 262. Alternatively, the second bank 274 may be spaced apart without overlapping with the first electrode 262.

Further, the second bank 274 has a thickness thicker than that of the first bank 272. For example, the thickness of the first bank 272 may be 0.2 μm to 0.5 μm, and the thickness of the second bank 274 may be 1 μm to 1.5 μm, but is not limited thereto.

The second bank 274 may be formed of an organic insulating material having hydrophobic properties. Alternatively, the second bank 274 may be formed of an organic material having hydrophilic properties and then subjected to hydrophobic treatment.

Meanwhile, the hydrophilic first bank 272 and the hydrophobic second bank 274 are made of the same material and may be integrally formed.

The first bank 272 and the second bank 274 expose a central portion of the first electrode 262, and a light emitting layer 280 is formed on the exposed first electrode 262. The light emitting layer 280 includes a first hole auxiliary layer 282 and a first blocking layer 284 sequentially positioned from the top of the first electrode 262, a light emitting material layer 285, a second blocking layer 286, and 1 electron auxiliary layer 287 and a second electron auxiliary layer 288 are included. Here, the first hole auxiliary layer 282 is formed through a solution process, and the first blocking layer 284, the light emitting material layer 285, the second blocking layer 286, and the first electron auxiliary layer 287 And the second electron auxiliary layer 288 is formed through a thermal evaporation process.

In more detail, a first hole auxiliary layer 282 is formed on the exposed first electrode 262. At least one side of the first hole auxiliary layer 282 is surrounded by the second bank 274, contacts the top and side surfaces of the first bank 272, and contacts the side surface of the second bank 274.

The first hole auxiliary layer 282 is formed by being separated and having different thicknesses for each of the first, second, and third pixel regions P1, P2, and P3. That is, the first hole auxiliary layers 282a, 282b, 282c of the first, second, and third pixel regions P1, P2, and P3 are respectively first, second, and third thicknesses t1, t2, and t3. And the second thickness t2 is larger than the third thickness t3 and smaller than the first thickness t1.

The first hole auxiliary layer 282 is formed through a solution process. At this time, a portion of the first hole auxiliary layer 282 in contact with the first electrode 262 has a uniform thickness and height, and the closer to the second bank 274 the height of the first hole auxiliary layer 282 is It gets higher. That is, when the solution is dried, the first hole auxiliary layer 282 in the portion adjacent to the second bank 274 due to the difference in the drying rate of the solvent in the portion adjacent to the second bank 274 and the other portion The closer to the bank 274, the higher its height.

The thickness of the first hole auxiliary layer 282 is thicker than that of the first hole auxiliary layer (182 in FIG. 3) of the first embodiment. The thickness of the first hole auxiliary layer 282 may be equal to the sum of the thickness of the first hole auxiliary layer (182 in FIG. 3) and the thickness of the second hole auxiliary layer (183 in FIG. 3) in the first embodiment.

A first blocking layer 284 is formed on the first hole auxiliary layer 282. The first blocking layer 284 may be formed substantially on the entire surface of the substrate 200.

The first blocking layer 284 is simultaneously formed in the first, second, and third pixel regions P1, P2 and P3 through a thermal evaporation process. Accordingly, the first blocking layer 284 is located on the first electrode 262 and also on the side and upper surfaces of the second bank 274 and contacts the side and upper surfaces of the second bank 274. In addition, the first blocking layers 284 of the first, second, and third pixel regions P1, P2, and P3 are connected to each other to be integrally formed, and have the same thickness.

Next, a light emitting material layer 285 is formed on the first blocking layer 284. The light-emitting material layer 285 includes first, second, and third light-emitting material layers 285a, 285b, and 285c respectively corresponding to the first, second, and third pixel regions P1, P2, and P3. Each of the first, second, and third light emitting material layers 285a, 285b, and 285c is surrounded by a second bank 274 and has a substantially uniform thickness in each of the pixel regions P1, P2, and P2. . Here, each of the first, second, and third light emitting material layers 285a, 285b, and 285c of the first, second, and third pixel regions P1, P2, and P3 is a lower first hole auxiliary layer 282 ), the height may be increased as the portion adjacent to the second bank 274 approaches the second bank 274.

Each of the first, second, and third light-emitting material layers 285a, 285b, and 285c may be made of a light-emitting material that emits any one of red, green, and blue light, and the light-emitting material is a phosphorescent compound or a fluorescent compound. It may be the same organic light-emitting material or an inorganic light-emitting material such as a quantum dot.

The first, second, and third light-emitting material layers 285a, 285b, and 285c are formed separately for each of the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process using a fine metal mask. do.

A second blocking layer 286 is formed on the light emitting material layer 285. The second blocking layer 286 may be formed substantially on the entire surface of the substrate 200.

The second blocking layer 286 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the second blocking layer 286 is also located above the first electrode 262 and the side and upper surfaces of the second bank 274, and the second blocking layer 286 is disposed on the side and the upper surface of the second bank 274. It contacts the first blocking layer 284 located on the upper surface. In addition, the second blocking layers 286 of the first, second, and third pixel regions P1, P2, and P3 are connected to each other to be integrally formed and have the same thickness.

A first electron auxiliary layer 287 is formed on the second blocking layer 286. The first electron auxiliary layer 287 may be formed substantially on the entire surface of the substrate 200.

The first electron auxiliary layer 287 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the first electron auxiliary layer 287 is also located on the first electrode 262 and on the side surfaces and the top surfaces of the second bank 274, and the first, second, and third pixel regions P1, P2, P3 ) Of the first electron auxiliary layer 287 is connected to each other to form an integral, and have the same thickness.

A second electron assist layer 288 is formed on the first electron assist layer 287. The second electron auxiliary layer 288 may be formed substantially on the entire surface of the substrate 200.

The second electron auxiliary layer 288 is simultaneously formed in the first, second, and third pixel regions P1, P2, and P3 through a thermal evaporation process. Accordingly, the second electron auxiliary layer 288 is also located on the first electrode 262 and on the side surfaces and the top surfaces of the second bank 274, and the first, second, and third pixel regions P1, P2, P3 The second electron auxiliary layers 288 of) are connected to each other to be integrally formed and have the same thickness.

A second electrode 290 is formed on the second electron auxiliary layer 288. The second electrode 290 may be formed substantially on the entire surface of the substrate 200. Accordingly, the second electrode 290 is located above the first electrode 262 and also on the side and upper surfaces of the second bank 274, and the first, second, and third pixel regions P1, P2, P3 The second electrodes 290 are connected to each other to be integrally formed, and have the same thickness.

The first electrode 262, the emission layer 280, and the second electrode 290 in each of the pixel regions P1, P2, and P3 form a light emitting diode De.

A capping layer 295 is formed on the second electrode 290. The capping layer 295 may be formed substantially on the entire surface of the substrate 200. Accordingly, the capping layer 295 is located above the first electrode 262 and also on the side and upper surfaces of the second bank 274, and the capping layer 295 is formed in the first, second, and third pixel regions P1, P2, and P3. The ping layers 295 are connected to each other to be integrally formed, and have the same thickness.

Each of the pixel regions P1, P2, and P3 according to the second exemplary embodiment of the present invention may have the same configuration as those shown in FIGS. 4 to 7.

As described above, in the second embodiment of the present invention, a hydrophilic first bank 272 and a hydrophobic second bank 274 covering an edge of the first electrode 262 are formed, and on the first electrode 262 The first hole auxiliary layers 282a, 282b, and 283c separated for each of the pixel regions P1, P2, and P3 are formed through a solution process. Then, the first blocking layer 284, the light emitting material layers 285a, 285b, 285c, the second blocking layer 286, and the first hole auxiliary layers 282a, 282b, 283c through a thermal evaporation process. The 1 electron auxiliary layer 287 and the second electron auxiliary layer 288 are sequentially formed, and a fine metal mask is used only when forming the light emitting material layers 285a, 285b, and 285c.

Accordingly, since the number of micrometal masks and/or layers to be stacked can be minimized, manufacturing cost and manufacturing process can be reduced.

In addition, since the first hole auxiliary layers 282a, 282b, 283c are formed separately for each of the first, second, and third pixel regions P1, P2, P3, the first hole auxiliary layer with relatively high electrical mobility ( A leakage current may be prevented between adjacent pixel regions P1, P2, and P3 through 282a, 282b, and 283c, and crosstalk may be prevented.

In addition, by varying the thickness of the first hole auxiliary layers 282a, 282b, 283c corresponding to the first, second, and third pixel regions P1, P2, and P3, respectively, the first, second, and third pixels By varying the thickness of the emission layers 280a, 280b, and 280c corresponding to the regions P1, P2, and P3, respectively, a micro-cavity effect may be implemented.

In addition, by forming the light emitting material layers 285a, 285b, and 285c through the thermal evaporation process, optical efficiency may be further increased by forming a thinner thickness than the light emitting material layer formed through the solution process.

Meanwhile, in the second embodiment of the present invention, the second hole auxiliary layer (183 in FIG. 1) of the first embodiment is omitted, and the thickness of the first hole auxiliary layer 282 is changed to the first hole auxiliary layer of the first embodiment. (182 in FIG. 1) and the thickness of the second hole auxiliary layer (183 in FIG. 1). Accordingly, by further reducing the number of layers to be stacked, manufacturing cost and manufacturing process can be further reduced, and since the first hole auxiliary layer 282 is formed through a solution process, thickness control is easy.

In the foregoing embodiments, it has been described that the hydrophilic first bank and the hydrophobic second bank are formed both between adjacent subpixels of the same color and between adjacent subpixels of a different color, but are not limited thereto. Alternatively, the hydrophobic second bank may be formed only between adjacent subpixels of different colors, and the hydrophilic first bank may be formed only between adjacent subpixels of the same color.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims. You will understand that you can do it.

100: substrate 162: first electrode
180: light emitting layer 182: first hole auxiliary layer
183: second hole auxiliary layer 184: first blocking layer
185: light-emitting material layer 186: second blocking layer
187: first electronic auxiliary layer 188: second electronic auxiliary layer
190: second electrode 195: capping layer
De: light emitting diodes P1, P2, P3: first, second, and third pixel regions

Claims (11)

A substrate on which first, second, and third pixel regions are defined;
A first electrode positioned in each of the first, second, and third pixel regions on the substrate;
A bank covering an edge of the first electrode;
A first hole auxiliary layer on the first electrode, at least one side of which is surrounded by the bank;
A first blocking layer over the first hole auxiliary layer and the bank;
A light-emitting material layer over the first blocking layer, at least one side of which is surrounded by the bank;
A second blocking layer over the light-emitting material layer and the first blocking layer;
A first electron auxiliary layer over the second blocking layer; And
A second electrode on the first electron auxiliary layer
Including,
The electroluminescent display device having a height of the first hole auxiliary layer increasing as it approaches the bank.
The method of claim 1,
The bank includes a hydrophilic first bank and a hydrophobic second bank.
The method of claim 2,
The first hole auxiliary layer is in contact with an upper surface and a side surface of the first bank and a side surface of the second bank.
The method of claim 2,
The first blocking layer is in contact with an upper surface and a side surface of the second bank.
The method of claim 2,
An electroluminescent display device further comprising a second hole auxiliary layer between the first hole auxiliary layer and the first blocking layer.
The method of claim 5,
The second hole auxiliary layer is an electroluminescent display device in contact with an upper surface and a side surface of the second bank.
The method of claim 2,
An electroluminescent display device in which the first bank and the second bank are integrally formed.
The method of claim 1,
The thickness of the first hole auxiliary layer at the center of the second pixel area is smaller than the thickness of the first hole auxiliary layer at the center of the first pixel area and larger than the thickness of the first hole auxiliary layer at the center of the third pixel area. Electroluminescent display device.
The method of claim 8,
The thickness of the light emitting material layer is less than or equal to the thickness of the first hole auxiliary layer in the center of the third pixel area.
The method of claim 1,
An electroluminescent display device further comprising a second electron assist layer between the first electron assist layer and the second electrode.
The method according to any one of claims 1 to 10,
An electroluminescent display device further comprising at least one thin film transistor between the substrate and the first electrode, wherein the first electrode is connected to the at least one thin film transistor.

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