KR20210013248A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20210013248A
KR20210013248A KR1020210008952A KR20210008952A KR20210013248A KR 20210013248 A KR20210013248 A KR 20210013248A KR 1020210008952 A KR1020210008952 A KR 1020210008952A KR 20210008952 A KR20210008952 A KR 20210008952A KR 20210013248 A KR20210013248 A KR 20210013248A
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South Korea
Prior art keywords
contact plug
metal layer
semiconductor device
laser
substrate
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KR1020210008952A
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Korean (ko)
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KR102262292B1 (en
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류정도
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(주)알엔알랩
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Priority claimed from KR1020180118311A external-priority patent/KR102208545B1/en
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Priority to KR1020210008952A priority Critical patent/KR102262292B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair

Abstract

A method for manufacturing a semiconductor device includes: providing a substrate; forming an insulating layer on a substrate; forming an opening exposing the substrate by etching the insulating layer; forming a contact plug serving as a wiring for electrical connection on the opening and the insulating layer; and forming a metal layer on the contact plug and irradiating a laser to the metal layer, wherein the step of irradiating the laser to the metal layer includes removing a void or a seam in the contact plug by indirectly heating the contact plug by directly heating the metal layer.

Description

반도체 디바이스 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

본 발명은 반도체 디바이스 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device.

반도체 디바이스는 휘발성 기억 장치 및 비휘발성 기억 장치로 구분될 수 있다. 휘발성 기억 장치는 대표적으로 디램(DRAM) 장치 또는 에스램(SRAM) 장치를 포함한다. 비휘발성 기억 장치는 플래시(flash) 기억 장치가 대표적이다.Semiconductor devices can be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices typically include DRAM devices or SRAM devices. A typical nonvolatile memory device is a flash memory device.

한편, 전자 산업이 고도로 발전함에 따라, 반도체 디바이스의 고집적화가 진행되면서 반도체 디바이스 제조 공정에서는 상, 하부 패턴간의 안정적인 전기적 접속을 위해 콘택 플러그를 형성하고 있다.On the other hand, as the electronics industry is highly developed, high integration of semiconductor devices progresses, and in semiconductor device manufacturing processes, contact plugs are formed for stable electrical connection between upper and lower patterns.

그러나, 종래의 방법에 따라 콘택 플러그를 형성하는 경우, 콘택 플러그 내에 보이드(Void)가 발생하게 되고, 이러한 보이드가 후속 공정에서 외부로 노출되어 심(Seam)과 같은 표면 결함으로 나타남으로써 배선 저항 증가가 유발되는 등의 소자 특성 저하가 발생한다.However, when the contact plug is formed according to the conventional method, voids are generated in the contact plug, and these voids are exposed to the outside in a subsequent process and appear as surface defects such as seams, thereby increasing wiring resistance. The deterioration of device characteristics, such as causing an error, occurs.

선행기술문헌: 한국등록특허 10-0465063호Prior Art Document: Korean Patent Registration No. 10-0465063

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 보이드 또는 심이 제거된 콘택 플러그를 포함하는 반도체 디바이스를 제조하는 방법을 제공하고자 한다.In order to solve the above problems, the present invention is to provide a method of manufacturing a semiconductor device including a contact plug from which voids or shims are removed.

다만, 본 실시예가 이루고자 하는 기술적 과제는 상기된 바와 같은 기술적 과제들로 한정되지 않으며, 또 다른 기술적 과제들이 존재할 수 있다.However, the technical problem to be achieved by the present embodiment is not limited to the technical problems as described above, and other technical problems may exist.

상술한 기술적 과제를 달성하기 위한 기술적 수단으로서, 본 발명의 일 실시예는 기판을 제공하는 단계, 상기 기판 상에 절연층을 형성하는 단계, 상기 절연층을 식각하여 상기 기판을 노출시키는 개구부를 형성하는 단계, 상기 개구부 및 상기 절연층 상에 전기적 접속을 위한 배선 역할을 하는 콘택 플러그를 형성하는 단계, 상기 콘택 플러그 상에 메탈층을 형성하는 단계 및 상기 메탈층에 레이저를 조사하는 단계를 포함하고, 상기 메탈층에 레이저를 조사하는 단계는 상기 메탈층을 직접 가열하여 상기 콘택 플러그를 간접 가열함으로써 상기 콘택 플러그 내의 보이드(Void) 또는 심(Seam)을 제거하는 단계를 포함하는 반도체 디바이스 제조 방법을 제공할 수 있다.As a technical means for achieving the above-described technical problem, an embodiment of the present invention includes providing a substrate, forming an insulating layer on the substrate, and etching the insulating layer to form an opening exposing the substrate. And forming a contact plug serving as a wiring for electrical connection on the opening and the insulating layer, forming a metal layer on the contact plug, and irradiating a laser on the metal layer, , In the step of irradiating a laser to the metal layer, a method for manufacturing a semiconductor device comprising the step of removing voids or seams in the contact plug by indirectly heating the contact plug by directly heating the metal layer. Can provide.

일 실시예에 따르면, 반도체 디바이스 제조 방법은 메탈층을 제거하는 단계를 더 포함할 수 있다.According to an embodiment, the method of manufacturing a semiconductor device may further include removing the metal layer.

일 실시예에 따르면, 상기 콘택 플러그와 상기 메탈층 사이에 이들 간의 반응 또는 상호확산을 방지하는 삽입층을 형성하는 단계를 더 포함할 수 있고, 상기 콘택 플러그 상에 상기 삽입층과 상기 메탈층이 구비된 상태에서 상기 레이저를 조사하는 단계를 수행할 수 있다.According to an embodiment, it may further include forming an insertion layer between the contact plug and the metal layer to prevent a reaction or diffusion between them, and the insertion layer and the metal layer are formed on the contact plug. In the provided state, the step of irradiating the laser may be performed.

일 실시예에 따르면, 절연층은 산화물, 질화물 및 산화 질화물 중 적어도 하나를 포함할 수 있다.According to an embodiment, the insulating layer may include at least one of oxide, nitride, and oxynitride.

일 실시예에 따르면, 개구부는 듀얼 다마신 패턴, 비아홀 및 트렌치 중 적어도 하나를 포함할 수 있다.According to an embodiment, the opening may include at least one of a dual damascene pattern, a via hole, and a trench.

일 실시예에 따르면, 콘택 플러그는 폴리실리콘 또는 메탈일 수 있다.According to an embodiment, the contact plug may be polysilicon or metal.

일 실시예에 따르면, 메탈층은 티타늄(Ti), 질화티타늄(TiN), 규화티타늄(TiSi), 탄탈륨(Ta), 질화탄탈륨(TaN), 코발트(Co), 규화코발트(CoSi), 니켈(Ni), 규화니켈(NiSi), 루테늄(Ru), 텅스텐(W), 규화텅스텐(WSi), 구리(Cu), 레늄(Re), 몰리브데넘(Mo), 나이오븀(Nb), 크롬(Cr) 중 적어도 하나를 포함할 수 있다.According to an embodiment, the metal layer is titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), cobalt silicide (CoSi), nickel ( Ni), nickel silicide (NiSi), ruthenium (Ru), tungsten (W), tungsten silicide (WSi), copper (Cu), rhenium (Re), molybdenum (Mo), niobium (Nb), chromium ( Cr) may contain at least one of.

일 실시예에 따르면,콘택 플러그는 무기질을 함유하는 물질을 포함할 수 있다.According to an embodiment, the contact plug may include a material containing an inorganic material.

일 실시예에 따르면, 상기 레이저는 YAG 레이저, 다이오드 레이저, CO2 레이저 또는 파이버(fiber) 레이저일 수 있다. 일 실시예에 따르면, 상기 콘택 플러그는 SiO2 및 Si3N4 중 선택된 적어도 하나의 무기질 물질을 함유할 수 있다.According to an embodiment, the laser may be a YAG laser, a diode laser, a CO 2 laser, or a fiber laser. According to an embodiment, the contact plug may contain at least one inorganic material selected from SiO 2 and Si 3 N 4 .

전술한 본 발명의 과제 해결 수단 중 어느 하나에 의하면, 콘택 플러그 내의 보이드 또는 심이 제거됨으로써 낮은 저항의 특성을 가지는 반도체 디바이스를 제공할 수 있다. 또한, 보이드 또는 심을 제거하는 과정에서 대상물이 용융, 고화되는 과정에서 재결정화가 되어 보다 낮은 저항의 특성을 반도체 디바이스에 제공할 수 있다.According to any one of the above-described problem solving means of the present invention, a semiconductor device having a low resistance characteristic can be provided by removing voids or shims in a contact plug. In addition, in the process of removing voids or shims, the object is recrystallized in the process of melting and solidifying, thereby providing a lower resistance characteristic to the semiconductor device.

도 1은 본 발명의 일 실시예에 따른 반도체 디바이스 제조 방법을 설명하기 위한 도면이다.
도 2는 콘택 플러그에 레이저를 조사하는 것을 설명하기 위한 도면이다.
도 3은 본 발명의 일 실시예에 따른 반도체 디바이스 제조 방법을 나타낸 흐름도이다.1 is a diagram illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.
2 is a diagram for explaining irradiation of a laser to a contact plug.
3 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

아래에서는 첨부한 도면을 참조하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 본 발명의 실시예를 상세히 설명한다. 그러나 본 발명은 여러 가지 상이한 형태로 구현될 수 있으며 여기에서 설명하는 실시예에 한정되지 않는다. 그리고 도면에서 본 발명을 명확하게 설명하기 위해서 설명과 관계없는 부분은 생략하였으며, 명세서 전체를 통하여 유사한 부분에 대해서는 유사한 도면 부호를 붙였다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art can easily implement the present invention. However, the present invention may be implemented in various different forms and is not limited to the embodiments described herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and similar reference numerals are assigned to similar parts throughout the specification.

명세서 전체에서, 어떤 부분이 다른 부분과 "연결"되어 있다고 할 때, 이는 "직접적으로 연결"되어 있는 경우뿐 아니라, 그 중간에 다른 소자를 사이에 두고 "전기적으로 연결"되어 있는 경우도 포함한다. 또한 어떤 부분이 어떤 구성요소를 "포함"한다고 할 때, 이는 특별히 반대되는 기재가 없는 한 다른 구성요소를 제외하는 것이 아니라 다른 구성요소를 더 포함할 수 있는 것을 의미하며, 하나 또는 그 이상의 다른 특징이나 숫자, 단계, 동작, 구성요소, 부분품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해되어야 한다. Throughout the specification, when a part is said to be "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element interposed therebetween. . In addition, when a part "includes" a certain component, it means that other components may be further included, and one or more other features, not excluding other components, unless specifically stated to the contrary. It is to be understood that it does not preclude the presence or addition of any number, step, action, component, part, or combination thereof.

본 명세서에 있어서 '부(部)'란, 하드웨어에 의해 실현되는 유닛(unit), 소프트웨어에 의해 실현되는 유닛, 양방을 이용하여 실현되는 유닛을 포함한다. 또한, 1 개의 유닛이 2 개 이상의 하드웨어를 이용하여 실현되어도 되고, 2 개 이상의 유닛이 1 개의 하드웨어에 의해 실현되어도 된다.In the present specification, the term "unit" includes a unit realized by hardware, a unit realized by software, and a unit realized using both. Further, one unit may be realized using two or more hardware, or two or more units may be realized using one hardware.

이하 첨부된 도면을 참고하여 본 발명의 일 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 일 실시예에 따른 반도체 디바이스 제조 방법을 설명하기 위한 도면이다. 1 is a diagram illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

도 1을 참조하면, 기판(100)이 제공된다(a). 예를 들어, 기판(100)은 실리콘(Si) 또는 게르마늄(Ge)중에서 선택된 적어도 하나를 포함할 수 있다.Referring to FIG. 1, a substrate 100 is provided (a). For example, the substrate 100 may include at least one selected from silicon (Si) and germanium (Ge).

이후, 기판(100) 상에 절연층(110)이 형성된다(a). 절연층(110)은 화학적 기상 증착(CVD: Chemical Vapor Deposition) 또는 물리적 기상 증착(PVD: Physical Vapor Deposition)으로 형성될 수 있다. Thereafter, the insulating layer 110 is formed on the substrate 100 (a). The insulating layer 110 may be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

절연층(110)은 산화물, 질화물 또는 산화 질화물 중 적어도 하나를 포함할 수 있다. The insulating layer 110 may include at least one of oxide, nitride, or oxynitride.

이어서, 절연층(110)을 식각하여 기판을 노출시키는 개구부(120)가 형성된다(b). 개구부(120)는 듀얼 다마신 패턴, 비아홀 또는 트렌치일 수 있다.Subsequently, an opening 120 exposing the substrate by etching the insulating layer 110 is formed (b). The opening 120 may be a dual damascene pattern, a via hole, or a trench.

여기서, 절연층(110) 상에 레지스트 패턴(미도시)이 형성되고, 레지스트 패턴을 마스크로 하여 절연층(110)을 식각함으로써 개구부(120)가 형성될 수 있다.Here, a resist pattern (not shown) is formed on the insulating layer 110, and the opening 120 may be formed by etching the insulating layer 110 using the resist pattern as a mask.

이때, 식각 공정은 화학적 건식 식각 공정 또는 습식 식각 공정 중에서 선택된 적어도 하나에 의해 수행될 수 있다. In this case, the etching process may be performed by at least one selected from a chemical dry etching process or a wet etching process.

이후, 개구부(120) 및 절연층(110) 상에 콘택 플러그(130)가 형성된다(c). 여기서, 콘택 플러그(130)는 화학적 기상 증착 또는 물리적 기상 증착에 의해 형성될 수 있고, 폴리실리콘(예컨대, 비정질실리콘(Amorphous-Si)) 또는 메탈일 수 있다.Thereafter, the contact plug 130 is formed on the opening 120 and the insulating layer 110 (c). Here, the contact plug 130 may be formed by chemical vapor deposition or physical vapor deposition, and may be polysilicon (eg, amorphous silicon (Amorphous-Si)) or metal.

여기서, 콘택 플러그(130) 내에 보이드(Void) 또는 심(Seam)(10)이 존재할 수 있다. 이러한 보이드 또는 심은 배선 저항 증가를 유발시켜 소자 특성을 저하시킨다.Here, a void or seam 10 may exist in the contact plug 130. Such voids or shims cause an increase in wiring resistance and deteriorate device characteristics.

콘택 플러그(130) 내의 보이드 또는 심을 제거하기 위하여 콘택 플러그(130)에 레이저를 조사하는 방법이 있다. There is a method of irradiating a laser on the contact plug 130 to remove voids or shims in the contact plug 130.

즉, 콘택 플러그(130)에 레이저(20)를 조사하면 콘택 플러그(130)가 용융된 후 다시 고체로 고상화되는데, 이때 원자들이 우수한 결정성을 갖는 결정 형태로 재배열되고, 이에 따라 그레인 사이즈 또한 증가됨으로써 콘택 플러그(130) 내의 보이드 또는 심이 제거될 수 있다.That is, when the laser 20 is irradiated to the contact plug 130, the contact plug 130 is melted and then solidified again. At this time, the atoms are rearranged into a crystal form having excellent crystallinity, and accordingly, the grain size In addition, by increasing the voids or shims in the contact plug 130 may be removed.

이와 관련하여, 도 2는 콘택 플러그에 레이저를 조사하는 것을 설명하기 위한 도면이다.In this regard, FIG. 2 is a diagram for explaining irradiating a laser to a contact plug.

도 2를 참조하면, 콘택 플러그(130)에 레이저(20)를 직접 조사할 경우, 콘택 플러그(130)가 가열되어 레이저(20)의 조사 부위에 돌기(protrusion)(30)가 발생하는 문제점이 있다. 돌기(protrusion)가 발생하는 이유는 용융(melt)된 물질이 고화될 때 재결정화(recrystallization)가 되며, 이때, 결정립(grain)이 형성된다. 결정과 결정면 사이의 결정립 경계(grain boundary)에 impurity 농도가 높아져 고화되는 시간이 grain 중심보다 늦어지게 되며, 이때 grain boundary 사이에서 돌기(protrusion) 현상이 발생하는 것으로 여겨진다.Referring to FIG. 2, when the laser 20 is directly irradiated onto the contact plug 130, the contact plug 130 is heated and a protrusion 30 is generated at the irradiated portion of the laser 20. have. The reason for the occurrence of protrusion is recrystallization when the melted material is solidified, and at this time, grains are formed. The impurity concentration at the grain boundary between the crystal and the crystal plane increases, so that the solidification time becomes later than the grain center, and it is believed that a protrusion phenomenon occurs between the grain boundaries.

따라서, 본 발명에서는 콘택 플러그(130) 상에 메탈층(140)을 형성하고, 메탈층(140)을 직접 가열하여 콘택 플러그(130)를 간접 가열하여 상술한 문제점을 해결하고 있다.Accordingly, in the present invention, the metal layer 140 is formed on the contact plug 130 and the metal layer 140 is directly heated to indirectly heat the contact plug 130 to solve the above-described problem.

또한, 금속은 자유전자가 상대적으로 많아 레이저에 의해 매우 높은 온도(예를 들어, 2000도 내지 3000도)로 가열될 수 있다. 이에 반하여, 레이저를 통해 무기질(예를 들어, SiO2, Si, Si3N4)을 함유하는 물질을 가열시키는 것은 상대적으로 어렵다.In addition, metals are relatively high in free electrons and can be heated to a very high temperature (for example, 2000 to 3000 degrees) by a laser. In contrast, it is relatively difficult to heat a material containing inorganic materials (eg, SiO 2 , Si, Si 3 N 4 ) through a laser.

본 발명은 이러한 특성을 이용하여, 메탈층(140)과 콘택 플러그(130)를 인접하여 배치(예컨대, 서로 접촉하여 배치)한 후에, 레이저를 메탈층(140)에 직접 조사하여 콘택 플러그(130)를 간접 가열함으로써 콘택 플러그(130)를 효과적으로 가열할 수 있다.According to the present invention, after the metal layer 140 and the contact plug 130 are disposed adjacent to each other (eg, disposed in contact with each other) using these characteristics, the laser is directly irradiated to the metal layer 140 to form the contact plug 130. ) By indirectly heating the contact plug 130 can be effectively heated.

구체적으로, 콘택 플러그(130) 상에 메탈층(140)이 형성된다(d). 여기서, 메탈층(130)은 티타늄(Ti), 질화티타늄(TiN), 규화티타늄(TiSi), 탄탈륨(Ta), 질화탄탈륨(TaN), 코발트(Co), 규화코발트(CoSi), 니켈(Ni), 규화니켈(NiSi), 루테늄(Ru), 텅스텐(W), 규화텅스텐(WSi), 구리(Cu), 레늄(Re), 몰리브데넘(Mo), 나이오븀(Nb), 크롬(Cr) 중 적어도 하나를 포함할 수 있다.Specifically, the metal layer 140 is formed on the contact plug 130 (d). Here, the metal layer 130 is titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), cobalt silicide (CoSi), nickel (Ni ), nickel silicide (NiSi), ruthenium (Ru), tungsten (W), tungsten silicide (WSi), copper (Cu), rhenium (Re), molybdenum (Mo), niobium (Nb), chromium (Cr) ) May include at least one of.

이때, 콘택 플러그(130)가 효과적으로 간접 가열될 수 있도록 메탈층(140)에 레이저(20)를 조사하여 발생하는 열이 콘택 플러그(130)에 레이저(20)를 조사하여 발생하는 열 보다 더 많도록 콘택 플러그(130) 및 메탈층(140)의 물질을 선택할 수 있다. 예를 들어, 콘택 플러그(130)는 무기질(예를 들어, SiO2, Si, Si3N4)을 함유하는 물질일 수 있다.At this time, the heat generated by irradiating the laser 20 to the metal layer 140 so that the contact plug 130 can be effectively indirectly heated is greater than the heat generated by irradiating the laser 20 to the contact plug 130. The material of the contact plug 130 and the metal layer 140 may be selected so as to be used. For example, the contact plug 130 may be a material containing an inorganic material (eg, SiO 2 , Si, Si 3 N 4 ).

이어서, 메탈층(140)에 레이저(20)가 조사된다(e). 레이저(20)는 YAG 레이저, 다이오드 레이저, CO2 레이저 또는 파이버(fiber)레이저일 수 있다.Subsequently, the laser 20 is irradiated onto the metal layer 140 (e). The laser 20 may be a YAG laser, a diode laser, a CO2 laser or a fiber laser.

메탈층(140)에 레이저(20)가 조사됨으로써 메탈층(140)이 직접 가열되고 메탈층(140)과 인접한 콘택 플러그(130)는 간접 가열된다. As the laser 20 is irradiated onto the metal layer 140, the metal layer 140 is directly heated and the contact plug 130 adjacent to the metal layer 140 is indirectly heated.

이때, 콘택 플러그(130)가 간접 가열되어 재결정 과정이 진행되고, 그레인 사이즈 또한 증가됨으로써, 콘택 플러그(130) 내의 보이드 또는 심이 제거될 수 있다.At this time, the contact plug 130 is indirectly heated to perform a recrystallization process, and the grain size is also increased, so that voids or shims in the contact plug 130 may be removed.

이와 같이, 콘택 플러그(130) 내의 보이드 또는 심(10)이 제거됨으로써 반도체 디바이스가 낮은 저항의 특성을 가지게 된다.In this way, since the voids or the shims 10 in the contact plug 130 are removed, the semiconductor device has a characteristic of low resistance.

이때, 고온가열에 따른 메탈층(140)과 콘택 플러그(130)간의 반응 혹은 상호확산(interdiffusion)이 발생할 수 있는데, 이를 방지할 수 있는 하나 이상의 물질을 메탈층(140)과 콘택 플러그(130) 사이에 포함시킬 수도 있다. 왜냐하면, 반응 혹은 상호확산이 발생하게 되면, 후술하는 메탈층(140)을 제거하는 단계에서 메탈층(140)의 제거가 용이하지 않을 수 있기 때문이다. At this time, a reaction or interdiffusion between the metal layer 140 and the contact plug 130 may occur due to high temperature heating, and at least one material capable of preventing this may be used for the metal layer 140 and the contact plug 130. You can also include them in between. This is because, when reaction or interdiffusion occurs, it may not be easy to remove the metal layer 140 in the step of removing the metal layer 140 to be described later.

이러한 물질은 예를 들어, SiO2 막, Si3N4, 폴리실리콘(Polysilicon) 및 비정질실리콘(Amorphous-Si) 중 하나를 포함할 수 있다.Such materials are, for example, SiO 2 films, Si 3 N 4 , It may include one of polysilicon and amorphous-Si.

콘택 플러그(130) 내의 보이드 또는 심(10)이 제거된 후, 메탈층(140)이 제거된다(e).After the void or shim 10 in the contact plug 130 is removed, the metal layer 140 is removed (e).

도 3은 본 발명의 일 실시예에 따른 반도체 디바이스 제조 방법을 나타낸 흐름도이다.3 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

도 3은 참조하면, 단계 S300에서 기판을 제공된다. 단계 S210에서 기판 상에 절연층이 형성된다.Referring to FIG. 3, a substrate is provided in step S300. In step S210, an insulating layer is formed on the substrate.

단계 S320에서 절연층을 식각하여 기판을 노출시키는 개구부가 형성된다.In step S320, an opening is formed to expose the substrate by etching the insulating layer.

단계 S330에서 개구부 및 절연층 상에 콘택 플러그가 형성된다. 단계 S340에서 콘택 플러그 상에 메탈층이 형성된다.In step S330, a contact plug is formed on the opening and the insulating layer. In step S340, a metal layer is formed on the contact plug.

단계 S350에서 메탈층에 레이저가 조사된다.In step S350, a laser is irradiated on the metal layer.

전술한 본 발명의 설명은 예시를 위한 것이며, 본 발명이 속하는 기술분야의 통상의 지식을 가진 자는 본 발명의 기술적 사상이나 필수적인 특징을 변경하지 않고서 다른 구체적인 형태로 쉽게 변형이 가능하다는 것을 이해할 수 있을 것이다. 그러므로 이상에서 기술한 실시예들은 모든 면에서 예시적인 것이며 한정적이 아닌 것으로 이해해야만 한다. 예를 들어, 단일형으로 설명되어 있는 각 구성 요소는 분산되어 실시될 수도 있으며, 마찬가지로 분산된 것으로 설명되어 있는 구성 요소들도 결합된 형태로 실시될 수 있다. The above description of the present invention is for illustrative purposes only, and those of ordinary skill in the art to which the present invention pertains will be able to understand that it can be easily modified into other specific forms without changing the technical spirit or essential features of the present invention. will be. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting. For example, each component described as a single type may be implemented in a distributed manner, and similarly, components described as being distributed may also be implemented in a combined form.

본 발명의 범위는 상기 상세한 설명보다는 후술하는 특허청구범위에 의하여 나타내어지며, 특허청구범위의 의미 및 범위 그리고 그 균등 개념으로부터 도출되는 모든 변경 또는 변형된 형태가 본 발명의 범위에 포함되는 것으로 해석되어야 한다.The scope of the present invention is indicated by the claims to be described later rather than the detailed description, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

10: 보이드 또는 심
20: 레이저
30: 돌기
100: 기판
110: 절연층
120: 개구부
130: 콘택 플러그
140: 메탈층10: void or shim
20: laser
30: protrusion
100: substrate
110: insulating layer
120: opening
130: contact plug
140: metal layer

Claims (5)

반도체 디바이스 제조 방법에 있어서,
기판을 제공하는 단계;
상기 기판 상에 절연층을 형성하는 단계;
상기 절연층을 식각하여 상기 기판을 노출시키는 개구부를 형성하는 단계;
상기 개구부를 채우는 전기적 접속을 위한 콘택 플러그를 형성하는 단계;
상기 콘택 플러그 상에 메탈층을 형성하는 단계; 및
상기 메탈층에 레이저를 조사하는 단계를 포함하고,
상기 메탈층에 레이저를 조사하는 단계는 상기 메탈층을 직접 가열하여 상기 콘택 플러그를 간접 가열함으로써 상기 콘택 플러그 내의 보이드(Void) 또는 심(Seam)을 제거하는 단계를 포함하는,
반도체 디바이스 제조 방법.
In the semiconductor device manufacturing method,
Providing a substrate;
Forming an insulating layer on the substrate;
Etching the insulating layer to form an opening exposing the substrate;
Forming a contact plug for electrical connection filling the opening;
Forming a metal layer on the contact plug; And
Including the step of irradiating a laser to the metal layer,
Irradiating a laser to the metal layer includes removing voids or seams in the contact plug by indirectly heating the contact plug by directly heating the metal layer,
Semiconductor device manufacturing method.
 제 1 항에 있어서,
상기 메탈층을 제거하는 단계
를 더 포함하는 것인, 반도체 디바이스 제조 방법.
The method of claim 1,
Removing the metal layer
The method of manufacturing a semiconductor device further comprising a.
 반도체 디바이스 제조 방법에 있어서,
기판을 제공하는 단계;
상기 기판 상에 절연층을 형성하는 단계;
상기 절연층을 식각하여 상기 기판을 노출시키는 개구부를 형성하는 단계;
상기 개구부를 채우는 전기적 접속을 위한 콘택 플러그를 형성하는 단계;
상기 콘택 플러그 상에 메탈층을 형성하는 단계; 및
상기 메탈층에 레이저를 조사하는 단계를 포함하고,
상기 메탈층에 레이저를 조사하는 단계는 상기 메탈층을 직접 가열하여 상기 콘택 플러그를 간접 가열함으로써 상기 콘택 플러그 내의 보이드(Void) 또는 심(Seam)을 제거하는 단계를 포함하며,
상기 콘택 플러그와 상기 메탈층 사이에 이들 간의 반응 또는 상호확산을 방지하는 삽입층을 형성하는 단계를 더 포함하고, 상기 콘택 플러그 상에 상기 삽입층과 상기 메탈층이 구비된 상태에서 상기 레이저를 조사하는 단계를 수행하는,
반도체 디바이스 제조 방법.
In the semiconductor device manufacturing method,
Providing a substrate;
Forming an insulating layer on the substrate;
Etching the insulating layer to form an opening exposing the substrate;
Forming a contact plug for electrical connection filling the opening;
Forming a metal layer on the contact plug; And
Including the step of irradiating a laser to the metal layer,
The step of irradiating the laser to the metal layer includes removing voids or seams in the contact plug by indirectly heating the contact plug by directly heating the metal layer,
Further comprising the step of forming an insertion layer between the contact plug and the metal layer to prevent reaction or diffusion between them, wherein the laser is irradiated while the insertion layer and the metal layer are provided on the contact plug. To perform the steps,
Semiconductor device manufacturing method.
 제 1 항 또는 제 3 항에 있어서,
상기 메탈층은 티타늄(Ti), 질화티타늄(TiN), 규화티타늄(TiSi), 탄탈륨(Ta), 질화탄탈륨(TaN), 코발트(Co), 규화코발트(CoSi), 니켈(Ni), 규화니켈(NiSi), 루테늄(Ru), 텅스텐(W), 규화텅스텐(WSi), 구리(Cu), 레늄(Re), 몰리브데넘(Mo), 나이오븀(Nb), 크롬(Cr) 중 적어도 하나를 포함하는 것인, 반도체 디바이스 제조 방법.
The method of claim 1 or 3,
The metal layer is titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), cobalt silicide (CoSi), nickel (Ni), nickel silicide (NiSi), ruthenium (Ru), tungsten (W), tungsten silicide (WSi), copper (Cu), rhenium (Re), molybdenum (Mo), niobium (Nb), at least one of chromium (Cr) A semiconductor device manufacturing method comprising a.
 제 1 항 또는 제 3 항에 있어서,
상기 콘택 플러그는 무기질을 함유하는 물질을 포함하는 것인, 반도체 디바이스 제조 방법.The method of claim 1 or 3,
The method of manufacturing a semiconductor device, wherein the contact plug comprises a material containing an inorganic substance.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220144462A (en) * 2021-04-20 2022-10-27 (주)알엔알랩 Method of fabricating semiconductor device having recess gate structure

Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6348841A (en) * 1986-08-19 1988-03-01 Fujitsu Ltd Manufacture of semiconductor device
KR900002686A (en) * 1988-08-17 1990-03-23 미노 시게가스 Threshing device
JPH05304149A (en) * 1991-01-28 1993-11-16 Fujitsu Ltd Fabrication of semiconductor device
JPH06169020A (en) * 1992-12-01 1994-06-14 Nec Corp Manufacture of semiconductor device
KR19980029400A (en) * 1996-10-25 1998-07-25 김광호 Method of forming semiconductor device metal wiring
JPH10313005A (en) * 1997-05-13 1998-11-24 Sony Corp Reflowing of metal film
JPH1197542A (en) * 1997-09-19 1999-04-09 Nec Corp Semiconductor device and manufacture therefor
KR100268950B1 (en) * 1997-11-24 2000-12-01 김영환 Method for forming contact metal line of semiconductor device
JP2001358211A (en) * 2000-06-14 2001-12-26 Nec Corp Semiconductor device and its manufacturing method
US6376369B1 (en) * 1998-02-12 2002-04-23 Micron Technology, Inc. Robust pressure aluminum fill process
US6391778B1 (en) * 1998-09-03 2002-05-21 Micron Technology, Inc. Contact/via force fill techniques and resulting structures
KR20030003321A (en) * 2001-06-30 2003-01-10 주식회사 하이닉스반도체 Method for fabricating capacitor in semiconductor memory device
KR20040008018A (en) * 2002-07-15 2004-01-28 주식회사 하이닉스반도체 Method of forming a copper wiring in a semiconductor device
JP2005509292A (en) * 2001-11-08 2005-04-07 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Method for forming highly reliable Cu wiring
US20060024429A1 (en) * 2004-08-02 2006-02-02 Hideki Horii Laser reflowing of phase changeable memory element to close a void therein
US7224065B2 (en) * 1998-09-03 2007-05-29 Micron Technology, Inc. Contact/via force fill techniques and resulting structures
JP2010129890A (en) * 2008-11-28 2010-06-10 Shibuya Kogyo Co Ltd Bonding head
KR20130026671A (en) * 2011-09-06 2013-03-14 엘지디스플레이 주식회사 Crystallization method and method for manufacturing display device using the same
KR20150127367A (en) * 2014-05-07 2015-11-17 삼성전자주식회사 Method of filling an opening and method of manufacturing a phase-change memory device using the same
KR20160057545A (en) * 2014-11-13 2016-05-24 삼성전자주식회사 Manufacturing method of semiconductor device
KR20170015883A (en) * 2014-06-16 2017-02-10 인텔 코포레이션 Seam healing of metal interconnects

Patent Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6348841A (en) * 1986-08-19 1988-03-01 Fujitsu Ltd Manufacture of semiconductor device
KR900002686A (en) * 1988-08-17 1990-03-23 미노 시게가스 Threshing device
JPH05304149A (en) * 1991-01-28 1993-11-16 Fujitsu Ltd Fabrication of semiconductor device
JPH06169020A (en) * 1992-12-01 1994-06-14 Nec Corp Manufacture of semiconductor device
KR19980029400A (en) * 1996-10-25 1998-07-25 김광호 Method of forming semiconductor device metal wiring
JPH10313005A (en) * 1997-05-13 1998-11-24 Sony Corp Reflowing of metal film
JPH1197542A (en) * 1997-09-19 1999-04-09 Nec Corp Semiconductor device and manufacture therefor
KR100268950B1 (en) * 1997-11-24 2000-12-01 김영환 Method for forming contact metal line of semiconductor device
US6376369B1 (en) * 1998-02-12 2002-04-23 Micron Technology, Inc. Robust pressure aluminum fill process
US6391778B1 (en) * 1998-09-03 2002-05-21 Micron Technology, Inc. Contact/via force fill techniques and resulting structures
US7224065B2 (en) * 1998-09-03 2007-05-29 Micron Technology, Inc. Contact/via force fill techniques and resulting structures
JP2001358211A (en) * 2000-06-14 2001-12-26 Nec Corp Semiconductor device and its manufacturing method
KR20030003321A (en) * 2001-06-30 2003-01-10 주식회사 하이닉스반도체 Method for fabricating capacitor in semiconductor memory device
JP2005509292A (en) * 2001-11-08 2005-04-07 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Method for forming highly reliable Cu wiring
KR20050056925A (en) * 2001-11-08 2005-06-16 어드밴스드 마이크로 디바이시즈, 인코포레이티드 Method of forming reliable cu interconnects
KR20040008018A (en) * 2002-07-15 2004-01-28 주식회사 하이닉스반도체 Method of forming a copper wiring in a semiconductor device
KR20060012182A (en) * 2004-08-02 2006-02-07 삼성전자주식회사 Methods of forming phase change memory devices
US20060024429A1 (en) * 2004-08-02 2006-02-02 Hideki Horii Laser reflowing of phase changeable memory element to close a void therein
JP2010129890A (en) * 2008-11-28 2010-06-10 Shibuya Kogyo Co Ltd Bonding head
KR20130026671A (en) * 2011-09-06 2013-03-14 엘지디스플레이 주식회사 Crystallization method and method for manufacturing display device using the same
KR20150127367A (en) * 2014-05-07 2015-11-17 삼성전자주식회사 Method of filling an opening and method of manufacturing a phase-change memory device using the same
KR20170015883A (en) * 2014-06-16 2017-02-10 인텔 코포레이션 Seam healing of metal interconnects
JP2017520108A (en) * 2014-06-16 2017-07-20 インテル・コーポレーション Metal interconnect seam repair
KR20160057545A (en) * 2014-11-13 2016-05-24 삼성전자주식회사 Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220144462A (en) * 2021-04-20 2022-10-27 (주)알엔알랩 Method of fabricating semiconductor device having recess gate structure

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