KR20210004343A - Method for operating spikes in a neuromodule device - Google Patents

Abstract

The present invention relates to a method for operating spikes in a neuromorphic device, comprising the steps of: (a) receiving an address of a spiking neuron; (b) providing an index address concurrently designating a previous and a posterior neuron element existing at each of a plurality of parallel look-up table (LUT) modules divided according to a first synapse address among synapse addresses; (c) providing at least one between a presynaptic neuron address and a postsynaptic neuron address existing at the previous and the posterior neuron element according to the index address; (d) comparing the spiking neuron address with one between the presynaptic neuron address and the postsynaptic neuron address; and (e) when a coincidence is generated through the comparison, merging the first synapse address with the index address outputs the merged address as the address of a synapse connected to the spiking neuron. The present invention processes spike routing rapidly to provide arbitrary updates with respect to a synapse weighting factor.

Description

Spikes calculation method of neuromorphic device {METHOD FOR OPERATING SPIKES IN A NEUROMODULE DEVICE}

The present invention relates to a technique for calculating a spike in a neuromorphic device, and more particularly, to a method for calculating a spike in a neuromorphic device that performs a spike operation between a neuron and a synapse based on a reconfigurable neural network architecture based on a lookup table. .

Deep learning technology is attracting tremendous attention due to its outstanding success in various tasks such as high-precision face recognition, automatic image colorization and game mastering. This success is mainly due to deep neural networks. In general, such networks are built on general purpose hardware, although primarily powered by application-specific integrated circuits such as tensor processing units. Despite this continued success, skepticism has emerged with astronomical estimates of the required machine performance in relation to the complexity of the operation. Conversely, the human brain can perform high-complexity tasks with limited synaptic operations (about 1015 SynOP/s) that consume only about 15W.

Neuromorphic engineering aims to build biologically plausible Spike Neural Networks (SNNs) on silicon wafers to realize the ability to perform tasks in an energy-efficient way like the human brain. Neuromorphic systems can be built using neurons that are interconnected through synapses. The implementation of neurons and synapses varies, and analog and/or digital integrated circuits (ICs) based on standard CMOS technology are common.

Korean Patent Laid-Open Publication No. 10-2018-0093245 (2018.08.21) relates to a neuromorphic calculation device, a technology providing a neuromorphic calculation device that converts and outputs a result of an operation processed in an analog manner into a digital value. Is being disclosed.

Korean Patent Laid-Open Publication No. 10-2019-0008670 (2019.01.25) relates to a neuron circuit and a neuromorphic system including the same, and provides a neuron circuit for improving the recognition rate of a synaptic device having a nonlinear resistance characteristic. Disclosed is a technology for providing a neuromorphic system including a circuit.

Korean Patent Publication No. 10-2018-0093245 (2018.08.21) Korean Patent Publication No. 10-2019-0008670 (2019.01.25)

An embodiment of the present invention is to provide a method for calculating a spike in a neuromorphic device that performs a spike operation between a neuron and a synapse based on a reconfigurable neural network architecture based on a lookup table.

An embodiment of the present invention is to provide a spike calculation method of a neuromorphic device capable of processing spike routing by using a lookup table reading technique for on-chip learning.

An embodiment of the present invention is to provide a method for calculating a spike in a neuromorphic device capable of providing random updates to synaptic weights by processing spike routing at high speed by performing parallel search on a plurality of partitions. .

Among the embodiments, a method for calculating a spike of a neuromorphic device includes: (a) receiving an address of a spiking neuron, (b) a plurality of parallel look-up tables (LUTs) divided into a first synaptic address among synaptic addresses. Providing an index address that simultaneously designates anterior and posterior neuron elements in each of the modules, (c) providing at least one of addresses of presynaptic neurons and post-synaptic neurons in the anterior and posterior neuron elements according to the index address, (d) comparing the address of the spiking neuron with one of the addresses of the presynaptic neuron or the post-synaptic neuron, and (e) merging the first synaptic address and the index address when a match occurs through the comparison And outputting the address of the synapse connected to the spiking neuron.

The step (b) may include providing the index address by sequentially designating the front and rear neuron elements from start to finish.

The step (b) may further include temporarily stopping the provision of the index address when the match occurs through the comparison.

The step (b) may include restarting the provision of the index address when the output of the synaptic address is completed in association with the match.

The step (c) may include providing addresses of presynaptic neurons and post synaptic neurons in the front and rear neuron elements according to the index address.

The step (d) may include outputting a trigger signal for synaptic update when the match occurs through the comparison.

The step (d) may include determining a spike progress signal according to whether the matched neuron is a presynaptic neuron or a post-synaptic neuron.

The step (e) may include completing the address of the synapse by merging the first synaptic address into an upper bit string and the index address into a lower bit string.

Among the embodiments, a method of calculating a spike of a neuromorphic device includes (a) detecting a spiking neuron, (b) receiving an address of the spiking neuron, (c) based on the address of the spiking neuron. Determining at least one of addresses of a presynaptic neuron and a postsynaptic neuron by simultaneously designating each of a plurality of parallel Look-up Table (LUT) modules, (d) the address of the spiking neuron and the presynaptic neuron or Comparing the address of the post-synaptic neuron and (e) if a match occurs through the comparison, the module address of the parallel LUT module and the index address corresponding to the address of the presynaptic neuron or the post-synaptic neuron in the parallel LUT module And outputting as an address of a synapse connected to the spiking neuron by merging.

The disclosed technology can have the following effects. However, since it does not mean that a specific embodiment should include all of the following effects or only the following effects, it should not be understood that the scope of the rights of the disclosed technology is limited thereby.

The spike calculation method of a neuromorphic device according to an embodiment of the present invention may process spike routing using a lookup table reading technique for on-chip learning.

The spike calculation method of a neuromorphic device according to an embodiment of the present invention may perform spike routing at high speed by performing parallel search on a plurality of partitioned partitions to provide arbitrary updates to synaptic weights.

1 is a diagram illustrating a neuromorphic device according to an embodiment of the present invention.
2 is a diagram illustrating an embodiment of a network composed of neurons and synapses.
3 is a diagram illustrating an LUT used in the topology block of FIG. 1.
4 is a diagram illustrating signals used in a neuromorphic device according to an embodiment of the present invention.
5 is a diagram illustrating a RAM technique and a CAM technique.
6 is a diagram for explaining an operation in the topology block of FIG. 1.
7 is a diagram illustrating experimental results for a maximum network size for different routing techniques.
8 is a block diagram illustrating a functional configuration of a neuromorphic device according to an embodiment of the present invention.
9 is a flowchart illustrating a spiking operation process performed in a neuromorphic device according to an embodiment of the present invention.

Since the description of the present invention is merely an embodiment for structural or functional description, the scope of the present invention should not be construed as being limited by the embodiments described in the text. That is, since the embodiments can be variously changed and have various forms, the scope of the present invention should be understood to include equivalents capable of realizing the technical idea. In addition, since the object or effect presented in the present invention does not mean that a specific embodiment should include all of them or only those effects, the scope of the present invention should not be understood as being limited thereto.

Meanwhile, the meaning of terms described in the present application should be understood as follows.

Terms such as "first" and "second" are used to distinguish one component from other components, and the scope of rights is not limited by these terms. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

When a component is referred to as being "connected" to another component, it should be understood that although it may be directly connected to the other component, another component may exist in the middle. On the other hand, when it is mentioned that a certain component is "directly connected" to another component, it should be understood that no other component exists in the middle. On the other hand, other expressions describing the relationship between the constituent elements, that is, "between" and "just between" or "neighboring to" and "directly neighboring to" should be interpreted as well.

Singular expressions are to be understood as including plural expressions unless the context clearly indicates otherwise, and terms such as “comprise” or “have” refer to implemented features, numbers, steps, actions, components, parts, or It is to be understood that it is intended to designate that a combination exists and does not preclude the presence or addition of one or more other features or numbers, steps, actions, components, parts, or combinations thereof.

In each step, the identification code (for example, a, b, c, etc.) is used for convenience of explanation, and the identification code does not describe the order of each step, and each step has a specific sequence clearly in context. Unless otherwise stated, it may occur differently from the stated order. That is, each of the steps may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

The present invention can be embodied as computer-readable codes on a computer-readable recording medium, and the computer-readable recording medium includes all types of recording devices storing data that can be read by a computer system. . Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, and optical data storage devices. Further, the computer-readable recording medium is distributed over a computer system connected by a network, so that the computer-readable code can be stored and executed in a distributed manner.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the field to which the present invention belongs, unless otherwise defined. Terms defined in commonly used dictionaries should be construed as having meanings in the context of related technologies, and cannot be construed as having an ideal or excessive formal meaning unless explicitly defined in the present application.

Neuromorphic systems can be built using neurons that are interconnected through synapses. Neurons and synapses are implemented in various ways, and analog and/or digital integrated circuits (ICs) based on standard CMOS (complementary metal oxide semiconductor) technology are common. Some new approaches are using new devices such as phase change memory, magnetic tunnel junctions, volatile threshold switches and floating-gate transistors. In general, event routing between neurons can be classified into i) a dedicated routing method and ii) a lookup table (LUT) based routing method.

In a dedicated routing scheme, neurons can be connected via hardwires or a set of synapses that are directly assigned by encoder-decoder pairs. This method may have the advantage that a semi- or fully parallel event routing protocol can support real-time computation of SNNs even if they do not target fast neurons and synaptic ICs.

However, the limited reconfigurability can act as a disadvantage if N ² programmable synapses are not applied to N neurons. The use of a fully connected network may be limited depending on the network of interest, for example, a reward prediction network with a feedback connection has a specific unique synaptic path, and learning may change weights along that path. Thus, only some of the N ² synapses can be used in this case and can be exposed to the problem of synapse redundancy.

The LUT-based routing technique solves this problem by tabulating the connections of all neurons in the LUT and sending events according to the LUT, instead of physically implementing the connection. In other words, all synapses in the synaptic array can be used for any pair of neurons according to the network architecture in order to maximize the reconfigurability.

As a result, the possibility of reconfiguration can be maintained with a much smaller number of embedded synapses than N ² . This routing technique can be applied not only to single neuromorphic cores, but also to large multicore neuromorphic systems such as SpiNNaker, TrueNorth, Neurogrid, HiAER, DYNAPs and Loihi. Most of these examples are based on the Address Event Representation (AER) protocol, which marks each spike with the address of the emitting neuron and queues the spikes for sequential transmission.

The AER protocol is easily adaptable using standard memory technology, but requires a high clock rate. Moreover, large-scale neuromorphic systems are often only suitable for "inference" (not including on-chip learning). On-chip local learning can be based on updating synaptic weights in local learning rules that rely only on local information, and the main difficulty of real-time on-chip local learning arises from inverse lookup, which consumes considerable time and interferes with real-time learning. I can.

1 is a diagram illustrating a neuromorphic device according to an embodiment of the present invention.

Referring to FIG. 1, the neuromorphic device 100 may include a synapse block, a neuron block, a queue register block 110 and a topology block.

The neuromorphic device 100 may correspond to an architecture for signal transmission in a neural network in order to integrate a reconfigurable spiking neural network. In addition, the neuromorphic device 100 may correspond to a neuromorphic core, and may be implemented and operated as a single system.

Signal transmission of a spike operating in the neuromorphic device 100 may operate as follows. The address of the neuron where the spike has occurred is temporarily stored in a queue register block, so that it can wait for an acknowledgment (ACK) of the topology block according to the handshaking protocol. Upon permission of the topology block, the address of the neuron is transferred to the topology block and starts reading the LookUp Table (LUT), which records the connection information of all neurons, and retrieves information of all neurons connected to this neuron. can do. The information of neurons in the connection relationship is sequentially identified and the spike is immediately transmitted to the neuron. At this time, the connection weight of the connection is added to the synaptic block, and the information is transferred to the postsynaptic neuron. At the same time, the information is transferred to the postsynaptic neuron. It can increase the membrane potential.

The neuromorphic device 100 enables implementation of on-chip learning as well as inference, and considers the connection relationship of synapses and spike timing of pre and postsynaptic neurons. It has the advantage of enabling real-time connection weight updates that enable on-chip learning.

The synaptic block may include a synaptic array composed of a plurality of synapses, and each of the plurality of synapses may uniquely have a synaptic address. That is, the synaptic arrangement may be designated as an S_ADR pointer indicating a specific synapse.

The neuron block may include a neuron array composed of a plurality of neurons, and each of the plurality of neurons may uniquely have an address of a neuron. That is, the neuron array may be designated as a POST_ADR pointer indicating a specific neuron. In addition, each neuron may be externally designated through the EXT_ADR pointer, and may be simulated by the EXT_SPIKE signal.

The queue register block 110 may correspond to a standard FIFO (First In First Out) buffer that stores addresses of neurons according to a spiking time sequence generated by neurons for sequential transmission of spikes. When a specific neuron generates a spike, the address (N_ADR) of the neuron may be transmitted and stored in the queue register block 110. The queue register block 110 may communicate with the topology block via a handshake protocol. When receiving an event related to a spike, the queue register block 110 may transmit a routing request signal (REQ) to the topology block to remove the event from the queue, and wait for an acknowledgment signal (ACK) from the topology block. I can.

The topology block may correspond to a memory array that stores event routing LUT(s). Since SRAM is used as LUT memory, it can be fast enough to read within a single clock cycle over the clock rate range (10 to 200 MHz). A commonly used LUT is a two-column table, and the length of each row can be equal to the total number of synapses in the network. When the REQ is received from the queue register block 110, the topology block may transmit an ACK when in an idle state, and the LUT may search for fan-in and/or fan-out connections related to a corresponding neuron by reading N_ADR.

2 is a diagram illustrating an embodiment of a network composed of neurons and synapses. 3 is a diagram illustrating an LUT used in the topology block of FIG. 1.

Referring to FIG. 2, LUTs may be aligned according to synaptic indexes (or addresses). In the case of the network of FIG. 2, synapse 73 may have PRE_ADR and POST_ADR of 1 and 2, respectively. Accordingly, in FIG. 3, in the LUT of the network, a 73 th row with 1 and 2 in the left and right columns, respectively, may exist. If a given neuron is a postsynaptic neuron (hereinafter referred to as a postsynaptic neuron), the synapse may correspond to a fan-in synapse of the neuron. For example, in FIG. 2, in the case of neuron 2, synapses 74 and 75 may correspond to this. A synapse in which a given neuron is a presynaptic neuron (hereinafter referred to as a presynaptic neuron) may correspond to a fan-out synapse. For example, in the case of neuron 2, synapses 73 and 77 may correspond to this.

4 is a diagram illustrating signals used in a neuromorphic device according to an embodiment of the present invention.

Referring to FIG. 4, the indication of signals used in the neuromorphic device 100 can be confirmed in detail. Representatively, N_ADR may correspond to an event address, POST_ADR may correspond to an address of a post-synaptic neuron, and S_ADR may correspond to a synaptic address. In addition, S_W may correspond to a synaptic weight. PRE_ADR may correspond to the address of a presynaptic neuron, and S_UPD may correspond to a synaptic update signal. UPD_SEL may correspond to a signal indicating whether the synapse designated by S-ADR is a fan-in synapse or a fan-out synapse.

5 is a diagram illustrating a RAM technique and a CAM technique. 7 is a diagram illustrating experimental results for a maximum network size for different routing techniques.

LUT discovery may correspond to a time consuming operation. In other words, the more synapses constituting the network, the more time can be consumed because a larger LUT is required. Accordingly, as events accumulate in the queue register block 110, the possibility of a delay in routing may increase. To prevent this, the total event routing time (T _srch + T _send + T _upd ) needs to be shorter than the average Inter Spike Interval (ISI) for all spikes from all neurons sharing the same pipeline in the queue register block 110. There is. Assuming a Poisson neuron in which spike transmission follows a Poisson (update) process, this state can be expressed as Equation 1 below.

[Equation 1]

Here, 1/aN is the average ISI for Poisson spikes, and a and N may correspond to the spiking activity of each neuron and the total number of neurons. Therefore, in order to increase the SNN size (N) without traffic congestion, it is necessary to reduce T _srch , T _send and/or T _upd .

Referring to FIG. 5, RAM and CAM techniques can be identified as event routing techniques applicable to the topology block of FIG. 1. The RAM and CAM techniques can support full sequential search and parallel search of the LUT in two extreme cases, respectively.

In Figure 5 (a), the RAM scheme can use a single RAM array for the LUT configured in the same manner as in Figure 3. The LUT may correspond to an S*2 matrix (S is the number of synapses). The number of synapses may correspond to the sum of the number of fan neurons (F _in ) _in all N neurons constituting the network, and may correspond to the sum of the number of fan-out neurons (F _out ). It can be expressed as in Equation 2.

[Equation 2]

Here, the superscript i of F _in ⁱ and F _out ⁱ may correspond to the neuron index. The LUT can be accessed by an address pointer (S_ADR) to retrieve a row containing a specific N_ADR. The address pointer can be generated by the index address generator (ADR GEN). The LUT can be sequentially read row by row while outputting PRE_ADR and POST_ADR of each row.

In addition, the comparator COMP may detect a match between N_ADR and PRE_ADR (POST_ADR), and when a match is detected, the comparator may output S_UPD (= 1) as a trigger for updating. Since each column is read and compared simultaneously within a single clock cycle, the LUT seek time may correspond to S/f _clk , i.e. T _srch = S/f _clk .

In addition, since both the spike transmission and update process can be performed simultaneously with the LUT search, T _send and T _upd may correspond to 0, and in this case, Equation 1 becomes S ≤ f _clk /(aN), so that the maximum number of synapses May correspond to (S _max ), and may be expressed as Equation 3 below.

[Equation 3]

This relationship for different clock rates can be seen in Figure a in Figure 7 for a = 50 Hz. Assuming uniform neuronal interconnection, Equation 2 may correspond to S = NF _in = NF _out . In this case, the maximum allowed F _out (F _{out_max} ) can be derived from Equation 3 as F _{out_max} = f _clk /(aN ² ) (Fig. 7 b). That is, the RAM technique can support an F _{out_max} of 100 for each of a total of 200 neurons at a clock speed of 200 MHz. This theoretical estimate can be verified by routing of real-time monitoring events in a network (N = 100) implemented in an FPGA at a 50MHz clock rate.

In addition, we can change S from 6000 to 14000 (along the red dashed line in Figure 7 in Figure 7) and evaluate routing traffic congestion on average-average number of events stacked in queue register block 110 per neuron per second (B). Can be parameterized with B can correspond to 0 without traffic congestion. All neurons can be simulated externally to create Poisson spikes at a = 50Hz. In Fig. 7 c, it is possible to support the theoretical estimation that event build-up (traffic congestion) is apparent when S exceeds 10,000, such as S _max in Equation 3.

In Figure 5 (b), the LUT (S*2 matrix) can be stored in the CAM array. Meanwhile, each memory row can have an independent comparator. During spike routing, all rows in the LUT can be retrieved at once in the process of searching for rows containing N_ADR, and the search result for all rows-“0” (does not match) or “1” (matches)- May be temporarily stored in the buffer BUF.

The buffer may correspond to an S element memory array-one entry for each row of the LUT-and may be connected to a priority encoder that outputs the matched synaptic address S_ADR. Each entry of “1” in the buffer can be converted to a corresponding address (S_ADR) by the priority encoder, and can be transmitted simultaneously with S_UPD (= 1). On the next clock cycle, the corresponding entry in the buffer is deleted, and the next entry of "1" (if any) can be transmitted at once. This process can be repeated until the buffer becomes empty.

The search time T _srch of the CAM scheme may correspond to the sum of the CAM matching latency and the time required to transmit the matching data to the buffer. Assuming that the CAM is fast enough within the clock speed range, both of the above operations can be performed within a single clock cycle, and thus, T _srch = 1/f _clk .

Also, the spike transmission time T _send may correspond to the time required to designate all matches of the buffer. For uniform neuron interconnection, 2F _out (F _out = F _in ) matches exist per event, so T _send = 2F _out /f _clk , where F _out = S/N.

In addition, neuron and synaptic updates occur simultaneously with spike transmission, so that T _upd = 0 can be effectively _achieved . Therefore, Equation 1 for this technique may _correspond to S ≤ f _clk /(2a)-N/2 by applying S _max and F _{out_max} expressed as in Equation 4 below.

[Equation 4]

Figure d of FIG. 7 can confirm S _max in relation to N for different clock speeds, in which case a can be set to 50 Hz. The estimated S _max value exceeds the value of the RAM technique several times more (Fig. 7 b), and can accommodate more neurons and synapses. Figure e of FIG. 7 may indicate the performance of a larger F _{out_max} .

For example, each of 20,000 neurons can have a F _out of 100 at 200 MHz f _clk without congestion in routing traffic. The theoretical estimate can be verified by simulating event routing for a network of 500 neurons (a = 50 Hz) at a 10 MHz clock rate.

In this case, B can be monitored with various S values from 60,000 to 140,000 (along the red dashed line in Fig. 7 d). Figure f of FIG. 7 may indicate that there is no delay in event routing for S of S _max (about 100,000) or less. Theoretical estimates can only be verified by simulation as the CAM implementation on the FPGA board is limited to a small SNN.

6 is a diagram for explaining an operation in the topology block of FIG. 1.

Referring to FIG. 6, the neuromorphic apparatus 100 according to an embodiment of the present invention may divide the entire LUT (S*2 matrix) into M lower LUTs, and each lower LUT as in FIG. 3 Likewise, it may include P*2 entries (P = S/M). Each divided partition may be composed of a RAM array (for example, RAM_0 or RAM_1) and a comparator COMP. All partitions can share the same address pointer (PTR) specifying a specific row for all M sub-LUTs at once.

For example, in FIG. 3, a PTR (= 2) generated by ADR GEN may designate all second rows of M lower LUTs at the same time. Next, it is possible to detect a matching entry by comparing PRE_ADR and POST_ADR, which are outputs of each lower LUT, with N_ADR. In this case, all M comparisons for all partitions may be performed in parallel. The PTR may be generated up to P rows, and a match result for each row-"0" (disconsistency) and "1" (match)-may be transmitted to the buffer BUF.

The RAM array may include front and rear neuron elements, each consisting of addresses of presynaptic neurons and post synaptic neurons. The RAM array may include an output unit (OUTPUT) that outputs PRE_ADR as a presynaptic neuron address and POST_ADR as a post-synaptic neuron address in the front and rear neuron elements designated by the PTR.

The total search time per event performed in the topology block may be expressed as T _srch = P/f _clk . The total event transmission time is the same as in the case of the CAM technique, and may correspond to T _send = 2F _out /f _clk with F _out = S/N for uniform neuron interconnection. In addition, neuron and synaptic updates can occur simultaneously with event transmission. Therefore, S _max and F _{out_max} can be expressed by the following equation (5) for the method of the present invention.

[Equation 5]

Figure g of FIG. 7 can show the relationship between a = 50Hz and P = 256. F _{out_max} per neuron can be seen in Figure h of FIG. 7. As indicated by the red dashed line in Figure h, for each of about 9,000 neurons, an F _{out_max} of 100 can be supported by the method of the present invention at a clock rate of 200 MHz. Thus, the capacity may correspond between RAM and CAM techniques (see comparison of Figures h and b, e in Figure 7).

When P = 1, the method of the present invention becomes the same as the CAM technique, and Equation 5 may be the same as Equation 4. To verify this theoretical estimate, the network (N = 500, a = 50 Hz and P = 256) to which the method of the present invention is applied (implemented on an FPGA board at a clock rate of 20 MHz) is monitored in real time to obtain S (80,000 to 210,000) ), the event buildup B can be analyzed. The result of Figure i of FIG. 7 can verify Equation 5 in that routing traffic congestion starts at 136,000 synapses equal to the theoretical S _max value.

8 is a block diagram illustrating a functional configuration of a neuromorphic device according to an embodiment of the present invention.

Referring to FIG. 8, the neuromorphic device 100 includes a neuron address receiving unit 810, an index address providing unit 820, a matching detection unit 830, a synaptic address output unit 840, and a control unit 850. I can.

The neuron address receiver 810 may receive an address of a spiking neuron. When a specific neuron generates a spike, it may correspond to a spiking neuron, and the address of the specific neuron may be transmitted to the topology block through the queue register block 110, and the neuron address receiver 810 By receiving the neuron's address, it can initiate the spiking operation. Here, the spiking operation may correspond to processing an operation in which a spike is transmitted through a neural network. The neuron address receiver 810 may provide the address of the spiking neuron to the matching detector 830.

The index address providing unit 820 may provide an index address for simultaneously designating front and rear neuron elements in each of a plurality of parallel look-up table (LUT) modules divided into a first synaptic address among synaptic addresses. Here, the parallel look-up table (LUT) module may be generated by dividing a memory array into a plurality of memory arrays, may store each divided LUT, and may be arranged to perform LUT search in parallel. That is, the parallel LUT module may correspond to a partitioned RAM. The parallel LUT module may be designated by a first synaptic address corresponding to some of the synaptic addresses, and the front and rear neuron elements stored in the parallel LUT module may be designated by an index address provided by the index address providing unit 820.

The parallel LUT module may store anterior and posterior neuron elements, and the anterior and posterior neuronal elements may contain addresses of presynaptic neurons and post-synaptic neurons. The anteroposterior neuron element is a unit stored in a parallel LUT module, and each parallel LUT module can store the same number of anteroposterior neuron elements. For example, if the total number of synapses is S and the number of parallel LUT modules is M, each parallel LUT module can store S/M (= P) front and rear neuron elements.

In an embodiment, the index address providing unit 820 may provide an index address by sequentially designating front and rear neuron elements from start to finish. For example, the index address providing unit 820 may generate the index address PTR while increasing by 1 from 0 to P-1, and each parallel LUT module sequentially sequentially selects the front and rear neuron elements designated by the PTR. You can explore. In FIG. 6, both of the RAM arrays RAM_0 and RAM_1 may store four front-rear neuron elements, and each front-rear neuron element may be designated as an index from 0 to 3. In this case, the index address providing unit 820 may sequentially provide 0 to 3 as index addresses.

In one embodiment, the index address providing unit 820 may temporarily stop providing the index address when a match occurs through comparison. If a match is detected, the synaptic address is calculated based on the current index address in order to propagate the spike to the next neuron according to the matching, and thus the index address providing unit 820 so that the current index address is not changed. Can pause the operation.

In an embodiment, the index address providing unit 820 may resume providing the index address when output of the synaptic address is completed in association with matching. The spiking operation may be performed on all neurons connected to the spiking neuron, and the index address providing unit 820 provides an index address after processing for a specific index address is completed to search for all neurons connected to the spiking neuron. In order to do so, you can resume the operation.

The matching detection unit 830 provides at least one of the addresses of presynaptic neurons and post-synaptic neurons in the front and rear neuron elements according to the index address, and compares the address of the spiking neuron with one of the addresses of presynaptic neurons or post-synaptic neurons. I can. In one embodiment, the matching detection unit 830 may provide addresses of presynaptic neurons and post-synaptic neurons in front and rear neuron elements according to the index address.

In FIG. 6, when PTR = 0 is provided as an index address by ADR GEN, the matching detection unit 830 sets the address PRE_ADR of the presynaptic neuron of the front and rear neuron element stored in the index 0 of RAM_0 and RAM_1 and the address of the post synaptic neuron POST_ADR, respectively It may be provided as an output (OUTPUT in FIG. 6), and it may be compared with the address N_ADR of the spiking neuron received by the neuron address receiver 810 to determine whether to match (COM of FIG. 6). In this case, PRE_ADR and POST_ADR provided by OUTPUT may be provided independently, respectively, and may be provided simultaneously.

In an embodiment, the matching detection unit 830 may output a trigger signal for synapse update when a match occurs through comparison. In FIG. 6, when a match is detected through the comparator COMP, the matching detection unit 830 may output a result thereof, and output S_UPD as a trigger signal for synaptic update.

In an embodiment, the matching detection unit 830 may determine a spike progress signal according to whether the neuron in which the match has occurred is a pre-synaptic neuron or a post-synaptic neuron. More specifically, when the address N_ADR of the spiking neuron matches the address PRE_ADR of the presynaptic neuron, the matching detection unit 830 may determine the spike progress signal UPD_SEL = 1. That is, when UPD_SEL = 1, the synapse designated by the synaptic address S_ADR output from the topology block may correspond to a fan-out synapse.

When a match occurs through comparison, the synaptic address output unit 840 may merge the first synaptic address and the index address to output the synaptic address connected to the spiking neuron. More specifically, the synaptic address output unit 840 may generate a synaptic address by integrating a bit string corresponding to the first synaptic address and a bit string corresponding to the index address into one. At this time, the ADR GEN that generates the index address may temporarily stop the operation.

In an embodiment, the synaptic address output unit 840 may complete the synaptic address by merging the first synaptic address into the upper bit string and the index address into the lower bit string. In FIG. 6, the first synaptic address may correspond to PART = 1 as an address for RAM_1 where matching is detected, and the index address may correspond to PTR = 0 as an index address of a neuron element before and after a match is detected. In this case, the synaptic address output unit 840 may generate “100” as the address of the synapse by connecting the bit string “1” corresponding to PART = 1 and the bit string “00” corresponding to PTR = 0 with each other. , As a result, the synaptic address S_ADR = 4 may be output.

The control unit 850 controls the overall operation of the neuromorphic device 100, and a control flow between the neuron address receiving unit 810, the index address providing unit 820, the matching detection unit 830, and the synaptic address output unit 840 Or you can manage the data flow.

9 is a flowchart illustrating a spiking operation process performed in a neuromorphic device according to an embodiment of the present invention.

Referring to FIG. 9, the neuromorphic device 100 may receive an address of a spiking neuron through the neuron address receiver 810 (step S910). The neuromorphic device 100 is an index that simultaneously designates front and rear neuron elements in each of a plurality of parallel look-up table (LUT) modules divided into a first synaptic address among synaptic addresses through the index address providing unit 820 An address can be provided (step S930). The neuromorphic device 100 may provide at least one of the addresses of presynaptic neurons and postsynaptic neurons in the front and rear neuron elements according to the index address through the matching detection unit 830 (step S950).

Further, the neuromorphic device 100 may compare the address of the spiking neuron with one of the addresses of a presynaptic neuron or a post-synaptic neuron through the matching detection unit 830 (step S970). When a match occurs through comparison through the synaptic address output unit 840, the neuromorphic device 100 may merge the first synaptic address and the index address and output it as an address of a synapse connected to the spiking neuron (step S990. ).

In one embodiment, the neuromorphic device 100 detects a spiking neuron, receives an address of a spiking neuron, a plurality of parallel look-up table (LUT) modules based on the address of the spiking neuron Determining at least one of the addresses of presynaptic neurons and post-synaptic neurons by designating each of them simultaneously, comparing the addresses of spiking neurons with the addresses of presynaptic neurons or post-synaptic neurons, and when matching occurs The spiking operation is processed by merging the module address of the parallel LUT module and the index address corresponding to the address of the presynaptic neuron or post-synaptic neuron in the parallel LUT module and outputting it as the address of the synapse connected to the spiking neuron. can do.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims. You will understand that you can do it.

100: neuromorphic device 110: queue register block
810: neuron address receiving unit 820: index address providing unit
830: matching detection unit 840: synaptic address output unit
850: control unit

Claims (9)

(a) receiving an address of a spiking neuron;
(b) providing an index address for simultaneously designating anterior and posterior neuron elements in each of a plurality of parallel look-up table (LUT) modules divided into a first synaptic address among synaptic addresses;
(c) providing at least one of an address of a presynaptic neuron and a postsynaptic neuron in the anterior and posterior neuron element according to the index address;
(d) comparing the address of the spiking neuron with one of the addresses of the presynaptic neuron or the post-synaptic neuron; And
(e) when a match occurs through the comparison, the first synaptic address and the index address are merged and output as an address of a synapse connected to the spiking neuron. .
The method of claim 1, wherein step (b)
And providing the index address by sequentially designating the front and rear neuron elements from the beginning to the end of the neuromorphic device.
The method of claim 1, wherein step (b)
And temporarily stopping the provision of the index address when the match occurs through the comparison.
The method of claim 3, wherein step (b) is
And resuming the provision of the index address when the output of the synaptic address is completed in association with the matching.
The method of claim 1, wherein step (c)
And providing the addresses of the presynaptic neurons and the post-synaptic neurons in the front and rear neuron elements according to the index address.
The method of claim 1, wherein step (d)
And outputting a trigger signal for synaptic update when the match occurs through the comparison.
The method of claim 6, wherein step (d)
And determining a spike progress signal according to whether the matched neuron is a pre-synaptic neuron or a post-synaptic neuron.
The method of claim 1, wherein step (e)
And completing the address of the synapse by merging the first synaptic address into an upper bit string and the index address into a lower bit string.
In the method for calculating a spike of a neuromorphic device including a plurality of synapses and a plurality of neurons,
(a) detecting spiking neurons;
(b) receiving the address of the spiking neuron;
(c) simultaneously designating each of a plurality of parallel Look-up Table (LUT) modules based on the address of the spiking neuron to determine at least one of the addresses of the presynaptic neuron and the postsynaptic neuron;
(d) comparing the address of the spiking neuron and the address of the presynaptic neuron or the post-synaptic neuron; And
(e) When a match occurs through the comparison, the module address of the parallel LUT module and the index address corresponding to the address of the presynaptic neuron or the post-synaptic neuron in the parallel LUT module are merged to be connected to the spiking neuron. Spike calculation method of a neuromorphic device comprising the step of outputting as an address of.

Images