KR20180093245A - Neuromorphic arithmetic device - Google Patents

Abstract

The present invention relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device according to the present invention includes first and second synapse circuits, a charging and discharging circuit, a comparator, and a counter. The first synapse circuit generates a first current by performing a first multiplication operation on a first PWM signal and a first weight and the second synapse circuit generates a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging and discharging circuit stores charges by the first current and the second current during a charging period and discharges the charges during a discharging period. The comparator compares the voltage levels of the charges discharged in the discharge period with the level of a reference voltage. The counter counts the output pulses of an oscillator based on the comparison result of the comparator. Accordingly, the present invention can reduce current consumption.

Description

[0001] NEUROMORPHIC ARITHMETIC DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a neurometry computing apparatus, and more particularly, to a neuromotion computing apparatus implemented in an analog manner.

A neuromorphic computing device is a device for processing information by imitating human nervous system or brain. Unlike the conventional configuration in which the computer, the instruction processor, and the storage device, which are based on the computer central processing unit, are independent from each other, the novelrom computing unit can parallelize and process the information. New Lomographic computing devices can process information centered on newly occurring events, even in the process of processing information.

A neodrome computing device can be defined as a two-dimensional or three-dimensional connection of a plurality of neurons. Each neuron can consist of a circuit corresponding to an axon, a dendrite, and a cell body (soma), just like the components of a biological neuron. In particular, an operation is performed in a synapse circuit that connects a neuron and a neuron.

The role of the synapse circuit (operator) is very important in order to process the information input to the neopromplex computing device in parallel and swiftly. In order to quickly process such vast amounts of data, a general neuromorphic computing device is equipped with a calculator implemented in a digital manner. According to this configuration, as the amount of data to be processed increases, the power consumption increases greatly, and the chip area also increases greatly. Thus, in applications where power consumption is an issue, circuit expansion is very limited.

 Generally, in a synapse of an analog type neuromorphic computing device, the capacitance of the metal line generated to implement the dendrite protrusion is used. At this time, the oscillator is operated, and the node is directly charged or discharged to perform addition and multiplication operations. However, in this type of operation, the metal line having a very large capacitance value is directly charged or discharged by using an oscillator. Therefore, when the operating frequency is high, there is a problem that the waste of electric charge is very serious and power consumption is also increased. In addition, since the capacitance of the metal line increases as the number of synapse circuits increases, there is a problem that the size of the current source must be increased at the synapse in order to generate the same operating frequency.

It is an object of the present invention to provide a neuromorphic computing device which converts the result of an analog-processed operation into a digital value and outputs the digital value.

A neuromotion computing apparatus according to an embodiment of the present invention includes a first synapse circuit configured to perform a first multiplication operation on a first PWM signal and a first weight to generate a first current, A second synapse circuit configured to generate a second current by performing a second multiplication operation on the first weight and the second weight to store charges due to the first current and the second current in a charging interval, A comparator for comparing a voltage level of the discharged electric charges in the discharge interval with a level of a reference voltage and a counter for counting output pulses of the oscillator based on the comparison result of the comparator can do.

For example, the neuromorphic computing device may further comprise a first PWM converter for converting the first input to the first PWM signal, and a second PWM converter for converting the second input to the second PWM signal have.

For example, the first synapse circuit may include a first AND gate that performs an AND operation on the first PWM signal and the first weight, and a second AND gate that generates the first current according to the output of the first AND gate Wherein the second synapse circuit includes a second AND gate for performing an AND operation on the second PWM signal and the second weight and a second AND gate for performing an AND operation on the second PWM signal and the second weight, 2 < / RTI > current. ≪ RTI ID = 0.0 > The first charge current source is configured such that the voltage level of the charge and discharge circuit by the first current increases linearly, and the second charge current source is configured to increase the voltage level of the charge and discharge circuit by the charge and discharge circuit May be configured to increase linearly.

For example, the charging and discharging circuit may include a capacitor for storing the charges in the charging period, and a discharging current source configured to linearly reduce the voltage level of the capacitor by the charges in the discharging period can do.

For example, the comparator may output an enable signal which is activated in a period in which the voltage level of the discharged electric charges is larger than the reference voltage. The comparator may be a differential amplifier operating in a period in which the charge and discharge circuit is discharged. The counter may count the output pulses of the oscillator in a period in which the enable signal is activated. The neuromorph operation apparatus may further include a switch for switching on the oscilloscope in response to the activation of the enable signal and for connecting the oscillator and the counter.

For example, the neuromotion computing apparatus may further include a level shifter for shifting a digital value output from the counter.

According to the embodiment of the present invention, various operations are processed in an analog manner by using the charge and discharge circuit provided in the neuromorph operation apparatus. Therefore, since it is not necessary to oscillate the dendrite capacitor every time, the consumption current can be reduced.

Further, according to the embodiment of the present invention, since the neuromorphic computing device is implemented using analog elements, the chip size and manufacturing cost can be reduced.

1 is a block diagram showing a neuromorphic computing apparatus according to an embodiment of the present invention.
Fig. 2 is a view showing the operation of the PWM converters shown in Fig. 1. Fig.
3 is a block diagram illustrating an exemplary configuration of the synapse circuits shown in FIG.
4 is a block diagram illustrating an exemplary configuration of the charge and discharge circuit and comparator shown in FIG.
FIG. 5A is a diagram showing the operation of the charging and discharging circuit shown in FIG. 4 when charging. FIG.
FIG. 5B is a diagram showing the operation of discharging the charging and discharging circuit shown in FIG. 4; FIG.
Figure 6 is a graph showing the operation of the charge and discharge circuit and the comparator described in Figures 5A and 5B.
7 is a block diagram showing a neuromorphic computing apparatus according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, details such as detailed configurations and structures are provided merely to assist in an overall understanding of embodiments of the present invention. Modifications of the embodiments described herein can be made by those skilled in the art without departing from the spirit and scope of the invention. Furthermore, descriptions of well-known functions and structures are omitted for clarity and brevity. The terms used in this specification are defined in consideration of the functions of the present invention and are not limited to specific functions. Definitions of terms may be determined based on the description in the detailed description.

Modules in the following figures or detailed description may be shown in the drawings or may be connected to others in addition to the components described in the detailed description. The connections between the modules or components may be direct or non-direct, respectively. The connections between the modules or components may be a communication connection or a physical connection, respectively.

The components described with reference to terms such as a unit or a unit, a module, a layer or the like used in the detailed description may be implemented in the form of software, hardware, or a combination thereof. Illustratively, the software may be machine code, firmware, embedded code, and application software. For example, the hardware may include an electrical circuit, an electronic circuit, a processor, a computer, an integrated circuit, integrated circuit cores, a pressure sensor, an inertial sensor, a MEMS (Micro Electro Mechanical System), a passive device, .

Unless otherwise defined, all terms including technical and scientific meanings used herein have the same meaning as can be understood by one of ordinary skill in the art to which this invention belongs. Generally, terms defined in the dictionary are interpreted to have equivalent meaning to the contextual meanings in the related art and are not to be construed as having ideal or overly formal meaning unless expressly defined in the text.

1 is a block diagram showing a neuromorphic arithmetic device according to an embodiment of the present invention. The novelogram computation apparatus 100 includes a plurality of PWM converters 111 to 11n, a plurality of synapse circuits 121 to 12n, a charging and discharging circuit 130, a comparator 140, and a counter 150 .

The novelogram computation device 100 may be configured to perform a plurality of multiplications on a plurality of multipliers and multiplicands. For example, the synaptic circuits 121 to 12n provided in the neuromorphic computing apparatus 100 may operate as multipliers for performing multiplication operations. Further, the neuromorphic computing device 100 may be configured to perform a sum operation on a plurality of multiplications. For example, the charge and discharge circuit 130 included in the neuromorphic computing device 100 may operate as an adder that performs a sum operation on product operations.

The plurality of pulse width modulator converters 111 to 11n may receive the plurality of inputs INPUT1 to INPUTn to generate the PWM signals PWM1 to PWMn, respectively. For example, the plurality of inputs INPUT1 to INPUTn may be binary values, and each of the PWM signals PWM1 to PWMn may correspond to each of the plurality of inputs INPUT1 to INPUTn. That is, the PWM signals PWM1 to PWMn may have different pulse widths depending on the input values. Each of the PWM signals PWM1 to PWMn may have a high value at logic '1' of the binary input and a low value at the logic '0' of the binary input. For example, the PWM converters 111 to 11n may be activated by the first enable signal EN1.

The plurality of synapse circuits 121 to 12n can receive the plurality of PWM signals PWM1 to PWMn, respectively. For example, the lines in which the PWM signals PWM1 to PWMn are respectively received may correspond to the axon of the neuron. The plurality of synapse circuits 121 to 12n can receive the weights W1 to Wn, respectively. Alternatively, the weights W1 to Wn may be values stored in each of the synapse circuits 121 to 12n. For example, the PWM signals PWM1 to PWMn may be multiplicands which are multiplied numbers. The weights W1 to Wn may be multipliers, which are multipliers.

Each of the plurality of synapse circuits 121 to 12n may be configured to perform a multiplication operation on multiplicands (e.g., any one of PWM1 to PWMn) and multipliers (e.g., any one of W1 to Wn). To perform the multiplication operation, each of the plurality of synapse circuits 121 to 12n may include a current source, a logic gate, and a switch. Each of the plurality of synapse circuits 121 to 12n can output the currents I1 to In as a result of the multiplication operation.

The charging and discharging circuit 130 may be configured to charge or discharge charges corresponding to the sum of the currents I1 to In. For example, the charging and discharging circuit 130 may correspond to a dendrite of a nerve cell. To implement the dendrites, the charging and discharging circuit 130 may include a metal line having its own capacitance component. Alternatively, the charging and discharging circuit 130 may include a separate capacitor. Hereinafter, in the present specification, the capacitor described as being included in the charging and discharging circuit 130 means at least one of a metal line having its own capacitance component provided for realizing the water dendrite, or a capacitor provided separately .

The charging and discharging circuit 130 charges charges from the current sources provided in the synapse circuits 121 to 12n in the section in which the first activating signal EN1 is activated or in the section in which the second enabling signal EN2 is inactivated Can be supplied. For example, the time when the charge and discharge circuit 130 receives charge from the current sources provided in the synapse circuits 121 to 12n is determined by the PWM signals PWM1 to PWMn by the PWM converters 111 to 11n, And it is possible to prevent the charge from being supplied during a period in which the PWM signals PWM1 to PWMn are not generated.

Alternatively, the charging and discharging circuit 130 may be configured to charge the charge stored in the charging and discharging circuit 130 in a period in which the first activating signal EN1 is inactivated or in a period in which the second enabling signal EN2 is inactivated Lt; / RTI > On the other hand, the charging and discharging circuit 130 may be configured to discharge the charges stored in the charging and discharging circuit 130 in a period in which the second enable signal EN2 is activated.

The comparator 140 may be configured to compare the voltage level of the node N with the voltage level of the reference voltage Vref to generate the third enable signal EN3. For example, the comparator 140 may not operate in a period in which the second enable signal EN2 is inactivated. On the other hand, the comparator 140 can compare the voltage level of the node N with the level of the reference voltage Vref in a period in which the second enable signal EN2 is activated.

For example, in a period in which the second enable signal EN2 is inactivated, the currents I1 to In outputted from the synapse circuits 121 to 12n are supplied to the storage elements provided in the charging and discharging circuit 130 Can be charged. Thus, the voltage at node N will continue to increase. On the other hand, when the second enable signal EN2 is activated, the charging and discharging circuit 130 discharges the stored charges, so that the voltage at the node N will be lowered. At this time, the comparator 140 compares the voltage level of the node N to be lowered with the level of the reference voltage Vref to generate the third enable signal EN3. For example, the comparator 140 can generate the third enable signal EN3, which is activated in a period in which the voltage level of the node N is higher than the level of the reference voltage Vref.

The counter 150 may count pulses output from the oscillator OSC in a period in which the third enable signal EN3 is activated. For example, the oscillator OSC and the counter 150 may be connected by a switch SW that is switched on by the third enable signal EN3. For example, when the oscillator OSC and the counter 150 are connected by switching on the switch SW by the third enable signal EN3, the counter 150 counts pulses outputted from the oscillator OSC (Or clocks).

However, the configuration shown in FIG. 1 is merely an example, and various configurations are possible in which the output signal OUTPUT can be generated by counting the pulses output from the oscillator OSC in a period in which the third enable signal EN3 is activated. Or logic elements can be applied.

According to the embodiment described above, depending on the operation of the PWM converters 111 to 11n, the synapse circuits 121 to 12n, the charge and discharge circuit 130, and the comparator 140 implemented as analog circuits, And a summation result of the final sum operation is provided as a digital value based on the signal output from the comparator 140 (i.e., EN3) and the pulses output from the oscillator OSC . Since most of the arithmetic operations are performed by analog circuits, the circuit configuration can be simplified and the chip size can be reduced.

Fig. 2 is a view showing the operation of the PWM converters shown in Fig. 1. Fig. The operation of the first PWM converter 111 of the plurality of converters 111 to 11n is illustrated by way of example and the configuration and operation of the other converters 112 to 11n are substantially the same as those of the first PWM converter 111 Do.

The first PWM converter 111 may receive the first input INPUT1 to generate the first PWM signal PWM1. Illustratively, the first input INPUT1 is shown as being an 8-bit binary number. The waveforms of the PWM signals output from the first PWM converter 111 and the binary numbers input to the first PWM converter 111 are illustratively shown. For example, the first PWM converter 111 can output a bit '1' in a logic high interval of an input binary number and output a bit '0' in a logic low interval of an input binary number.

3 is a block diagram illustrating an exemplary configuration of the synapse circuits shown in FIG. For simplicity of illustration, only the first and n th synapse circuits 121 and 12n of the synapse circuits 121 to 12n are shown. The first synapse circuit 121 may include an AND gate, a first charging power source (CCS1), and a first switch (SW1). The n-th synapse circuit 121 may include an AND gate, an n-th charged-state power source current source (CCSn), and an n-th switch (SWn).

The AND gates of the synapse circuits 121 to 12n can receive the PWM signals PWM1 to PWMn generated by the PWM converters 111 to 11n, respectively. For example, the PWM signals PWM1 to PWMn may be multiplicities that are multiplied by a multiplication operation. Meanwhile, the weights W1 to Wn may also be input to the AND gates of the synapse circuits 121 to 12n, respectively. For example, the weights W1 to Wn may be multipliers that are multipliers. For example, the weights W1 to Wn may be inputted from the outside or stored in the synapse circuits 121 to 12n.

Each of the switches SW1 to SWn may be switched on or switched off depending on the operation result performed by the AND gates provided in each of the synapse circuits 121 to 12n. For example, if the result of the operation performed by the AND gate is logic '1', the switch will be switched on, and if the result of the operation performed by the AND gate is logic '0', the switch will be switched off. By switching on the switches SW1 to SWn, the current generated by the charge current sources CCS1 to CCSn will flow through the node N. [

The charge current sources CCS1 to CCSn may be configured such that the voltage level by the charge stored in the charge element (for example, which may be provided in the charge and discharge circuit 130 in Fig. 1) linearly increases. In general, when a storage element such as a capacitor is charged, the voltage level across the capacitor increases exponentially. However, even if the current generated by the charging current sources CCS1 to CCSn charges the charging and discharging circuit (Fig. 1, 130) through the node N, the storage element of the charging and discharging circuit , Capacitors, etc.) or the voltage level at node N will increase linearly.

According to the configuration shown in Fig. 3, sum operations for a plurality of multiplication operations can be performed. For example, the first synapse circuit 121 may perform a first multiplication operation on multiplier PWM1 and multiplicand W1. Similarly, the nth synapse circuit 12n may perform an n-th multiply operation on multiplier PWMn and multiplicand Wn. Here, the result of the first multiplication operation may be represented by current I1, and the result of the n-th product operation may be represented by current In. Eventually, the sum of the first product operation to the n-th product operation will appear as the sum of the currents I1 to In.

If the linearity of the storage elements (e.g., capacitors, etc.) of the charge and discharge circuit (Figs. 1 and 130) is not guaranteed, the sum of the currents I1 to In will not represent the sum of the first to nth product operations . However, since the charge current sources CCS1 to CCSn are configured to ensure the linearity of the storage elements (e.g., capacitors and the like) of the charge and discharge circuits (Figs. 1 and 130), the sum of the first- Can represent the sum of the currents I1 to In.

4 is a block diagram illustrating an exemplary configuration of the charge and discharge circuit 130 and comparator 140 shown in FIG.

The charge and discharge circuit 130 may be configured to charge the electric charge corresponding to the currents I1 to In according to the second enable signal EN2 or to discharge the charged electric charge. Illustratively, the charging and discharging circuit 130 is shown as including a capacitor C, a discharging current source (DCS), and a discharging switch DSW. However, various configurations can be applied to charge or discharge according to the second enable signal EN2. For example, not only a discharge current source (DCS), a capacitor (C), but also various active elements and passive elements can be further employed.

The discharge current source DCS helps the voltage level of the node N linearly decrease when the charging and discharging circuit 130 discharges. Generally, upon discharge of the capacitor, the charge stored in the capacitor decreases exponentially. However, in order to perform a sum operation on a plurality of multiplication operations, linearity must be ensured. Therefore, by providing the discharge current source DCS, the voltage level of the node N at the time of discharge decreases linearly.

The comparator 140 can compare the voltage level of the node N with the level of the reference voltage Vref and output the third enable signal EN3 according to the comparison result. For example, the comparator 140 can output the third activation signal EN3 only when the voltage level of the node N is higher than the level of the reference voltage Vref. The comparator 140 may comprise an operational amplifier or a differential amplifier, but is not limited thereto. For example, the comparator 140 may be implemented in various configurations for comparing the two voltage levels and outputting the third activation signal EN3 according to the comparison result.

Fig. 5A is a diagram showing the operation of the charging and discharging circuit 130 shown in Fig. 4 when charged.

Upon charging of the charging and discharging circuit 130, the second activation signal EN2 is inactivated. Therefore, charges due to the currents I1 to In flowing through the node N will be stored in the capacitor C. [ As the capacitor C is charged, the voltage level at node N will increase linearly. Since the currents I1 to In are based on the charge current sources CCS1 to CCSn having linearity. On the other hand, since the second activation signal EN2 is in an inactive state, the comparator 140 does not operate. Therefore, the third enable signal EN3 is also not output.

FIG. 5B is a diagram showing the operation of the charging and discharging circuit 130 shown in FIG. 4 during discharging.

When the charging and discharging circuit 130 is discharged, the second activating signal EN2 is activated. The discharge switch DSW is switched on by the second enable signal EN2 so that the capacitor C is grounded through the discharge current source DCS. At this time, due to the linear discharge current source DCS, the voltage level of the node N will decrease linearly.

On the other hand, since the second activation signal EN2 is in the active state, the comparator 140 will perform the comparison operation. The comparator 140 can compare the voltage level of the node N with the level of the reference voltage Vref and the third enable signal EN3 that is activated in a period in which the voltage level of the node N is higher than the level of the reference voltage Vref, Lt; / RTI >

FIG. 6 is a graph showing the operation of the charge and discharge circuit 130 and the comparator 140 described in FIGS. 5A and 5B. The horizontal axis of the graph represents time, and the vertical axis represents the voltage level of the capacitor C (or node N). One calculation cycle may include a charging interval and a discharging interval. 1, 3, 5a, and 5b will be described together to facilitate understanding of the description.

In the charging period, the first enable signal EN1 is activated, and the second enable signal EN2 and the third enable signals EN3_A and EN3_B are inactivated. That is, in the charging period, only the multiplication operation by the synapse circuits 121 to 12n and the sum operation by the charging and discharging circuit 130 are performed. On the other hand, discharging by the charging and discharging circuit 130 does not occur, and the comparator 140 does not operate either.

The charging period may represent a process in which product operations are performed on the synapse circuits 121 to 12n and a process in which product operations are added. 5a and 5b, since the voltage level Vcap of the capacitor increases linearly in the charging period, the sum of the currents I1 to In through node N can indicate that the multiplication operations are summed up have. This linearity can be ensured by the charge current sources CCS1 to CCSn provided in each of the synapse circuits 121 to 12n.

If the sum of the product operations is relatively large, the voltage level of the capacitor C (or node N) (e.g., V _A ) will be relatively large. In this case, the summed result may correspond to the graph indicated by A. On the other hand, if the sum of the product operations is relatively small, the voltage level of the capacitor C (or node N) (e.g., V _B ) would be relatively small. In this case, the summed result may correspond to the graph indicated by B.

In the discharge period, the first enable signal EN1 is inactivated, and the second enable signal EN2 and the third enable signals EN3_A and EN3_B are activated. Activation of the second enable signal EN2 means that the charging and discharging circuit 130 is discharged. However, the third enable signals EN3_A and EN3_B are not always activated in the discharge interval. That is, the third enable signals EN3_A and EN3_B are activated only during a period when the voltage level of the capacitor C (or the voltage level of the node N) is higher than the level of the reference voltage Vref.

In the discharge interval, a process of digitizing or digitizing the summed result expressed by the amount of charge stored in the capacitor C may be performed. 5A and 5B, the voltage level Vcap of the capacitor decreases linearly in the discharge interval. This linearity can be ensured by a discharge current source (DCS) provided in the charging and discharging circuit 130.

If the value of the sum operation for the multiplication operations is relatively large, the voltage level of the capacitor C (or the node N) will be relatively long in a section where the voltage level is higher than the level of the reference voltage Vref. On the other hand, if the sum of the sum operations for the multiplications is relatively small, the voltage level of the capacitor C (or node N) will be relatively short in a period in which the voltage level is higher than the level of the reference voltage Vref.

During the interval during which the third enable signals EN3_A and EN3_B are activated in the discharge interval, the counter 150 connected to the output of the comparator 140 may count the output pulses of the oscillator OSC. The counted result (i. E., OUTPUT) may be suitably shifted (e. G., By a level shifter, etc.) and used accordingly.

According to the above-described configuration, an analog circuit composed of comparatively simple elements such as a discharge switch (DSW), a discharge current source (DCS), a capacitor C and a comparator 140 is used to perform a sum operation Can be performed, and the operation result can be represented by a digital value through the counter. Therefore, the configuration of the circuit can be simplified, and the manufacturing cost can also be reduced. In addition, since the linearity of charging and discharging occurring in the charging and discharging circuit 130 is ensured, the result of the sum operation on the multiplication operations can be accurately quantified.

7 is a block diagram showing a neuromorphic computing apparatus according to an embodiment of the present invention. The neuromotion computing apparatus 1000 includes PWM converters 211 to 21n, synapse circuits 311 to 318, 321 to 328 to 3n1 to 3n8, charge and discharge circuits 401 to 408, An oscillator (OSC), a switching circuit 600, counters 701 to 708, and a summer 800. In addition,

The basic structure of the neuromorphic computing apparatus 1000 may be similar to the neuromorphic computing apparatus described above with reference to Figs. 1 to 6 above. However, synapse circuits are arranged in matrix form along the row and column directions. A charge and discharge circuit, a comparator, a switch, and a counter are disposed in each column.

Each of the PWM converters 211 to 21n may be arranged for each row of the synapse circuits 311 to 318, 321 to 328, ..., 3n1 to 3n8. For example, the first PWM converter 211 may be connected to the synapse circuits 310. The second PWM converter 212 may be coupled to the synapse circuits 320. Other PWM converters may be similarly arranged.

The PWM converters 211 to 21n may receive the plurality of inputs INPUT1 to INPUTn to generate the PWM signals PWM1 to PWMn, respectively. The plurality of inputs INPUT1 to INPUTn may be binary values and the PWM signals PWM1 to PWMn may be signals having different pulse widths corresponding to the inputs INPUT1 to INPUTn, respectively. The PWM converters 211 to 21n can be activated by the first enable signal EN1.

The synapse circuits 311 to 318, 321 to 328, ..., 3n1 to 3n8 may be arranged in a matrix form along the row and column directions. For example, the synapse circuits 310 may be disposed along the first row, and the synapse circuits 320 may be disposed along the second row. Other synapse circuits are similarly arranged. Illustratively, the synapse circuits are shown as being arranged in n rows and 8 columns, but are not limited thereto.

The synapse circuits 311 to 318 disposed in the first row may be configured to perform a first multiplication operation on the first multiplicand and the first multiplier. For example, each of the synapse circuits 311 to 318 may receive the first PWM signal PWM1 as the first multiplicand.

The synapse circuits 311 to 318 can receive the first multiplier. Alternatively, the first multiplier may be pre-stored in each synapse circuit. However, each synapse circuit may receive only one bit of the first multiplier. For example, suppose the first multiplier is an 8-bit binary input, the synapse circuit 311 may store the most significant bit (MSB) of the first multiplier, and the synapse circuit 318 may store the most significant bit (LSB) of the first multiplier Least Significant Bit). Synapse circuits 312-317 may sequentially store the remaining bits between the MSB and LSB of the first multiplier.

Each of the synapse circuits 311 to 318 may perform a partial product on the first multiplicand, the first PWM signal PWM1 and the first multiplicand. For example, the synapse circuit 311 may perform a multiplication operation on the MSB of the first multiplicand and the first PWM signal PWM1. The synapse circuit 318 may perform a multiplication operation on the first PWM signal PWM1 and the LSB of the first multiplicand. The remaining synapse circuits 312 to 317 may also multiply the first PWM signal PWM1 and the remaining bits of the first multiplicand.

The result of the multiplication operation performed by each of the synapse circuits 311 to 318 can be represented by the current output from each synapse circuit, as described above with reference to Figs. That is, the results of the first multiplication operation performed by the synapse circuits 311 - 318 may be stored in the charge and discharge circuits 401 - 408, respectively.

The synapse circuits 321-328 disposed in the second row may be configured to perform a second multiplication operation on the second multiplicand and the second multiplier. For example, each of the synapse circuits 321-328 may receive a second PWM signal PWM2 as a second multiplicand. Similar to what has been described above, each of the synaptic circuits 321-328 can receive one of the bits constituting the second multiplier. The partial multiplication of the second multiplicand and the second multiplier, performed by each of the synapse circuits 321-328, can be represented by the current output from each synapse circuit, and the charge and discharge circuits 401 To 408, respectively.

In addition to the result of the first multiplication operation performed previously by the synapse circuits 311 through 318, the result of the second multiplication operation performed by the synapse circuits 321 through 328 is applied to the charge and discharge circuits 401 through 408 ), The sum operation by the charge and discharge circuits 401 to 408 is performed.

The remaining synapse circuits are similarly partially performed, and the result will be stored in the charge and discharge circuits 401 to 408.

Thereafter, discharging by the charging and discharging circuits 401 to 408, voltage comparison by the comparators 500, and counting of the counters 700 in accordance with the switching-on of the switching circuit 600 are performed at the time of discharging will be. Their operations are generally similar to those described above with reference to Figures 1-6.

After the results of the multiplication operations by the synapse circuits 311 to 318, 321 to 328, ..., 3n1 to 3n8 are accumulated in the charge and discharge circuits 401 to 408, the first enable signal EN1 is deactivated Will be. Then, the second enable signal EN2 is activated and discharges in the charge and discharge circuits 401 to 408 will occur. The voltage levels of the capacitors provided in the charge and discharge circuits 401 to 408 will decrease linearly as shown in FIG. This linearity is due to the discharge current source provided in the charge and discharge circuits 401 to 408.

Simultaneously with the discharge in the charge and discharge circuits 401 to 408, the comparators 500 are activated by the second enable signal EN2. As a result, the voltage level across the capacitor of each of the charging and discharging circuits 401 to 408 will be compared with the voltage level of the reference voltage Vref. The comparators 500 generate the third enable signals EN3 that are activated in a period in which the voltage levels across the capacitors provided in the charge and discharge circuits 401 to 408 are higher than the level of the reference voltage Vref .

Each of the switches constituting the switching circuit 600 may be switched on in a period in which the third enable signal EN3 is activated. At this time, pulses (or clocks) output from the oscillator OSC are input to the counters 701 to 708, and counting by the counters 701 to 708 can be performed. The counting results by the counters 701 to 708 will be output as digital values.

However, the digital values output from the counters 701 to 708 are not considered in which bits the partial product performed on the multiplier and multiplicand is the operation on the bit. Therefore, proper shifting (or level shifting) must be performed on the digital values output from the counters 701 to 708 in order to obtain a perfect calculation result.

For example, the digital value output from the counter 701 is the sum of the multiplicands and the partial products of the MSBs of the multipliers. Therefore, the digital value output from the counter 701 must be multiplied by 2 ⁷ (i.e., 128). For example, the digital value output from the counter 708 is the sum of the multiplicands and the partial products of the LSBs of the multipliers. Thus, ²⁰ (that is, 1) for the digital value outputted from the counter 708 to be multiplied. Shifting should be similarly performed on the digital values output from the other counters 702 to 707. This shifting can be performed, for example, by a level shifter (not shown) or the like.

The summer 800 may add the shifted digital values and output the summation result OUTPUT. The summer 800 may be composed of various logic elements that can add a plurality of digital values and output the results.

According to the configuration described above, the relatively simple elements such as the charge and discharge circuits 400, the comparators 500, the switching circuit 600, and the counters 700, each including the discharging switch, the discharging current source and the capacitor A novel Lomographic computation device can be implemented using a configured analog circuit. Therefore, the configuration of the circuit can be simplified, and the manufacturing cost can also be reduced. Furthermore, since the linearity of charge and discharge occurring in the charge and discharge circuits 400 is ensured, the result of the sum operation on the multiplications can be accurately obtained.

The above description is a concrete example for carrying out the present invention. The present invention includes not only the above-described embodiments, but also embodiments that can be simply modified or easily changed. In addition, the present invention includes techniques that can be easily modified by using the above-described embodiments.

100: New Lomographic computing device
111 ~ 11n: PWM converters
121 ~ 12n: Synapse circuits
130: Charging and discharging circuit
140: comparator
150: Counter

Claims (10)

A first synapse circuit configured to perform a first multiplication operation on a first PWM signal and a first weight to generate a first current;
A second synapse circuit configured to perform a second multiplication operation on the second PWM signal and the second weight to generate a second current;
A charging and discharging circuit configured to store charges by the first current and the second current in a charging period and to discharge the charges in a discharging period;
A comparator for comparing the voltage level of the discharged charges in the discharge interval with the level of the reference voltage; And
And a counter for counting output pulses of the oscillator based on the comparison result of the comparator. The method according to claim 1,
A first PWM converter for converting a first input to the first PWM signal; And
And a second PWM converter for converting the second input to the second PWM signal. The method according to claim 1,
The first synapse circuit comprising:
A first AND gate for performing an AND operation on the first PWM signal and the first weight; And
And a first charge current source for generating the first current according to the output of the first AND gate,
Said second synapse circuit comprising:
A second AND gate for performing an AND operation on the second PWM signal and the second weight; And
And a second charge current source for generating the second current according to the output of the second AND gate. The method of claim 3,
Wherein the first charge current source is configured to linearly increase the voltage level of the charge and discharge circuit by the first current,
Wherein the second charge current source is configured to linearly increase the voltage level of the charge and discharge circuit by the second current. The method according to claim 1,
The charging and discharging circuit comprises:
A capacitor for storing the charges in the charging period; And
And a discharging current source configured to linearly reduce the voltage level of the capacitor by the charges in the discharging interval. The method according to claim 1,
Wherein the comparator outputs an enable signal which is activated in a period in which the voltage level of the discharged electric charges is larger than the reference voltage. The method according to claim 6,
Wherein the comparator is a differential amplifier that operates in a period in which the charge and discharge circuit is discharged. 8. The method of claim 7,
Wherein the counter counts the output pulses of the oscillator in a period in which the enable signal is activated. 9. The method of claim 8,
Further comprising: a switch for switching on the oscillator according to the activation of the enable signal and connecting the oscillator to the counter. The method according to claim 1,
And a level shifter for shifting the digital value output from the counter.

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