KR20200144078A - Pixel circuit and display device including the same - Google Patents

Abstract

A pixel circuit includes a light emitting diode, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a storage capacitor. The light emitting diode includes an anode electrode connected to a power supply voltage. The first NMOS transistor and the second NMOS transistor are connected in series with each other between a data line and a first node. The third NMOS transistor includes: a drain electrode connected to a cathode electrode of the light emitting diode; a gate electrode connected to the first node; a source electrode connected to a ground voltage; and a body electrode connected to the ground voltage. The storage capacitor is connected between the first node and the ground voltage. The gate electrode of the first NMOS transistor and the gate electrode of the second NMOS transistor are commonly connected to a scan line, the source electrode and the body electrode of the first NMOS transistor are electrically connected to each other, and the source electrode and the body electrode of the second NMOS transistor are electrically connected to each other. A drain electrode of the first NMOS transistor is connected to the data line, and a source electrode and the body electrode of the first NMOS transistor are connected to a second node. A drain electrode of the second NMOS transistor is connected to the first node, and a source electrode and the body electrode of the second NMOS transistor are connected to the second node.

Description

A pixel circuit and a display device including the same TECHNICAL FIELD

The present invention relates to a display device, and more particularly, to a pixel circuit included in the display device.

Recently, various types of flat panel display devices have been developed that can reduce the weight and volume, which is a disadvantage of a cathode ray tube.

Among flat panel display devices, a light emitting diode (LED) display device is a device that displays an image by controlling the intensity of the current flowing through the light emitting diode and adjusting the brightness of light generated from the light emitting diode. At the same time, there is an advantage of being driven with low power consumption.

In general, the LED display device is classified into a passive matrix type LED display device and an active matrix type LED display device according to a method of driving the LED.

The active matrix LED display device includes a plurality of pixel circuits connected to a plurality of scan lines and a plurality of data lines and arranged in a matrix form.

In addition, each of the pixel circuits is typically a light emitting diode, a switch transistor for transmitting a data signal, a capacitor for maintaining a data voltage corresponding to the data signal, and a driving transistor for driving the light emitting diode according to the data voltage. Consists of

Although such an active matrix type LED display device has the advantage of low power consumption, the size of the data voltage stored in the capacitor of the pixel circuit is not kept constant during one frame, and the size of the data voltage stored in the capacitor due to loss of charge. When is changed, there is a problem that the quality of the displayed image is deteriorated.

An object of the present invention for solving the above problems is to provide a pixel circuit capable of maintaining a constant magnitude of a data voltage stored in a capacitor of a pixel circuit for one frame.

Another object of the present invention is to provide a light emitting diode display device including the pixel circuit.

In order to achieve the object of the present invention described above, a pixel circuit according to an embodiment of the present invention includes a light emitting diode, a first NMOS transistor, a second NMOS transistor, and a storage capacitor. The light emitting diode includes an anode electrode connected to a power supply voltage. The first NMOS transistor includes a drain electrode connected to a data line, a gate electrode connected to a scan line, a source electrode connected to a first node, and a body electrode connected to the first node. The second NMOS transistor includes a drain electrode connected to a cathode electrode of the light emitting diode, a gate electrode connected to the first node, a source electrode connected to a boosting line, and a body electrode connected to the boosting line. The storage capacitor is connected between the first node and the boosting line.

In order to achieve one object of the present invention, a display device according to an embodiment of the present invention includes a pixel unit, a scan driver, a boost driver, and a data driver. The pixel portion includes a plurality of scan lines, a plurality of boosting lines, and a plurality of pixel circuits positioned at each intersection of the plurality of data lines. The scan driver provides a scan signal to the plurality of scan lines. The boosting driver provides a boosting signal to the plurality of boosting lines. The data driver provides a data signal to the plurality of data lines. Each of the plurality of furnace circuits includes a light emitting diode including an anode electrode connected to a power supply voltage, a drain electrode connected to a corresponding data line, a gate electrode connected to a corresponding scan line, and a source electrode connected to a first node. , And a first NMOS transistor including a body electrode connected to the first node, a drain electrode connected to the cathode electrode of the light emitting diode, a gate electrode connected to the first node, and a source electrode connected to a corresponding boosting line And a second NMOS transistor including a body electrode connected to the corresponding boosting line, and a storage capacitor connected between the first node and the corresponding boosting line.

In order to achieve the object of the present invention described above, a pixel circuit according to an embodiment of the present invention includes a light emitting diode, a first PMOS transistor, a second PMOS transistor, and a storage capacitor. The light emitting diode includes a cathode electrode connected to a ground voltage. The first PMOS transistor includes a source electrode connected to a data line, a gate electrode connected to a scan line, a drain electrode connected to a first node, and a body electrode connected to the data line. The second PMOS transistor includes a drain electrode connected to the anode electrode of the light emitting diode, a gate electrode connected to the first node, a source electrode connected to a boosting line, and a body electrode connected to the boosting line. The storage capacitor is connected between the first node and the boosting line.

In order to achieve one object of the present invention, a display device according to an embodiment of the present invention includes a pixel unit, a scan driver, a boost driver, and a data driver. The pixel portion includes a plurality of scan lines, a plurality of boosting lines, and a plurality of pixel circuits positioned at each intersection of the plurality of data lines. The scan driver provides a scan signal to the plurality of scan lines. The boosting driver provides a boosting signal to the plurality of boosting lines. The data driver provides a data signal to the plurality of data lines. Each of the plurality of furnace circuits includes a light emitting diode including a cathode electrode connected to a ground voltage, a source electrode connected to a corresponding data line, a gate electrode connected to a corresponding scan line, and a drain electrode connected to a first node. , And a first PMOS transistor including a body electrode connected to the corresponding data line, a drain electrode connected to the anode electrode of the light emitting diode, a gate electrode connected to the first node, and a source connected to a corresponding boosting line And a second PMOS transistor including an electrode and a body electrode connected to the corresponding boosting line, and a storage capacitor connected between the first node and the corresponding boosting line.

In order to achieve the object of the present invention described above, a pixel circuit according to an embodiment of the present invention includes a light emitting diode, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a storage capacitor. The light emitting diode includes an anode electrode connected to a power supply voltage. The first NMOS transistor and the second NMOS transistor are connected in series between a data line and a first node. The third NMOS transistor includes a drain electrode connected to a cathode electrode of the light emitting diode, a gate electrode connected to the first node, a source electrode connected to a ground voltage, and a body electrode connected to the ground voltage. The storage capacitor is connected between the first node and the ground voltage. A gate electrode of the first NMOS transistor and a gate electrode of the second NMOS transistor are commonly connected to a scan line, a source electrode and a body electrode of the first NMOS transistor are electrically connected to each other, and The source electrode and the body electrode are electrically connected to each other.

In order to achieve the object of the present invention described above, a display device according to an embodiment of the present invention includes a pixel portion, a scan driver, and a data driver. The pixel portion includes a plurality of pixel circuits positioned at each intersection of a plurality of scan lines and a plurality of data lines. The scan driver provides a scan signal to the plurality of scan lines. The data driver provides a data signal to the plurality of data lines. Each of the plurality of furnace circuits includes a light emitting diode including an anode electrode connected to a power supply voltage, a first NMOS transistor and a second NMOS transistor connected in series between a corresponding data line and a first node, and the light emitting diode. A third NMOS transistor including a drain electrode connected to the cathode electrode of, a gate electrode connected to the first node, a source electrode connected to a ground voltage, and a body electrode connected to the ground voltage, and the first node And a storage capacitor connected between the ground voltage. The gate electrode of the first NMOS transistor and the gate electrode of the second NMOS transistor are commonly connected to a corresponding scan line, the source electrode and the body electrode of the first NMOS transistor are electrically connected to each other, and the second NMOS transistor The source electrode and the body electrode of the transistor are electrically connected to each other.

In order to achieve the object of the present invention described above, a pixel circuit according to an embodiment of the present invention includes a light emitting diode, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a storage capacitor. The light emitting diode includes a cathode electrode connected to a ground voltage. The first PMOS transistor and the second PMOS transistor are connected in series between a data line and a first node. The third PMOS transistor includes a drain electrode connected to the anode electrode of the light emitting diode, a gate electrode connected to the first node, a source electrode connected to a power voltage, and a body electrode connected to the power voltage. The storage capacitor is connected between the first node and the power voltage. The gate electrode of the first PMOS transistor and the gate electrode of the second PMOS transistor are commonly connected to a scan line, the source electrode and the body electrode of the first PMOS transistor are electrically connected to each other, and The source electrode and the body electrode are electrically connected to each other.

In order to achieve the object of the present invention described above, a display device according to an embodiment of the present invention includes a pixel portion, a scan driver, and a data driver. The pixel portion includes a plurality of pixel circuits positioned at each intersection of a plurality of scan lines and a plurality of data lines. The scan driver provides a scan signal to the plurality of scan lines. The data driver provides a data signal to the plurality of data lines. Each of the plurality of furnace circuits includes a light emitting diode including a cathode electrode connected to a ground voltage, a first PMOS transistor and a second PMOS transistor connected in series between a corresponding data line and a first node, and the light emitting diode. A third PMOS transistor including a drain electrode connected to the anode electrode of, a gate electrode connected to the first node, a source electrode connected to a power voltage, and a body electrode connected to the power voltage, and the first node And a storage capacitor connected between the power supply voltages. The gate electrode of the first PMOS transistor and the gate electrode of the second PMOS transistor are commonly connected to a corresponding scan line, the source electrode and the body electrode of the first PMOS transistor are electrically connected to each other, and the second PMOS transistor The source electrode and the body electrode of the transistor are electrically connected to each other.

The pixel circuit according to the exemplary embodiments of the present invention effectively prevents loss of charge stored in the capacitor, and maintains the level of the voltage stored in the capacitor constant for one frame, thereby maintaining a high quality of the provided image.

1 is a block diagram illustrating a display device according to an embodiment of the present invention.
2 is a circuit diagram illustrating an example of a pixel circuit included in the display device of FIG. 1.
3 is a timing diagram illustrating an operation of the display device of FIG. 1.
4 is a block diagram illustrating a display device according to another exemplary embodiment of the present invention.
5 is a circuit diagram illustrating an example of a pixel circuit included in the display device of FIG. 4.
6 is a timing diagram illustrating an operation of the display device of FIG. 4.
7 is a block diagram illustrating a display device according to another embodiment of the present invention.
8 is a circuit diagram illustrating an example of a pixel circuit included in the display device of FIG. 7.
9 is a circuit diagram illustrating another example of a pixel circuit included in the display device of FIG. 7.
10 is a block diagram illustrating a display device according to another exemplary embodiment of the present invention.
11 is a circuit diagram illustrating an example of a pixel circuit included in the display device of FIG. 10.
12 is a circuit diagram illustrating another example of a pixel circuit included in the display device of FIG. 10.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions have been exemplified only for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be implemented in various forms. It should not be construed as being limited to the embodiments described in.

Since the present invention can apply various changes and have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific form of disclosure, it is to be understood as including all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "just between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

The terms used in the present application are used only to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the presence of a set feature, number, step, action, component, part, or combination thereof, and one or more other features or numbers It is to be understood that the possibility of addition or presence of, steps, actions, components, parts, or combinations thereof is not preliminarily excluded.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning of the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions for the same elements are omitted.

1 is a block diagram illustrating a display device according to an embodiment of the present invention.

Referring to FIG. 1, the display apparatus 10 includes a pixel portion 100a, a scan driver 200, a boosting driver 300, and a data driver 400.

The scan driver 200, the boosting driver 300, and the data driver 400 may be implemented as a single integrated circuit (IC) chip.

The pixel portion 100a is connected to the scan driver 200 through a plurality of scan lines S1, S2, ..., Sn (n is a positive integer), and a plurality of boosting lines B1, B2, ..., Bn) is connected to the boosting driving unit 300, and connected to the data driving unit 400 through a plurality of data lines D1, D2, ..., Dm (m is a positive integer).

The pixel portion 100a includes a plurality of scan lines S1, S2, ..., Sn, a plurality of boosting lines B1, B2, ..., Bn, and a plurality of data lines D1, D2, ..., Dm. It includes n*m pixel circuits 110 positioned at each intersection of.

Each of the plurality of pixel circuits 110 operates using a power supply voltage VDD.

In an embodiment, each of the plurality of pixel circuits 110 may receive a power voltage VDD provided from the outside.

In another embodiment, each of the plurality of pixel circuits 110 may receive a power voltage VDD generated from a voltage generator included in the display device 10.

As will be described later with reference to FIG. 2, each of the plurality of pixel circuits 110 includes a light emitting diode (LED). In addition, each of the plurality of pixel circuits 110 is implemented using an N-type Metal Oxide Semiconductor (NMOS) transistor.

The scan driver 200 provides a scan signal to each of the plurality of pixel circuits 110 through a plurality of scan lines S1, S2, ..., Sn.

The boosting driver 300 provides a boosting signal to each of the plurality of pixel circuits 110 through the plurality of boosting lines B1, B2, ..., Bn.

The data driver 400 provides a data signal to each of the plurality of pixel circuits 110 through the plurality of data lines D1, D2, ..., Dm.

Each of the plurality of pixel circuits 110 displays an image by emitting the light emitting diode at a brightness corresponding to the data signal using the scan signal, the boosting signal, and the data signal.

2 is a circuit diagram illustrating an example of a pixel circuit included in the display device of FIG. 1.

Each of the plurality of pixel circuits 110 included in the display device 10 of FIG. 1 may be implemented with the pixel circuit 110 shown in FIG. 2.

In FIG. 2, the pixel circuit 110 located in row j and column i (i and j are positive integers) will be described as an example.

The pixel circuit 110 receives the scan signal S_S from the scan driver 200 shown in FIG. 1 through the scan line Sj, and receives the boosting line Bj from the boosting driver 300 shown in FIG. 1. Through the boosting signal B_S, the data signal D_S may be received from the data driver 400 shown in FIG. 1 through the data line Di.

Referring to FIG. 2, the pixel circuit 110 may include a light emitting diode LD, a first NMOS transistor MN1, a second NMOS transistor MN2, and a storage capacitor Cst.

The first NMOS transistor MN1 may include a drain electrode connected to the data line Di, a gate electrode connected to the scan line Sj, and a source electrode connected to the first node N1.

Meanwhile, the body electrode of the first NMOS transistor MN1 may be electrically connected to the source electrode of the first NMOS transistor MN1. Accordingly, the body electrode of the first NMOS transistor MN1 may be connected to the first node N1.

The second NMOS transistor MN2 includes a drain electrode connected to the cathode electrode of the light emitting diode LD, a gate electrode connected to the first node N1, and a source electrode connected to the boosting line Bj. can do.

Meanwhile, the body electrode of the second NMOS transistor MN2 may be electrically connected to the source electrode of the second NMOS transistor MN2. Accordingly, the body electrode of the second NMOS transistor MN2 may be connected to the boosting line Bj.

The light emitting diode LD may include an anode electrode connected to the power voltage VDD and a cathode electrode connected to the drain electrode of the second NMOS transistor MN2.

The storage capacitor Cst may be connected between the first node N1 and the boosting line Bj.

The first NMOS transistor MN1 may operate as a switch transistor of the pixel circuit 110, and the second NMOS transistor MN2 may operate as a driving transistor of the pixel circuit 110.

In an embodiment, the first NMOS transistor MN1 and the second NMOS transistor MN2 may be formed as a single chip.

In this case, the source electrode and the body electrode of the first NMOS transistor MN1 may be electrically connected to each other inside the chip, and the source electrode and the body electrode of the second NMOS transistor MN2 may be electrically connected to each other inside the chip. have.

In addition, a drain electrode, a gate electrode, and a source electrode of the first NMOS transistor MN1 and a drain electrode, a gate electrode, and a source electrode of the second NMOS transistor MN2 may be connected to external fins of the chip, respectively.

As will be described later with reference to FIG. 3, when the pixel circuit 110 according to an embodiment of the present invention stores the data signal D_S provided through the data line Di in the storage capacitor Cst, the boosting line The boosting effect by the boosting signal B_S provided through (Bj) is used.

3 is a timing diagram illustrating an operation of the display device of FIG. 1.

The pixel portion 100a included in the display device 10 of FIG. 1 will be described as including the pixel circuit 110 of FIG. 2.

3 shows signals applied to the pixel circuits 110 during one frame period.

In FIG. 3, S_S[1] represents a scan signal S_S provided from the scan driver 200 to the pixel circuits 110 connected to the first scan line S1 through the first scan line S1. , S_S[2] represents a scan signal S_S provided from the scan driver 200 to the pixel circuits 110 connected to the second scan line S2 through the second scan line S2, and S_S[ n] represents a scan signal S_S provided from the scan driver 200 to the pixel circuits 110 connected to the n-th scan line Sn through the n-th scan line Sn. Meanwhile, B_S[1] denotes a boosting signal B_S provided from the boosting driver 300 to the pixel circuits 110 connected to the first boosting line B1 through the first boosting line B1, and B_S [2] denotes a boosting signal B_S provided from the boosting driver 300 to the pixel circuits 110 connected to the second boosting line B2 through the second boosting line B2, and B_S[n] Denotes a boosting signal B_S provided from the boosting driver 300 to the pixel circuits 110 connected to the nth boosting line Bn through the nth boosting line Bn. Meanwhile, D_S[i] represents a data signal D_S provided from the data driver 400 to the pixel circuits 110 connected to the i-th data line Di through the i-th data line Di.

The scan driver 200 provides a scan signal S_S that is sequentially activated at a logic high level to a plurality of scan lines S1, S2, ..., Sn, and thus a plurality of scan lines S1, S2, ..., Sn ) Can be selected sequentially.

In addition, the boosting driver 300 may provide a boosting signal B_S that is sequentially activated to a logic high level to the plurality of boosting lines B1, B2, ..., Bn in synchronization with the scan driver 200.

Specifically, as shown in FIG. 3, when the scan signal S_S applied to the scan line Sj is activated from the logic low level to the logic high level, the boosting signal B_S applied to the boosting line Bj Is increased from the first voltage V1 to the second voltage V2, and when the scan signal S_S applied to the scan line Sj is deactivated from the logic high level to the logic low level, the boosting line Bj is The applied boosting signal B_S may drop from the second voltage V2 to the first voltage V1.

In this case, the boosting voltage Vd corresponding to the difference between the second voltage V2 and the first voltage V1 is the maximum voltage and the lowest voltage that the data signal D_S applied to the data line Di can have. Can be greater than the difference.

Meanwhile, the data driver 400 may provide a data signal D_S corresponding to image data to be displayed on the pixel circuit 110 to the data line Di.

At this time, the data signal D_S applied to the data line Di has a voltage level higher by the boosting voltage Vd than the voltage level corresponding to the target brightness of the light emitting diode LD included in the pixel circuit 110. Can have.

For example, as shown in FIG. 3, when the voltage level corresponding to the target brightness of the light emitting diode LD included in the pixel circuit 110 is the same as the first graph A, the data driver 400 As in the second graph (B), a signal having a voltage level higher than the voltage level corresponding to the first graph (A) by the boosting voltage (Vd) may be provided as the data signal (D_S) to the data line (Di). .

Hereinafter, specific operations of the pixel circuit 110 will be described in detail with reference to FIGS. 1 to 3.

The first NMOS transistor MN1 may be turned on while the scan signal S_S applied to the corresponding scan line Sj is activated to a logic high level.

When the first NMOS transistor MN1 is turned on, the data signal D_S applied to the data line Di may be transmitted to the first node N1.

As described above, while the scan signal S_S applied to the scan line Sj is activated to a logic high level, the boosting signal B_S applied to the boosting line Bj is a voltage raised to the second voltage V2. Has.

Accordingly, a voltage corresponding to the difference between the voltage corresponding to the data signal D_S and the second voltage V2 may be stored in the storage capacitor Cst.

Thereafter, when the scan signal S_S applied to the scan line Sj is deactivated from the logic high level to the logic low level, the first NMOS transistor MN1 is turned off and the gate electrode of the second NMOS transistor MN2 is turned off. The corresponding first node N1 may be blocked from the data line Di.

As described above, when the scan signal S_S applied to the scan line Sj is deactivated from a logic high level to a logic low level, the boosting signal B_S applied to the boosting line Bj is the second voltage V2 ) To the first voltage V1 by the boosting voltage Vd. However, since the first NMOS transistor MN1 is turned off and the first node N1 is cut off from the data line Di, the boosting signal B_S is a boosting voltage from the second voltage V2 to the first voltage V1. When the voltage falls by (Vd), the voltage of the first node N1 may also decrease by the boosting voltage Vd from the voltage corresponding to the data signal D_S. Therefore, the voltage stored in the storage capacitor Cst may be maintained at a voltage corresponding to the difference between the voltage corresponding to the data signal D_S and the second voltage V2 regardless of the voltage level change of the boosting signal B_S. .

As shown in FIG. 2, since the storage capacitor Cst is connected between the gate electrode and the source electrode of the second NMOS transistor MN2, the second NMOS transistor MN2 has the magnitude of the voltage stored in the storage capacitor Cst. A drain current corresponding to is generated, and the light emitting diode LD may emit light with a brightness corresponding to the magnitude of the drain current.

When the scan signal S_S applied to the scan line Sj is activated again at a logic high level in the next frame period, and a new data signal D_S applied to the data line Di is transmitted to the first node N1 Until, the light emitting diode LD may emit light with a brightness corresponding to the magnitude of the voltage stored in the storage capacitor Cst during one frame period.

At this time, when the magnitude of the voltage stored in the storage capacitor Cst is not kept constant for one frame period and the magnitude of the voltage stored in the storage capacitor Cst changes due to the loss of charge stored in the storage capacitor Cst, the display Since the quality of the image displayed on the device 10 is deteriorated, the magnitude of the voltage stored in the storage capacitor Cst needs to be kept constant for one frame period.

On the other hand, even after the scan signal S_S applied to the scan line Sj is deactivated from a logic high level to a logic low level and the first NMOS transistor MN1 is turned off, the data line Di is located in other rows. The data signal D_S to be provided to the pixel circuits 110 may be continuously applied.

At this time, even when the first NMOS transistor MN1 is turned off, since the body electrode of the first NMOS transistor MN1 is connected to the first node N1, the first node N1 is connected to the data line Di. When the data signal D_S having a voltage lower than the voltage of is applied, current flows from the body electrode of the first NMOS transistor MN1 to the data line Di, so that the magnitude of the voltage stored in the storage capacitor Cst changes. do.

However, when the scan signal S_S is deactivated from the logic high level to the logic low level and the first NMOS transistor MN1 is turned off, the boosting signal B_S is boosted from the second voltage V2 to the first voltage V1. Since the voltage falls by the voltage Vd, the voltage of the first node N1 has a voltage level lowered by the boosting voltage Vd from the voltage corresponding to the data signal D_S.

However, as described above, the boosting voltage Vd corresponding to the difference between the second voltage V2 and the first voltage V1 is the maximum voltage that the data signal D_S applied to the data line Di can have. Since it is greater than the difference between the voltage and the lowest voltage, the voltage of the data line Di even when the data signal D_S having the lowest voltage is applied to the data line Di while the first NMOS transistor MN1 is turned off. Is higher than the voltage of the first node N1.

Therefore, when the first NMOS transistor MN1 is turned off, the voltage of the first node N1 is always kept lower than the voltage of the data line Di. Therefore, the voltage stored in the storage capacitor Cst is limited. It can be kept constant throughout the frame.

As described above with reference to FIGS. 1 to 3, the pixel circuit 110 according to an exemplary embodiment of the present invention includes a first NMOS transistor MN1 and a second NMOS transistor MN2 having a body electrode electrically connected to the source electrode. Although implemented by using, since the magnitude of the voltage stored in the storage capacitor Cst is kept constant for one frame, the image quality can be maintained at a high level.

4 is a block diagram illustrating a display device according to another exemplary embodiment of the present invention.

Referring to FIG. 4, the display device 20 includes a pixel portion 100b, a scan driver 200, a boosting driver 300, and a data driver 400.

The scan driver 200, the boosting driver 300, and the data driver 400 may be implemented as a single integrated circuit (IC) chip.

The pixel portion 100b is connected to the scan driver 200 through a plurality of scan lines S1, S2, ..., Sn (n is a positive integer), and a plurality of boosting lines B1, B2, ..., Bn) is connected to the boosting driving unit 300, and connected to the data driving unit 400 through a plurality of data lines D1, D2, ..., Dm (m is a positive integer).

The pixel portion 100b includes a plurality of scan lines S1, S2, ..., Sn, a plurality of boosting lines B1, B2, ..., Bn, and a plurality of data lines D1, D2, ..., Dm. It includes n*m pixel circuits 120 positioned at each intersection of.

Each of the plurality of pixel circuits 120 operates using a ground voltage GND.

In an embodiment, each of the plurality of pixel circuits 120 may receive a ground voltage GND provided from the outside.

In another embodiment, each of the plurality of pixel circuits 120 may receive a ground voltage GND generated from a voltage generator included in the display device 20.

As will be described later with reference to FIG. 5, each of the plurality of pixel circuits 120 includes a light emitting diode (LED). In addition, each of the plurality of pixel circuits 120 is implemented using a P-type Metal Oxide Semiconductor (PMOS) transistor.

The scan driver 200 provides a scan signal to each of the plurality of pixel circuits 120 through a plurality of scan lines S1, S2, ..., Sn.

The boosting driver 300 provides a boosting signal to each of the plurality of pixel circuits 120 through the plurality of boosting lines B1, B2, ..., Bn.

The data driver 400 provides a data signal to each of the plurality of pixel circuits 120 through the plurality of data lines D1, D2, ..., Dm.

Each of the plurality of pixel circuits 120 displays an image by emitting the light emitting diode at a brightness corresponding to the data signal using the scan signal, the boosting signal, and the data signal.

5 is a circuit diagram illustrating an example of a pixel circuit included in the display device of FIG. 4.

Each of the plurality of pixel circuits 120 included in the display device 20 of FIG. 4 may be implemented with the pixel circuit 120 shown in FIG. 5.

In FIG. 2, the pixel circuit 120 located in row j and column i (i, j is a positive integer) will be described as an example.

The pixel circuit 120 receives the scan signal S_S from the scan driver 200 shown in FIG. 4 through the scan line Sj, and receives the boosting line Bj from the boosting driver 300 shown in FIG. 4. Through the boosting signal B_S, the data signal D_S may be received from the data driver 400 shown in FIG. 4 through the data line Di.

Referring to FIG. 5, the pixel circuit 120 may include a light emitting diode LD, a first PMOS transistor MP1, a second PMOS transistor MP2, and a storage capacitor Cst.

The first PMOS transistor MP1 may include a source electrode connected to the data line Di, a gate electrode connected to the scan line Sj, and a drain electrode connected to the second node N2.

Meanwhile, the body electrode of the first PMOS transistor MP1 may be electrically connected to the source electrode of the first PMOS transistor MP1. Accordingly, the body electrode of the first PMOS transistor MP1 may be connected to the data line Di.

The second PMOS transistor MP2 may include a drain electrode connected to the anode electrode of the light emitting diode LD, a gate electrode connected to the second node N2, and a source electrode connected to the boosting line Bj. .

Meanwhile, the body electrode of the second PMOS transistor MP2 may be electrically connected to the source electrode of the second PMOS transistor MP2. Accordingly, the body electrode of the second PMOS transistor MP2 may be connected to the boosting line Bj.

The light emitting diode LD may include a cathode electrode connected to the ground voltage GND and an anode electrode connected to the drain electrode of the second PMOS transistor MP2.

The storage capacitor Cst may be connected between the second node N2 and the boosting line Bj.

The first PMOS transistor MP1 may operate as a switch transistor of the pixel circuit 120, and the second PMOS transistor MP2 may operate as a driving transistor of the pixel circuit 120.

In an embodiment, the first PMOS transistor MP1 and the second PMOS transistor MP2 may be formed as one chip.

In this case, the source electrode and the body electrode of the first PMOS transistor MP1 may be electrically connected to each other inside the chip, and the source electrode and the body electrode of the second PMOS transistor MP2 may be electrically connected to each other inside the chip. have.

In addition, a drain electrode, a gate electrode, and a source electrode of the first PMOS transistor MP1 and a drain electrode, a gate electrode, and a source electrode of the second PMOS transistor MP2 may be connected to external fins of the chip, respectively.

As will be described later with reference to FIG. 6, when the pixel circuit 120 according to an embodiment of the present invention stores the data signal D_S provided through the data line Di in the storage capacitor Cst, the boosting line The boosting effect by the boosting signal B_S provided through (Bj) is used.

6 is a timing diagram illustrating an operation of the display device of FIG. 4.

The pixel portion 100b included in the display device 20 of FIG. 4 will be described as including the pixel circuit 120 of FIG. 5.

6 shows signals applied to the pixel circuits 120 during one frame period.

In FIG. 6, S_S[1] represents a scan signal S_S provided from the scan driver 200 to the pixel circuits 120 connected to the first scan line S1 through the first scan line S1. , S_S[2] denotes a scan signal S_S provided from the scan driver 200 to the pixel circuits 120 connected to the second scan line S2 through the second scan line S2, and S_S[ n] represents a scan signal S_S provided from the scan driver 200 to the pixel circuits 120 connected to the nth scan line Sn through the nth scan line Sn. Meanwhile, B_S[1] denotes a boosting signal B_S provided from the boosting driver 300 to the pixel circuits 120 connected to the first boosting line B1 through the first boosting line B1, and B_S [2] denotes a boosting signal B_S provided from the boosting driver 300 to the pixel circuits 120 connected to the second boosting line B2 through the second boosting line B2, and B_S[n] Denotes a boosting signal B_S provided from the boosting driver 300 to the pixel circuits 120 connected to the nth boosting line Bn through the nth boosting line Bn. Meanwhile, D_S[i] represents a data signal D_S provided from the data driver 400 to the pixel circuits 120 connected to the i-th data line Di through the i-th data line Di.

The scan driver 200 provides scan signals S_S that are sequentially activated at a logic low level to a plurality of scan lines S1, S2, ..., Sn, and thus a plurality of scan lines S1, S2, ..., Sn ) Can be selected sequentially.

In addition, the boosting driver 300 may provide a boosting signal B_S that is sequentially activated at a logic low level to the plurality of boosting lines B1, B2, ..., Bn in synchronization with the scan driver 200.

Specifically, as shown in FIG. 6, when the scan signal S_S applied to the scan line Sj is activated from a logic high level to a logic low level, the boosting signal B_S applied to the boosting line Bj Is lowered from the third voltage V3 to the fourth voltage V4, and when the scan signal S_S applied to the scan line Sj is deactivated from the logic low level to the logic high level, the boosting line Bj is The applied boosting signal B_S may rise from the fourth voltage V4 to the third voltage V3.

At this time, the boosting voltage Vd corresponding to the difference between the third voltage V3 and the fourth voltage V4 is the maximum voltage and the lowest voltage that the data signal D_S applied to the data line Di can have. Can be greater than the difference.

Meanwhile, the data driver 400 may provide a data signal D_S corresponding to image data to be displayed on the pixel circuit 120 to the data line Di.

In this case, the data signal D_S applied to the data line Di has a voltage level lower by the boosting voltage Vd than the voltage level corresponding to the target brightness of the light emitting diode LD included in the pixel circuit 120. Can have.

For example, as shown in FIG. 6, when the voltage level corresponding to the target brightness of the light emitting diode LD included in the pixel circuit 120 is the same as the first graph A, the data driver 400 As in the second graph (B), a signal having a voltage level lower than the voltage level corresponding to the first graph (A) by the boosting voltage (Vd) may be provided as the data signal (D_S) to the data line (Di). .

Hereinafter, specific operations of the pixel circuit 120 will be described in detail with reference to FIGS. 4 to 6.

The first PMOS transistor MP1 may be turned on while the scan signal S_S applied to the corresponding scan line Sj is activated to a logic low level.

When the first PMOS transistor MP1 is turned on, the data signal D_S applied to the data line Di may be transmitted to the second node N2.

As described above, while the scan signal S_S applied to the scan line Sj is activated to a logic low level, the boosting signal B_S applied to the boosting line Bj is a voltage lowered to the fourth voltage V4. Has.

Accordingly, a voltage corresponding to the difference between the voltage corresponding to the data signal D_S and the fourth voltage V4 may be stored in the storage capacitor Cst.

Thereafter, when the scan signal S_S applied to the scan line Sj is deactivated from the logic low level to the logic high level, the first PMOS transistor MP1 is turned off and is applied to the gate electrode of the second PMOS transistor MP2. The corresponding second node N2 may be blocked from the data line Di.

As described above, when the scan signal S_S applied to the scan line Sj is deactivated from the logic low level to the logic high level, the boosting signal B_S applied to the boosting line Bj is the fourth voltage V4 ) To the third voltage V3 by the boosting voltage Vd. However, since the first PMOS transistor MP1 is turned off and the second node N2 is cut off from the data line Di, the boosting signal B_S is a boosting voltage from the fourth voltage V4 to the third voltage V3. When the voltage increases by (Vd), the voltage of the second node N2 may also increase by the boosting voltage Vd from the voltage corresponding to the data signal D_S. Therefore, the voltage stored in the storage capacitor Cst may be maintained at a voltage corresponding to the difference between the voltage corresponding to the data signal D_S and the fourth voltage V4 regardless of the voltage level change of the boosting signal B_S. .

As shown in FIG. 5, since the storage capacitor Cst is connected between the gate electrode and the source electrode of the second PMOS transistor MP2, the second PMOS transistor MP2 has the magnitude of the voltage stored in the storage capacitor Cst. A drain current corresponding to is generated, and the light emitting diode LD may emit light with a brightness corresponding to the magnitude of the drain current.

When the scan signal S_S applied to the scan line Sj is activated again at a logic low level in the next frame period, and a new data signal D_S applied to the data line Di is transmitted to the second node N2 Until, the light emitting diode LD may emit light with a brightness corresponding to the magnitude of the voltage stored in the storage capacitor Cst during one frame period.

At this time, when the magnitude of the voltage stored in the storage capacitor Cst is not kept constant for one frame period and the magnitude of the voltage stored in the storage capacitor Cst changes due to the loss of charge stored in the storage capacitor Cst, the display Since the quality of the image displayed on the device 20 is deteriorated, the magnitude of the voltage stored in the storage capacitor Cst needs to be kept constant for one frame period.

On the other hand, even after the scan signal S_S applied to the scan line Sj is deactivated from a logic low level to a logic high level and the first PMOS transistor MP1 is turned off, the data line Di is located in other rows. The data signal D_S to be provided to the pixel circuits 120 may be continuously applied.

At this time, even when the first PMOS transistor MP1 is turned off, the body electrode of the first PMOS transistor MP1 is connected to the data line Di, so that the second node N2 is connected to the data line Di. When the data signal D_S having a voltage higher than the voltage is applied, current flows from the body electrode of the first PMOS transistor MP1 to the second node N2, so that the magnitude of the voltage stored in the storage capacitor Cst changes. do.

However, when the scan signal S_S is deactivated from the logic low level to the logic high level and the first PMOS transistor MP1 is turned off, the boosting signal B_S is boosted from the fourth voltage V4 to the third voltage V3. Since the voltage increases by the voltage Vd, the voltage of the second node N2 has a voltage level that is increased by the boosting voltage Vd from the voltage corresponding to the data signal D_S.

However, as described above, the boosting voltage Vd corresponding to the difference between the third voltage V3 and the fourth voltage V4 is the maximum voltage that the data signal D_S applied to the data line Di can have. Since it is greater than the difference between the voltage and the lowest voltage, the voltage of the data line Di is applied even when the data signal D_S having the maximum voltage is applied to the data line Di while the first PMOS transistor MP1 is turned off. Is lower than the voltage of the second node N2.

Therefore, when the first PMOS transistor MP1 is turned off, the voltage of the second node N2 is always maintained higher than the voltage of the data line Di, so that the voltage stored in the storage capacitor Cst is limited. It can be kept constant throughout the frame.

As described above with reference to FIGS. 4 to 6, the pixel circuit 120 according to an embodiment of the present invention includes a first PMOS transistor MP1 and a second PMOS transistor MP2 electrically connected to a source electrode with a body electrode. Although implemented by using, since the magnitude of the voltage stored in the storage capacitor Cst is kept constant for one frame, the image quality can be maintained at a high level.

7 is a block diagram illustrating a display device according to another embodiment of the present invention.

Referring to FIG. 7, the display device 30 includes a pixel portion 100c, a scan driver 200, and a data driver 400.

The scan driver 200 and the data driver 400 may be implemented as one integrated circuit (IC) chip.

The pixel portion 100c is connected to the scan driver 200 through a plurality of scan lines S1, S2, ..., Sn (n is a positive integer), and a plurality of data lines D1, D2, ..., Dm) (m is a positive integer) is connected to the data driver 400.

The pixel portion 100c includes n*m pixel circuits 130 positioned at each intersection of the plurality of scan lines S1, S2, ..., Sn and the plurality of data lines D1, D2, ..., Dm. Includes them.

Each of the plurality of pixel circuits 130 operates using a power voltage VDD and a ground voltage GND.

In an embodiment, each of the plurality of pixel circuits 130 may receive a power voltage VDD and a ground voltage GND provided from the outside.

In another embodiment, each of the plurality of pixel circuits 130 may receive a power voltage VDD and a ground voltage GND generated from a voltage generator included in the display device 30.

As will be described later with reference to FIGS. 8 and 9, each of the plurality of pixel circuits 130 includes a light emitting diode (LED). In addition, each of the plurality of pixel circuits 130 is implemented using an N-type Metal Oxide Semiconductor (NMOS) transistor, and two NMOS transistors connected in series with each other operate as a switch transistor.

The scan driver 200 provides a scan signal to each of the plurality of pixel circuits 130 through a plurality of scan lines S1, S2, ..., Sn.

The data driver 400 provides a data signal to each of the plurality of pixel circuits 130 through the plurality of data lines D1, D2, ..., Dm.

Each of the plurality of pixel circuits 130 displays an image by emitting the light emitting diode at a brightness corresponding to the data signal using the scan signal and the data signal.

8 is a circuit diagram illustrating an example of a pixel circuit included in the display device of FIG. 7.

Each of the plurality of pixel circuits 130 included in the display device 30 of FIG. 7 may be implemented with the pixel circuit 130a shown in FIG. 8.

In FIG. 8, the pixel circuit 130a located in the j row and i column (i, j is a positive integer) will be described as an example.

The pixel circuit 130a receives the scan signal S_S from the scan driver 200 shown in FIG. 7 through the scan line Sj, and receives the data line Di from the data driver 400 shown in FIG. 7. Through the data signal D_S may be received.

Referring to FIG. 8, the pixel circuit 130a includes a light emitting diode LD, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a storage capacitor Cst. can do.

The third NMOS transistor MN3 and the fourth NMOS transistor MN4 may be connected in series between the data line Di and the third node N3. In addition, the gate electrode of the third NMOS transistor MN3 and the gate electrode of the fourth NMOS transistor MN4 may be commonly connected to the scan line Sj.

Specifically, the third NMOS transistor MN3 may include a drain electrode connected to the data line Di, a gate electrode connected to the scan line Sj, and a source electrode connected to the fourth node N4. .

Meanwhile, the body electrode of the third NMOS transistor MN3 may be electrically connected to the source electrode of the third NMOS transistor MN3. Accordingly, the body electrode of the third NMOS transistor MN3 may be connected to the fourth node N4.

The fourth NMOS transistor MN4 may include a drain electrode connected to the third node N3, a gate electrode connected to the scan line Sj, and a source electrode connected to the fourth node N4.

Meanwhile, the body electrode of the fourth NMOS transistor MN4 may be electrically connected to the source electrode of the fourth NMOS transistor MN4. Accordingly, the body electrode of the fourth NMOS transistor MN4 may be connected to the fourth node N4.

The fifth NMOS transistor MN5 includes a drain electrode connected to the cathode electrode of the light emitting diode LD, a gate electrode connected to the third node N3, and a source electrode connected to the ground voltage GND. can do.

Meanwhile, the body electrode of the fifth NMOS transistor MN5 may be electrically connected to the source electrode of the fifth NMOS transistor MN5. Accordingly, the body electrode of the fifth NMOS transistor MN5 may be connected to the ground voltage GND.

The light emitting diode LD may include an anode electrode connected to the power voltage VDD and a cathode electrode connected to the drain electrode of the fifth NMOS transistor MN5.

The storage capacitor Cst may be connected between the third node N3 and the ground voltage GND.

The third NMOS transistor MN3 and the fourth NMOS transistor MN4 may operate as a switch transistor of the pixel circuit 130a, and the fifth NMOS transistor MN5 may operate as a driving transistor of the pixel circuit 130a.

In an embodiment, the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 may be formed as a single chip.

In this case, the source electrode and the body electrode of the third NMOS transistor MN3 are electrically connected to each other inside the chip, and the source electrode and the body electrode of the fourth NMOS transistor MN4 are electrically connected to each other inside the chip. , The source electrode and the body electrode of the fifth NMOS transistor MN5 may be electrically connected to each other inside the chip.

In addition, the drain electrode, the gate electrode, and the source electrode of the third NMOS transistor MN3, the drain electrode, the gate electrode, and the source electrode of the fourth NMOS transistor MN4, and the drain electrode of the fifth NMOS transistor MN5, The gate electrode and the source electrode may be connected to external pins of the chip, respectively.

Hereinafter, specific operations of the pixel circuit 130a will be described in detail with reference to FIGS. 7 and 8.

The scan driver 200 provides a scan signal S_S that is sequentially activated to a logic high level to a plurality of scan lines S1, S2, ..., Sn during one frame period, thereby providing a plurality of scan lines S1 and S2. , …, Sn) can be selected sequentially.

Meanwhile, the data driver 400 may provide a data signal D_S corresponding to image data to be displayed on the pixel circuit 130a to the data line Di.

The third NMOS transistor MN3 and the fourth NMOS transistor MN4 may be turned on while the scan signal S_S applied to the corresponding scan line Sj is activated to a logic high level.

When the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned on, the data signal D_S applied to the data line Di may be transmitted to the third node N3.

Since the storage capacitor Cst is connected between the third node N3 and the ground voltage GND, the voltage corresponding to the difference between the voltage corresponding to the data signal D_S and the ground voltage GND is the storage capacitor Cst. Can be stored in.

Thereafter, when the scan signal S_S applied to the scan line Sj is deactivated from the logic high level to the logic low level, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off to turn off the fifth NMOS transistor. The third node N3 corresponding to the gate electrode of the transistor MN5 may be blocked from the data line Di.

As shown in FIG. 8, since the storage capacitor Cst is connected between the gate electrode and the source electrode of the fifth NMOS transistor MN5, the fifth NMOS transistor MN5 has the magnitude of the voltage stored in the storage capacitor Cst. A drain current corresponding to is generated, and the light emitting diode LD may emit light with a brightness corresponding to the magnitude of the drain current.

When the scan signal S_S applied to the scan line Sj is activated again at a logic high level in the next frame period, and a new data signal D_S applied to the data line Di is transmitted to the third node N3 Until, the light emitting diode LD may emit light with a brightness corresponding to the magnitude of the voltage stored in the storage capacitor Cst during one frame period.

At this time, when the magnitude of the voltage stored in the storage capacitor Cst is not kept constant for one frame period and the magnitude of the voltage stored in the storage capacitor Cst changes due to the loss of charge stored in the storage capacitor Cst, the display Since the quality of the image displayed on the device 30 is deteriorated, the magnitude of the voltage stored in the storage capacitor Cst needs to be kept constant for one frame period.

On the other hand, even after the scan signal S_S applied to the scan line Sj is deactivated from the logic high level to the logic low level, the data line Di ) May be continuously applied with a data signal D_S to be provided to the pixel circuits 130a located in different rows.

At this time, even when the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, the data line is formed through the body electrode of the third NMOS transistor MN3 or the body electrode of the fourth NMOS transistor MN4. If a current path is formed between (Di) and the third node N3, the magnitude of the voltage stored in the storage capacitor Cst changes.

However, when the data signal D_S having a voltage lower than the voltage of the third node N3 is applied to the data line Di while the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off. , Since the body electrode of the fourth NMOS transistor MN4 is connected to the fourth node N4, the third node N3 has a higher potential than the body electrode of the fourth NMOS transistor MN4, and thus the third node ( A current path is not formed between N3) and the fourth node N4.

In addition, while the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, a data signal D_S having a voltage higher than the voltage of the third node N3 is applied to the data line Di. In this case, since the body electrode of the third NMOS transistor MN3 is connected to the fourth node N4, the data line Di has a higher potential than the body electrode of the third NMOS transistor MN3, and thus the data line Di A current path is not formed between) and the fourth node N4.

Therefore, when the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, the data line Di and the third node are irrespective of the voltage level of the data signal D_S applied to the data line Di. Since a current path is not formed between (N3), the magnitude of the voltage stored in the storage capacitor Cst may be kept constant for one frame.

As described above with reference to FIGS. 7 and 8, the pixel circuit 130a according to an exemplary embodiment of the present invention includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4 in which a body electrode is electrically connected to a source electrode. , And the fifth NMOS transistor MN5, since the magnitude of the voltage stored in the storage capacitor Cst is kept constant for one frame, the image quality can be maintained at a high level.

9 is a circuit diagram illustrating another example of a pixel circuit included in the display device of FIG. 7.

Each of the plurality of pixel circuits 130 included in the display device 30 of FIG. 7 may be implemented with the pixel circuit 130b of FIG. 9.

In FIG. 9, the pixel circuit 130b located in the j row and i column (i, j is a positive integer) will be described as an example.

The pixel circuit 130b receives the scan signal S_S from the scan driver 200 shown in FIG. 7 through the scan line Sj, and receives the data line Di from the data driver 400 shown in FIG. 7. Through the data signal D_S may be received.

Referring to FIG. 9, the pixel circuit 130b includes a light emitting diode LD, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a storage capacitor Cst. can do.

The third NMOS transistor MN3 and the fourth NMOS transistor MN4 may be connected in series between the data line Di and the third node N3. In addition, the gate electrode of the third NMOS transistor MN3 and the gate electrode of the fourth NMOS transistor MN4 may be commonly connected to the scan line Sj.

Specifically, the third NMOS transistor MN3 may include a source electrode connected to the data line Di, a gate electrode connected to the scan line Sj, and a drain electrode connected to the fourth node N4. .

Meanwhile, the body electrode of the third NMOS transistor MN3 may be electrically connected to the source electrode of the third NMOS transistor MN3. Accordingly, the body electrode of the third NMOS transistor MN3 may be connected to the data line Di.

The fourth NMOS transistor MN4 may include a source electrode connected to the third node N3, a gate electrode connected to the scan line Sj, and a drain electrode connected to the fourth node N4.

Meanwhile, the body electrode of the fourth NMOS transistor MN4 may be electrically connected to the source electrode of the fourth NMOS transistor MN4. Accordingly, the body electrode of the fourth NMOS transistor MN4 may be connected to the third node N3.

The fifth NMOS transistor MN5 includes a drain electrode connected to the cathode electrode of the light emitting diode LD, a gate electrode connected to the third node N3, and a source electrode connected to the ground voltage GND. can do.

Meanwhile, the body electrode of the fifth NMOS transistor MN5 may be electrically connected to the source electrode of the fifth NMOS transistor MN5. Accordingly, the body electrode of the fifth NMOS transistor MN5 may be connected to the ground voltage GND.

The light emitting diode LD may include an anode electrode connected to the power voltage VDD and a cathode electrode connected to the drain electrode of the fifth NMOS transistor MN5.

The storage capacitor Cst may be connected between the third node N3 and the ground voltage GND.

The third NMOS transistor MN3 and the fourth NMOS transistor MN4 may operate as a switch transistor of the pixel circuit 130b, and the fifth NMOS transistor MN5 may operate as a driving transistor of the pixel circuit 130a.

In an embodiment, the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 may be formed as a single chip.

In this case, the source electrode and the body electrode of the third NMOS transistor MN3 are electrically connected to each other inside the chip, and the source electrode and the body electrode of the fourth NMOS transistor MN4 are electrically connected to each other inside the chip. , The source electrode and the body electrode of the fifth NMOS transistor MN5 may be electrically connected to each other inside the chip.

In addition, the drain electrode, the gate electrode, and the source electrode of the third NMOS transistor MN3, the drain electrode, the gate electrode, and the source electrode of the fourth NMOS transistor MN4, and the drain electrode of the fifth NMOS transistor MN5, The gate electrode and the source electrode may be connected to external pins of the chip, respectively.

Hereinafter, a detailed operation of the pixel circuit 130b will be described with reference to FIGS. 7 and 9.

The scan driver 200 provides a scan signal S_S that is sequentially activated to a logic high level to a plurality of scan lines S1, S2, ..., Sn during one frame period, thereby providing a plurality of scan lines S1 and S2. , …, Sn) can be selected sequentially.

Meanwhile, the data driver 400 may provide a data signal D_S corresponding to image data to be displayed on the pixel circuit 130a to the data line Di.

The third NMOS transistor MN3 and the fourth NMOS transistor MN4 may be turned on while the scan signal S_S applied to the corresponding scan line Sj is activated to a logic high level.

When the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned on, the data signal D_S applied to the data line Di may be transmitted to the third node N3.

Since the storage capacitor Cst is connected between the third node N3 and the ground voltage GND, the voltage corresponding to the difference between the voltage corresponding to the data signal D_S and the ground voltage GND is the storage capacitor Cst. Can be stored in.

Thereafter, when the scan signal S_S applied to the scan line Sj is deactivated from the logic high level to the logic low level, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off to turn off the fifth NMOS transistor. The third node N3 corresponding to the gate electrode of the transistor MN5 may be blocked from the data line Di.

As shown in FIG. 9, since the storage capacitor Cst is connected between the gate electrode and the source electrode of the fifth NMOS transistor MN5, the fifth NMOS transistor MN5 has the magnitude of the voltage stored in the storage capacitor Cst. A drain current corresponding to is generated, and the light emitting diode LD may emit light with a brightness corresponding to the magnitude of the drain current.

When the scan signal S_S applied to the scan line Sj is activated again at a logic high level in the next frame period, and a new data signal D_S applied to the data line Di is transmitted to the third node N3 Until, the light emitting diode LD may emit light with a brightness corresponding to the magnitude of the voltage stored in the storage capacitor Cst during one frame period.

At this time, when the magnitude of the voltage stored in the storage capacitor Cst is not kept constant for one frame period and the magnitude of the voltage stored in the storage capacitor Cst changes due to the loss of charge stored in the storage capacitor Cst, the display Since the quality of the image displayed on the device 30 is deteriorated, the magnitude of the voltage stored in the storage capacitor Cst needs to be kept constant for one frame period.

On the other hand, even after the scan signal S_S applied to the scan line Sj is deactivated from the logic high level to the logic low level, the data line Di ) May be continuously applied with a data signal D_S to be provided to the pixel circuits 130a located in different rows.

At this time, even when the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, the data line is formed through the body electrode of the third NMOS transistor MN3 or the body electrode of the fourth NMOS transistor MN4. If a current path is formed between (Di) and the third node N3, the magnitude of the voltage stored in the storage capacitor Cst changes.

However, when the data signal D_S having a voltage lower than the voltage of the third node N3 is applied to the data line Di while the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off. , Since the body electrode of the third NMOS transistor MN3 is connected to the data line Di, the body electrode of the third NMOS transistor MN3 has a potential lower than the voltage of the fourth node N4, and thus the fourth node No current path is formed between (N4) and the data line (Di).

In addition, while the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, a data signal D_S having a voltage higher than the voltage of the third node N3 is applied to the data line Di. In this case, since the body electrode of the fourth NMOS transistor MN4 is connected to the third node N3, the fourth node N4 has a higher potential than the body electrode of the fourth NMOS transistor MN4, and thus the fourth node A current path is not formed between (N4) and the third node (N3).

Therefore, when the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, the data line Di and the third node are irrespective of the voltage level of the data signal D_S applied to the data line Di. Since a current path is not formed between (N3), the magnitude of the voltage stored in the storage capacitor Cst may be kept constant for one frame.

As described above with reference to FIGS. 7 and 9, the pixel circuit 130b according to an exemplary embodiment of the present invention includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4 in which a body electrode is electrically connected to a source electrode. , And the fifth NMOS transistor MN5, since the magnitude of the voltage stored in the storage capacitor Cst is kept constant for one frame, the image quality can be maintained at a high level.

10 is a block diagram illustrating a display device according to another exemplary embodiment of the present invention.

Referring to FIG. 10, the display device 40 includes a pixel portion 100d, a scan driver 200, and a data driver 400.

The scan driver 200 and the data driver 400 may be implemented as one integrated circuit (IC) chip.

The pixel portion 100d is connected to the scan driver 200 through a plurality of scan lines S1, S2, ..., Sn (n is a positive integer), and a plurality of data lines D1, D2, ..., Dm) (m is a positive integer) is connected to the data driver 400.

The pixel portion 100d includes n*m pixel circuits 140 positioned at each intersection of the plurality of scan lines S1, S2, ..., Sn and the plurality of data lines D1, D2, ..., Dm. Includes them.

Each of the plurality of pixel circuits 140 operates using a power voltage VDD and a ground voltage GND.

In an embodiment, each of the plurality of pixel circuits 140 may receive a power voltage VDD and a ground voltage GND provided from the outside.

In another embodiment, each of the plurality of pixel circuits 140 may receive a power voltage VDD and a ground voltage GND generated from a voltage generator included in the display device 40.

As will be described later with reference to FIGS. 11 and 12, each of the plurality of pixel circuits 140 includes a light emitting diode (LED). Further, each of the plurality of pixel circuits 130 is implemented using a P-type Metal Oxide Semiconductor (PMOS) transistor, and two PMOS transistors connected in series with each other operate as a switch transistor.

The scan driver 200 provides a scan signal to each of the plurality of pixel circuits 140 through a plurality of scan lines S1, S2, ..., Sn.

The data driver 400 provides a data signal to each of the plurality of pixel circuits 140 through the plurality of data lines D1, D2, ..., Dm.

Each of the plurality of pixel circuits 140 displays an image by emitting the light emitting diode at a brightness corresponding to the data signal using the scan signal and the data signal.

11 is a circuit diagram illustrating an example of a pixel circuit included in the display device of FIG. 10.

Each of the plurality of pixel circuits 140 included in the display device 40 of FIG. 10 may be implemented with the pixel circuit 140a shown in FIG. 11.

In FIG. 11, the pixel circuit 140a located in the j row and i column (i and j are positive integers) will be described as an example.

The pixel circuit 140a receives the scan signal S_S from the scan driver 200 shown in FIG. 10 through the scan line Sj, and receives the data line Di from the data driver 400 shown in FIG. 10. Through the data signal D_S may be received.

Referring to FIG. 11, the pixel circuit 140a includes a light emitting diode LD, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a storage capacitor Cst. can do.

The third PMOS transistor MP3 and the fourth PMOS transistor MP4 may be connected in series between the data line Di and the fifth node N5. Also, the gate electrode of the third PMOS transistor MP3 and the gate electrode of the fourth PMOS transistor MP4 may be commonly connected to the scan line Sj.

Specifically, the third PMOS transistor MP3 may include a drain electrode connected to the data line Di, a gate electrode connected to the scan line Sj, and a source electrode connected to the sixth node N6. .

Meanwhile, the body electrode of the third PMOS transistor MP3 may be electrically connected to the source electrode of the third PMOS transistor MP3. Accordingly, the body electrode of the third PMOS transistor MP3 may be connected to the sixth node N6.

The fourth PMOS transistor MP4 may include a drain electrode connected to the fifth node N5, a gate electrode connected to the scan line Sj, and a source electrode connected to the sixth node N6.

Meanwhile, the body electrode of the fourth PMOS transistor MP4 may be electrically connected to the source electrode of the fourth PMOS transistor MP4. Accordingly, the body electrode of the fourth PMOS transistor MP4 may be connected to the sixth node N6.

The fifth PMOS transistor MP5 may include a drain electrode connected to the anode electrode of the light emitting diode LD, a gate electrode connected to the fifth node N5, and a source electrode connected to the power voltage VDD. .

Meanwhile, the body electrode of the fifth PMOS transistor MP5 may be electrically connected to the source electrode of the fifth PMOS transistor MP5. Accordingly, the body electrode of the fifth PMOS transistor MP5 may be connected to the power voltage VDD.

The light emitting diode LD may include a cathode electrode connected to the ground voltage GND and an anode electrode connected to the drain electrode of the fifth PMOS transistor MP5.

The storage capacitor Cst may be connected between the fifth node N5 and the power voltage VDD.

The third PMOS transistor MP3 and the fourth PMOS transistor MP4 may operate as a switch transistor of the pixel circuit 140a, and the fifth PMOS transistor MP5 may operate as a driving transistor of the pixel circuit 140a.

In an embodiment, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 may be formed as a single chip.

In this case, the source electrode and the body electrode of the third PMOS transistor MP3 are electrically connected to each other inside the chip, and the source electrode and the body electrode of the fourth PMOS transistor MP4 are electrically connected to each other inside the chip. , The source electrode and the body electrode of the fifth PMOS transistor MP5 may be electrically connected to each other in the chip.

Further, a drain electrode, a gate electrode, and a source electrode of the third PMOS transistor MP3, a drain electrode, a gate electrode, and a source electrode of the fourth PMOS transistor MP4, and a drain electrode of the fifth PMOS transistor MP5, The gate electrode and the source electrode may be connected to external pins of the chip, respectively.

Hereinafter, specific operations of the pixel circuit 140a will be described in detail with reference to FIGS. 10 and 11.

The scan driver 200 provides a scan signal S_S that is sequentially activated at a logic low level to a plurality of scan lines S1, S2, ..., Sn during one frame period, thereby providing a plurality of scan lines S1 and S2. , …, Sn) can be selected sequentially.

Meanwhile, the data driver 400 may provide a data signal D_S corresponding to image data to be displayed on the pixel circuit 140a to the data line Di.

The third PMOS transistor MP3 and the fourth PMOS transistor MP4 may be turned on while the scan signal S_S applied to the corresponding scan line Sj is activated to a logic low level.

When the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned on, the data signal D_S applied to the data line Di may be transmitted to the fifth node N5.

Since the storage capacitor Cst is connected between the fifth node N5 and the power voltage VDD, the voltage corresponding to the difference between the voltage corresponding to the data signal D_S and the power voltage VDD is the storage capacitor Cst. Can be stored in.

Thereafter, when the scan signal S_S applied to the scan line Sj is deactivated from the logic low level to the logic high level, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off and thus the fifth PMOS transistor MP4 is turned off. The fifth node N5 corresponding to the gate electrode of the transistor MP5 may be blocked from the data line Di.

As shown in FIG. 11, since the storage capacitor Cst is connected between the gate electrode and the source electrode of the fifth PMOS transistor MP5, the fifth PMOS transistor MP5 has the magnitude of the voltage stored in the storage capacitor Cst. A drain current corresponding to is generated, and the light emitting diode LD may emit light with a brightness corresponding to the magnitude of the drain current.

When the scan signal S_S applied to the scan line Sj is activated again at a logic low level in the next frame period, and a new data signal D_S applied to the data line Di is transmitted to the fifth node N5 Until, the light emitting diode LD may emit light with a brightness corresponding to the magnitude of the voltage stored in the storage capacitor Cst during one frame period.

At this time, when the magnitude of the voltage stored in the storage capacitor Cst is not kept constant for one frame period and the magnitude of the voltage stored in the storage capacitor Cst changes due to the loss of charge stored in the storage capacitor Cst, the display Since the quality of the image displayed on the device 40 is deteriorated, the magnitude of the voltage stored in the storage capacitor Cst needs to be kept constant for one frame period.

On the other hand, even after the scan signal S_S applied to the scan line Sj is deactivated from a logic low level to a logic high level and the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, ) May be continuously applied with a data signal D_S to be provided to the pixel circuits 140a located in different rows.

At this time, even when the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, the data line is connected through the body electrode of the third PMOS transistor MP3 or the body electrode of the fourth PMOS transistor MP4. If a current path is formed between (Di) and the fifth node N5, the magnitude of the voltage stored in the storage capacitor Cst changes.

However, when the data signal D_S having a voltage lower than the voltage of the fifth node N5 is applied to the data line Di while the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off. , Since the body electrode of the fourth PMOS transistor MP4 is connected to the sixth node N6, the fifth node N5 has a higher potential than the body electrode of the fourth PMOS transistor MP4, and thus the fifth node ( A current path is not formed between N5 and the sixth node N6.

In addition, when the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, a data signal D_S having a voltage higher than the voltage of the fifth node N5 is applied to the data line Di. In this case, since the body electrode of the third PMOS transistor MP3 is connected to the sixth node N6, the data line Di has a higher potential than the body electrode of the third PMOS transistor MP3 and thus the data line Di A current path is not formed between) and the sixth node N6.

Therefore, when the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, the data line Di and the fifth node are irrespective of the voltage level of the data signal D_S applied to the data line Di. Since a current path is not formed between (N5), the magnitude of the voltage stored in the storage capacitor Cst may be kept constant for one frame.

As described above with reference to FIGS. 10 and 11, the pixel circuit 140a according to an embodiment of the present invention includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4 having a body electrode electrically connected to the source electrode. , And the fifth PMOS transistor MP5, since the magnitude of the voltage stored in the storage capacitor Cst is kept constant for one frame, the image quality can be maintained at a high level.

12 is a circuit diagram illustrating another example of a pixel circuit included in the display device of FIG. 10.

Each of the plurality of pixel circuits 140 included in the display device 40 of FIG. 10 may be implemented with the pixel circuit 140b of FIG. 12.

In FIG. 12, the pixel circuit 140a located in the j row and i column (i, j is a positive integer) will be described as an example.

The pixel circuit 140b receives the scan signal S_S from the scan driver 200 shown in FIG. 10 through the scan line Sj, and receives the data line Di from the data driver 400 shown in FIG. 10. Through the data signal D_S may be received.

Referring to FIG. 12, the pixel circuit 140b includes a light emitting diode LD, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a storage capacitor Cst. can do.

The third PMOS transistor MP3 and the fourth PMOS transistor MP4 may be connected in series between the data line Di and the fifth node N5. Also, the gate electrode of the third PMOS transistor MP3 and the gate electrode of the fourth PMOS transistor MP4 may be commonly connected to the scan line Sj.

Specifically, the third PMOS transistor MP3 may include a source electrode connected to the data line Di, a gate electrode connected to the scan line Sj, and a drain electrode connected to the sixth node N6. .

Meanwhile, the body electrode of the third PMOS transistor MP3 may be electrically connected to the source electrode of the third PMOS transistor MP3. Accordingly, the body electrode of the third PMOS transistor MP3 may be connected to the data line Di.

The fourth PMOS transistor MP4 may include a source electrode connected to the fifth node N5, a gate electrode connected to the scan line Sj, and a drain electrode connected to the sixth node N6.

Meanwhile, the body electrode of the fourth PMOS transistor MP4 may be electrically connected to the source electrode of the fourth PMOS transistor MP4. Accordingly, the body electrode of the fourth PMOS transistor MP4 may be connected to the fifth node N5.

The fifth PMOS transistor MP5 may include a drain electrode connected to the anode electrode of the light emitting diode LD, a gate electrode connected to the fifth node N5, and a source electrode connected to the power voltage VDD. have.

Meanwhile, the body electrode of the fifth PMOS transistor MP5 may be electrically connected to the source electrode of the fifth PMOS transistor MP5. Accordingly, the body electrode of the fifth PMOS transistor MP5 may be connected to the power voltage VDD.

The light emitting diode LD may include a cathode electrode connected to the ground voltage GND and an anode electrode connected to the drain electrode of the fifth PMOS transistor MP5.

The storage capacitor Cst may be connected between the fifth node N5 and the power voltage VDD.

The third PMOS transistor MP3 and the fourth PMOS transistor MP4 may operate as a switch transistor of the pixel circuit 140b, and the fifth PMOS transistor MP5 may operate as a driving transistor of the pixel circuit 140b.

In an embodiment, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 may be formed as a single chip.

In this case, the source electrode and the body electrode of the third PMOS transistor MP3 are electrically connected to each other inside the chip, and the source electrode and the body electrode of the fourth PMOS transistor MP4 are electrically connected to each other inside the chip. , The source electrode and the body electrode of the fifth PMOS transistor MP5 may be electrically connected to each other in the chip.

Further, a drain electrode, a gate electrode, and a source electrode of the third PMOS transistor MP3, a drain electrode, a gate electrode, and a source electrode of the fourth PMOS transistor MP4, and a drain electrode of the fifth PMOS transistor MP5, The gate electrode and the source electrode may be connected to external pins of the chip, respectively.

Hereinafter, a detailed operation of the pixel circuit 140b will be described with reference to FIGS. 10 and 12.

The scan driver 200 provides a scan signal S_S that is sequentially activated at a logic low level to a plurality of scan lines S1, S2, ..., Sn during one frame period, thereby providing a plurality of scan lines S1 and S2. , …, Sn) can be selected sequentially.

Meanwhile, the data driver 400 may provide a data signal D_S corresponding to image data to be displayed on the pixel circuit 140a to the data line Di.

The third PMOS transistor MP3 and the fourth PMOS transistor MP4 may be turned on while the scan signal S_S applied to the corresponding scan line Sj is activated to a logic low level.

When the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned on, the data signal D_S applied to the data line Di may be transmitted to the fifth node N5.

Since the storage capacitor Cst is connected between the fifth node N5 and the power voltage VDD, the voltage corresponding to the difference between the voltage corresponding to the data signal D_S and the power voltage VDD is the storage capacitor Cst. Can be stored in.

Thereafter, when the scan signal S_S applied to the scan line Sj is deactivated from the logic low level to the logic high level, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off and thus the fifth PMOS transistor MP4 is turned off. The fifth node N5 corresponding to the gate electrode of the transistor MP5 may be blocked from the data line Di.

As shown in FIG. 12, since the storage capacitor Cst is connected between the gate electrode and the source electrode of the fifth PMOS transistor MP5, the fifth PMOS transistor MP5 has the magnitude of the voltage stored in the storage capacitor Cst. A drain current corresponding to is generated, and the light emitting diode LD may emit light with a brightness corresponding to the magnitude of the drain current.

When the scan signal S_S applied to the scan line Sj is activated again at a logic low level in the next frame period, and a new data signal D_S applied to the data line Di is transmitted to the fifth node N5 Until, the light emitting diode LD may emit light with a brightness corresponding to the magnitude of the voltage stored in the storage capacitor Cst during one frame period.

At this time, when the magnitude of the voltage stored in the storage capacitor Cst is not kept constant for one frame period and the magnitude of the voltage stored in the storage capacitor Cst changes due to the loss of charge stored in the storage capacitor Cst, the display Since the quality of the image displayed on the device 40 is deteriorated, the magnitude of the voltage stored in the storage capacitor Cst needs to be kept constant for one frame period.

On the other hand, even after the scan signal S_S applied to the scan line Sj is deactivated from a logic low level to a logic high level and the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, ) May be continuously applied with a data signal D_S to be provided to the pixel circuits 140b located in other rows.

At this time, even when the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, the data line is connected through the body electrode of the third PMOS transistor MP3 or the body electrode of the fourth PMOS transistor MP4. If a current path is formed between (Di) and the fifth node N5, the magnitude of the voltage stored in the storage capacitor Cst changes.

However, when the data signal D_S having a voltage lower than the voltage of the fifth node N5 is applied to the data line Di while the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off. , Since the body electrode of the third PMOS transistor MP3 is connected to the data line Di, the body electrode of the third PMOS transistor MP3 has a potential lower than the voltage of the sixth node N6 and thus the sixth node No current path is formed between (N6) and the data line (Di).

In addition, when the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, a data signal D_S having a voltage higher than the voltage of the fifth node N5 is applied to the data line Di. In this case, since the body electrode of the fourth PMOS transistor MP4 is connected to the fifth node N5, the sixth node N6 has a higher potential than the body electrode of the fourth PMOS transistor MP4, and thus the sixth node A current path is not formed between (N6) and the fifth node (N5).

Therefore, when the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, the data line Di and the fifth node are irrespective of the voltage level of the data signal D_S applied to the data line Di. Since a current path is not formed between (N5), the magnitude of the voltage stored in the storage capacitor Cst may be kept constant for one frame.

As described above with reference to FIGS. 10 and 12, the pixel circuit 140b according to an embodiment of the present invention includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4 having a body electrode electrically connected to the source electrode. , And the fifth PMOS transistor MP5, since the magnitude of the voltage stored in the storage capacitor Cst is kept constant for one frame, the image quality can be maintained at a high level.

The present invention can be usefully used to create a display device capable of providing a high-quality image by maintaining a constant magnitude of a data voltage stored in a capacitor of a pixel circuit for one frame.

As described above, the present invention has been described with reference to preferred embodiments of the present invention, but those of ordinary skill in the relevant technical field may vary the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims You will understand that it can be modified and changed.

10, 20, 30, 40: display device 100: pixel portion
110, 120, 130, 140: pixel circuit 200: scan driver
300: boosting driving unit 400: data driving unit

Claims (8)

A light emitting diode including an anode electrode connected to a power supply voltage;
A first NMOS transistor and a second NMOS transistor connected in series between the data line and the first node;
A third NMOS transistor including a drain electrode connected to the cathode electrode of the light emitting diode, a gate electrode connected to the first node, a source electrode connected to a ground voltage, and a body electrode connected to the ground voltage; And
A storage capacitor connected between the first node and the ground voltage,
The gate electrode of the first NMOS transistor and the gate electrode of the second NMOS transistor are commonly connected to a scan line,
The source electrode and the body electrode of the first NMOS transistor are electrically connected to each other,
The source electrode and the body electrode of the second NMOS transistor are electrically connected to each other,
A drain electrode of the first NMOS transistor is connected to the data line, the source electrode and the body electrode of the first NMOS transistor are connected to a second node,
A pixel circuit in which a drain electrode of the second NMOS transistor is connected to the first node, and the source electrode and the body electrode of the second NMOS transistor are connected to the second node. A light emitting diode including an anode electrode connected to a power supply voltage;
A first NMOS transistor and a second NMOS transistor connected in series between the data line and the first node;
A third NMOS transistor including a drain electrode connected to the cathode electrode of the light emitting diode, a gate electrode connected to the first node, a source electrode connected to a ground voltage, and a body electrode connected to the ground voltage; And
A storage capacitor connected between the first node and the ground voltage,
The gate electrode of the first NMOS transistor and the gate electrode of the second NMOS transistor are commonly connected to a scan line,
The source electrode and the body electrode of the first NMOS transistor are electrically connected to each other,
The source electrode and the body electrode of the second NMOS transistor are electrically connected to each other,
The source electrode and the body electrode of the first NMOS transistor are connected to the data line, the drain electrode of the first NMOS transistor is connected to a second node,
The source electrode and the body electrode of the second NMOS transistor are connected to the first node, and the drain electrode of the second NMOS transistor is connected to the second node. A pixel unit including a plurality of pixel circuits positioned at each intersection of a plurality of scan lines and a plurality of data lines;
A scan driver providing scan signals to the plurality of scan lines; And
And a data driver providing data signals to the plurality of data lines,
Each of the plurality of furnace circuits,
A light emitting diode including an anode electrode connected to a power supply voltage;
A first NMOS transistor and a second NMOS transistor connected in series between a corresponding data line and a first node;
A third NMOS transistor including a drain electrode connected to the cathode electrode of the light emitting diode, a gate electrode connected to the first node, a source electrode connected to a ground voltage, and a body electrode connected to the ground voltage; And
A storage capacitor connected between the first node and the ground voltage,
The gate electrode of the first NMOS transistor and the gate electrode of the second NMOS transistor are commonly connected to a corresponding scan line,
The source electrode and the body electrode of the first NMOS transistor are electrically connected to each other,
The source electrode and the body electrode of the second NMOS transistor are electrically connected to each other,
A drain electrode of the first NMOS transistor is connected to the corresponding data line, the source electrode and the body electrode of the first NMOS transistor are connected to a second node,
A display device wherein a drain electrode of the second NMOS transistor is connected to the first node, and the source electrode and the body electrode of the second NMOS transistor are connected to the second node. A pixel unit including a plurality of pixel circuits positioned at each intersection of a plurality of scan lines and a plurality of data lines;
A scan driver providing scan signals to the plurality of scan lines; And
And a data driver providing data signals to the plurality of data lines,
Each of the plurality of furnace circuits,
A light emitting diode including an anode electrode connected to a power supply voltage;
A first NMOS transistor and a second NMOS transistor connected in series between a corresponding data line and a first node;
A third NMOS transistor including a drain electrode connected to the cathode electrode of the light emitting diode, a gate electrode connected to the first node, a source electrode connected to a ground voltage, and a body electrode connected to the ground voltage; And
A storage capacitor connected between the first node and the ground voltage,
The gate electrode of the first NMOS transistor and the gate electrode of the second NMOS transistor are commonly connected to a corresponding scan line,
The source electrode and the body electrode of the first NMOS transistor are electrically connected to each other,
The source electrode and the body electrode of the second NMOS transistor are electrically connected to each other,
The source electrode and the body electrode of the first NMOS transistor are connected to the corresponding data line, the drain electrode of the first NMOS transistor is connected to a second node,
The source electrode and the body electrode of the second NMOS transistor are connected to the first node, and the drain electrode of the second NMOS transistor is connected to the second node. A light-emitting diode including a cathode electrode connected to a ground voltage;
A first PMOS transistor and a second PMOS transistor connected in series between the data line and the first node;
A third PMOS transistor including a drain electrode connected to the anode electrode of the light emitting diode, a gate electrode connected to the first node, a source electrode connected to a power voltage, and a body electrode connected to the power voltage; And
A storage capacitor connected between the first node and the power voltage,
The gate electrode of the first PMOS transistor and the gate electrode of the second PMOS transistor are commonly connected to a scan line,
The source electrode and the body electrode of the first PMOS transistor are electrically connected to each other,
The source electrode and the body electrode of the second PMOS transistor are electrically connected to each other,
A drain electrode of the first PMOS transistor is connected to the data line, the source electrode and the body electrode of the first PMOS transistor are connected to a second node,
A pixel circuit in which a drain electrode of the second PMOS transistor is connected to the first node, and the source electrode and the body electrode of the second PMOS transistor are connected to the second node. A light-emitting diode including a cathode electrode connected to a ground voltage;
A first PMOS transistor and a second PMOS transistor connected in series between the data line and the first node;
A third PMOS transistor including a drain electrode connected to the anode electrode of the light emitting diode, a gate electrode connected to the first node, a source electrode connected to a power voltage, and a body electrode connected to the power voltage; And
A storage capacitor connected between the first node and the power voltage,
The gate electrode of the first PMOS transistor and the gate electrode of the second PMOS transistor are commonly connected to a scan line,
The source electrode and the body electrode of the first PMOS transistor are electrically connected to each other,
The source electrode and the body electrode of the second PMOS transistor are electrically connected to each other,
The source electrode and the body electrode of the first PMOS transistor are connected to the data line, the drain electrode of the first PMOS transistor is connected to a second node,
The source electrode and the body electrode of the second PMOS transistor are connected to the first node, and the drain electrode of the second PMOS transistor is connected to the second node. A pixel unit including a plurality of pixel circuits positioned at each intersection of a plurality of scan lines and a plurality of data lines;
A scan driver providing scan signals to the plurality of scan lines; And
And a data driver providing data signals to the plurality of data lines,
Each of the plurality of furnace circuits,
A light-emitting diode including a cathode electrode connected to a ground voltage;
A first PMOS transistor and a second PMOS transistor connected in series between a corresponding data line and a first node;
A third PMOS transistor including a drain electrode connected to the anode electrode of the light emitting diode, a gate electrode connected to the first node, a source electrode connected to a power voltage, and a body electrode connected to the power voltage; And
A storage capacitor connected between the first node and the power voltage,
The gate electrode of the first PMOS transistor and the gate electrode of the second PMOS transistor are commonly connected to a corresponding scan line,
The source electrode and the body electrode of the first PMOS transistor are electrically connected to each other,
The source electrode and the body electrode of the second PMOS transistor are electrically connected to each other,
A drain electrode of the first PMOS transistor is connected to the corresponding data line, the source electrode and the body electrode of the first PMOS transistor are connected to a second node,
A display device wherein a drain electrode of the second PMOS transistor is connected to the first node, and the source electrode and the body electrode of the second PMOS transistor are connected to the second node. A pixel unit including a plurality of pixel circuits positioned at each intersection of a plurality of scan lines and a plurality of data lines;
A scan driver providing scan signals to the plurality of scan lines; And
And a data driver providing data signals to the plurality of data lines,
Each of the plurality of furnace circuits,
A light-emitting diode including a cathode electrode connected to a ground voltage;
A first PMOS transistor and a second PMOS transistor connected in series between a corresponding data line and a first node;
A third PMOS transistor including a drain electrode connected to the anode electrode of the light emitting diode, a gate electrode connected to the first node, a source electrode connected to a power voltage, and a body electrode connected to the power voltage; And
A storage capacitor connected between the first node and the power voltage,
The gate electrode of the first PMOS transistor and the gate electrode of the second PMOS transistor are commonly connected to a corresponding scan line,
The source electrode and the body electrode of the first PMOS transistor are electrically connected to each other,
The source electrode and the body electrode of the second PMOS transistor are electrically connected to each other,
The source electrode and the body electrode of the first PMOS transistor are connected to the corresponding data line, the drain electrode of the first PMOS transistor is connected to a second node,
The source electrode and the body electrode of the second PMOS transistor are connected to the first node, and the drain electrode of the second PMOS transistor is connected to the second node.

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