KR20200142153A - Semiconductor device - Google Patents

Abstract

Disclosed is a semiconductor device which is easy to be manufactured comprises: an active region protruding upward from a substrate; a plurality of channel patterns spaced apart from each other in a first direction on the active region; and a gate electrode extending in the first direction on the active region and covering the plurality of channel patterns. Each of the plurality of channel patterns includes a plurality of semiconductor patterns spaced apart from each other in a direction perpendicular to an upper surface of the active region. The gate electrode covers the upper surface of the active region between the plurality of channel patterns.

Description

Semiconductor device {Semiconductor device}

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor.

The semiconductor device includes an integrated circuit composed of MOS field effect transistors (Metal Oxide Semiconductor (MOS) FETs). As the size and design rules of semiconductor devices are gradually reduced, the scale down of MOS field effect transistors is also accelerating. As the size of the MOS field effect transistors are reduced, the operating characteristics of the semiconductor device may be deteriorated. Accordingly, various methods for forming a semiconductor device with superior performance while overcoming the limitation due to the high integration of the semiconductor device are being studied.

An object of the present invention is to provide a semiconductor device that is easy to manufacture.

Another technical problem to be achieved by the present invention is to provide a semiconductor device with increased degree of freedom in designing an integrated circuit.

The semiconductor device according to the present invention includes an active region protruding upward from a substrate, a plurality of channel patterns spaced apart from each other in a first direction on the active region, and the plurality of channel patterns extending in the first direction on the active region. It may include a gate electrode covering them. Each of the plurality of channel patterns may include a plurality of semiconductor patterns spaced apart from each other in a direction perpendicular to an upper surface of the active region. The gate electrode may cover the upper surface of the active region between the plurality of channel patterns.

According to the concept of the present invention, a plurality of channel patterns may be arranged to be spaced apart from each other in a first direction on a single active area, and a gate electrode extends in the first direction on the single active area to cover the plurality of channel patterns I can. A plurality of source/drain patterns may be disposed on both sides of the channel patterns on the single active region. Each of the plurality of channel patterns may include semiconductor patterns spaced apart from each other in a direction perpendicular to an upper surface of the active region. Since the channel patterns are disposed to be spaced apart from each other in the first direction on the single active region, it may be easy to form the channel patterns including the semiconductor patterns. In addition, widths of the channel patterns and widths of the source/drain patterns may be variously adjusted, and accordingly, the channel patterns, the source/drain patterns, and the transistor including the gate electrode have various characteristics. It can be implemented to have.

Therefore, it is easy to manufacture a semiconductor device, and the degree of freedom in designing a semiconductor integrated circuit including the transistor can be increased.

1 is a plan view of a semiconductor device according to some embodiments of the present invention.
2A, 2B, and 2C are cross-sectional views taken along lines A-A', B-B', and CC' of FIG. 1, respectively.
3A to 9A, 3B to 9B, and 3C to 9C are diagrams illustrating a method of manufacturing a semiconductor device according to some embodiments of the present invention, respectively, A-A' and B- of FIG. These are cross-sectional views corresponding to B'and C-C'.
10 is a plan view of a semiconductor device according to some embodiments of the present invention.
11A, 11B, and 11C are cross-sectional views taken along lines A-A', B-B', and CC' of FIG. 10, respectively.
12 is a plan view of a semiconductor device according to some embodiments of the present invention.
13A, 13B, and 13C are cross-sectional views taken along lines A-A', B-B', and CC' of FIG. 12, respectively.
14 is a plan view of a semiconductor device according to some embodiments of the present invention.
15 is a cross-sectional view taken along line AA′ of FIG. 14.
16 is a plan view of a semiconductor device according to some embodiments of the present invention.
17 is a cross-sectional view taken along line AA′ of FIG. 16.
18 is a plan view of a semiconductor device according to some embodiments of the present invention.
19A, 19B, and 19C are cross-sectional views taken along lines A-A', BB', and CC' of FIG. 18, respectively.

Hereinafter, the present invention will be described in detail by describing exemplary embodiments of the present invention with reference to the accompanying drawings.

1 is a plan view of a semiconductor device according to some embodiments of the present invention. 2A, 2B, and 2C are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 1, respectively.

1, 2A, 2B, and 2C, an active region 102 may be disposed on a substrate 100. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate or a silicon on insulator (SOI) substrate. The active region 102 may protrude upward from the substrate 100. The active region 102 may extend in a first direction D1 and a second direction D2 parallel to the bottom surface 100B of the substrate 100, and the bottom surface of the substrate 100 It may protrude from the substrate 100 along a third direction D3 perpendicular to 100B. The first direction D1 and the second direction D2 may cross each other.

Device isolation patterns ST may be disposed on the substrate 100 to define the active region 102. The device isolation patterns ST may be disposed on the substrate 100 on both sides of the active region 102. For example, the device isolation patterns ST may be spaced apart from each other in the first direction D1 with the active region 102 interposed therebetween, and may extend in the second direction D2. The active region 102 may be a single active region 102 interposed between the device isolation patterns ST. The device isolation patterns ST may include oxide, nitride, and/or oxynitride. According to some embodiments, the device isolation patterns ST may expose upper side surfaces of the active region 102. That is, the upper surfaces ST_U of the device isolation patterns ST may be at a level lower than the upper surface 102U of the active region 102. In this specification, “level” refers to a height measured from the bottom surface 100B of the substrate 100.

A plurality of channel patterns AP may be disposed on the active region 102. The channel patterns AP may be spaced apart from each other in the first direction D1 on the upper surface 102U of the active region 102. Each of the channel patterns AP is a plurality of semiconductor patterns 104 stacked along a direction perpendicular to the upper surface 102U of the active region 102 (for example, the third direction D3) It may include. The semiconductor patterns 104 may be spaced apart from each other along the direction perpendicular to the upper surface 102U of the active region 102 (for example, the third direction D3). The lowermost semiconductor pattern 104 of the semiconductor patterns 104 is the active region along the direction perpendicular to the upper surface 102U of the active region 102 (for example, the third direction D3). It may be spaced apart from the upper surface (102U) of (102). The number of the semiconductor patterns 104 is illustrated as three, but the concept of the present invention is not limited thereto. The semiconductor patterns 104 may include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

Each of the active region 102 and the channel patterns AP may have a width along the first direction D1. Each width W1, W2, or W3 of the channel patterns AP may be the width of each of the semiconductor patterns 104 of the channel patterns AP. The width 102W of the active region 102 may be greater than the sum of the widths W1, W2, and W3 of the channel patterns AP (ie, 102W>(W1+W2+W3)). The width 102W of the active region 102 is less than the sum of the widths W1, W2, W3 of the channel patterns AP and the distances d1, d2 between the channel patterns AP It can be greater than or equal to (ie, 102W≥(W1+W2+W3+d1+d2)). Each of the distances d1 and d2 between the channel patterns AP is the first direction D1 between a pair of adjacent channel patterns AP among the channel patterns AP It may be a distance according to. The width 102W of the active region 102 may be the width of the uppermost portion of the active region 102. According to some embodiments, a width W1 of at least one channel pattern AP among the channel patterns AP is a width W2 or W3 of another channel pattern AP among the channel patterns AP Can be different from According to some embodiments, the widths W1, W2, W3 of the channel patterns AP may be different from each other, and according to other embodiments, the widths W1 and W3 of the channel patterns AP W2, W3) may be identical to each other.

According to some embodiments, the distance d1 between at least one pair of channel patterns AP among the channel patterns AP is determined by the other pair of channel patterns ( It may be different from the distance d2 between APs). According to other embodiments, the distances d1 and d2 between the channel patterns AP may be the same.

For example, the channel patterns AP include a first sub-channel pattern APa, a second sub-channel pattern APb, and a third spaced apart from each other in the first direction D1 on the active region 102. It may include a sub channel pattern APc. According to some embodiments, the width W1 of the first sub-channel pattern APa, the width W2 of the second sub-channel pattern APb, and the width W3 of the third sub-channel pattern APc ) Can be different. The distance d1 between the first sub channel pattern APa and the second sub channel pattern APb is a distance d2 between the second sub channel pattern APb and the third sub channel pattern APc ) May be different. A plurality of source/drain patterns SD may be disposed on the active region 102, and on the upper surface 102U of the active region 102, the first direction D1 and the second direction ( It can be arranged along D2). The source/drain patterns SD may include source patterns SDa and drain patterns SDb. The source patterns SDa may be arranged along the first direction D1 and may be respectively connected to one side surface of the channel patterns AP. The drain patterns SDb may be spaced apart from the source patterns SDa in the second direction D2. The drain patterns SDb may be arranged along the first direction D1 and may be connected to the other side surfaces of the channel patterns AP, respectively.

Each of the source/drain patterns SD may have a width along the first direction D1. The width 102W of the active region 102 may be greater than the sum of the widths W1a, W2a, and W3a of the source patterns SDa (that is, 102W>(W1a+W2a+W3a)). According to some embodiments, a width W1a of at least one source pattern SDa among the source patterns SDa is a width W2a or W3a of another source pattern SDa among the source patterns SDa Can be different from According to some embodiments, the widths W1a, W2a, and W3a of the source patterns SDa may be different from each other, and according to other embodiments, the widths W1a of the source patterns SDa, W2a and W3a) may be identical to each other. Each of the drain patterns SDb may have substantially the same width as a corresponding source pattern SDa among the source patterns SDa.

Each of the channel patterns AP may be interposed between a corresponding source pattern SDa among the source patterns SDa and a corresponding drain pattern SDb among the drain patterns SDb, and the It may be connected to the corresponding source pattern SDa and the corresponding drain pattern SDb. Each of the semiconductor patterns 104 of the channel patterns AP may be interposed between the corresponding source pattern SDa and the corresponding drain pattern SDb, and the corresponding source pattern SDa And contact with the corresponding drain pattern SDb. Each of the semiconductor patterns 104 of the channel patterns AP may connect the corresponding source pattern SDa and the corresponding drain pattern SDb to each other. Each of the channel patterns AP, the corresponding source pattern SDa, and the corresponding drain pattern SDb may constitute an active structure AS. Accordingly, a plurality of active structures AS may be disposed to be spaced apart from each other in the first direction D1 on the upper surface 102U of the active region 102.

The source/drain patterns SD may be epitaxial patterns formed using the semiconductor patterns 104 and the active regions 102 of the channel patterns AP, respectively. The source/drain patterns SD may include at least one of silicon germanium (SiGe), silicon (Si), and silicon carbide (SiC). According to some embodiments, the source/drain patterns SD may be configured to provide a stretchable strain to the channel patterns AP. For example, when the semiconductor patterns 104 include silicon (Si), the source/drain patterns SD may include silicon (Si) and/or silicon carbide (SiC). According to other embodiments, the source/drain patterns SD may be configured to provide compressible strain to the channel patterns AP. For example, when the semiconductor patterns 104 include silicon (Si), the source/drain patterns SD may include silicon germanium (SiGe). The source/drain patterns SD may further include impurities. The impurities may be employed to improve electrical characteristics of transistors including the source/drain patterns SD. When the transistors are NMOSFETs, the impurity may be phosphorus (P), for example. When the transistors are PMOSFETs, the impurity may be boron (B), for example.

A gate structure GS may be disposed on the active region 102 and extends in the first direction D1 to cross the plurality of active structures AS and the device isolation patterns ST. I can. In a plan view, the channel patterns AP may overlap the gate structure GS, and the source/drain patterns SD may be disposed on both sides of the gate structure GS.

The gate structure GS extends in the first direction D1 to cover the plurality of channel patterns AP, each of the gate electrode GE and the channel patterns AP A gate insulating pattern GI therebetween, gate spacers GSP on side surfaces of the gate electrode GE, and a gate capping pattern CAP on an upper surface of the gate electrode GE may be included. The gate insulating pattern GI may extend between the gate electrode GE and the gate spacers GSP, and the uppermost surface of the gate insulating pattern GI is substantially the upper surface of the gate electrode GE. You can achieve coexistence. The gate electrode GE may cover an uppermost surface of each of the channel patterns AP, and may cover side surfaces of the channel patterns AP that face each other in the first direction D1. The gate electrode GE may cover the upper surface 102U of the active region 102 between the channel patterns AP, and extend in the first direction D1 to the device isolation patterns ST. The upper surfaces ST_U of may be covered. The gate electrode GE may fill spaces between each of the channel patterns AP and the active region 102 and between the semiconductor patterns 104. The gate insulating pattern GI may be interposed between each of the semiconductor patterns 104 and the gate electrode GE. Each of the semiconductor patterns 104 may be spaced apart from the gate electrode GE with the gate insulating pattern GI interposed therebetween. The gate insulating pattern GI may extend along the bottom surface of the gate electrode GE, and between the gate electrode GE and the active region 102, and between the gate electrode GE and the device isolation pattern. It may be interposed between each of the fields (ST). Each of the active structures AS and the gate electrode GE may constitute a gate-all-around type field effect transistor.

The gate electrode GE may include a doped semiconductor, a conductive metal nitride, and/or a metal. The gate insulating pattern GI may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a high dielectric film. The high dielectric film may include a material having a higher dielectric constant than a silicon oxide film, such as a hafnium oxide film (HfO), an aluminum oxide film (AlO), or a tantalum oxide film (TaO). Each of the gate spacers GSP and the gate capping pattern CAP may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

Spacer patterns 110 may be disposed between each of the source/drain patterns SD and the gate electrode GE. The spacer patterns 110 may be spaced apart from each other along the third direction D3. The spacer patterns 110 and the semiconductor patterns 104 may be alternately and repeatedly stacked along the third direction D3. Each of the spacer patterns 110 may be disposed between the semiconductor patterns 104 adjacent to each other, or between the semiconductor pattern 104 of the lowermost layer and the active region 102. A pair of spacer patterns 110 among the spacer patterns 110 may be disposed between a pair of semiconductor patterns 104 adjacent to each other among the semiconductor patterns 104. The pair of spacer patterns 110 may be spaced apart from each other in the second direction D2 with the gate electrode GE interposed therebetween. The pair of spacer patterns 110 may be disposed between a corresponding pair of source/drain patterns SD among the source/drain patterns SD.

Each of the source/drain patterns SD may contact the semiconductor patterns 104 and may be spaced apart from the gate electrode GE with the spacer patterns 110 interposed therebetween. The gate insulating pattern GI may be interposed between each of the gate electrode GE and the semiconductor patterns 104, and may extend between the gate electrode GE and each of the spacer patterns 110. I can. Each of the spacer patterns 110 may contact the gate insulating pattern GI. The spacer patterns 110 may include silicon nitride. For example, the spacer patterns 110 may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN.

A lower interlayer insulating layer 120 may be disposed on the substrate 100 to cover the gate structure GS and the source/drain patterns SD. The lower interlayer insulating layer 120 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a low dielectric layer. The upper surface of the gate capping pattern CAP may be substantially coplanar with the upper surface of the lower interlayer insulating layer 120. The gate spacer GSP may be interposed between the gate capping pattern CAP and the lower interlayer insulating layer 120.

An upper interlayer insulating layer 130 may be disposed on the lower interlayer insulating layer 120. The upper interlayer insulating layer 130 may include an oxide layer, a nitride layer, and/or an oxynitride layer. Contact plugs CT may pass through the upper interlayer insulating layer 130 and the lower interlayer insulating layer 120 to be electrically connected to the source/drain patterns SD. The contact plugs CT may be disposed on both sides of the gate structure GS. Among the source/drain patterns SD, the source patterns SDa may be connected to each other by one of the contact plugs CT. Among the source/drain patterns SD, the drain patterns SDb may be connected to each other by another contact plug CT among the contact plugs CT. Although not shown, a gate contact plug may pass through the upper interlayer insulating layer 130 and be electrically connected to the gate electrode GE. Wires may be disposed on the upper interlayer insulating layer 130 and may be connected to the contact plugs CT and the gate contact plug. The contact plugs CT and the gate contact plug may include a conductive metal nitride and/or a metal. For example, the contact plugs CT and the gate contact plug may include metal nitrides such as TiN, WN, and TaN, and/or metals such as Ti, W, and Ta. The wirings may include a conductive material.

According to the concept of the present invention, the plurality of channel patterns AP may be disposed to be spaced apart from each other in the first direction D1 on the single active region 102, and the plurality of source/drain patterns ( SD) may be disposed on both sides of the channel patterns AP on the single active region 102. As the channel patterns AP are disposed to be spaced apart from each other in the first direction D1 on the single active region 102, as will be described later, formation of the channel patterns AP may be facilitated. . In addition, the widths W1, W2, W3 of the channel patterns AP and the widths W1a, W2a, W3a of the source/drain patterns SD may be variously adjusted, and accordingly, A degree of freedom in designing a semiconductor integrated circuit including a transistor implemented by the channel patterns AP, the source/drain patterns SD, and the gate structure GS may increase.

3A to 9A, 3B to 9B, and 3C to 9C are diagrams illustrating a method of manufacturing a semiconductor device according to some embodiments of the present invention, respectively, A-A' and B- of FIG. These are cross-sectional views corresponding to B'and C-C'. For the sake of simplicity, descriptions overlapping with the semiconductor devices described with reference to FIGS. 1 and 2A to 2C are omitted.

1 and 3A to 3C, sacrificial layers 150 and semiconductor layers 152 may be alternately and repeatedly stacked on the substrate 100. The sacrificial layers 150 and the semiconductor layers 152 are shown to be repeatedly stacked three times, but the concept of the present invention is not limited thereto. The sacrificial layers 150 may include a material having etch selectivity with respect to the semiconductor layers 152. For example, the sacrificial layers 150 may be one of SiGe, Si, and Ge, and the semiconductor layers 152 may be the other one of SiGe, Si, and Ge. The sacrificial layers 150 and the semiconductor layers 152 may be formed by performing an epitaxial growth process using the substrate 100 as a seed. The sacrificial layers 150 and the semiconductor layers 152 may be formed to have the same thickness or different thicknesses.

An active region 102 may be formed on the substrate 100. The active region 102 is formed by sequentially patterning the sacrificial layers 150, the semiconductor layers 152, and the upper portions of the substrate 100 to form the active region 102 in the substrate 100. It may include forming trenches T defining ). The trenches T may be spaced apart from each other in the first direction D1 and may have a line shape extending in the second direction D2. Device isolation patterns ST may be formed to fill the trenches T, respectively. The device isolation patterns ST may be formed on the substrate 100 on both sides of the active region 102. The device isolation patterns ST may extend in the second direction D2 and may be spaced apart from each other in the first direction D1 with the active region 102 interposed therebetween. Forming the device isolation patterns ST includes forming an insulating layer filling the trenches T on the substrate 100, and the sacrificial layers 150 and the semiconductor layers 152 It may include recessing the insulating layer so that the sides of the are exposed. As the insulating layer is recessed, upper surfaces ST_U of the device isolation patterns ST may be at a lower level than the upper surface 102U of the active region 102.

1 and 4A to 4C, a plurality of preliminary channel patterns PAP may be formed on the upper surface 102U of the active region 102. The preliminary channel patterns PAP may be formed by sequentially patterning the sacrificial layers 150 and the semiconductor layers 152. The preliminary channel patterns PAP may be spaced apart from each other in the first direction D1 on the upper surface 102U of the active region 102 and have a line shape extending in the second direction D2. I can. Each of the preliminary channel patterns PAP may include preliminary sacrificial patterns 150P and preliminary semiconductor patterns 152P respectively formed by patterning the sacrificial layers 150 and the semiconductor layers 152. have. The preliminary sacrificial patterns 150P and the preliminary semiconductor patterns 152P may be alternately and repeatedly stacked along the third direction D3. Each of the preliminary sacrificial patterns 150P and the preliminary semiconductor patterns 152P may have a line shape extending in the second direction D2 on the upper surface 102U of the active region 102.

Each of the preliminary channel patterns PAP may have a width along the first direction D1. According to some embodiments, a width of at least one preliminary channel pattern PAP among the preliminary channel patterns PAP may be different from a width of another preliminary channel pattern PAP among the preliminary channel patterns PAP . According to some embodiments, widths of the preliminary channel patterns PAP may be different from each other, and according to other embodiments, the widths of the preliminary channel patterns PAP may be the same. According to some embodiments, a distance between at least one pair of preliminary channel patterns PAP among the preliminary channel patterns PAP is the other pair of preliminary channel patterns ( PAP) may differ from the distance between them. According to other embodiments, distances between the preliminary channel patterns PAP may be the same. Each of the distances between the preliminary channel patterns PAP is a distance in the first direction D1 between a pair of preliminary channel patterns PAP adjacent to each other among the preliminary channel patterns PAP Can be

Referring to FIGS. 1 and 5A to 5C, a sacrificial gate structure SGS may be formed to cross the plurality of preliminary channel patterns PAP. The sacrificial gate structure SGS may extend in the first direction D1 and do not cross the active region 102, the plurality of preliminary channel patterns PAP, and the device isolation patterns ST. You can. The sacrificial gate structure SGS may include an etch stop pattern 160, a sacrificial gate pattern 162, and a mask pattern 164 sequentially stacked on the substrate 100. The sacrificial gate pattern 162 may have a line shape extending in the first direction D1. The sacrificial gate pattern 162 may cover side surfaces of each of the preliminary channel patterns PAP, facing each other in the first direction D1, and an upper surface of each of the preliminary channel patterns PAP, The upper surface 102U of the active region 102 between the preliminary channel patterns PAP and the upper surfaces ST_U of the device isolation patterns ST may be covered. The etch stop pattern 160 may be interposed between the sacrificial gate pattern 162 and each of the preliminary channel patterns PAP, and between the sacrificial gate pattern 162 and the active region 102 and the It may extend between the sacrificial gate pattern 162 and each of the device isolation patterns ST.

The formation of the sacrificial gate pattern 162 and the etch stop pattern 160 includes the preliminary channel patterns PAP, the active region 102, and the device isolation patterns on the substrate 100. Forming an etch stop layer (not shown) and a sacrificial gate layer (not shown) sequentially covering the ST, and the mask pattern 164 defining a region on the sacrificial gate layer in which the sacrificial gate pattern 162 will be formed ), and sequentially patterning the sacrificial gate layer and the etch stop layer using the mask pattern 164 as an etching mask. The etch stop layer may include, for example, a silicon oxide layer. The sacrificial gate layer may include a material having etch selectivity with respect to the etch stop layer. The sacrificial gate layer may include, for example, polysilicon. The sacrificial gate pattern 162 may be formed by patterning the sacrificial gate layer using the mask pattern 164 as an etching mask. Patterning the sacrificial gate layer may include performing an etching process having an etch selectivity on the etch stop layer. After the sacrificial gate pattern 162 is formed, the etch stop layer on both sides of the sacrificial gate pattern 162 is removed to form the etch stop pattern 160 locally under the sacrificial gate pattern 162. have.

The sacrificial gate structure SGS may further include gate spacers GSP on both sides of the sacrificial gate pattern 162. Forming the gate spacers GSP may include a gate spacer layer (not shown) covering the mask pattern 164, the sacrificial gate pattern 162, and the etch stop pattern 160 on the substrate 100. ), and anisotropically etching the gate spacer layer. The mask pattern 164 and the gate spacers GSP may include, for example, silicon nitride.

Referring to FIGS. 1 and 6A to 6C, a plurality of channel patterns AP may be formed under the sacrificial gate structure SGS by patterning the preliminary channel patterns PAP. The plurality of channel patterns AP may be spaced apart from each other in the first direction D1, and each of the plurality of channel patterns AP may overlap the sacrificial gate structure SGS. Forming the channel patterns AP may include removing portions of the preliminary channel patterns PAP from both sides of the sacrificial gate structure SGS. The removal of the respective portions of the preliminary channel patterns PAP may be performed by using the mask pattern 164 and the gate spacers GSP as an etching mask. It may include etching portions. Etching the portions of each of the preliminary channel patterns PAP may be performed until the upper surface 102U of the active region 102 is exposed on both sides of the sacrificial gate structure SGS. . Each of the channel patterns AP may include sacrificial patterns 154 and semiconductor patterns 104 alternately and repeatedly stacked on the active region 102. The sacrificial patterns 154 may be formed by patterning the preliminary sacrificial patterns 150P, and the semiconductor patterns 104 may be formed by patterning the preliminary semiconductor patterns 152P. The sacrificial gate structure SGS may cover side surfaces of each of the channel patterns AP, facing each other in the first direction D1, and each of the channel patterns AP, the second Side surfaces facing each other in the direction D2 may be exposed.

On the side surfaces of the channel patterns AP exposed by the sacrificial gate structure SGS, the sacrificial patterns 154 are horizontally recessed to form recess regions 154R Can be. The recess regions 154R may be formed by performing a wet etching process of selectively etching the sacrificial patterns 154. Thereafter, spacer patterns 110 may be formed in the recess regions 154R, respectively. Forming the spacer patterns 110 includes conformally forming a spacer layer filling the recess regions 154R on the substrate 100, and the spacer patterns 110 forming the recesses The spacer layer may be anisotropically etched so as to be formed locally in the regions 154R. The spacer patterns 110 may include a low dielectric film (eg, silicon nitride).

Referring to FIGS. 1 and 7A to 7C, source/drain patterns SD may be formed on the active region 102 on both sides of the sacrificial gate structure SGS. The source/drain patterns SD may be formed by performing a selective epitaxial growth process using the semiconductor patterns 104 and the active region 102 as seeds. Each of the source/drain patterns SD may contact side surfaces of the semiconductor patterns 104 exposed by the sacrificial gate structure SGS, and the upper surface 102U of the active region 102 ). The source/drain patterns SD may be electrically connected to each other through each of the semiconductor patterns 104. The source/drain patterns SD may be spaced apart from each of the sacrificial patterns 154 with the spacer patterns 110 interposed therebetween. The source/drain patterns SD may contact the spacer patterns 110.

The source/drain patterns SD may include at least one of silicon-germanium (SiGe), silicon (Si), and silicon carbide (SiC). The forming of the source/drain patterns SD further includes doping the source/drain patterns SD with impurities simultaneously with the selective epitaxial growth process or after the selective epitaxial growth process. can do. The impurities may be employed to improve electrical characteristics of a transistor including the source/drain patterns SD. When the transistor is an NMOSFET, the impurity may be phosphorus (P), for example, and when the transistor is a PMOSFET, the impurity may be boron (B), for example.

A lower interlayer insulating layer 120 may be formed on the substrate 100 on which the source/drain patterns SD are formed. The lower interlayer insulating layer 120 may be formed to cover the source/drain patterns SD and the sacrificial gate structure SGS.

1 and 8A to 8C, the lower interlayer insulating layer 120 may be planarized until the sacrificial gate pattern 162 is exposed. The mask pattern 164 may be removed by the planarization process. The sacrificial gate pattern 162 and the etch stop pattern 160 may be removed, and accordingly, a gap region 170 may be formed in the lower interlayer insulating layer 120. The gap region 170 may be an empty region between the gate spacers GSP. The gap region 170 may expose the plurality of channel patterns AP. The formation of the gap region 170 may include performing an etching process having an etch selectivity on the gate spacer (GSP), the lower interlayer insulating layer 120, and the etch stop pattern 160 to form the sacrificial gate pattern ( It may include selectively etching the 162 and removing the etch stop pattern 160 to expose the semiconductor patterns 104 and the sacrificial patterns 154. The gap region 170 may have a line shape extending in the first direction D1 from a plan view, and may expose the upper surfaces ST_U of the device isolation patterns ST.

The exposed sacrificial patterns 154 may be selectively removed. As an example, when the sacrificial patterns 154 include silicon-germanium (SiGe) and the semiconductor patterns 104 include silicon (Si), the sacrificial patterns 154 are peracetic acid. acid) may be selectively removed by performing a wet etching process using as an etching source. During the selective removal process, the source/drain patterns SD may be protected by the interlayer insulating layer 120 and the spacer patterns 110. As the sacrificial patterns 154 are selectively removed, a blank area between the semiconductor patterns 104 and between the lowermost semiconductor pattern 104 and the active region 102 of the semiconductor patterns 104 Fields 172 may be formed. Each of the empty areas 172 may be connected to the gap area 170 to communicate with each other.

When a single channel pattern having substantially the same width as the single active region 102 is formed on the single active region 102, it may be difficult to remove the sacrificial patterns 154 in the single channel pattern. Accordingly, it may be difficult to form blank regions 172 between the semiconductor patterns 104 in the single channel pattern.

According to the concept of the present invention, the plurality of channel patterns AP may be formed to be spaced apart from each other in the first direction D1 on the single active region 102. Accordingly, it is possible to easily remove the sacrificial patterns 154 in each of the plurality of channel patterns AP, and between the semiconductor patterns 104 in each of the plurality of channel patterns AP It may be easy to form the blank areas 172 in the. Therefore, it can be easy to manufacture the semiconductor device.

1 and 9A to 9C, a gate insulating pattern GI and a gate electrode GE may be formed to fill the gap region 170 and the empty regions 172. The forming of the gate insulating pattern GI and the gate electrode GE includes forming a gate insulating layer conformally covering inner surfaces of the gap region 170 and the empty regions 172, and the gap region (170) and forming a gate conductive layer filling the remainder of the empty regions 172, and performing a planarization process until the lower interlayer insulating layer 120 is exposed, and the gate insulating pattern GI and the It may include forming the gate electrode GE locally in the gap region 170 and the empty regions 172. The gate electrode GE may be spaced apart from each of the semiconductor patterns 104 and the active region 102 with the gate insulating pattern GI interposed therebetween, and each of the spacer patterns 110 It may be spaced apart from each of the source/drain patterns SD while interposed therebetween.

Upper portions of the gate insulating pattern GI and the gate electrode GE may be recessed, so that a groove region may be formed between the gate spacers GSP. A gate capping pattern CAP may be formed in the groove area. The forming of the gate capping pattern CAP includes forming a gate capping layer filling the groove region on the lower interlayer insulating layer 120, and forming the gate capping layer until the lower interlayer insulating layer 120 is exposed. It may include flattening.

The gate insulating pattern GI, the gate electrode GE, the gate capping pattern CAP, and the gate spacers GSP may constitute a gate structure GS. A pair of source/drain patterns SD among the source/drain patterns SD may be spaced apart from each other in the second direction D2 with each of the channel patterns AP interposed therebetween, and the A pair of source/drain patterns SD may contact each of the semiconductor patterns 104 of the channel patterns AP. Each of the channel patterns AP and the pair of source/drain patterns SD may constitute an active structure AS, and a plurality of active structures AS may be formed on the active region 102. May be arranged to be spaced apart from each other in the first direction D1. Each of the active structures AS and the gate electrode GE may constitute a gate-all-around type field effect transistor.

Referring again to FIGS. 1 and 2A to 2C, an upper interlayer insulating layer 130 may be formed on the lower interlayer insulating layer 120. Contact plugs CT may be formed to pass through the upper interlayer insulating layer 130 and the lower interlayer insulating layer 120 to be electrically connected to the source/drain patterns SD, and a gate contact plug (not shown) ) May pass through the upper interlayer insulating layer 130 and be electrically connected to the gate electrode GE. Forming the contact plugs CT and the gate contact plug may include, for example, penetrating the upper interlayer insulating layer 130 and the lower interlayer insulating layer 120 to expose the source/drain patterns SD. Forming a gate contact hole penetrating the contact holes and the upper interlayer insulating layer 130 to expose the gate electrode GE, forming the contact holes and a conductive layer filling the gate contact hole, and the upper portion It may include planarizing the conductive layer until the upper surface of the interlayer insulating layer 130 is exposed. Wires (not shown) may be formed on the upper interlayer insulating layer 130, and may be formed to be connected to the contact plugs CT and the gate contact plug.

10 is a plan view of a semiconductor device according to some embodiments of the present invention. 11A, 11B, and 11C are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 10, respectively. For simplicity of explanation, differences from the semiconductor devices described with reference to FIGS. 1 and 2A to 2C will be mainly described.

10, 11A, 11B, and 11C, the contact plugs CT penetrate the upper interlayer insulating layer 130 and the lower interlayer insulating layer 120 to pass through the source/drain patterns SD. ) Can be electrically connected. According to the present embodiments, the source patterns SDa among the source/drain patterns SD may be respectively connected to corresponding contact plugs CT among the contact plugs CT. The contact plugs CT respectively connected to the source patterns SDa may be spaced apart from each other in the first direction D1 from one side of the gate structure GS. Among the source/drain patterns SD, the drain patterns SDb may be respectively connected to corresponding contact plugs CT among the contact plugs CT. The contact plugs CT respectively connected to the drain patterns SDb may be spaced apart from each other in the first direction D1 from the other side of the gate structure GS. Wires ML may be disposed on the upper interlayer insulating layer 130 and may be connected to the contact plugs CT. The contact plugs CT respectively connected to the source patterns SDa may be connected to each other by a corresponding wire ML among the wires ML. The contact plugs CT respectively connected to the drain patterns SDb may be connected to each other by a corresponding other wire ML among the wires ML. Except for the above-described difference, the semiconductor device according to the present embodiments is substantially the same as the semiconductor device described with reference to FIGS. 1 and 2A to 2C.

12 is a plan view of a semiconductor device according to some embodiments of the present invention. 13A, 13B, and 13C are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 12, respectively. For simplicity of explanation, differences from the semiconductor devices described with reference to FIGS. 1 and 2A to 2C will be mainly described.

12, 13A, 13B, and 13C, a plurality of active regions 102 may be disposed on the substrate 100. The plurality of active regions 102 may protrude from the substrate 100 along the third direction D3. Device isolation patterns ST may be disposed on the substrate 100 to define the plurality of active regions 102. The device isolation patterns ST may be disposed on side surfaces of the plurality of active regions 102. The plurality of active regions 102 are separated from each other in the first direction (D1) in a first active region (102a) and a second active region (102b), the second direction from the first active region (102a). A third active region 102c extending in (D2), and a fourth active region 102d extending in the second direction D2 from the second active region 102b. The first active region 102a and the second active region 102b may be spaced apart from each other in the first direction D1 with a corresponding device isolation pattern ST interposed between the device isolation patterns ST. And the third active region 102c and the fourth active region 102d are in the first direction D1 with a corresponding device isolation pattern ST among the device isolation patterns ST interposed therebetween. They can be separated from each other.

Each of the first to fourth active regions 102a, 102b, 102c, and 102d may have a width along the first direction D1. The width 102W1 of the first active area 102a may be larger than the width 102W3 of the third active area 102c, and the width 102W2 of the second active area 102b is the fourth active area 102b. It may be larger than the width 102W4 of the region 102d. According to some embodiments, the width 102W1 of the first active region 102a may be substantially the same as the width 102W2 of the second active region 102b.

A plurality of first channel patterns AP1 may be disposed on the first active region 102a. The first channel patterns AP1 may be spaced apart from each other in the first direction D1 on the upper surface 102aU of the first active region 102a. Each of the first channel patterns AP1 is a plurality of first channels stacked along a direction perpendicular to the top surface 102aU of the first active region 102a (for example, the third direction D3). It may include semiconductor patterns 104. Each of the first channel patterns AP1 may have a width W4 along the first direction D1. Each width W4 of the first channel patterns AP1 may be the width of each of the first semiconductor patterns 104 of the first channel patterns AP1. The width 102W of the first active region 102a may be greater than the sum of the widths W4 of the first channel patterns AP1. The width 102W of the first active region 102a may be greater than or equal to the sum of the distances between the widths W4 of the first channel patterns AP1 and the first channel patterns AP1. have. The distance between the first channel patterns AP1 may be a distance in the first direction D1 between the first channel patterns AP1 adjacent to each other among the first channel patterns AP1. .

A second channel pattern AP2 may be disposed on the second active region 102b. The second channel pattern AP2 includes a plurality of second semiconductor patterns stacked along a direction perpendicular to the upper surface 102bU of the second active region 102b (for example, the third direction D3). 104) may be included. The second channel pattern AP2 may have a width W5 along the first direction D1. The width W5 of the second channel pattern AP2 may be the width of the second semiconductor patterns 104 of the second channel pattern AP2. The width W5 of the second channel pattern AP2 may be greater than the width W4 of each of the first channel patterns AP1. The width W5 of the second channel pattern AP2 may be greater than the sum of the widths W4 of the first channel patterns AP1.

A third channel pattern AP3 may be disposed on the third active region 102c. The third channel pattern AP3 includes a plurality of third semiconductor patterns 104 stacked along a direction perpendicular to the upper surface of the third active region 102c (for example, the third direction D3). Can include. The third channel pattern AP3 may have a width W6 along the first direction D1. The width W6 of the third channel pattern AP3 may be the width of the third semiconductor patterns 104 of the third channel pattern AP3. The width W6 of the third channel pattern AP3 may be smaller than the width W5 of the second channel pattern AP2, and the width W4 of each of the first channel patterns AP1 ) May be substantially the same.

A fourth channel pattern AP4 may be disposed on the fourth active region 102d. The fourth channel pattern AP4 includes a plurality of fourth semiconductor patterns 104 stacked along a direction perpendicular to the upper surface of the fourth active region 102d (for example, the third direction D3). Can include. The fourth channel pattern AP4 may have a width W7 along the first direction D1. The width W7 of the fourth channel pattern AP4 may be the width of the fourth semiconductor patterns 104 of the fourth channel pattern AP4. The width W7 of the fourth channel pattern AP4 may be smaller than the width W5 of the second channel pattern AP2, and the width W4 of each of the first channel patterns AP1 ) May be substantially the same.

According to some embodiments, the third channel pattern AP3 may be arranged to be aligned with one of the first channel patterns AP1 along the second direction D2 from a plan view. The fourth channel pattern AP4 may be arranged to be aligned with an edge portion of the second channel pattern AP2 along the second direction D2 from a plan view. In this case, the width ST_W2 of the device isolation pattern ST between the third active region 102c and the fourth active region 102d is the first active region 102a and the second active region 102b. ) May be larger than the width ST_W1 of the device isolation pattern ST.

First source/drain patterns SD1 may be disposed on the first active region 102a. The first source/drain patterns SD1 may be disposed on one side of the first channel patterns AP1, and the first direction D1 on the upper surface 102aU of the first active region 102a ) Can be separated from each other. The first source/drain patterns SD1 may be connected to the first channel patterns AP1, respectively. Each of the first source/drain patterns SD1 may have a width W4a along the first direction D1. The width 102W of the first active region 102a may be greater than the sum of the widths W4a of the first source/drain patterns SD1.

A second source/drain pattern SD2 may be disposed on the second active region 102b. The second source/drain pattern SD2 may be disposed on one side of the second channel pattern AP2 and may be connected to the second channel pattern AP2. The second source/drain pattern SD2 may have a width W5a along the first direction D1. The width W5a of the second source/drain pattern SD2 may be larger than the width W4a of each of the first source/drain patterns SD1, and the first source/drain patterns SD1 It may be greater than the sum of the widths W4a of SD1).

A third source/drain pattern SD3 may be disposed on the third active region 102c. The third source/drain pattern SD3 may be disposed on one side of the third channel pattern AP3 and may be connected to the third channel pattern AP3. The third source/drain pattern SD3 may have a width W6a along the first direction D1. The width W6a of the third source/drain pattern SD3 may be smaller than the width W5a of the second source/drain pattern SD2, and the first source/drain patterns SD1 It may be substantially the same as each of the widths W4a.

A fourth source/drain pattern SD4 may be disposed on the fourth active region 102d. The fourth source/drain pattern SD4 may be disposed on one side of the fourth channel pattern AP4 and may be connected to the fourth channel pattern AP4. The fourth source/drain pattern SD4 may have a width W7a along the first direction D1. The width W7a of the fourth source/drain pattern SD4 may be smaller than the width W5a of the second source/drain pattern SD2, and the first source/drain patterns SD1 It may be substantially the same as each of the widths W4a.

A plurality of gate structures GS may be disposed to cross the active regions 102. The gate structures GS may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. One of the gate structures GS may cross the first and second active regions 102a and 102b and the device isolation pattern ST therebetween, and the plurality of first channel patterns AP1 ) And the second channel pattern AP2. Another one of the gate structures GS may cross the third and fourth active regions 102c and 102d and the device isolation pattern ST therebetween, and the third and fourth channel patterns (AP3, AP4) can be covered.

The first contact plug CT1 and the second contact plug CT2 may be disposed to be spaced apart from each other in the first direction D1 from one side of the one of the gate structures GS. The first contact plug CT1 may extend in the first direction D1 to connect the first source/drain patterns SD1 to each other, and the second contact plug CT2 may be provided with the second source/drain pattern. It may be connected to the drain pattern SD2. The third contact plug CT3 and the fourth contact plug CT4 may be disposed to be spaced apart from each other in the first direction D1 from one side of the other of the gate structures GS. The third contact plug CT3 and the fourth contact plug CT4 may be connected to the third source/drain pattern SD3 and the fourth source/drain pattern SD4, respectively.

14 is a plan view of a semiconductor device according to some embodiments of the present invention. 15 is a cross-sectional view taken along line A-A' of FIG. 14. Cross-sectional views taken along lines B-B' and C-C' of FIG. 14 are the same as those of FIGS. 13B and 13C, respectively.

14 and 15, according to the present embodiments, the third channel pattern AP3 is offset from the first channel patterns AP1 along the second direction D2 in a plan view. Can be placed. In a plan view, the fourth channel pattern AP4 may be arranged to be aligned with a central portion of the second channel pattern AP2 along the second direction D2. In this case, the width ST_W2 of the device isolation pattern ST between the third active region 102c and the fourth active region 102d is the first active region 102a and the second active region 102b. ) May be larger than the width ST_W1 of the device isolation pattern ST. Except for the above differences, the semiconductor device according to the present embodiments is substantially the same as the semiconductor device described with reference to FIGS. 12, 13A, 13B, and 13C.

16 is a plan view of a semiconductor device according to some embodiments of the present invention. 17 is a cross-sectional view taken along line A-A' of FIG. 16. Shaves according to B-B' and C-C' of FIG. 16 are the same as those of FIGS. 13B and 13C, respectively.

Referring to FIGS. 16 and 17, according to the present embodiments, the third channel pattern AP3 is formed in one of the first channel patterns AP1 along the second direction D2 in a plan view. It can be arranged to be aligned. The fourth channel pattern AP4 may be arranged to be aligned with an edge portion of the second channel pattern AP2 along the second direction D2 from a plan view. In this case, the width ST_W2 of the device isolation pattern ST between the third active region 102c and the fourth active region 102d is the first active region 102a and the second active region 102b. ) May be substantially the same as the width ST_W1 of the device isolation pattern ST. Except for the above differences, the semiconductor device according to the present embodiments is substantially the same as the semiconductor device described with reference to FIGS. 12, 13A, 13B, and 13C.

18 is a plan view of a semiconductor device according to some embodiments of the present invention. 19A, 19B, and 19C are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 18, respectively. For simplicity of explanation, differences from the semiconductor devices described with reference to FIGS. 1 and 2A to 2C will be mainly described.

18, 19A, 19B, and 19C, a plurality of active regions 102 may be disposed on the substrate 100. The plurality of active regions 102 may protrude from the substrate 100 along the third direction D3. The plurality of active regions 102 include a first active region 102a and second active regions 102b spaced apart from each other in the first direction D1 with the first active region 102a interposed therebetween. It may include. The second active regions 102b may have a line shape extending in the second direction D2. The plurality of active regions 102 may further include third active regions 102c disposed between the second active regions 102b. The third active regions 102c may be spaced apart from each other in the first direction D1 between the second active regions 102b, and extend in the second direction D2 to be the first active region Can be connected to (102a). The first active regions 102a and the third active regions 102c may have a first conductivity type (n-type or p-type), and the second active regions 102b may have the first conductivity type. It may have a second conductivity type (p-type or n-type) different from that. Device isolation patterns ST may be interposed between the plurality of active regions 102.

Each of the first to third active regions 102a, 102b, and 102c may have a width along the first direction D1. The width 102W1 of the first active region 102a may be larger than the width 102W2 of each of the second active regions 102b and the width 102W3 of each of the third active regions 102c. have. According to some embodiments, the width 102W1 of the first active region 102a may be greater than the sum of the widths 102W3 of the third active regions 102c.

A plurality of first channel patterns AP1 may be disposed on the first active region 102a. The first channel patterns AP1 may be spaced apart from each other in the first direction D1 on the upper surface 102aU of the first active region 102a. Each of the first channel patterns AP1 is a plurality of first channels stacked along a direction perpendicular to the top surface 102aU of the first active region 102a (for example, the third direction D3). It may include semiconductor patterns 104. Each of the first channel patterns AP1 may have a width W4 along the first direction D1. Each width W4 of the first channel patterns AP1 may be the width of each of the first semiconductor patterns 104 of the first channel patterns AP1. The width 102W1 of the first active region 102a may be greater than the sum of the widths W4 of the first channel patterns AP1. The width 102W of the first active region 102a may be greater than or equal to the sum of distances between the widths W4 of the first channel patterns AP1 and the first channel patterns AP1. have. Each of the distances between the first channel patterns AP1 is the first direction D1 between the pair of first channel patterns AP1 adjacent to each other among the first channel patterns AP1 It may be a distance according to.

A second channel pattern AP2 may be disposed on each of the second active regions 102b. The second channel pattern AP2 is a plurality of second semiconductors stacked along a direction perpendicular to the upper surface 102bU of each of the second active regions 102b (for example, the third direction D3). Patterns 104 may be included. The second channel pattern AP2 may have a width W5 along the first direction D1. The width W5 of the second channel pattern AP2 may be the width of the second semiconductor patterns 104 of the second channel pattern AP2. The width W5 of the second channel pattern AP2 may be substantially the same as the width W4 of each of the first channel patterns AP1. The second channel pattern AP2 may be arranged to be aligned with the first channel patterns AP1 along the first direction D1 from a plan view.

A third channel pattern AP3 may be disposed on each of the third active regions 102c. The third channel pattern AP3 includes a plurality of third semiconductor patterns stacked along a direction perpendicular to the upper surface of each of the third active regions 102c (for example, the third direction D3). can do. The third channel pattern AP3 may have a width W6 along the first direction D1. The width W6 of the third channel pattern AP3 may be the width of the third semiconductor patterns of the third channel pattern AP3. The width W6 of the third channel pattern AP3 may be substantially the same as the width W4 of each of the first channel patterns AP1. The third channel pattern AP3 may be arranged to be aligned with one of the first channel patterns AP1 along the second direction D2 from a plan view. An additional second channel pattern AP2 may be disposed on each of the second active regions 102b. The additional second channel pattern AP2 may be arranged to be aligned with the third channel pattern AP3 along the first direction D1 from a plan view.

First source/drain patterns SD1 may be disposed on the first active region 102a. The first source/drain patterns SD1 may be disposed on one side of the first channel patterns AP1, and the first direction D1 on the upper surface 102aU of the first active region 102a ) Can be separated from each other. The first source/drain patterns SD1 may be connected to the first channel patterns AP1, respectively. Each of the first source/drain patterns SD1 may have a width W4a along the first direction D1. The width 102W1 of the first active region 102a may be greater than the sum of the widths W4a of the first source/drain patterns SD1.

A second source/drain pattern SD2 may be disposed on each of the second active regions 102b. The second source/drain pattern SD2 may be disposed on one side of the second channel pattern AP2 and may be connected to the second channel pattern AP2. The second source/drain pattern SD2 may have a width W5a along the first direction D1. The width W5a of the second source/drain pattern SD2 may be substantially the same as the width W4a of each of the first source/drain patterns SD1.

A third source/drain pattern SD3 may be disposed on each of the third active regions 102c. The third source/drain pattern SD3 may be disposed on one side of the third channel pattern AP3 and may be connected to the third channel pattern AP3. The third source/drain pattern SD3 may have a width W6a along the first direction D1. The width W6a of the third source/drain pattern SD3 may be substantially the same as the width W4a of each of the first source/drain patterns SD1. An additional second source/drain pattern SD2 may be disposed on each of the second active regions 102b. The additional second source/drain pattern SD2 may be disposed on one side of the additional second channel pattern AP2 and may be connected to the additional second channel pattern AP2.

A plurality of gate structures GS may be disposed to cross the active regions 102. The gate structures GS may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. One of the gate structures GS may cross the first and second active regions 102a and 102b and the device isolation patterns ST therebetween, and the plurality of first channel patterns ( AP1) and the second channel pattern AP2 may be covered. The other of the gate structures GS may cross one of the second active regions 102b, one of the third active regions 102c, and a device isolation pattern ST therebetween, , The additional second channel pattern AP2 and the third channel pattern AP3 may be covered.

The first contact plug CT1 and the second contact plug CT2 may be disposed to be spaced apart from each other in the first direction D1 from one side of the one of the gate structures GS. The first contact plug CT1 may extend in the first direction D1 to connect the first source/drain patterns SD1 to each other, and the second contact plug CT2 may be provided with the second source/drain pattern. It may be connected to the drain pattern SD2. A third contact plug CT3 and an additional second contact plug CT2 may be disposed to be spaced apart from each other in the first direction D1 from one side of the other of the gate structures GS. The third contact plug CT3 and the additional second contact plug CT2 may be connected to the third source/drain pattern SD3 and the additional second source/drain pattern SD2, respectively.

The substrate 100 includes a first power line PW1 and second power lines PW2 spaced apart from each other in the first direction D1 with the first power line PW1 interposed therebetween. Can be placed on top. The first and second power lines PW1 and PW2 may be spaced apart from each other in the first direction D1 and may extend in the second direction D2. The first power line PW1 may be disposed on the device isolation pattern ST between the third active regions 102c, and extend in the second direction D2 so that the first active region 102a ) Can be crossed. The first power line PW1 may cross the gate structures GS and the first contact plug CT1 on the first active region 102a. The second power lines PW2 may be disposed adjacent to the second active regions 102b, respectively. For example, a drain voltage may be applied through the first power line PW1, and a source voltage may be applied through each of the second power lines PW2. The first and second power lines PW1 and PW2 may include a conductive material.

The above description of the embodiments of the present invention provides an example for describing the present invention. Therefore, the present invention is not limited to the above embodiments, and various modifications and changes are possible within the technical spirit of the present invention, such as by combining the above embodiments by a person having ordinary skill in the art. It is obvious.

100: substrate 102: active region
ST: device isolation pattern GS: gate structure
GI: gate insulation pattern GE: gate electrode
CAP: Gate capping pattern GSP: Gate spacer
AS: active structure AP: channel pattern
SD: source/drain patterns 104: semiconductor patterns
120: lower interlayer insulating film 130: upper interlayer insulating film
110: spacer patterns CT: contact plug

Claims (20)

An active region protruding upward from the substrate;
A plurality of channel patterns spaced apart from each other in a first direction on the active region; And
A gate electrode extending in the first direction on the active region and covering the plurality of channel patterns,
Each of the plurality of channel patterns includes a plurality of semiconductor patterns spaced apart from each other in a direction perpendicular to an upper surface of the active region,
The gate electrode covers the upper surface of the active region between the plurality of channel patterns. The method according to claim 1,
Further comprising device isolation patterns disposed on the substrate to define the active region,
The device isolation patterns are spaced apart from each other in the first direction with the active region interposed therebetween,
The active region is a single active region between the device isolation patterns. The method according to claim 1,
The gate electrode is a semiconductor device extending between each of the plurality of channel patterns and the active region, and between the plurality of semiconductor patterns. The method according to claim 1,
Each of the active region and the plurality of channel patterns has a width along the first direction,
A semiconductor device in which a width of the active region is greater than a sum of widths of the plurality of channel patterns. The method of claim 4,
The width of the active region is greater than or equal to the sum of the widths of the plurality of channel patterns and the distances between the plurality of channel patterns,
The distances between the plurality of channel patterns are distances along the first direction. The method of claim 5,
The plurality of channel patterns include a first sub channel pattern, a second sub channel pattern, and a third sub channel pattern spaced apart from each other in the first direction,
A semiconductor device in which a distance between the first sub channel pattern and the second sub channel pattern is different from a distance between the second sub channel pattern and the third sub channel pattern. The method of claim 4,
The plurality of channel patterns include a first sub channel pattern and a second sub channel pattern spaced apart from each other in the first direction,
A semiconductor device having a width of the first sub channel pattern different from that of the second sub channel pattern. The method according to claim 1,
Further comprising source/drain patterns disposed on both sides of the gate electrode on the active region,
The source/drain patterns are spaced apart from each other in a second direction crossing the first direction with each of the plurality of channel patterns interposed therebetween, and are connected to the plurality of semiconductor patterns of each of the plurality of channel patterns device. The method of claim 8,
Among the plurality of semiconductor patterns, further comprising spacer patterns disposed between a pair of semiconductor patterns adjacent to each other,
The spacer patterns are spaced apart from each other in the second direction and are disposed between the source/drain patterns. The method of claim 9,
The gate electrode extends between the spacer patterns,
Each of the spacer patterns is interposed between a corresponding one of the source/drain patterns and the gate electrode. The method according to claim 1,
Further comprising source/drain patterns disposed on one side of the gate electrode on the active region and spaced apart from each other in the first direction,
The source/drain patterns are respectively connected to the plurality of channel patterns,
Each of the source/drain patterns is connected to the plurality of semiconductor patterns of each of the plurality of channel patterns. The method of claim 11,
Each of the active region and the source/drain patterns has a width along the first direction,
A semiconductor device in which a width of the active region is greater than a sum of widths of the source/drain patterns. The method of claim 12,
A semiconductor device in which a width of at least one of the source/drain patterns is different from a width of another source/drain pattern of the source/drain patterns. The method of claim 11,
Further comprising a contact plug disposed on the one side of the gate electrode,
The contact plug extends in the first direction to connect the source/drain patterns to each other. The method of claim 11,
Contact plugs disposed on the one side of the gate electrode and spaced apart from each other in the first direction; And
Further comprising a wire connecting the contact plugs to each other,
The contact plugs are respectively connected to the source/drain patterns. A device isolation pattern on the substrate;
A first active region and a second active region protruding upward from the substrate and spaced apart from each other in a first direction with the device isolation pattern therebetween;
A plurality of first channel patterns spaced apart from each other in the first direction on the first active region;
A second channel pattern on the second active area; And
A gate electrode extending in the first direction, crossing the first and second active regions, and covering the plurality of first channel patterns and the second channel pattern,
Each of the plurality of first channel patterns includes a plurality of first semiconductor patterns spaced apart from each other in a direction perpendicular to an upper surface of the first active region,
The second channel pattern includes a plurality of second semiconductor patterns spaced apart from each other in a direction perpendicular to an upper surface of the second active region. The method of claim 16,
The first active region is a semiconductor device having a different conductivity type than the second active region. The method of claim 16,
Each of the first and second active regions has a width along the first direction,
A semiconductor device having a width of the first active region greater than a width of the second active region. The method of claim 18,
Each of the first channel patterns has a width along the first direction,
The width of the first active region is greater than a sum of widths of the first channel patterns. The method of claim 16,
Further comprising a first power line and a second power line separated from each other in the first direction and extending in a second direction crossing the first direction,
The first power line crosses the first active region and the gate electrode,
The second power line is a semiconductor device disposed adjacent to the second active region.

Images