KR20200108772A - Method of performing internal processing operations with pre-defined protocol interface of memory device - Google Patents

Abstract

Disclosed is a method for performing an internal processing operation by using a predetermined DDR or LPDDR protocol interface of a memory device. The memory device receives a specific address for dividing a first memory area and a second memory area of a memory cell array together with a command through a DDR or LPDDR protocol interface from a memory controller. The memory device generates an internal processing mode selection signal based on the specific address, converts the received command into an internal processing operation command in response to activation of the internal processing mode selection signal, and performs the internal processing operation according to the internal processing operation command.

Description

{Method of performing internal processing operations with pre-defined protocol interface of memory device}

The present invention relates to devices (apparatuses) and methods (methods), and more particularly, to a memory device that performs an internal processing operation using a predetermined protocol interface, a method of operating the same, and a memory system including the same. will be.

Applications such as high performance and/or graphics algorithms are data- and compute-intensive. Applications such as deep neural networks require computing systems with large computational and memory capabilities in order to more accurately train or learn different data sets. In order to perform some of the computation operations of a computing system through internal processing, a processor-in-memory (processor in memory: hereinafter referred to as “PIM”) type memory device has been developed. Through internal processing of the memory device, the computational operation burden of the computing system may be reduced.

However, when a separate interface for internal processing is required, hardware configurations and/or implementations of the memory device become complex and difficult, and thus, there is a problem such as an increase in cost for supporting an internal processing operation.

An object of the present invention is to provide a memory device that performs an internal processing operation using a predetermined protocol interface, a method of operating the same, and a memory system including the same.

A memory device according to embodiments of the present invention includes a memory cell array including a first memory area and a second memory area, command/address signal lines receiving a command and an address from outside the memory device, and An internal processing mode selection unit configured to generate a processing mode selection signal that controls an operation mode of the memory device to enter an internal processing mode based on an address, and an internal processing operation of the received command in response to activation of the internal processing mode selection signal And an internal processing command conversion unit configured to convert a command, and an internal processor configured to perform an internal processing operation by accessing the first memory area in response to the internal processing operation command in the internal processing mode.

A method of operating a memory device including a memory cell array and an internal processor performing an internal processing operation according to embodiments of the present invention includes receiving a command and an address from the outside of the memory device through a predetermined protocol interface, Generating a processing mode selection signal for controlling the operation mode of the memory device to enter the internal processing mode based on the address received together with, in response to the activation of the internal processing mode selection signal, the received command as an internal processing operation command Converting, and performing an internal processing operation by accessing a first memory area of the memory cell array in response to an internal processing operation command in an internal processing mode.

A memory system according to embodiments of the present invention includes a memory device and a memory controller that controls a memory device using a predetermined protocol interface connected to the memory device. The memory device receives a command and an address from a memory controller through a memory cell array including a first memory area and a second memory area, and a predetermined protocol interface, and the operation mode of the memory device is changed based on the address received with the command. An internal processing mode selection unit configured to generate a processing mode selection signal for controlling to enter the internal processing mode, an internal processing command conversion configured to convert a received command into an internal processing operation command in response to activation of the internal processing mode selection signal And an internal processor for performing an internal processing operation by accessing the first memory area in response to an internal processing operation command in the sub and internal processing mode.

According to the present invention, when an internal processing operation is performed by an internal processor of a memory device, a separate interface for supporting the internal processing operation is not required.

1 is a diagram illustrating a system including a memory device that performs an internal processing operation according to exemplary embodiments of the present invention.
2 is a block diagram illustrating a memory device according to an embodiment of the present invention.
3 to 5 are diagrams illustrating a part of the structure of the memory device of FIG. 2 by way of example.
6 is a flowchart illustrating an operation of the memory device of FIG. 2.
7 is a timing diagram illustrating an operation of the memory device of FIG. 2.
8 is a diagram illustrating a PIM mode selection unit of FIG. 2 by way of example.
9 is a flowchart for explaining the operation of the memory device of FIG. 2.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used in different drawings to indicate similar or identical items. The term "PIM" according to the present invention means "internal processing" performed by a processor-in-memory.

1 is a diagram illustrating a system including a memory device that performs an internal processing operation according to exemplary embodiments of the present invention.

Referring to FIG. 1, the system 100 may include a host device 110 and a memory device 120. The host device 110 may be communicatively connected to the memory device 120 through the memory bus 130.

Some examples may be described using the expression "connected" and/or "coupled" along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, a description using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. In addition, the terms "connection" and/or "bond" may mean that two or more elements are not in direct contact with each other but still cooperate or interact with each other.

The host device 110 is, by way of example, a computing system such as a computer, a notebook computer, a server, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, and a wearable device. I can. Alternatively, the host device 110 may be some of components included in a computing system such as a graphics card.

The host device 110 is a functional block that performs general computer operations in the system 100, and includes a central processing unit (CPU), a digital signal processor (DSP), and a graphic processing unit. It may correspond to (Graphics Processing Unit: GPU) or an Application Processor (AP). The host device 110 may include a memory controller 112 that manages data transmission/reception to/from the memory device 120.

The memory controller 112 may access the memory device 120 according to a memory request from the host device 110. The memory controller 112 is a memory physical layer interface for interfacing with the memory device 120 such as selecting a row and column corresponding to a memory location, writing data to a memory location, or reading written data. (Memory Physical Layer Interface, 114) may be included. Typically, the memory physical layer interface 114 is referred to as the memory PHY 114.

The memory controller 112 may include a control register 116 for initializing and/or controlling the memory device 120 according to operation characteristics. After system 100 is powered up, memory controller 112 may set control registers 116. The control register 116 may store various codes configured so that the memory controller 112 can normally interoperate with the memory device 120. For example, the control register 116 may store codes indicating frequency, timing, driving, detailed operation parameters, and the like of the memory device 120. In addition, specific address information for physically or logically classifying the memory cell array 121 according to an operation mode of the memory device 120 may be stored in the control register 116.

For example, the specific address information may indicate a specific address that divides the memory cell array 121 into the PIM area 122 and the normal memory area 124. The PIM area 122 may be a memory cell area accessed when the memory device 120 is operated in the internal processing mode, and the normal memory area 124 may be divided into a memory cell area accessed when the memory device 120 is operated in the normal mode. For example, the specific address indicates an address used to access the PIM region 122 and may serve as a basic signal for allowing the memory device 120 to enter the internal processing mode. The specific address may consist of, for example, a stack identification signal, a channel address or a bank address. Depending on the embodiment, the specific address may consist of a combination of a stack identification signal, a channel address, and/or a bank address.

The memory controller 112 may control a write operation or a read operation of the memory device 120 by providing the command CMD and the address ADDR to the memory device 120. Also, data DQ for a write operation and read data DQ may be transmitted and received between the memory controller 112 and the memory device 120. This memory access operation may be performed through the memory PHY 114 and the memory bus 130 between the memory controller 112 and the memory device 120.

The memory PHY 114 is a physical or electrical layer provided for signals, frequency, timing, driving, detailed operation parameters, and functionality required for efficient communication between the memory controller 112 and the memory device 120. And logical layers. The memory PHY 114 may support features of the DDR and/or LPDDR protocol of the Joint Electron Device Engineering Council (JEDEC) standard.

The memory PHY 114 may include connectors for connecting the memory controller 110 and the memory device 120. Connectors can be implemented as pins, balls, signal lines, or other hardware components. For example, a clock (CK, FIG. 7), a command (CMD), an address (ADDR), and data (DQ) are transmitted and received between the memory controller 110 and the memory device 120 through the memory PHY 114. I can.

Reuse of existing connectors in the memory PHY 114 can save significant occupied space in the integrated circuit (IC) and avoid the cost of extending additional wires to the memory device 120. In addition, avoiding additional pins and wires eliminates potential Electro-Magnetic Interference (EMI) from the presence of additional wires, and power conservation may be realized because many drivers and receivers are not required.

The memory bus 130 may include command/address signal lines 132 for transmitting command/addresses CMD/ADDR and data lines 134 for transmitting data DQ. For the sake of brevity, the command/address signal lines 132 and the data lines 134 between the memory controller 110 and the memory device 120 are shown to be respectively connected by one signal line. May be connected through a plurality of signal lines.

The memory device 120 may write data or read data under the control of the memory controller 112. For example, the memory device 120 may be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) device. However, the scope of the present invention is not limited thereto, and the memory device 120 includes a low power double data rate (LPDDR) SDRAM, a wide I/O DRAM, a high bandwidth memory (HBM), a hybrid memory cube (HMC), and the like. It may be any one of volatile memory devices. According to an embodiment, the memory device 120 may be any one of nonvolatile memory devices such as flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like. I can.

The memory device 120 may operate in one of a normal mode and an internal processing mode. The normal mode refers to an operation mode for performing general data transaction operations, and the internal processing mode refers to an operation mode for performing internal processing operations.

In the normal mode, the memory device 120 may perform a general data transaction operation under the control of the memory controller 112. A general data transaction operation refers to a data exchange operation performed according to a predetermined protocol such as DDR and/or LPDDR protocol.

In the internal processing mode, the memory device 120 may perform an internal processing operation under the control of the memory controller 112. The memory controller 112 uses a predetermined protocol such as a DDR and/or LPDDR protocol to store a specific address that is a basis for an internal processing operation to be performed by the memory device 120 through the command/address signal lines 132. It can be provided by the device 120. The memory device 120 may enter the internal processing mode based on a specific address. A specific address may be provided through an existing connector of memory PHY 114.

For example, when the memory device 120 is mounted in the system 100, a specific address that is the basis of the internal processing operation may be statically set. Static setting means that it can be fixed using one piece of specific address information. According to an embodiment, a specific address may be dynamically set before and after an internal processing operation of the memory device 120. Dynamic setting means that specific address information can be varied by using various combinations.

The memory device 120 may include a memory cell array 121 and a PIM command conversion unit 126. The memory cell array 121 may include a PIM area 122 and a normal memory area 124 that are physically or logically divided according to an operation mode of the memory device 120.

The PIM area 122 may refer to a memory cell area set to access internal processing data for an internal processing operation performed in the internal processing mode. The internal processing operation of the memory device 120 may include a write operation and/or a read operation to/from the PIM area 122.

The normal memory area 124 may refer to a memory cell area set to access data according to a general data transaction operation performed in the normal mode. The data transaction operation of the memory device 120 may include a write operation and/or a read operation to/from the normal memory area 124.

When the address ADDR received through the command/address signal lines 132 contains a specific address that is the basis of the internal processing operation, the PIM command conversion unit 126 receives it as the command/address signal lines 132 The command CMD to be converted may be converted into an internal processing operation command PIM_CMD. For example, the PIM command conversion unit 126 converts the command CMD received through the command/address signal lines 132 into a type of internal processing operation (e.g., data search, data add, It can be converted into an internal processing operation command (PIM_CMD) instructing data move, data inversion, data shift, data swap, data comparison, logical operations, and data processing/operations. The internal processing operation command PIM_CMD may include an internal processing read command and/or an internal processing write command related to the internal processing operation.

An internal processing operation of reading internal processing data from the PIM region 122 or writing internal processing data to the PIM region 122 may be performed by the internal processing operation command PIM_CMD. The internal processing data may refer to reference data or target data used in an internal processing operation. In addition, the internal processing data may include address information related to an internal processing operation such as data swap.

2 is a block diagram illustrating a memory device according to an embodiment of the present invention.

1 and 2, the memory device 120 includes a memory cell array 121 including a PIM area 122 and a normal memory area 124, a PIM command conversion unit 126, and a PIM mode selection unit ( 210 ), a first switch 231, a second switch 232, a PIM engine 250, and a data input/output circuit unit 260.

In the memory cell array 121, the PIM area 122 may be an area designated to access, that is, store and output internal processing data for an internal processing operation when the memory device 120 operates in an internal processing mode. The normal memory area 124 may be an area designated to access data according to a general data transaction operation when the memory device 120 operates in a normal mode. The PIM area 122 and the normal memory area 124 may be set as fixed areas in the memory cell array 121. Depending on the embodiment, the PIM area 122 and the normal memory area 124 may be set as variable areas in the memory cell array 121.

The PIM command conversion unit 126 may convert the command CMD received through the command/address signal lines 132 into an internal processing operation command PIM_CMD when the memory device 120 operates in the internal processing mode. have.

The PIM mode selection unit 210 receives the address ADDR from the memory controller 112 through the command/address signal lines 132 of the memory bus 130 and responds to the received address ADDR. The selection signal PIM_SEL can be output. The PIM mode selection unit 210 may determine whether the received address ADDR includes a specific address recognized as an awareness, and output a PIM mode selection signal PIM_SEL as a result of the determination.

The specific address recognized by the PIM mode selection unit 210 is the same as the specific address used to address the PIM area 122 stored in the control register 116 of the memory controller 112. The PIM mode selection signal PIM_SEL serves as a control signal for determining whether to operate by entering the internal processing mode or the memory device 120 to enter and operate the normal mode.

The PIM mode selection unit 210 may activate the PIM mode selection signal PIM_SEL when a specific address is included in the address ADDR received through the command/address signal lines 132. By activation of the PIM mode selection signal PIM_SEL, the memory device 120 may operate in an internal processing mode. The PIM mode selection unit 210 may deactivate the PIM mode selection signal PIM_SEL when a specific address is not included in the address ADDR received through the command/address signal lines 132. By deactivating the PIM mode selection signal PIM_SEL, the memory device 120 may operate in a normal mode. The PIM mode selection signal PIM_SEL may be provided to the first and second switches 231 and 232.

The first switch 231 converts the command/address signal lines 132 to the input signal lines 221 of the PIM command converter 126 or internal command signal lines 240 in response to the PIM mode selection signal PIM_SEL. ) And can be selectively linked. The second switch 232 connects the output signal lines 222 of the PIM command converter 126 or the internal command signal lines 240 to the memory cell array 121 and the PIM in response to the PIM mode selection signal PIM_SEL. It can be selectively connected to the engine 250.

The first switch 231 may connect the command/address signal lines 132 to the input signal lines 221 of the PIM command conversion unit 126 in response to activation of the PIM mode selection signal PIM_SEL. The first switch 231 may provide the command CMD received through the command/address signal lines 132 to the PIM command converter 126. The PIM command conversion unit 126 converts the command CMD received through the input signal lines 221 into an internal processing operation command PIM_CMD, and converts the internal processing operation command PIM_CMD to the output signal lines 222 Can be printed as The internal processing operation command PIM_CMD may be a command related to an internal processing operation performed in the internal processing mode.

The second switch 232 connects the output signal lines 222 of the PIM command conversion unit 126 to the memory cell array 121 and/or the PIM engine 250 in response to activation of the PIM mode selection signal PIM_SEL. You can connect. The second switch 232 transfers the internal processing operation command PIM_CMD output through the output signal lines 222 of the PIM command conversion unit 126 to the PIM region 122 and/or PIM of the memory cell array 121. It can be provided by the engine 250. The PIM engine 250 may access the PIM area 122 according to the internal processing operation command PIM_CMD to perform an internal processing operation. Illustratively, the internal processing operation includes internal processing data stored in the PIM area 122 such as data retrieval, data addition, data movement, data inversion, data shift, data swap, data comparison, logical operations, data processing/operations, etc. Can refer to the processing operation for

The first switch 231 connects the command/address signal lines 132 to the internal command signal lines 240 in response to deactivation of the PIM mode selection signal PIM_SEL, and the command/address signal lines 132 The command CMD received through the device may be provided to the internal command signal lines 240. The command CMD provided to the internal command signal lines 240 may be a command related to a data transaction operation performed in the normal mode.

The second switch 232 may connect the internal command signal lines 240 to the memory cell array 121 in response to deactivation of the PIM mode selection signal PIM_SEL. The normal memory area 124 of the memory cell array 121 may be accessed according to the command CMD provided to the internal command signal lines 240 to perform a data transaction operation.

When the memory device 120 operates in the internal processing mode, the PIM engine 250 may perform an internal processing operation according to the internal processing operation command PIM_CMD. The PIM engine 250 may perform an internal processing operation on internal processing data according to the internal processing operation command PIM_CMD by using the PIM region 122 of the memory cell array 121.

The PIM engine 250 is hardware having a processing function, similar to a processor (eg, a CPU) included in the host device 110. When referring to the PIM engine 250 as an internal processor, the term “internal” means that it exists within the memory device 120. Accordingly, a processor existing “outside” of the memory device 120 may refer to, for example, a processor of the host device 110.

The data input/output circuit unit 260 may operate as a write driver of the memory device 120 or as a sense amplifier. The data input/output circuit unit 260 receives data DQ from the memory controller 112 through the data lines 134 of the memory bus 130 and transmits the received data to the memory cell array 121 and/or the PIM engine. It can be provided as 250. The data input/output circuit unit 260 receives data DQ from the memory cell array 121 and/or the PIM engine 250, and transmits the received data DQ to the memory controller 112 through the data lines 134. Can be transferred to.

When the memory device 120 operates in an internal processing mode, the PIM engine 250 may perform an internal processing operation. In this case, the PIM engine 250 may transmit and receive data DQ to and from the memory controller 112 through the data input/output circuit unit 260 and the data lines 134.

For example, when the PIM engine 250 performs an internal processing operation in response to the internal processing operation command PIM_CMD, the data DQ received through the data lines 134 and the data input/output circuit unit 260 is As internal processing data, it may be stored in the PIM area 122 of the memory cell array 121. The PIM engine 250 may store internal processing data according to an internal processing operation performed in response to the internal processing operation command PIM_CMD in the PIM area 122. The PIM engine 250 may read internal processing data from the PIM area 122 by an internal processing operation command PIM_CMD. The PIM engine 250 may perform an internal processing operation based on internal processing data read from the PIM area 122. The PIM engine 250 may transmit internal processing data processed according to an internal processing operation to the memory controller 112 through the data input/output circuit unit 260 and the data lines 134.

In the internal processing operation, a data exchange operation performed by the internal processing operation command PIM_CMD may occupy a part or most. The data exchange operation reads internal processing data such as reference data, source data, destination data, or target data used in the internal processing operation from the PIM area 122. Shipping may include an operation of writing a processing result of an operation and/or an internal processing operation to the PIM area 122. For example, assume that the PIM engine 250 performs internal processing operations such as data search, data movement, data addition, and data swap according to the internal processing operation command PIM_CMD.

When the internal processing operation command PIM_CMD is a command for data search, the PIM engine 250 may search whether internal processing data corresponding to data search is stored in the PIM area 122. The PIM engine 250 may output hit/miss or corresponding address information as a result of processing the data search operation. The PIM engine 250 may write hit/miss or corresponding address information according to a data search operation in the PIM area 122.

When the internal processing operation command PIM_CMD is a command for data movement, the PIM engine 250 may move data corresponding to the reference address information from the PIM area 122 to the target area. The PIM engine 250 may output address information of the moved area as a result of processing the data movement operation. A data movement operation by the PIM engine 250 and an operation of writing address information of the moved region may be performed in the PIM region 122.

When the internal processing operation command (PIM_CMD) is a command for adding data, the PIM engine 250 reads data corresponding to the reference address information from the PIM area 122, adds internal processing data to the read data, and performs PIM. It can be stored in the area 122. The PIM engine 250 may output address information of a region in which the added data is stored as a result of the data adding operation. An operation of adding data by the PIM engine 250 and an operation of writing address information of a region in which the added data is stored may be performed in the PIM region 122.

When the internal processing operation command PIM_CMD is a command for data swap, the PIM engine 250 reads first and second data corresponding to the first and second reference address information, respectively, from the PIM area 122, and The read first and second data may be swapped with each other, and each of the swapped first and second data may be stored in memory cells corresponding to the first and second reference address information of the PIM area 122. A data swap operation by the PIM engine 250 may be performed in the PIM area 122.

When the memory device 120 operates in the normal mode, the data input/output circuit unit 260 transfers data DQ received from the memory controller 112 through the data lines 134 to the normal memory of the memory cell array 121. Data stored in the area 124 and read from the normal memory area 124 may be transmitted to the memory controller 112 through the data lines 134. The memory device 120 may perform a data transaction operation using the normal memory area 124.

3 is a diagram illustrating a part of the structure of the memory device of FIG. 2 by way of example.

2 and 3, the memory device 120 includes a plurality of stacked memory layers 301-308. For example, the memory device 120 may be an HBM. The memory layers 301-308 may be referred to as core dies. The memory layers 301-308 may constitute a number of independent interfaces called channels. Each of the memory layers 301-308 may be configured with 2 channels. In order to simplify the conceptual description and drawings of the present invention, odd-numbered channels (e.g., CH1a, CH3a, CH5a, CH7a, CH1b, CH3b, CH5b, CH7b) are arranged on the left side of each of the memory layers 301-308 3 shows an example configuration in which even-numbered channels (e.g., CH2a, CH4a, CH6a, CH8a, CH2b, CH4b, CH6b, CH8b) are arranged on the right side, but the memory layers 301-308 according to the present invention The arrangement is not limited thereto.

Exemplarily, the first memory layer 301 is composed of a CH1a channel and a CH2a channel, the second memory layer 302 is composed of a CH3a channel and a CH4a channel, and the third memory layer 303 is composed of a CH5a channel and a CH6a channel. Channels are configured, and the fourth memory layer 304 can be configured as a CH7a channel and a CH8a channel. The fifth memory layer 305 is composed of a CH1b channel and a CH2b channel, the sixth memory layer 306 is composed of a CH3b channel and a CH4b channel, and the seventh memory layer 307 is composed of a CH5b channel and a CH6b channel. , The eighth memory layer 308 may include a CH7b channel and a CH8b channel. In this embodiment, the memory device 120 provides an example in which eight memory layers 301-308 are stacked. Depending on the embodiment, various numbers of memory layers, such as two or four, may be stacked on the memory device 120.

The memory device 120 may further include a buffer die 310 at the bottom of the stacked memory layers 301-308. The buffer die 310 may be referred to as a memory buffer. The buffer die 310 may include an input buffer (or receiver) that receives a clock CK, a command CMD, an address ADDR, and data DQ from the memory controller 112 (FIG. 1). The buffer die 310 includes channels CH1a, CH2a, CH3a, CH4a, CH5a, CH6a, CH7a, CH8a, CH1b, CH2b, CH3b, CH4b, CH5b, CH6b, CH7b, and through through silicon vias TSV1-TSV8. It can provide signal distribution function and data input/output function for CH8b). The buffer die 310 may communicate with the memory controller 112 through conductive means formed on the outer surface of the memory device 120, such as bumps or solder balls.

The buffer die 310 includes a PIM command conversion unit 126, a PIM mode selection unit 210, a first switch 231, a second switch 232, a PIM engine 250, and data input/output as described in FIG. 2. A circuit unit 260 may be included.

The stacked memory layers 301-308 may correspond to the memory cell array 121 including the PIM area 122 and the normal memory area 124 described in FIG. 2. Of the stacked memory layers 301-308, the lower 4 memory layers 301-304 are allocated as the PIM area 122, and the upper 4 memory layers 305-308 are the normal memory area 124. Can be assigned as According to an embodiment, the lower four memory layers 301-304 of the stacked memory layers 301-308 are allocated to the normal memory area 124, and the upper four memory layers 305-308 are It may be allocated to the PIM area 122.

The memory layers 301-304 of the PIM area 122 and the memory layers 305-308 of the normal memory area 124 are formed of through silicon vias TSV1-TSV8 and through silicon vias TSV1-TSV8. ) And the common channels CH1 through electrode pads P1a, P2a, P3a, P4a, P5a, P6a, P7a, P8a, P1b, P2b, P3b, P4b, P5b, P6b, P7b, P8b). -CH8) can be configured. For the sake of brevity of the drawing, the electrode pads P1a, P2a, P3a, P4a, P5a, P6a, P7a, P8a, P1b, P2b, P3b, P4b, P5b, P6b, P7b, P8b are shown in circles. This means that each of the electrode pads P1a, P2a, P3a, P4a, P5a, P6a, P7a, P8a, P1b, P2b, P3b, P4b, P5b, P6b, P7b, P8b is electrically connected to each of the through silicon vias TSVs. It will be understood to indicate that it is connected.

For example, the CH1a channel of the first memory layer 301 is connected to TSV1 through silicon vias through the P1a electrode pad, and the CH1b channel of the fifth memory layer 305 is through TSV1 through silicon vias through the P1b electrode pad. Can be connected with. The CH1a channel and the CH1b channel electrically connected to the TSV1 through silicon vias may constitute a first common channel CH1. In addition, the CH2a channel of the first memory layer 301 is connected to the TSV2 through silicon vias through the P2a electrode pad, and the CH2b channel of the fifth memory layer 305 is connected to the TSV2 through silicon vias through the P2b electrode pad. I can. The CH2a channel and the CH2b channel electrically connected to the TSV2 through silicon vias may form a second common channel CH2.

The CH3a channel of the second memory layer 302 may be connected to the TSV3 through silicon vias through the P3a electrode pad, and the CH3b channel of the sixth memory layer 306 may be connected to the TSV3 through silicon vias through the P3b electrode pad. . The CH3a channel and the CH3b channel electrically connected to the TSV3 through silicon vias may constitute a third common channel CH3. The CH4a channel of the second memory layer 302 is connected to the TSV4 through silicon vias through the P4a electrode pad, and the CH4b channel of the sixth memory layer 306 is connected to the TSV4 through silicon vias through the P4b electrode pad. I can. The CH4a channel and the CH4b channel electrically connected to the TSV4 through silicon vias may constitute a fourth common channel CH2.

The CH5a channel of the third memory layer 303 may be connected to TSV5 through silicon vias through the P5a electrode pad, and the CH5b channel of the seventh memory layer 307 may be connected to TSV5 through silicon vias through the P5b electrode pad. . The CH5a channel and the CH5b channel electrically connected to the TSV5 through silicon vias may constitute a fifth common channel CH5. In addition, the CH6a channel of the third memory layer 303 is connected to the TSV6 through silicon vias through the P6a electrode pad, and the CH6b channel of the seventh memory layer 307 is connected to the TSV6 through silicon vias through the P6b electrode pad. I can. The CH6a channel and the CH6b channel electrically connected to the TSV6 through silicon vias may form a sixth common channel CH6.

The CH7a channel of the fourth memory layer 304 may be connected to the TSV7 through silicon vias through the P7a electrode pad, and the CH7b channel of the eighth memory layer 308 may be connected to the TSV7 through silicon vias through the P7b electrode pad. . The CH7a channel and the CH7b channel electrically connected to the TSV7 through silicon vias may constitute a seventh common channel CH5. In addition, the CH8a channel of the fourth memory layer 304 is connected to the TSV8 through silicon vias through the P8a electrode pad, and the CH8b channel of the eighth memory layer 308 is connected to the TSV8 through silicon vias through the P8b electrode pad. I can. The CH8a channel and the CH8b channel electrically connected to the TSV8 through silicon vias may form an eighth common channel CH8.

The first to eighth common channels CH1 to CH8 of the memory cell array 121 may be connected to the buffer die 310. In the first to eighth common channels CH1-CH8, the PIM region 122 and the normal memory region 124 separate the lower memory layers 301-304 and the upper memory layers 305-308. It may be selectively accessed by a stack identification signal (SID). For example, when the stack identification signal SID is logic "0", the lower memory layers 301-304, that is, the PIM region 122, among the first to eighth common channels CH1-CH8 are accessed. Can be. When the stack identification signal SID is a logic “1”, the upper memory layers 305-308, that is, the normal memory region 124 among the first to eighth common channels CH1-CH8 may be accessed. .

As described above with reference to FIG. 2, when the memory device 120 operates in an internal processing mode, the PIM area 122 may be accessed. In order for the memory device 120 to operate in the internal processing mode, a stack identification signal SID is included in the address ADDR received through the command/address signal lines 132 of the memory bus 130 and the stack identification is performed. The signal SID is provided as a logic "0", and the PIM mode selection signal PIM_SEL may be activated by the PIM mode selection unit 210. Upon activation of the PIM mode selection signal PIM_SEL, the memory device 120 may operate in an internal processing mode by accessing the PIM region 122.

When the memory device 120 operates in the normal mode, the normal memory area 124 may be accessed. In order for the memory device 120 to operate in the normal mode, a stack identification signal SID of logic “1” is included in the address ADDR received through the command/address signal lines 132 of the memory bus 130. Then, the PIM mode selection signal PIM_SEL may be deactivated by the PIM mode selection unit 210. When the PIM mode selection signal PIM_SEL is deactivated, the memory device 120 may access the normal memory area 124 to operate in the normal mode.

In this embodiment, the stack identification signal (SID) is a specific memory cell array 121 stored in the control register 116 of the memory controller 112 is divided into a PIM area 122 and a normal memory area 124. It can be an address. In addition, the stack identification signal SID may be a specific address used to address the PIM area 122 recognized by the PIM mode selection unit 210.

4 is a diagram illustrating a part of the structure of the memory device of FIG. 2 by way of example.

Referring to FIG. 4, compared to the memory device 120 of FIG. 3, the memory device 120a differs in that the memory cell array 121 is composed of first to fourth memory layers 301-304. There is. Hereinafter, a description of the memory device 120a that is duplicated with FIG. 3 will be omitted.

In the memory cell array 121 of the memory device 120a, the first and second memory layers 301 and 302 are allocated to the PIM area 122, and the third and fourth memory layers 303 and 304 May be allocated as the normal memory area 124. According to an embodiment, the first and second memory layers 301 and 302 are allocated to the normal memory area 124, and the third and fourth memory layers 303 and 304 are allocated to the PIM area 122. Can be.

Each of the eight channels CH1a-CH8a of the first to fourth memory layers 301-304 may be connected to the buffer die 310 through through silicon vias TSV1-TSV8. The eight channels CH1a-CH8a may be addressed by a 3-bit channel address. When the most significant bit of the channel address is "0", channels CH1a, CH2a, CH3a, and CH4a of the first and second memory layers 301 and 302 may be selected. Conversely, when the most significant bit of the channel address is "1", channels CH5a, CH6a, CH7a, and CH8a of the third and fourth memory layers 303 and 304 may be selected. As a result, the PIM area 122 and the normal memory area 124 may be selectively accessed by the most significant bit of the channel address.

The most significant bit of the channel address is a specific address that separates the memory cell array 121 of the memory device 120a from the PIM area 122 and the normal memory area 124, and is stored in the control register 116 of the memory controller 112 Can be. In addition, the most significant bit of the channel address may be a specific address used to address the PIM area 122 recognized by the PIM mode selection unit 210.

5 is a diagram illustrating a part of the structure of the memory cell array of FIG. 2.

Referring to FIG. 5, the memory cell array 121 may include, for example, eight banks BANK1-BANK8. The first to fourth banks BANK-BANK4 may be allocated to the PIM region 122, and the fifth to eighth banks BANK5-BANK8 may be allocated to the normal memory region 124. The eight banks BANK1-BANK8 may be addressed by a 3-bit bank address. When the most significant bit of the bank address is "0", the first to fourth banks BANK-BANK4 may be selected. Conversely, when the most significant bit of the bank address is "1", the fifth to eighth banks BANK5-BANK8 may be selected. As a result, the PIM area 122 and the normal memory area 124 may be selectively accessed by the most significant bit of the bank address.

The most significant bit of the bank address is a specific address that separates the memory cell array 121 from the PIM region 122 and the normal memory region 124 and may be stored in the control register 116 of the memory controller 112. In addition, the most significant bit of the bank address may be a specific address used to address the PIM area 122 recognized by the PIM mode selection unit 210.

The PIM area 122 and the normal memory area 124 described with reference to FIGS. 3 to 5 are set as fixed areas in the memory cell array 121 by a stack identification signal (SID), a channel address, or a bank address. It is exemplary. Specific address information for setting the PIM area 122 and the normal memory area 124 as a fixed area may be statically set in the control register 116 of the memory controller 112.

According to the implementation method of the present invention, the PIM area 122 and the normal memory area 124 are variable areas in the memory cell array 121 by a combination of a stack identification signal (SID), a channel address and/or a bank address. Can be set to Specific address information for setting the PIM area 122 and the normal memory area 124 to a variable area may be dynamically set in the control register 116 of the memory controller 112.

6 is a flowchart illustrating an operation of the memory device of FIG. 2.

1, 2, and 6, in step S610, the memory device 120 transmits specific address information on the PIM area 122 and the normal memory area 124 of the memory cell array 121 to the memory controller. 112). The specific address information may include a specific address that separates the memory cell array 121 from the PIM area 122 and the normal memory area 124. The specific address is an address used to address the PIM region 122 and may include, for example, a stack identification signal (SID), a channel address, and/or a bank address. Specific address information may be stored in the control register 116 of the memory controller 112.

In operation S620, the memory device 120 may receive a specific address together with the command CMD from the memory controller 112 through the command/address signal lines 132. The memory controller 112 may issue a command CMD for accessing the memory device 120 based on a memory request from the host device 110. In this case, the command CMD and a specific address may be provided through the memory PHY 114 supporting the JEDEC standard DDR and/or LPDDR protocol between the memory controller 112 and the memory device 120. For example, it is assumed that the specific address is a stack identification signal (SID), as described in FIG. 3.

In step S630, the memory device 120 may determine whether the stack identification signal SID received as a specific address along with the command CMD in step S620 addresses the PIM region 122 of the memory cell array 121. . As described in FIG. 3, when the stack identification signal SID is provided as a logic “0”, the lower memory layers 301-304 of the first to eighth common channels CH1-CH8, that is, the PIM Area 122 will be accessed. Conversely, when the stack identification signal SID is provided as a logic "1", the upper memory layers 305-308 of the first to eighth common channels CH1-CH8, that is, the normal memory area 124 Will be accessed.

When the stack identification signal SID is a logic "0", in step S640, the memory device 120 may enter an internal processing mode. The PIM mode selection unit 210 of the memory device 120 may activate the PIM mode selection signal PIM_SEL in response to the stack identification signal SID of logic “0”. By activation of the PIM mode selection signal PIM_SEL, the memory device 120 may operate in an internal processing mode.

In step S641, the memory device 120 may convert the command CMD received in step S620 into an internal processing operation command PIM_CMD. The PIM command conversion unit 126 of the memory device 120 converts the received command CMD into a type of internal processing operation, such as data search, data addition, data movement, data inversion, data shift, data swap, data comparison, Logic operations and/or data processing/operations may be converted into an internal processing operation command PIM_CMD.

In step S642, the memory device 120 may perform an internal processing operation according to the internal processing operation command PIM_CMD. The PIM engine 250 of the memory device 120 may perform an internal processing operation using the PIM region 122 of the memory cell array 121 according to the internal processing operation command PIM_CMD. The PIM engine 250 may store internal processing data, which is a processing result of an internal processing operation performed in response to the internal processing operation command PIM_CMD, in the PIM area 122. Alternatively, the PIM engine 250 may read internal processing data from the PIM area 122 in response to the internal processing operation command PIM_CMD, and perform an internal processing operation based on the read internal processing data. When the internal processing operation in step S642 is completed, the memory device 120 may move to step S620 and receive the next command CMD together with a specific address.

Meanwhile, as a result of the determination in step S630, if the stack identification signal SID is not logic “0”, in step S650, the memory device 120 may enter the normal mode. The PIM mode selection unit 210 of the memory device 120 may deactivate the PIM mode selection signal PIM_SEL in response to the stack identification signal SID of logic “1”. By deactivating the PIM mode selection signal PIM_SEL, the memory device 120 may operate in a normal mode.

In step S651, the memory device 120 may perform a data transaction operation according to the command CMD received in step S620. The command CMD may be associated with a data transaction operation performed in the normal mode. The memory device 120 stores the data DQ received from the memory controller 112 through the data lines 134 according to the command CMD in the normal memory area 124 of the memory cell array 121, and Data may be read from the normal memory area 124, and the read data may be transmitted to the memory controller 112 as data DQ through the data lines 134. When the data transaction operation in step S651 is completed, the memory device 120 may move to step S620 and receive the next command CMD together with a specific address.

7 is a timing diagram illustrating an operation of the memory device of FIG. 2. 7 shows a timing diagram operating based on a clock signal (CK) according to a DDR and/or LPDDR protocol. FIG. 7 conceptually describes a write operation and a read operation in which data DQ to/from the memory device 120 is input/output through the data lines 134 for conciseness and convenience of description. It should be noted that the timing diagrams described in the present invention are not necessarily drawn to scale.

1, 2, and 7, at a time point Ta, the memory device 120 receives a read command RD and an address ADDR including a stack identification signal SID from the memory controller 112. can do. In this case, the stack identification signal SID may be provided as a logic “0”. Although not shown in the drawing, the active command associated with the read command RD may be received from the memory controller 112 before the point Ta.

In response to a logic "0" of the stack identification signal SID at a point in time Ta, the memory device 120 may enter the internal processing mode. In the internal processing mode, the read command RD is converted into an internal processing read command by the PIM command conversion unit 126, and the PIM engine 250 converts the PIM region of the memory cell array 121 according to the internal processing read command. At 122), internal processing data written in memory cells corresponding to the address signal ADDR may be read, and an internal processing operation may be performed using the read internal processing data. In this embodiment, a case in which internal processing data read from the PIM area 122 is not transmitted to the memory controller 112 outside the memory device 120 is shown. According to another embodiment, the internal processing data processed by the PIM engine 250 may be transmitted to the memory controller 112 as data DQ through the data lines 134 of the memory bus 130.

At time Tb, the memory device 120 may receive an address ADDR including a stack identification signal SID together with a read command RD from the memory controller 112. In this case, the stack identification signal SID may be provided as a logic “1”.

In response to the logic "1" of the stack identification signal SID at the time point Tb, the memory device 120 may enter the normal mode. In the normal mode, the memory device 120 reads data D written to memory cells corresponding to the address signal ADDR from the normal memory area 124 of the memory cell array 121 according to the read command RD. Can be shipped. The read data D may be transmitted to the memory controller 112 as data DQ through the data lines 134 of the memory bus 130.

At time Tc, the memory device 120 may receive the address ADDR including the stack identification signal SID together with the write command WR from the memory controller 112. In this case, the stack identification signal SID may be provided as a logic “0”.

In response to the logic "0" of the stack identification signal SID at the time point Tc, the memory device 120 may enter the internal processing mode. In the internal processing mode, the PIM command conversion unit 126 converts the write command WR into an internal processing write command, and the PIM engine 250 performs an internal processing operation to internally process the internal processing data obtained as a result of the processing. In accordance with the write command, memory cells corresponding to the address signal ADDR may be written in the PIM area 122 of the memory cell array 121.

At time Td, the memory device 120 may receive the address ADDR including the stack identification signal SID together with the write command WR from the memory controller 112. In this case, the stack identification signal SID may be provided as a logic “1”.

In response to the logic "1" of the stack identification signal SID at the time point Td, the memory device 120 may enter the normal mode. In the normal mode, the memory device 120 may write data D into memory cells corresponding to the address signal ADDR in the normal memory area 124 of the memory cell array 121 according to the write command WR. have. In this case, the write data D may be received from the memory controller 112 as data DQ through the data lines 134 of the memory bus 130.

Timing parameter called CAS-to-CAS Delay (tCCD), which is the minimum time interval required between successive read commands between the read command RD at the time point Ta and the read command RD at the time Tb Exists. Also, between the write command WR at the time point Tc and the write command WR at the time point Td, there is a tCCD timing parameter that is the minimum time interval required between successive write commands. The tCCD time between the time Ta and the time Tb may satisfy the tCCD timing requirements specified in the DDR and/or LPDDR standards of the JEDEC standard. In addition, the tCCD time between the time Tc and the time Td may also satisfy the tCCD timing requirements specified in the DDR and/or LPDDR standards of the JEDEC standard.

A timing parameter called a read-to-write delay (tRTW) exists between the read command RD at the time point Tb and the write command WR at the time point Tc. The tRTW time between the Tb time point and the Tc time point may satisfy the tRTW timing requirements specified in the DDR and/or LPDDR standard of the JEDEC standard.

8 is a diagram illustrating a PIM mode selection unit of FIG. 2 by way of example.

Referring to FIG. 8, the PIM mode selection unit 210a is compared with the PIM mode selection unit 210 of FIG. 2, and the command CMD and the command/address signal lines 132 of the memory bus 130 are used. Instead of determining whether a specific address used to address the PIM area 122 is included in the address ADDR received together, the addresses ADDR received with the command CMD are matched with the PIM mode entry code. There is a difference in determining whether or not it is matched to the PIM mode exit code.

The PIM mode selection unit 210a may include a PIM mode entry check circuit 810, a PIM mode exit check circuit 820, and a PIM mode selection signal generation circuit 830.

The PIM mode entry check circuit 810 stores the PIM mode entry code, compares the bit values of the addresses ADDRs sequentially received by the PIM mode selection unit 210a with the bit values of the PIM mode entry code, As a result of the comparison, a PIM mode entry signal (PIM_ENTER) may be output. The PIM mode entry check circuit 810 outputs a PIM mode entry signal (PIM_ENTER) of logic "1" when the bit values of the sequential addresses ADDRs and the bit values of the PIM mode entry code match. If not, a PIM mode entry signal (PIM_ENTER) of logic "0" can be output. The PIM mode entry signal PIM_ENTER may be provided to the PIM mode selection signal generation circuit 830.

In the PIM mode entry code, for example, the bit values of the addresses corresponding to each of the sequential write commands WR are 0xFFFF, 0x1F1F, 0xAAFF, 0x0000, 0x1111, 0x4444, 0x3333, 0x0000. to-back address sequence).

The PIM mode exit check circuit 820 stores the PIM mode exit code, compares the bit values of the addresses ADDRs sequentially received by the PIM mode selection unit 210a with the bit values of the PIM mode exit code, As a result of the comparison, the PIM mode exit signal PIM_EXIT may be output. The PIM mode exit check circuit 820 outputs a PIM mode exit signal (PIM_EXIT) of logic "1" when the bit values of the sequential addresses ADDRs and the bit values of the PIM mode exit code match. If not, the PIM mode exit signal PIM_EXIT of logic “0” may be output. The PIM mode exit signal PIM_EXIT may be provided to the PIM mode selection signal generation circuit 830.

In the PIM mode escape code, for example, the bit values of the address corresponding to each of the sequential write commands WR are set in a continuous address sequence such as 0x0000, 0x2F2F, 0xFFAA, 0x0000, 0x6666, 0xF2F3, 0x2333, 0xFFFF. I can.

The PIM mode selection signal generation circuit 830 may generate a PIM mode selection signal PIM_SEL based on the PIM mode entry signal PIM_ENTER and the PIM mode exit signal PIM_EXIT. The PIM mode selection signal generation circuit 830 may activate the PIM mode selection signal PIM_SEL in response to the PIM mode entry signal PIM_ENTER of logic "1" and the PIM mode exit signal PIM_EXIT of logic "0". . By activation of the PIM mode selection signal PIM_SEL, the memory device 120 may operate in an internal processing mode.

The PIM mode selection signal generation circuit 830 may deactivate the PIM mode selection signal PIM_SEL in response to the PIM mode entry signal PIM_ENTER of logic "0" or the PIM mode exit signal PIM_EXIT of logic "1". . By deactivating the PIM mode selection signal PIM_SEL, the memory device 120 may operate in a normal mode.

The PIM mode entry code and the PIM mode exit code described with reference to FIG. 8 are exemplary, and the scope of the present invention is not limited thereto. According to the implementation method of the present invention, the PIM mode entry code and the PIM mode exit code may be variously configured. The same code values may be stored in the control register 116 of the memory controller 112 and the PIM mode selection unit 210a.

9 is a flowchart for explaining the operation of the memory device of FIG. 2.

1, 2, 8, and 9, in step S905, the memory device 120 receives an address from the memory controller 112 through the command/address signal lines 132 together with the command CMD. ADDR) can be sequentially received.

In step S911, the memory device 120 determines the bit values of the addresses ADDRs sequentially received by the PIM mode entry check circuit 810 of the PIM mode selection unit 210a and the bit values of the PIM mode entry code. The comparison is performed and, as a result of the comparison, a PIM mode entry signal PIM_ENTER may be output.

In step S912, the memory device 120 calculates the bit values of the addresses ADDRs sequentially received by the PIM mode exit check circuit 820 of the PIM mode selection unit 210a and the bit values of the PIM mode exit code. The comparison is performed, and as a result of the comparison, a PIM mode exit signal PIM_EXIT may be output.

In step S920, the memory device 120 selects the PIM mode based on the PIM mode entry signal (PIM_ENTER) and the PIM mode exit signal (PIM_EXIT) by the PIM mode selection signal generation circuit 830 of the PIM mode selection unit 210a. A signal PIM_SEL may be generated. For example, the PIM mode selection signal generation circuit 830 generates a PIM mode selection signal PIM_SEL in response to a PIM mode entry signal PIM_ENTER of logic "1" and a PIM mode exit signal PIM_EXIT of logic "0". Can be activated. The PIM mode selection signal generation circuit 830 may deactivate the PIM mode selection signal PIM_SEL in response to the PIM mode entry signal PIM_ENTER of logic "0" or the PIM mode exit signal PIM_EXIT of logic "1". .

In step S930, the memory device 120 may determine whether the PIM mode selection signal PIM_SEL generated in step S920 is in an active state.

When the PIM mode selection signal PIM_SEL is in an active state, in step S940, the memory device 120 may enter an internal processing mode.

In operation S941, the memory device 120 may convert the command CMD received in operation S920 into an internal processing operation command PIM_CMD. The PIM command conversion unit 126 of the memory device 120 converts the received command CMD into a type of internal processing operation, such as data search, data addition, data movement, data inversion, data shift, data swap, data comparison, Logic operations and/or data processing/operations may be converted into an internal processing operation command PIM_CMD.

In operation S942, the memory device 120 may perform an internal processing operation according to the internal processing operation command PIM_CMD. The PIM engine 250 of the memory device 120 may perform an internal processing operation using the PIM region 122 of the memory cell array 121 according to the internal processing operation command PIM_CMD. The PIM engine 250 may store internal processing data, which is a processing result of an internal processing operation performed in response to the internal processing operation command PIM_CMD, in the PIM area 122. Alternatively, the PIM engine 250 may read internal processing data from the PIM area 122 in response to the internal processing operation command PIM_CMD, and perform an internal processing operation based on the read internal processing data.

Meanwhile, as a result of the determination in step S930, when the PIM mode selection signal PIM_SEL is in an inactive state, in step S950, the memory device 120 may enter the normal mode.

In step S951, the memory device 120 may perform a data transaction operation according to the command CMD received in step S905. The command CMD may be associated with a data transaction operation performed in the normal mode. The memory device 120 stores the data DQ received from the memory controller 112 through the data lines 134 according to the command CMD in the normal memory area 124 of the memory cell array 121, and The data DQ may be read from the normal memory area 124, and the read data may be transmitted to the memory controller 112 as data DQ through the data lines 134.

Although the present disclosure has been described with reference to the embodiment shown in the side, this is only exemplary, and those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

In the memory device,
A memory cell array including a first memory area and a second memory area;
Command/address signal lines for receiving commands and addresses from outside the memory device;
An internal processing mode selection unit, configured to generate a processing mode selection signal for controlling an operation mode of the memory device to enter an internal processing mode based on an address received with the command;
An internal processing command conversion unit configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal; And
And an internal processor configured to perform an internal processing operation by accessing the first memory area in response to the internal processing operation command in the internal processing mode. The method of claim 1,
And the command/address signal lines are connected to a memory physical layer interface supporting a double data rate (DDR) or a low power double data rate (LPDDR) protocol external to the memory device. The method of claim 1,
Wherein the internal processing mode selection unit generates the processing mode selection signal in response to a specific address that separates the first and second memory areas included in the address received together with the command. . The method of claim 3,
The memory cell array includes stacked memory layers,
The stacked memory layers constitute common channels through through silicon vias and electrode pads electrically interconnected with the through silicon vias, and the stacked memory layers belonging to the first memory region in the common channels And the stacked memory layers belonging to the second memory area are selectively accessed by a stack identification signal,
And the specific address is configured with the stack identification signal for accessing the stacked memory layers belonging to the first memory area. The method of claim 3,
The memory cell array includes stacked memory layers,
The stacked memory layers constitute channels through through silicon vias, and in the channels, the stacked memory layers belonging to the first memory region and the stacked memory layers belonging to the second memory region are at channel addresses. Selectively accessed by
And the specific address is composed of the channel address for accessing the stacked memory layers belonging to the first memory area. The method of claim 3,
The memory cell array includes a plurality of banks,
Among the plurality of banks, banks belonging to the first memory region and banks belonging to the second memory region are selectively accessed by a bank address,
And the specific address is constituted by the bank address for accessing the banks belonging to the first memory area. The method of claim 3,
And the first memory area and the second memory area are set as fixed areas by the specific address. The method of claim 3,
And the first memory area and the second memory area are set as variable areas according to the specific address. The method of claim 1,
The memory device sequentially receives a first command through the command/address signal lines, sequentially receives addresses corresponding to each of the sequential first commands,
And the internal processing mode selection unit determines whether sequential addresses match an internal processing mode entry code and an internal processing mode exit code, and generates the processing mode selection signal based on a determination result. The method of claim 9,
Wherein the internal processing mode selection unit activates the processing mode selection signal when the sequential addresses match the internal processing mode entry code and the sequential addresses do not match the internal processing mode exit code. . The method of claim 9,
The internal processing mode selection unit performs the processing so that the operation mode of the memory device enters the normal mode when the sequential addresses do not match the internal processing mode entry code or when the sequential addresses match the internal processing mode exit code. A memory device comprising inactivating a mode selection signal. A method of operating a memory device including a memory cell array including a first memory area and a second memory area and an internal processor performing an internal processing operation,
Receiving a command and an address from outside the memory device through a predetermined protocol interface;
Generating a processing mode selection signal for controlling an operation mode of the memory device to enter an internal processing mode based on an address received with the command;
In response to activation of the internal processing mode selection signal, converting the received command into an internal processing operation command; And
And performing an internal processing operation by accessing the first memory area of the memory cell array in response to the internal processing operation command in the internal processing mode. The method of claim 12,
The predetermined protocol interface is a memory physical layer interface supporting a double data rate (DDR) or a low power double data rate (LPDDR) protocol. The method of claim 12, wherein the generating a processing mode selection signal for controlling an operation mode of the memory device to enter the internal processing mode based on the address received with the command comprises:
Determining whether the address received with the command includes a specific address that distinguishes the first and second memory areas; And
Activating the internal processing mode selection signal when the specific address is included in the address received with the command; And
And deactivating the processing mode selection signal when the specific address is not included in the address received with the command. The method of claim 12, wherein the generating a processing mode selection signal for controlling an operation mode of the memory device to enter the internal processing mode based on the address received with the command comprises:
Sequentially receiving a first command through the predetermined protocol interface;
Sequentially receiving addresses in response to each of the sequential first commands through the predetermined protocol interface;
Determining whether the sequential addresses match an internal processing mode entry code and an internal processing mode exit code; And
And generating the processing mode selection signal based on a result of the determination. The method of claim 15, wherein generating the processing mode selection signal based on the determination result comprises:
Activating the processing mode selection signal when the sequential addresses match the internal processing mode entry code and the sequential addresses do not match the internal processing mode exit code; And
And inactivating the processing mode selection signal when the sequential addresses do not match the internal processing mode entry code or when the sequential addresses match the internal processing mode exit code. Memory device; And
A memory controller that controls the memory device using a predetermined protocol interface connected to the memory device,
The memory device,
A memory cell array including a first memory area and a second memory area;
To generate a processing mode selection signal for receiving a command and an address from the memory controller through the predetermined protocol interface, and controlling an operation mode of the memory device to enter an internal processing mode based on an address received with the command. An internal processing mode selection unit configured;
An internal processing command conversion unit configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal; And
And an internal processor performing an internal processing operation by accessing the first memory area in response to the internal processing operation command in the internal processing mode. The method of claim 17,
The predetermined protocol interface is a memory physical layer interface supporting a double data rate (DDR) or a low power double data rate (LPDDR) protocol. The method of claim 17,
And the internal processing mode selection unit generates the processing mode selection signal in response to a specific address that separates the first and second memory areas included in an address received with the command. The method of claim 17,
The memory device sequentially receives a first command through the command/address signal lines, sequentially receives addresses corresponding to each of the sequential first commands,
And the internal processing mode selection unit determines whether sequential addresses match an internal processing mode entry code and an internal processing mode exit code, and generates the processing mode selection signal based on a determination result.

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