KR20200107189A - Apparatus and method of qprbs checker for pam-4 - Google Patents

Abstract

Embodiments may provide a technique for effectively verifying whether a test data pattern transmitted in pulse amplitude modulation-4 (PAM-4) scheme is normally operated. A quaternary pseudo random binary sequence (QPRBS) checker device for PAM-4 and a method thereof are disclosed. According to an embodiment of the present invention, a QPRBS checker device comprises: a PRBS checker which performs a check operation on a QPRBSp signal in response to an EN signal; a determiner for determining whether the output of the PRBS checker is normal, and generating an Err signal including at least one of total error information, no error information, and partial error information based on the determination result; and an error detector which detects whether an error has occurred in the QPRBSp signal in response to the Err signal.

Description

QPRBS checker device and method for PAM-4 {APPARATUS AND METHOD OF QPRBS CHECKER FOR PAM-4}

The following embodiments relate to an apparatus and method for a QPRBS checker for PAM-4.

PAM-4 (Pulse Amplitude Modulation-4) is a modulation method used for high-speed transmission in the physical layer, and maps one symbol per 2 bits, and each symbol has four signal levels (e.g., -3, -1). , +1, +3). The modulation of the PAM-4 method enables high-speed serial transmission even at 28 Gbps or more compared to the non-return to zero (NRZ) method, which is a method that has been widely used in conventional data transmission.

At this time, among the methods of checking or verifying the correct data transmission over the high-speed communication link, the transmitting end transmits the test pattern by using the already known data string as the test pattern, and transmits after checking whether it matches the data pattern received at the receiving end. There is a way to verify that it was done correctly without this error. This test method can be used to determine the influence of factors that can cause errors such as channel loss and intersymbol interference. In general, the test pattern mainly used in the test for NRZ data transmission is PRBS (Pseudo Random Binary Sequence), while one of the main test patterns additionally used in addition to PRBS in the test for PAM-4 data transmission is QPRBS.

QPRBS, one of the test patterns for PAM-4, is defined in IEEE 802.3bj (100Gbase-KP4) Section 94 (Clause 94), which is a standard specified by the IEEE, and is named “QPRBS13” in the standard. QPRBS13 refers to the “Quaternary PRBS13” pattern, which repeats a sequence of 8191 symbols. Each test pattern is a pattern generated by encoding from the pattern generator corresponding to PRBS13. In the first cycle, a non-inverted data pattern of PRBS13 is generated, and in the second cycle, the inverted data pattern of PRBS13 is generated. Is created. Here, PRBS13 refers to a data pattern generated with a length of 213-1 in the PRBS data pattern.

In general, the generation and check methods of PRBS data patterns widely used for testing in NRZ data transmission can be classified into two types.

One is the case of setting in advance when transmitting and receiving an initial value to generate and check a data pattern. At this time, the test pattern corresponding to the initial value is called a seed, and the sequence of the next data pattern is determined by the determined seed. Therefore, there are various data pattern methods for transmission by various seeds, and error-free data by searching for a predetermined seed for the received data, and checking whether the sequence is sequentially received in a predetermined data pattern from the received data at the time of the search. There is a method of checking whether to transmit.

Another method is to check whether the data has been transmitted with the correct sequence by considering the sequential association of consecutively received data patterns even if the receiving end does not know the seed.

Embodiments may provide a technique for effectively verifying whether a test data pattern transmitted in a PAM-4 modulation scheme is normally operated.

Embodiments may provide a technique for performing a function of checking a QPRBS data pattern without a seed.

A QPRBS checker according to an embodiment is a PRBS checker that performs a check operation on a QPRBSp signal in response to an EN signal, and determines whether the output of the PRBS checker is a settlement, and based on the determination result, Total Error information, No Error And a determiner for generating an Err signal including at least one of information and partial error information, and an error detector for detecting whether an error has occurred in the QPRBSp signal in response to the Err signal.

1A is a diagram for describing an example of a method of generating and checking a PRBS data pattern.
1B is a diagram illustrating another example of a method of generating and checking a PRBS data pattern.
2A shows an example of a QPRBS generator.
2B shows an example of a QPRBS checker.
3 shows a communication system according to an embodiment.
4A shows a schematic block diagram of the QPRBS generator shown in FIG. 3.
4B shows a timing diagram of the QPRBS generator shown in FIG. 3.
5A shows a schematic block diagram of the QPRBS checker shown in FIG. 3.
5B shows a timing diagram of the QPRBS checker shown in FIG. 3.
6 is a view for explaining the operation of the operator shown in FIG. 5A.
7 is a diagram for explaining logic for generating a polarity signal by the PRBS controller shown in FIG. 5A.
FIG. 8 is a diagram illustrating an operation of generating an err signal by the determiner shown in FIG. 5A.
9 is a diagram for explaining a timing diagram of generating an Err signal.
FIG. 10 is a flowchart illustrating an operation of the FSM (Finite State Machine) of the error detector shown in FIG. 5A.
11 is a diagram for describing a case in which an error occurs in some bit strings in a QPRBS data pattern.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. However, since various changes may be made to the embodiments, the scope of the rights of the patent application is not limited or limited by these embodiments. It should be understood that all changes, equivalents, or substitutes to the embodiments are included in the scope of the rights.

The terms used in the examples are used for illustrative purposes only and should not be interpreted as limiting. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present specification, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, but one or more other features. It is to be understood that the presence or addition of elements or numbers, steps, actions, components, parts, or combinations thereof, does not preclude in advance.

Terms such as first or second may be used to describe various components, but the components should not be limited by terms. The terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of rights according to the concept of the embodiment, the first component may be named as the second component, and similarly The second component may also be referred to as a first component.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiment belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. Does not.

In addition, in the description with reference to the accompanying drawings, the same reference numerals are assigned to the same components regardless of the reference numerals, and redundant descriptions thereof will be omitted. In describing the embodiments, when it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the embodiments, the detailed description thereof will be omitted.

1A is a diagram for describing an example of a method of generating and checking a PRBS data pattern.

1A corresponds to Synchronous PRBS among methods of generating and checking a PRBS data pattern. This is also referred to as PRBS in a form called “additive” scrambler method. Or, it represents the Synchronous PRBS method. This is because a pseudo-random noise (PN) sequence is added to the input signal while modulo-2 is processed. Therefore, in generating the PN sequence, the sequence of the transmitter and the receiver must be synchronized. In this method, there is a precondition that the seed of the PN sequence must already share the same value between the transmitter and receiver.

1B is a diagram illustrating another example of a method of generating and checking a PRBS data pattern. In some cases, the receiving end does not know or shares the seed of the data pattern generated by the transmitting end, so it is necessary to operate according to the input of the continuously received PN sequence.In this case, the PRBS of the receiving unit without external information or a previously determined seed The checker needs to be synchronized to the PN sequence. 2 corresponds to Self-Synchronous PRBS among the methods of generating and checking a PRBS data pattern. The Self-Synchronous PRBS method creates and checks PRBS using a self-synchronous method, and is also called a multiplicative method. This is especially because the input signal operates by multiplication or division of polynomials.

2A shows an example of a QPRBS generator, and FIG. 2B shows an example of a QPRBS checker.

2A, the QPRBS generator 100 performs a method of generating a QPRBS pattern by performing Bitwise XOR operation on the PRBS pattern generated by the PRBS generator 10 and the Mask value generated by the Mask generator 110. do.

As shown in FIG. 2B, the QPRBS checker 200 includes a QPRBS generator 100, an error masking circuit 217, and an FSM controller 220 for logic control. The QPRBS checker 200 compares the pattern generated by the QPRBS generator 100 including the seed and the received data, but when it reaches a certain pattern length, sets a non-inverted or inverted value of the received data as an initial value as a seed, The QPRBS generator 100 outputs the non-inverted PRBS data pattern and the inverted PRBS data pattern, and compares it with the received data.

The above-described technique has been described by employing a synchronous pattern generation and check method requiring a seed.

In the case of the self-synchronous method, since the seed is not used, it is difficult to operate the checker normally with the existing technology. Hereinafter, a QPRBS verification apparatus and method for determining whether a QPRBS data pattern is correctly received when a QPRBS data pattern is received based on the Self-Synchronous method according to an embodiment will be described.

3 shows a communication system according to an embodiment.

The communication system 30 includes a transmitting device 300A and a receiving device 300B. The transmitting device 300A includes a QPRBS generator 400 and a transmitter 310, and the receiving device 300B includes a receiver 330 and a QPRBS checker 500.

The QPRBS generator 400 of the transmission device 300A may generate a QPRBS test pattern (eg, a QPRBS test pattern for PAM-4). The transmitter 310 of the transmitting device 300A may transmit the QPRBS test pattern to the receiving device 300B through a communication link.

The receiver 330 of the receiving device 300B may receive the QPRBS test pattern through a communication link. The self-synchronous (or multicative) PRBS checker 500 may check whether a QPRBS test pattern is normally received and detect an error.

4A shows a schematic block diagram of the QPRBS generator shown in FIG. 3, and FIG. 4B shows a timing diagram of the QPRBS generator shown in FIG. 3.

The QPRBS generator 400 includes a PRBS generator 410, a PRBS controller 430, and an XOR operator 450.

The PRBS generator 410 may be driven in a Self-Synchronous manner. The PRBS generator 410 may start generating the PN sequence in response to the EN signal. For example, when the EN signal is activated to '1', the PRBS generator 410 may generate a PN sequence. The PRBS generator 410 may output the generated PN sequence to the XOR operator 450. The output value of the generated PN sequence corresponds to PRBSn. Here, PRBSn may mean a PN sequence of 2n-1 length.

The PRBS controller 430 may include a counter 435. The PRBS controller 430 may operate the counter 435. The operating counter 435 may repeatedly generate values of '1' and '0' for every 2n-1 period of polarity, and may output the generated polarity value to the XOR operator 450.

The XOR operator 450 may generate a QPRBS output pattern through an XOR operation on the polarity value and the PN sequence PRBSn.

The XOR operator 450 may periodically generate a PRBSn or PRBSn# pattern repeatedly. Here, PRBSn# may mean that each bit of a 2n-1 length PN sequence has an inverted value. For example, PRBSn is '010010... If it has a data pattern of', PRBSn# has a value in which each bit is inverted, so that '101101... It can have a data pattern of'.

FIG. 5A shows a schematic block diagram of the QPRBS checker shown in FIG. 3, and FIG. 5B shows a timing diagram of the QPRBS checker shown in FIG. 3.

The QPRBS checker 500 includes a calculator 505, a PRBS checker 510, a PRBS controller 530, a determiner 550, and an error detector 570.

Like the PRBS generator 410, the PRBS checker 510 may be driven in a Self-Synchronous manner. The PRBS checker 510 may start a check operation in response to an EN signal.

In response to the clock signal, the PRBS controller 530 may repeatedly generate values of '1' and '0' periodically for each clock with a polarity value together with the EN signal.

The operator 505 may generate a QPRBSp signal by performing an XOR operation on the polarity value generated by the PRBS controller 530 with a QPRBS signal as input data. The QPRBS signal may be a data pattern in which a PRBSn signal having a length of 2n-1 and a PRBSn# signal having a length of 2n-1 are periodically repeated. The PRBSn# signal represents an inverted PRBSn data pattern of the PRBSn signal. A polarity signal whose value is periodically changed for each clock and a QPRBSp signal, which is an output value obtained by performing an XOR operation, may periodically repeat the prbs data pattern and the prbs# data pattern for each clock. Here, prbs is a pattern that occurs during one clock cycle among the PRBSn data patterns, and may correspond to one of patterns having a length of 2n-1. Also, prbs# may correspond to an inverted value for each bit of prbs.

Like the PRBS generator 410, the PRBS checker 510 may be driven in a Self-Synchronous manner. The PRBS checker 510 may start a check operation in response to an EN signal. The PRBS checker 510 receiving the QPRBSp signal may generate an error for all bit strings in succession because the prbs data and the prbs# data are periodically repeated. In the case of the self-synchronous PRBS checker 510, if the previous input data and the current input data pattern have a normal input sequence, there is no error, but if the previous input data and the current input data have an inversion relationship, an error occurs. do. Therefore, errors may occur continuously for a length of 2n-1. However, in the first start data pattern of PRBSn# in the QPRBS signal, since the previous input data and the current input data have a non-inverted relationship, an error does not occur and can be recognized as a normal input sequence.

The determiner 550 may determine whether the output of the PRBS checker 510 is normal, and may generate an Err signal. The determiner 550 may output an Err signal to the error detector 570. For example, the Err signal may include Total Error, No Error, or Partial Error.

The information on the Err signal is defined as "Total Error" when all bit strings are errors for the input of the PRBS checker 510, and "Partial Error" when some bit strings are errors, and all bits are The case where the heat is normal without error can be defined as “No Error”.

5A shows that the determiner 550 is implemented outside the PRBS checker 510, but is not limited thereto, and the determiner 550 is implemented inside the PRBS checker 510 according to an embodiment Can be.

The error detector 570 may receive an Err signal and determine that it is in normal operation in the case of “Total Error” and in the case of “No Error”, and may determine that an error has occurred with respect to “Partial Error”.

6 is a view for explaining the operation of the operator shown in FIG. 5A.

The operator 505 may generate a QPRBS signal as a QPRBSp signal. The QPRBS signal is a signal having a data width of W, and the operator 505 may perform a function of inverting or non-inverting the QPRBS signal data bit by bit by receiving a signal corresponding to polarity for each data bit.

For example, when the polarity signal is '1', the operator 505 may output inverted values to signal values corresponding to the QPRBS data bit sequence. When the polarity signal is '0', the operator 505 may output the same value as the signal value corresponding to the QPRBS data bit string.

7 is a diagram for explaining logic for generating a polarity signal by the PRBS controller shown in FIG. 5A.

The PRBS controller 530 may include a flip-flop 533 and an inverter 535. The polarity signal may perform a function of periodically inverting the polarity signal every clock after the EN signal for enabling the PRBS checker 510 is activated. After all, it operates like a signal that divides the clock signal period by 1/2.

FIG. 8 is a diagram illustrating an operation of generating an err signal by the determiner shown in FIG. 5A.

The determiner 550 may determine whether the output of the PRBS checker 510 is normal, and may generate an Err signal. The PRBS checker 510 may have an input data width W and output a value of '0' when it is normal and output a value of '1' at the position of a corresponding bit when there is an error depending on whether or not the input sequences are in error.

For a sequence having a data width W input to QPRBSp, as shown in FIG. 5B, when the prbs pattern and the prbs# pattern are repeated every clock, the output value (or result value) of the PRBS checker 510 is W For a bit string of width, all bit strings have a value of '1' because all bit strings are errors. In this case, for data of W width, the determiner 550 performs an AND operation on the result value of W width because all bits are in an error state ('1') to generate an Err signal including'Total Error'. Can be generated.

On the other hand, at the interface between PRBSn and PRBSn#, the QPRBSp signal corresponds to the case where the prbs pattern or the prbs# pattern is continuous and there is no error, so all the W-width checker result values have a value of '0'. In this case, for data of W width, the determiner 550 may generate an Err signal including'No Error' by performing a NOR operation because all bits of the Err signal are in a normal state ('0'). .

In addition, when an error occurs in some bits of the prbs pattern or prbs# pattern during transmission, an error ('1') occurs in the corresponding bit, and therefore, both Total Error and No Error have a value of '0'. In this case, for data having a width of W, the determiner 550 may generate an Err signal including'Partial Error' by performing a NOR operation of total error and no error values.

9 is a diagram for explaining a timing diagram of generating an Err signal.

For each clock in which the PRBS signal data is input to the PRBS checker 510, the PRBS checker 510 processes the previous input data and the current input data, and outputs an Err signal as '0' in the case of a valid PRBS pattern in a normal order, and For data, when the current input data has an abnormal sequence that is not valid or has an abnormal data pattern value, an Err signal can be output as '1'.

As shown in (a) of FIG. 9, when the pattern generated for each clock of the PRBS signal data is indicated as prbs and the inverted pattern in bit units is indicated as prbs#, when the prbs value continues every clock, the normal data pattern Because of this, the Err signal maintains the '0' value.

However, as shown in (b) of FIG. 9, when the value of prbs is maintained and then converted to the value of prbs#, and when the value of prbs# is maintained and then converted to the value of prbs, the Err signal transitions to a value of '1'. Is done.

In this operating situation, as shown in (c) of FIG. 9, when the QPRBSp signal data is input, the QPRBSp signal data periodically repeats the prbs data pattern and the prbs# data pattern every clock. In this case, the PRBS checker Reference numeral 510 outputs '1' as a result of the Err signal as the current input data pattern is an abnormal pattern every time with respect to the previous input data.

The QPRBS signal data is changed from the prbs data pattern to the prbs# data pattern at the boundary point because the prbs# data pattern is input after all the PRBS data patterns are input. The length of the PRBS pattern is 2^N-1, and since the polarity signal is inverted every clock, the prbs# data pattern is continuously input as described in FIG. 9 at the boundary point. Therefore, in this case, the Err signal has a normal order and a value of '0' is output.

FIG. 10 is a flowchart illustrating an operation of the FSM (Finite State Machine) of the error detector shown in FIG. 5A.

The information on the Err signal is defined as "Total Error" when all bit strings are errors for the input of the PRBS checker 510, and "Partial Error" when some bit strings are errors, and all bits are The case where the heat is normal without error can be defined as “No Error”.

The error detector 570 initially waits in the WAIT state while waiting for input of the data pattern. After the data is input, the initial data is'Total Error' in which an error occurs in the entire bit string because there is no existing input PRBS data pattern, and at this time, the status of the error detector 570 is DATA_Compare. Transition to state. On the other hand, when'Partial Error' or'No Error' is input, the state of the error detector 570 maintains the WAIT state.

In the DATA_compare state, when'Total Error' is output by comparing the current data pattern input to the previous data pattern, the state of the error detector 570 maintains the current state, and when'No Error' is output, the error detector 570 The state of is transitioned to the Inversion state, and when'Partial Error' is output, the state of the error detector 570 transitions back to the WAIT state. Therefore, when the current input data pattern and the previous input data pattern are compared and the prbs pattern and the prbs# pattern are respectively input, a'Total Error' occurs and a normal pattern is input, so the status of the error detector 570 continues to be in the DATA_compare state. Keep it.

On the other hand, when the current input data pattern and the previous input data pattern are compared and the prbs pattern and the prbs pattern are respectively input,'No Error' occurs, and it is the time when the PRBS pattern and PRBS# pattern are changed in the QPRBS data pattern. 570) transitions to the Inversion state.

The Inversion state, which is the time when the QPRBS data pattern is changed from the PRBS pattern to the PRBS# pattern or from the PRBS# pattern to the PRBS pattern, exists only for one clock cycle. Therefore, when'Total Error' is output, the state of the error detector 570 transitions back to the DATA_compare state, whereas when'No Error' or'Partial Error' occurs, the state of the error detector 570 returns to the WAIT state. It makes a transition.

11 is a diagram for describing a case in which an error occurs in some bit strings in a QPRBS data pattern.

QPRBSp data repeats the non-inverted prbs pattern and the inverted prbs# pattern every clock. In the case of transmission due to an error in some of the data bit strings, like the prbs# pattern (1120) in the middle, the prbs# pattern A'Partial Error' signal 1140 corresponding to some errors in the Err signal is generated by the determiner 550 between the 1120 and the previous prbs pattern 1110.

In addition, between the prbs# pattern 1120 and the next prbs pattern 1130, a'Partial Error' signal 1140 corresponding to a partial error in the Err signal is generated by the determiner 550.

Accordingly, a'Partial Error' signal 1140 is generated during two clock cycles, and the WAIT state 1150 is maintained for two clock cycles as shown in FIG. 10. Accordingly, when the'Partial Error' signal 1140 occurs in the WAIT state 1150, an error occurs in a part of the data pattern, and the error detector 570 detects this as an error.

'Total Error' and'Partial Error' shown in FIGS. 10 and 11 may be described as follows. For example, if the current data pattern is '0101' and the previous data pattern is '1010' for 4-bit columns of data received by the determiner 550, the operation result of the determiner 550 by the two is Since both the previous bit stream and the current bit stream have '1' by bitwise XOR operation, they are equivalent to'Total Error'. On the other hand, if the current data pattern is '0101' and the previous data pattern is '1011', the operation result of the determiner 550 by the two is bitwise XOR operation result, the first three have '1' and the last is '0. Becomes'and the result is '1110'. Therefore, in this case, it corresponds to'Partial Error'.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the embodiment, or may be known and usable to those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. -A hardware device specially configured to store and execute program instructions such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of the program instructions include not only machine language codes such as those produced by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operation of the embodiment, and vice versa.

The software may include a computer program, code, instructions, or a combination of one or more of these, configuring the processing unit to behave as desired or processed independently or collectively. You can command the device. Software and/or data may be interpreted by a processing device or to provide instructions or data to a processing device, of any type of machine, component, physical device, virtual equipment, computer storage medium or device. , Or may be permanently or temporarily embodyed in a transmitted signal wave. The software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

As described above, although the embodiments have been described by the limited drawings, a person of ordinary skill in the art can apply various technical modifications and variations based on the above. For example, the described techniques are performed in a different order from the described method, and/or components such as a system, structure, device, circuit, etc. described are combined or combined in a form different from the described method, or other components Alternatively, even if substituted or substituted by an equivalent, an appropriate result can be achieved.

Therefore, other implementations, other embodiments and claims and equivalents fall within the scope of the following claims.

Claims (1)

A PRBS checker for performing a check operation on a QPRBSp signal in response to an EN signal;
A determiner for determining whether an output of the PRBS checker is a settlement, and generating an Err signal including at least one of total error information, no error information, and partial error information based on the determination result; And
Error detector that detects whether an error has occurred in the QPRBSp signal in response to the Err signal
QPRBS checker comprising a.

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