KR20200106888A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

A semiconductor device having a large ON current is provided. The first oxide, the second oxide on the first oxide, the third oxide on the second oxide, the first insulator on the third oxide, the conductor on the first insulator, and the top surface of the second oxide. A part, a part of the side surface of the second oxide, and a second insulator in contact with a part of the side surface of the third oxide, the third insulator on the second insulator, the upper surface of the third oxide, the upper surface of the first insulator, the conductor It has an upper surface and a fourth insulator in contact with the upper surface of the third insulator, the second oxide has a first region, a second region, and a third region positioned between the first region and the second region, and the conductor It is provided above the third region so as to overlap with the third region, a part of the third oxide and a part of the first insulator are provided between the side of the conductor and the side of the third insulator, and the second insulator is the first region and the second insulator. A semiconductor device in contact with two regions.

Description

Semiconductor device and manufacturing method of semiconductor device

One embodiment of the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. Alternatively, one embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

In addition, in this specification and the like, a semiconductor device refers to an entire device capable of functioning using semiconductor properties. In addition to semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are one form of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc. may be said to have semiconductor devices. .

In addition, one embodiment of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

Silicon-based semiconductor materials are widely known as semiconductor thin films that can be applied to transistors, but oxide semiconductors are attracting attention as other materials. As oxide semiconductors, not only oxides of single-component metals such as indium oxide and zinc oxide, but also oxides of multi-component metals are known. Among the oxides of multi-component metals, studies on In-Ga-Zn oxide (hereinafter, also referred to as IGZO) are actively being conducted.

By research on IGZO, a c-axis aligned crystalline (CAAC) structure and a nanocrystalline (nc) structure have been discovered in oxide semiconductors that are neither single crystal nor amorphous (see Non-Patent Documents 1 to 3). In Non-Patent Literature 1 and Non-Patent Literature 2, a technique for fabricating a transistor using an oxide semiconductor having a CAAC structure is also disclosed. Further, it is shown in Non-Patent Document 4 and Non-Patent Document 5 that even if the oxide semiconductor has a lower crystallinity than the CAAC structure and the nc structure, it has microscopic crystals.

Further, a transistor using IGZO as an active layer has a very low off-current (see Non-Patent Document 6), and LSI and displays using the characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8).

S. Yamazaki et al., "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, pp.183-186 S. Yamazaki et al., "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 S. Ito et al., "The Proceedings of AM-FPD'13 Digest of Technical Papers", 2013, pp.151-154 S. Yamazaki et al., "ECS Journal of Solid State Science and Technology", 2014, volume 3, issue 9, p.Q3012-Q3022 S. Yamazaki, "ECS Transactions", 2014, volume 64, issue 10, pp.155-164 K. Kato et al., "Japanese Journal of Applied Physics", 2012, volume 51, p.021201-1-021201-7 S. Matsuda et al., "2015 Symposium on VLSI Technology Digest of Technical Papers", 2015, p.T216-T217 S. Amano et al., "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, pp.626-629

One aspect of the present invention is to provide a semiconductor device having a large ON current. Alternatively, one aspect of the present invention is to provide a semiconductor device having a high frequency characteristic as one of the problems. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of the present invention is to provide a semiconductor device capable of miniaturization or high integration. Another object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. Alternatively, one embodiment of the present invention makes it one of the problems to provide a semiconductor device with high productivity.

One aspect of the invention is to provide a semiconductor device capable of holding data for a long period of time. One of the objects of the present invention is to provide a semiconductor device having a high data recording speed. One aspect of the present invention is to provide a semiconductor device with a high degree of design freedom. One aspect of the present invention is to provide a semiconductor device capable of suppressing power consumption. One aspect of the present invention makes it one of the problems to provide a novel semiconductor device.

In addition, description of these issues does not hinder the existence of other issues. In addition, it is assumed that one embodiment of the present invention does not need to solve all of these problems. In addition, the problems other than these are naturally apparent from the description of the specification, drawings, claims, and the like, and other problems can be extracted from the description of the specification, drawings, claims, and the like.

One aspect of the present invention is a first oxide, a second oxide on the first oxide, a third oxide on the second oxide, a first insulator on the third oxide, a conductor on the first insulator, A second insulator in contact with a part of the top surface of the second oxide, a part of the side surface of the second oxide, and a part of the side surface of the third oxide, a third insulator over the second insulator, the top surface of the third oxide, and the first insulator And a fourth insulator in contact with the upper surface of the conductor, the upper surface of the third insulator, and the second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. And, the resistance of the first region and the second region is lower than that of the third region, the conductor is provided above the third region so as to overlap the third region, and a part of the third oxide and a part of the first insulator It is provided between the side surface of the conductor and the side surface of the third insulator, and the second insulator is a semiconductor device in contact with the first region and the second region.

In the above, it is preferable that the first region and the second region contain one of phosphorus and boron.

In the above, it is preferable that the first region and the second region have more oxygen vacancies than the third region.

In the above, it is preferable that the first region and the second region have more hydrogen than the third region.

In the above, it is preferable that the third oxide overlaps a part of the first region and a part of the second region.

According to one embodiment of the present invention, a semiconductor device having a large ON current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high reliability can be provided. Alternatively, a semiconductor device capable of miniaturization or high integration can be provided according to one embodiment of the present invention. Alternatively, according to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high productivity can be provided.

Alternatively, a semiconductor device capable of holding data for a long period of time can be provided. Alternatively, a semiconductor device having a high data recording speed can be provided. Alternatively, a semiconductor device having a high degree of design freedom can be provided. Alternatively, a semiconductor device capable of suppressing power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

In addition, description of these effects does not interfere with the existence of other effects. In addition, one embodiment of the present invention does not have to have all of these effects. In addition, effects other than these will become apparent from the description of the specification, drawings, claims, and the like, and other effects can be extracted from the description of the specification, drawings, and claims.

1 is a top view and a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
3 is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
4 is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
5 is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
6 is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
7 is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
8 is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
9 is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
10 is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
11 is a cross-sectional view showing a configuration of a storage device according to an embodiment of the present invention.
12 is a cross-sectional view showing a configuration of a storage device according to an embodiment of the present invention.
13 is a block diagram and perspective view showing a configuration example of a memory device according to an embodiment of the present invention.
14 is a circuit diagram showing a configuration example of a memory device according to an embodiment of the present invention.
15 is a schematic diagram of a semiconductor device according to an embodiment of the present invention.
16 is a schematic diagram of a storage device according to an embodiment of the present invention.
17 is a diagram showing an electronic device according to an embodiment of the present invention.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments may be implemented in many different forms, and it may be easily understood by those of ordinary skill in the art that the form and details may be variously changed without departing from the spirit and scope. Therefore, the present invention is not interpreted as being limited to the description of the following embodiments.

In addition, in the drawings, the size, the thickness of the layer, or the region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. In addition, since the drawings schematically show an ideal example, the shape or value shown in the drawings is not limited. For example, in an actual manufacturing process, a layer or a resist mask may be unintentionally reduced by a treatment such as etching, but there are cases that this is not reflected in the drawings for easier understanding. In addition, in the drawings, the same reference numerals are used in common among different drawings for the same part or parts having the same function, and a repetitive description thereof may be omitted. In addition, in the case of indicating a portion having the same function, the hatch pattern is made the same, and there is a case where no special reference numeral is given.

In addition, in particular in a top view (also referred to as a'plan view') or a perspective view, description of some constituent elements may be omitted in order to facilitate understanding of the invention. In addition, description of some hidden lines or the like may be omitted.

In addition, ordinal numbers such as'first' and'second' in this specification and the like are used for convenience and do not indicate a process order or a stacking order. Therefore, for example,'first' may be appropriately substituted with'second' or'third', and the like can be described. In addition, the ordinal numbers described in this specification and the like may not coincide with the ordinal numbers used to specify one embodiment of the present invention.

In addition, in this specification and the like, words indicating an arrangement such as'above' and'below' are used for convenience in order to describe the positional relationship between the components with reference to the drawings. In addition, the positional relationship between the configurations is appropriately changed according to the direction in which each configuration is described. Therefore, it is not limited to the words described in the specification, and may be appropriately expressed according to circumstances.

For example, in this specification and the like, when it is explicitly stated that X and Y are connected, when X and Y are directly connected, when X and Y are electrically connected, and X and It is assumed that the case where Y is functionally connected is disclosed in this specification or the like. Therefore, it is assumed that a predetermined connection relationship is not limited to, for example, a connection relationship shown in a drawing or a sentence, and anything other than the connection relationship shown in a drawing or a sentence is described in the drawing or sentence.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

In addition, the function of the source and the drain may change when transistors of different polarities are employed, when the direction of current changes in circuit operation, and the like. Therefore, in this specification or the like, the terms of source and drain may be used interchangeably.

In addition, in this specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter, also referred to as'effective channel width') and the channel width shown in the top view of the transistor (hereinafter,'appearance channel width') Also referred to as'width') may be different. For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width is apparently larger than the channel width, and the influence cannot be ignored in some cases. For example, in a transistor that is fine and has a gate electrode covering the side surface of the semiconductor, the ratio of the channel formation regions formed on the side surface of the semiconductor may increase. In this case, the effective channel width is apparently larger than the channel width.

In this case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from a set value, it is necessary to assume that the shape of the semiconductor is known in advance. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

In the present specification, when simply described as the channel width, it may refer to the channel width in appearance. Alternatively, in the case of simply describing the channel width in the present specification, it may indicate an effective channel width. Further, the channel length, the channel width, the effective channel width, the apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

In addition, the impurity of a semiconductor means anything other than the main component which comprises a semiconductor, for example. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity. When impurities are included, for example, the density of states (DOS) of the semiconductor may increase, or crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, a group 1 element, a group 2 element, a group 13 element, a group 14 element, a group 15 element, and a transition metal other than the main component of the oxide semiconductor. ) And the like, and examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, water may also function as an impurity. In addition, in the case of an oxide semiconductor, oxygen vacancies may be formed due to, for example, mixing of impurities. In addition, when the semiconductor is silicon, examples of impurities that change the properties of the semiconductor include elements of Group 1, Group 2, Group 13, and Group 15 elements excluding oxygen and hydrogen.

In addition, in this specification and the like, silicon oxynitride refers to a composition containing more oxygen than nitrogen. In addition, silicon nitride oxide refers to a composition containing more nitrogen than oxygen.

In addition, in this specification and the like, the term'insulator' may be referred to as an insulating film or an insulating layer. In addition, the term'conductor' can be referred to as a conductive film or a conductive layer. In addition, the term "semiconductor" can be referred to as a semiconductor film or a semiconductor layer.

In addition,'parallel' in this specification and the like refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. In addition,'substantially parallel' refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. In addition,'vertical' refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. In addition,'substantially vertical' refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

In addition, in the present specification, the barrier film is a film having a function of suppressing the transmission of oxygen and impurities such as water and hydrogen, and when the barrier film has conductivity, it is sometimes referred to as a conductive barrier film.

In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. That is, when there is a description of an OS FET or an OS transistor, the transistor may be referred to as a transistor having an oxide or an oxide semiconductor.

In addition, in this specification and the like, normally off means that when a potential is not applied to the gate or a ground potential is supplied to the gate, the current per 1 μm of the channel width flowing through the transistor is 1 × 10 ^-20 A or less at room temperature and 1 × 10 ^-18 A at 85°C Hereinafter, or at 125°C, it refers to 1Х10 ^-16 A or less.

(Embodiment 1)

Hereinafter, an example of a specific configuration of a semiconductor device having a transistor 200 according to an embodiment of the present invention will be described with reference to FIGS. 1 to 10.

<Configuration example of semiconductor device>

1A, 1B, and 1C are top and cross-sectional views of a transistor 200 and a periphery of the transistor 200 according to an embodiment of the present invention.

1A is a top view of a semiconductor device having a transistor 200. 1B and 1C are cross-sectional views of the semiconductor device. Here, (B) of FIG. 1 is a cross-sectional view of a portion indicated by dashed-dotted lines A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Further, FIG. 1C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 1A, and is a cross-sectional view of the transistor 200 in the channel width direction. In addition, in the top view of Fig. 1A, some elements are omitted for clarity of the drawing. In addition, FIG. 2 is an enlarged view of the oxide 230b and its vicinity in FIG. 1B.

[Transistor (200)]

As shown in FIG. 1, the transistor 200 includes an oxide 230a disposed on a substrate (not shown), an oxide 230b disposed on the oxide 230a, and an upper surface of the oxide 230b. The layers 253a and 253b formed spaced apart, the insulator 280 disposed on the oxide 230b and overlapping between the layer 253a and the layer 253b to form an opening, and a conductor disposed in the opening ( 260, an oxide 230b and an insulator 250 disposed between the insulator 280 and the conductor 260, and an oxide 230b disposed between the oxide 230b and the insulator 280 and the insulator 250 ). Here, as shown in (B) and (C) of Figure 1, the top surface of the conductor 260 is preferably substantially identical to the top surface of the insulator 250, the oxide (230c), and the insulator 280 Do.

In addition, hereinafter, the oxide 230a, the oxide 230b, and the oxide 230c may be collectively referred to as an oxide 230. In addition, the layer 253a and the layer 253b are collectively referred to as a layer 253 in some cases.

In addition, as shown in FIG. 1, it is preferable that the insulator 224, the oxide 230a, and the insulator 256 be disposed between the oxide 230b and the insulator 280. Here, the insulator 256 is, as shown in (B) and (C) of FIG. 1, the top and side surfaces of the layer 253a, the top and side surfaces of the layer 253b, the oxide 230a and the oxide 230b. It is preferable to contact the side surface and the upper surface of the insulator 224.

In addition, a configuration in which three layers of oxide 230a, oxide 230b, and oxide 230c are stacked in a region in which a channel is formed in the transistor 200 (hereinafter, also referred to as a channel formation region) and the vicinity thereof is shown. The present invention is not limited thereto. For example, a two-layer structure of the oxide 230b and the oxide 230c, or a laminated structure of four or more layers may be provided. Further, each of the oxide 230a, the oxide 230b, and the oxide 230c may have a stacked structure of two or more layers. In addition, in the transistor 200, the conductor 260 is shown in a two-layer stacked structure, but the present invention is not limited thereto. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.

For example, when the oxide 230c has a stacked structure composed of a first oxide and a second oxide on the first oxide, the first oxide has the same composition as the oxide 230b, and the second oxide is the oxide 230a. It is preferable to have a composition such as ).

Here, the conductor 260 functions as a gate electrode of the transistor, and the layers 253a and 253b function as a source region or a drain region, respectively. As described above, the conductor 260 is formed so as to be buried in the opening of the insulator 280 and the insulator 256, and a region sandwiched between the layers 253a and 253b. Here, the arrangement of the conductor 260, the layer 253a, and the layer 253b is selected in a self-aligning manner with respect to the openings of the insulator 280 and the insulator 256. That is, in the transistor 200, the gate electrode may be self-aligned between the source electrode and the drain electrode. Accordingly, since the conductor 260 can be formed without providing a margin for positional alignment, the area occupied by the transistor 200 can be reduced. Thereby, miniaturization and high integration of the semiconductor device can be achieved.

In addition, as shown in FIG. 1, the conductor 260 has a conductor 260a provided inside the insulator 250 and a conductor 260b provided so as to be buried inside the conductor 260a. desirable.

In addition, the transistor 200 includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, and a conductor 205 disposed to be buried in the insulator 216. Wow, it is preferable to have an insulator 216 and an insulator 222 disposed over the conductor 205 and an insulator 224 disposed over the insulator 222. It is preferable that the oxide 230a is disposed on the insulator 224.

Further, it is preferable that an insulator 274 and an insulator 281 functioning as an interlayer film are disposed on the transistor 200. Here, the insulator 274 is preferably disposed in contact with the top surface of the conductor 260, the insulator 250, the oxide 230c, and the insulator 280.

It is preferable that the insulator 222, the insulator 256, and the insulator 274 have a function of suppressing diffusion of hydrogen (eg, hydrogen atoms, hydrogen molecules, etc.). For example, the insulator 222, the insulator 256, and the insulator 274 preferably have lower hydrogen permeability than the insulator 224, the insulator 250, and the insulator 280. Further, it is preferable that the insulator 222 and the insulator 256 have a function of suppressing diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.). For example, it is preferable that the insulator 222 and the insulator 256 have lower oxygen permeability than the insulator 224, the insulator 250, and the insulator 280.

Here, the insulator 224, the oxide 230a, the oxide 230b, and the insulator 250 are in the insulator 280 and the insulator 281, in the insulator 256, the oxide 230c, and the insulator 274. Are separated by Therefore, impurities such as hydrogen or excess oxygen contained in the insulator 280 and the insulator 281 can be suppressed from being mixed into the insulator 224, the oxide 230a, the oxide 230b, and the insulator 250. .

In addition, it is preferable that a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200 and functions as a plug is provided. Further, an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 serving as a plug. That is, the insulator 256, the insulator 280, the insulator 274, and the insulator 241 are provided in contact with the inner wall of the opening of the insulator 281. Further, the first conductor of the conductor 240 may be provided in contact with the side surface of the insulator 241, and the second conductor of the conductor 240 may be provided further inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be set to the same level. In addition, although a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked in the transistor 200 is shown, the present invention is not limited thereto. For example, the conductor 240 may be a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, there are cases in which ordinal numbers are added in order of formation to distinguish it.

In addition, the transistor 200 uses a metal oxide (hereinafter referred to as an oxide semiconductor) that functions as an oxide semiconductor for the oxide 230 (oxide 230a, oxide 230b, and oxide 230c) including the channel formation region. It is desirable to do. For example, as the metal oxide used as the channel formation region of the oxide 230, it is preferable to use a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more. As described above, by using a metal oxide having a large band gap, the leakage current (off current) in the non-conducting state of the transistor can be very small. By using such a transistor, it is possible to provide a semiconductor device with low power consumption.

For example, as oxide 230, In-M-Zn oxide (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, One or more metal oxides selected from lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. In particular, the element M may be aluminum, gallium, yttrium, or tin. Further, as the oxide 230, indium oxide, zinc oxide, In-Ga oxide, In-Zn oxide, Ga-Zn oxide, or gallium oxide may be used.

Here, in the oxide 230, when an element forming oxygen vacancies or an element binding with oxygen vacancies is added, the carrier density may increase and the resistance may be reduced. Representative examples of such an element include boron and phosphorus. Further, in addition to boron and phosphorus, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, and rare gases may be used. Further, representative examples of rare gases include helium, neon, argon, krypton, and xenon. In addition, the oxide 230 includes aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, Any one or a plurality of metal elements selected from metal elements such as ruthenium, iridium, strontium, and lanthanum may be added. Among the above, as the elements to be added, boron and phosphorus are preferable. For the addition of boron and phosphorus, equipment in the production line for amorphous silicon or low-temperature polysilicon can be used, so that equipment investment can be suppressed. The concentration of the element may be measured using a secondary ion mass spectrometry (SIMS) or the like.

The layer 253 is a layer formed by adding the element to the oxide 230. 1B and 2, the layer 253a and the layer 253b are formed to face each other by sandwiching the conductor 260, and the top surface is formed with the insulator 256 and the oxide 230c. It is desirable to touch. When viewed from the top, the side surfaces of the layers 253a and 253b on the side of the conductor 260 coincide with the side surfaces of the conductor 260, or a part of the layers 253a and 253b is a conductor. It is preferable to overlap with 260. Here, the concentration of the element in the layer 253 is preferably equal to or higher than the concentration of the element in the portion of the oxide 230 where the layer 253 is not formed. In addition, the amount of oxygen vacancies included in the layer 252 is preferably equal to or higher than the amount of oxygen vacancies in the portion of the oxide 230 where the layer 252 and the layer 253 are not formed. Accordingly, the layer 253 has a high carrier density and low resistance compared to a portion of the oxide 230 in which the layer 253 is not formed.

In the oxide 230, a region overlapping the conductor 260 is referred to as a region 234, and a region overlapping with the insulator 256 is referred to as a region 231 (region 231a and region 231b), The region between the region 234 and the region 231 is referred to as the region 232 (region 232a and region 232b). As shown in FIG. 2, the area 234 is located between the area 231a and the area 231b, the area 232a is located between the area 231a and the area 234, and the area 232b is an area It is located between (231b) and the area 234. Here, the region 231 is a region having high carrier density and low resistance compared to the region 234. Further, the region 232 is a region having a high carrier density and low resistance compared to the region 234, and a region having a low carrier density and high resistance compared to the region 231. Alternatively, the region 232 may have the same carrier density and the same resistance as the region 231. Accordingly, the region 234 functions as a channel formation region of the transistor 200, the region 231 functions as a source region or a drain region, and the region 232 functions as a junction region.

With such a configuration, it is possible to prevent an offset region from being formed between the channel formation region of the oxide 230 and the source region or drain region, and to suppress an effective channel length from being larger than the width of the conductor 260. . Thereby, the on-state current of the transistor 200 can be increased, the S value can be improved, and the frequency characteristics can be improved.

By forming a region 231 functioning as a source region or a drain region in the oxide 230, the conductor 240 serving as a plug can be connected to the region 231 without providing a source electrode and a drain electrode formed of metal. I can. When a source electrode and a drain electrode formed of metal are provided in contact with the oxide 230, when a high-temperature heat treatment is performed in a manufacturing process or a post-process of the transistor 200, the source electrode and drain electrode formed of the metal are oxidized. The ON current, S value, and frequency characteristics of (200) may deteriorate. However, in the semiconductor device shown in this embodiment, it is not necessary to provide a source electrode and a drain electrode formed of metal. Accordingly, even when a high-temperature heat treatment is performed in a manufacturing process or a post process of the transistor 200, a semiconductor device exhibiting good on-state current, S value, and frequency characteristics can be provided. For example, in the semiconductor device according to the present embodiment, a process in which a high temperature of about 750°C or more and 800°C or less is applied after fabrication of the transistor 200 can be performed.

In addition, as described above, by adding an element forming oxygen vacancies to the layer 253 and performing heat treatment, hydrogen contained in the region 234 serving as a channel formation region is added to the oxygen vacancies contained in the layer 253. In some cases, it can be captured. Accordingly, it is possible to improve reliability by imparting stable electrical characteristics to the transistor 200.

In addition, in FIG. 2, the layer 253 is formed in the vicinity of the interface between the oxide 230b and the insulator 256 and the oxide 230c in the thickness direction of the oxide 230b, but is not limited thereto. For example, the layer 253 may have substantially the same thickness as that of the oxide 230b, or may be formed on the oxide 230a as well. In addition, in FIG. 2, the layer 253 is formed in the region 231 and the region 232, but is not limited thereto. For example, it may be formed only in the region 231, may be formed in the region 231 and a part of the region 232, and the region 231, the region 232, and a part of the region 234 It may be formed in.

In addition, in the oxide 230, it may be difficult to clearly detect the boundary of each region. The concentrations of metal elements detected in each region and impurity elements such as hydrogen and nitrogen are not limited to stepwise changes for each region, and may be continuously changed (also referred to as gradation) within each region. In other words, the concentration of metal elements and impurity elements such as hydrogen and nitrogen should be decreased as the region is closer to the channel formation region.

From the above, it is possible to provide a semiconductor device having a transistor having a large ON current. Alternatively, a semiconductor device having a transistor having high frequency characteristics can be provided. Alternatively, it is possible to provide a semiconductor device with improved reliability while having stable electrical characteristics by suppressing fluctuations in electrical characteristics. Alternatively, a semiconductor device having a transistor having a small off current can be provided.

Hereinafter, a detailed configuration of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

The conductor 205 is disposed to overlap with the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably provided by being embedded in the insulator 216. Here, it is desirable to improve the flatness of the upper surface of the conductor 205. For example, the average surface roughness (Ra) of the upper surface of the conductor 205 may be 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. Thereby, the flatness of the insulator 224 formed on the conductor 205 can be improved, and the crystallinity of the oxide 230a, the oxide 230b, and the oxide 230c can be improved.

Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. In addition, the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In this case, Vth of the transistor 200 can be controlled by independently changing the potential applied to the conductor 205 without interlocking with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be made larger than 0V, and the off current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be made smaller than that when the conductor 205 is not applied.

In addition, the conductor 205 is preferably provided larger than the channel formation region in the oxide 230. In particular, as shown in FIG. 1C, the conductor 205 preferably extends in a region outside the end of the oxide 230 crossing the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap each other by interposing an insulator on the outside of the side surface of the oxide 230 in the channel width direction.

By having the above configuration, the channel formation region of the oxide 230 is electrically formed by the electric field of the conductor 260 functioning as the first gate electrode and the conductor 205 functioning as the second gate electrode. I can surround it.

In addition, as shown in Fig. 1C, the conductor 205 is extended to function as a wiring. However, the present invention is not limited thereto, and a structure in which a conductor functioning as a wiring is provided under the conductor 205 may be employed. In addition, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by a plurality of transistors.

In addition, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 205. In addition, although the conductor 205 is shown as a single layer, a laminated structure may be used, for example, titanium or titanium nitride may be laminated with the conductive material.

In addition, under the conductor 205, the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO _2, etc.), and copper atoms is suppressed. A conductor having a function (the impurities are difficult to penetrate) may be used. Alternatively, it is preferable to use a conductor having a function of suppressing diffusion of oxygen (eg, at least one of an oxygen atom, an oxygen molecule, etc.) (the oxygen is difficult to permeate). In addition, in the present specification, the function of suppressing diffusion of impurities or oxygen refers to a function of suppressing diffusion of one or both of the impurities and oxygen.

By using a conductor having a function of suppressing the diffusion of oxygen under the conductor 205, it is possible to suppress a decrease in the conductivity due to oxidation of the conductor 205. It is preferable to use tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like as a conductor having a function of suppressing the diffusion of oxygen. Therefore, as the first conductor of the conductor 205, the above-described conductive material may be used in a single layer or a laminated form.

The insulator 214 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from being mixed into the transistor 200 from the substrate side. Therefore, the insulator 214 has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO _2, etc.), and copper atoms. It is preferable to use an insulating material (which is difficult to penetrate the impurities). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate).

For example, it is preferable to use aluminum oxide or silicon nitride or the like as the insulator 214. Accordingly, it is possible to suppress diffusion of impurities such as water or hydrogen from the substrate side to the transistor 200 side rather than the insulator 214. Alternatively, it is possible to suppress diffusion of oxygen contained in the insulator 224 and the like toward the substrate rather than the insulator 214.

In addition, it is preferable that the insulator 216, the insulator 280, and the insulator 281 functioning as an interlayer film have a lower dielectric constant than the insulator 214. By using a material having a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance generated between wirings. For example, as the insulator 216, the insulator 280, and the insulator 281, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, Silicon oxide to which carbon and nitrogen are added, or silicon oxide having voids may be appropriately used.

Further, the insulator 216 may have a laminated structure. For example, the insulator 216 may be configured to provide an insulator similar to the insulator 214 at least at a portion in contact with the side surface of the conductor 205. By having such a configuration, it is possible to suppress oxidation of the conductor 205 due to oxygen contained in the insulator 216. Alternatively, absorption of oxygen contained in the insulator 216 by the conductor 205 can be suppressed.

The insulator 222 and the insulator 224 have a function as a gate insulator.

Here, it is preferable that oxygen is released from the insulator 224 in contact with the oxide 230 by heating. In the present specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride may be suitably used for the insulator 224. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 may be reduced, and reliability of the transistor 200 may be improved.

As the insulator 224, specifically, it is preferable to use an oxide material from which some oxygen is released by heating. An oxide from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis is 1.0 Х10 ¹⁸ atoms/cm ³ or more, preferably 1.0 Х10 ¹⁹ atoms/cm ³ or more, more preferably Is an oxide film of 2.0 Х10 ¹⁹ atoms/cm ³ or more, or 3.0 Х10 ²⁰ atoms/cm ³ or more. In addition, the surface temperature of the film in the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

In addition, as shown in FIG. 1B, it is preferable that the insulator 224 has a thickness of a region that does not overlap with the oxide 230b than that of other regions. With such a configuration, since the lower end of the conductor 260 can be positioned further below, the electric field of the conductor 260 functioning as the first gate electrode can easily act on the side surface of the oxide 230. . Accordingly, by increasing the on-state current of the transistor 200, it is possible to improve the frequency characteristics. Further, the insulator 224 may be overlapped with the oxide 230b and the oxide 230a to be provided in an island shape.

Like the insulator 214 or the like, the insulator 222 preferably functions as a barrier insulating film that suppresses contamination of impurities such as water or hydrogen from the substrate side to the transistor 200. For example, it is preferable that the insulator 222 has lower hydrogen permeability than the insulator 224. By enclosing the insulator 224, the oxide 230, and the insulator 250 by the insulator 222, the insulator 256, and the insulator 274, impurities such as water or hydrogen from outside the transistor 200 ) To prevent invasion.

In addition, it is preferable that the insulator 222 has a function of suppressing diffusion of oxygen (eg, at least one of an oxygen atom, an oxygen molecule, etc.) (the oxygen is difficult to permeate). For example, it is preferable that the insulator 222 has less oxygen permeability than the insulator 224. Since the insulator 222 has a function of suppressing the diffusion of oxygen or impurities, the diffusion of oxygen contained in the oxide 230 to the substrate side can be reduced, which is preferable. In addition, it is possible to suppress the reaction between oxygen and the conductor 205 of the insulator 224 or the oxide 230.

For the insulator 222, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 222 is formed using such a material, the insulator 222 prevents the release of oxygen from the oxide 230 or the incorporation of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200. It functions as a suppressing layer.

Alternatively, to these insulators, for example, one selected from aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the insulator.

In addition, in the insulator 222, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba,Sr)TiO ₃ (BST Insulators containing so-called high-k materials such as) may be used in single or laminated layers. As transistors are miniaturized and highly integrated, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

Further, the insulator 222 and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may be used. For example, an insulator such as the insulator 224 may be provided under the insulator 222.

The oxide 230 has an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b. By having the oxide 230a under the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed. In addition, by having the oxide 230c on the oxide 230b, diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.

In addition, it is preferable that the oxide 230 has a laminated structure made of oxides having different atomic ratios of metal atoms. Specifically, it is preferable that the atomic number ratio of the element M in the constituent elements in the metal oxide used for the oxide 230a is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. In addition, it is preferable that the atomic number ratio of the element M to In in the metal oxide used for the oxide 230a is greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In addition, it is preferable that the atomic number ratio of In to the element M in the metal oxide used for the oxide 230b is greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. In addition, the oxide 230c may be an oxide 230a or a metal oxide that can be used for the oxide 230b.

The oxide 230a, the oxide 230b, and the oxide 230c preferably have crystallinity, and in particular, it is preferable to use CAAC-OS. Oxides having crystallinity such as CAAC-OS have fewer impurities or defects (such as oxygen defects) and have a dense structure with high crystallinity. By having such an oxide 230, the transistor 200 is stabilized against a high temperature (so-called thermal budget) in the manufacturing process.

In addition, it is preferable that the energy at the lower end of the conduction band of the oxide 230a and the oxide 230c is higher than the energy at the lower end of the conduction band of the oxide 230b. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c is smaller than that of the oxide 230b. In this case, it is preferable to use a metal oxide that can be used for the oxide 230a as the oxide 230c. Specifically, it is preferable that the atomic number ratio of the element M in the constituent elements in the metal oxide used for the oxide 230c is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. In addition, it is preferable that the atomic number ratio of the element M to In in the metal oxide used for the oxide 230c is larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In addition, it is preferable that the atomic number ratio of In to the element M in the metal oxide used for the oxide 230b is greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 230c.

Here, the energy level at the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c gradually changes. In other words, the energy level at the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c can be said to be continuously changed or continuously joined. To do this, it is good to lower the density of defect states of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c.

Specifically, when the oxide 230a and the oxide 230b, the oxide 230b and the oxide 230c have a common element other than oxygen (by making it a main component), a mixed layer having a low density of defect states can be formed. . For example, when the oxide 230b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like may be used as the oxide 230a and the oxide 230c. Further, the oxide 230c may be used as a laminated structure. For example, a stacked structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a stacked structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide You can use In other words, a laminated structure of an In-Ga-Zn oxide and an oxide not containing In may be used as the oxide 230c.

Specifically, as the oxide 230a, a metal oxide of In:Ga:Zn=1:3:4 [atom number ratio] or 1:1:0.5 [atom number ratio] may be used. Further, as the oxide 230b, a metal oxide having In:Ga:Zn=4:2:3 [atom number ratio] or 3:1:2 [atom number ratio] may be used. In addition, as oxide 230c, In:Ga:Zn=1:3:4 [atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio], Ga:Zn=2:1 [atomic ratio] , Or a metal oxide of Ga:Zn=2:5 [atomic ratio] may be used. In addition, as a specific example in the case of using the oxide 230c as a stacked structure, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn =2:1 [atomic ratio], In:Ga :Zn=4:2:3[atomic ratio] and Ga:Zn=2:5[atomic ratio] stacked structure, In:Ga:Zn=4:2:3[atomic ratio] and gallium oxide stacked structure, etc. Can be mentioned.

At this time, the main path of the carrier is the oxide 230b. When the oxide 230a and the oxide 230c are configured as described above, the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence on carrier conduction due to interfacial scattering is small, and the transistor 200 can obtain high ON current and high frequency characteristics. In addition, when the oxide 230c is a stacked structure, in addition to the effect of lowering the density of defect states at the interface between the oxide 230b and the oxide 230c, the constituent element of the oxide 230c is the insulator 250 It is expected to suppress diffusion to the side. More specifically, since the oxide 230c is used as a stacked structure and an oxide not containing In is positioned above the stacked structure, In which may diffuse toward the insulator 250 can be suppressed. Since the insulator 250 functions as a gate insulator, when In is diffused, the characteristics of the transistor become defective. Therefore, by using the oxide 230c as a laminated structure, it is possible to provide a highly reliable semiconductor device.

The region between the layer 253a and the layer 253b is formed by overlapping the opening of the insulator 280. Accordingly, the conductor 260 can be self-aligned between the layer 253a and the layer 253b.

The insulator 250 functions as a gate insulator. It is preferable to arrange the insulator 250 in contact with the upper surface of the oxide 230c. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores are used. I can. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

It is preferable that the insulator 250 has a reduced concentration of impurities such as water or hydrogen in the insulator 250 like the insulator 224. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

Further, a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppresses oxygen diffusion from the insulator 250 to the conductor 260. As a result, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

In addition, the metal oxide may function as a part of a gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, it is preferable to use a metal oxide, which is a high-k material having a high relative dielectric constant, as the metal oxide. When the gate insulator is a laminated structure of the insulator 250 and the metal oxide, it is possible to obtain a laminated structure that is stable against heat and has a high relative dielectric constant. Accordingly, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Further, it becomes possible to reduce the equivalent oxide film thickness (EOT) of the insulator functioning as the gate insulator.

Specifically, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum or hafnium, aluminum oxide, hafnium oxide, and oxide (hafnium aluminate) containing aluminum and hafnium.

The conductor 260 has a two-layer structure in Fig. 1, but may have a single-layer structure or a stacked structure of three or more layers.

The conductor 260a has a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO _2, etc.), and a copper atom. It is preferable to use a conductor. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

In addition, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b due to oxygen contained in the insulator 250. As the conductive material having a function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

In addition, it is preferable to use a conductive material mainly containing tungsten, copper, or aluminum as the conductor 260b. Further, since the conductor 260 also functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductive material.

Further, a metal oxide that can be used as the oxide 230 may be provided between the insulator 250 and the conductor 260a. In this case, the metal oxide functions as a gate electrode like the conductor 260. By providing a metal oxide, oxygen can be supplied to at least one of the insulator 250 and the oxide 230, which is preferable. In addition, by using a metal oxide having a function of suppressing the transmission of oxygen as the metal oxide, oxidation of the conductor 260 due to oxygen contained in the insulator 250 or the insulator 280 can be suppressed. . Alternatively, oxygen included in the insulator 250 may be suppressed from being absorbed by the conductor 260.

In addition, as shown in (A) and (C) of FIG. 1, a region in the oxide 230b that does not overlap with the layer 253, in other words, in the channel formation region of the oxide 230, the oxide 230 It is arranged so that the side surface of is covered with the conductor 260. Thereby, the electric field of the conductor 260 functioning as the first gate electrode can be easily applied to the side surface of the oxide 230. Accordingly, by increasing the on-state current of the transistor 200, it is possible to improve the frequency characteristics.

Like the insulator 214, the insulator 256 preferably functions as a barrier insulating film for suppressing the incorporation of impurities such as water or hydrogen into the transistor 200 from the insulator 280 side. For example, it is preferable that the insulator 256 has a lower hydrogen permeability than the insulator 224. In addition, as shown in (B) and (C) of FIG. 1, the insulator 256 includes a part of the side surface of the oxide 230c, the upper surface and the side surface of the layer 253a, the upper surface and the side surface of the layer 253b, That is, it is preferable to contact a part of the upper surface and a part of the side surface of the oxide 230b, the side surface of the oxide 230a, and the upper surface of the insulator 224. With such a configuration, it is possible to prevent hydrogen contained in the insulator 280 from entering the oxide 230 from the oxide 230a, the oxide 230b, and the top or side surfaces of the insulator 224.

In addition, the insulator 256 preferably has a function of inhibiting diffusion of oxygen (eg, at least one of an oxygen atom, an oxygen molecule, etc.) (the oxygen is difficult to permeate). For example, it is preferable that the insulator 256 has less oxygen permeability than the insulator 280 or the insulator 224.

It is preferable that the insulator 256 is formed by using a sputtering method. Oxygen can be added in the vicinity of the region of the insulator 224 in contact with the insulator 256 by forming a film on the insulator 256 using a sputtering method in an atmosphere containing oxygen. Accordingly, oxygen can be supplied into the oxide 230 from the region through the insulator 224. Here, since the insulator 256 has a function of suppressing the diffusion of oxygen upward, it is possible to prevent the diffusion of oxygen from the oxide 230 to the insulator 280. In addition, since the insulator 222 has a function of suppressing the diffusion of oxygen downward, it is possible to prevent the diffusion of oxygen from the oxide 230 to the substrate side. In this way, oxygen is supplied to the channel formation region of the oxide 230. As a result, oxygen vacancies in the oxide 230 can be reduced, and normal mildness of the transistor can be suppressed.

As the insulator 256, it is preferable to form an insulator containing oxides of one or both of aluminum and hafnium, for example. In addition, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) or the like as an insulator containing an oxide of one or both of aluminum and hafnium.

Further, the insulator 256 may have a laminated structure. When the insulator 256 has a laminated structure, a second insulator may be formed on the first insulator formed by the sputtering method by using the ALD method. At this time, for the first insulator and the second insulator, the same material selected from the above-described materials may be used, or different materials may be used. For example, aluminum oxide formed by the sputtering method may be used as the first insulator, and aluminum oxide formed by the ALD method may be used as the second insulator. A film formed by the ALD method has high coverage, and a film having high uniformity can be formed even at a step portion due to a structure such as the oxide 230. In addition, it is preferable because a film formation defect in the first insulating film formed by a sputtering method can be preserved.

As described above, by covering the insulator 224 and the oxide 230 with the insulator 256 having barrier properties to hydrogen, the insulator 280 is separated from the insulator 224 and the oxide 230. Thereby, since it is possible to prevent impurities such as hydrogen from entering from the outside of the transistor 200, good electrical characteristics and reliability can be imparted to the transistor 200.

In addition, as the insulator 256, for example, an insulator made of aluminum nitride may be used. As the insulator 256, it is preferable to use a nitride insulator whose composition formula satisfies AlNx (x is a real number greater than 0 and less than 2, preferably x is greater than 0.5 and less than or equal to 1.5). As a result, since a film having excellent insulating properties and excellent thermal conductivity can be formed, heat dissipation of heat generated when the transistor 200 is driven can be improved. Further, as the insulator 256, aluminum nitride, titanium nitride, or the like may be used. In this case, by forming a film of the insulator 256 using a sputtering method, it is preferable because a film can be formed without using a gas having strong oxidizing properties such as oxygen or ozone as the film forming gas. In addition, silicon nitride or silicon nitride oxide may be used.

In addition, as the insulator 256, it is preferable to form an insulator containing an oxide of one or both of aluminum and hafnium, for example. In addition, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) or the like as an insulator containing an oxide of one or both of aluminum and hafnium. In this case, it is preferable that the insulator 256 is formed by using the ALD method. Since the ALD method is a film forming method having good coverage, it is possible to prevent the formation of a disconnection or the like due to irregularities in the insulator 256.

Further, as described later, the insulator 256 may have a function as a protective film when forming the layers 253a and 253b. When ion implantation or ion doping is used to form the layers 253a and 253b, by providing the insulator 256 as a protective film, the surface of the oxide 230 is not directly exposed to ions or plasma, and the layer ( It is preferable because it is possible to suppress damage to the oxide 230 in the formation of the 253a) and the layer 253b. Here, the damage of the oxide 230 refers to excessive formation of oxygen vacancies in the oxide 230 or excessive decrease in the crystallinity of the oxide 230. For example, as the insulator 256, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with carbon and nitrogen, or pores Eggplants may use silicon oxide or the like.

The insulator 280 is provided on the insulator 224 and the oxide 230 through the insulator 256. For example, as the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with carbon and nitrogen, or silicon oxide with pores, etc. It is preferable to have. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, a material such as silicon oxide, silicon oxynitride, or silicon oxide having pores is preferable because a region containing oxygen that is released by heating can be easily formed.

It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Further, the upper surface of the insulator 280 may be flattened.

Like the insulator 214, the insulator 274 preferably functions as a barrier insulating film that suppresses mixing of impurities such as water or hydrogen into the insulator 280 from above. As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 256, or the like may be used.

Further, it is preferable to provide an insulator 281 functioning as an interlayer film over the insulator 274. In the insulator 281, like the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the film is reduced.

Further, a conductor 240a and a conductor 240b are disposed in openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 256. The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Further, the heights of the upper surfaces of the conductors 240a and 240b may be the same as those of the insulator 281.

In addition, the insulator 281, the insulator 274, the insulator 280, and the insulator 241a are provided in contact with the inner wall of the opening of the insulator 256, and the first conductor of the conductor 240a is in contact with the side surface. Is formed. A layer 253a is positioned at at least a part of the bottom of the opening, and a conductor 240a contacts the layer 253a. Similarly, the insulator 281, the insulator 274, the insulator 280, and the insulator 241b are provided in contact with the inner wall of the opening of the insulator 256, and the first conductor of the conductor 240b is in contact with the side surface. Is formed. A layer 253b is positioned at at least a part of the bottom of the opening, and the conductor 240b contacts the layer 253b.

It is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component for the conductor 240a and the conductor 240b. In addition, the conductor 240a and the conductor 240b may have a laminated structure.

In addition, when the conductor 240 is a laminated structure, the oxide 230a, the oxide 230b, the insulator 256, the insulator 280, the insulator 274, the conductor in contact with the insulator 281 is described above. It is preferable to use a conductor having a function of suppressing diffusion of impurities such as water or hydrogen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Further, a conductive material having a function of suppressing diffusion of impurities such as water or hydrogen may be used as a single layer or a laminate. By using the conductive material, oxygen added to the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b. Further, impurities such as water or hydrogen from a layer above the insulator 281 can be suppressed from being mixed into the oxide 230 through the conductor 240a and the conductor 240b.

As the insulator 241a and the insulator 241b, an insulator that can be used for the insulator 214 or the like, for example, aluminum oxide or silicon nitride may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 256, impurities such as water or hydrogen from the insulator 280 are transmitted through the conductor 240a and the conductor 240b through the oxide 230. It can be suppressed from being mixed with. In addition, oxygen included in the insulator 280 may be prevented from being absorbed by the conductor 240a and the conductor 240b.

For the formation of the insulator 241a and the insulator 241b, an ALD method or a CVD method can be used.

Further, although not shown, a conductor serving as a wiring may be disposed in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. It is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor functioning as a wiring. Further, the conductor may have a laminated structure, for example, a laminate of titanium, titanium nitride, and the conductive material. The conductor may be formed to be buried in an opening provided in the insulator.

In addition, although not shown, it is preferable to provide an insulator having a resistivity of 1.0 Х10 ¹³ Ωcm or more and 1.0 Х10 ¹⁵ Ωcm or less, and preferably 5.0 Х10 ¹³ Ωcm or more and 5.0 Х10 ¹⁴ Ωcm or less so as to cover the conductor. By providing an insulator having a resistivity as described above on the conductor, the insulator distributes charge accumulated between wirings such as the transistor 200 and the conductor while maintaining the insulating property, and the transistor or the transistor due to the charge It is preferable because it is possible to suppress poor characteristics or electrostatic breakdown of an electronic device having a.

<Constituent materials of semiconductor devices>

Hereinafter, a constituent material that can be used for a semiconductor device will be described.

<<substrate>>

As the substrate on which the transistor 200 is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate. Further, examples of the semiconductor substrate include a semiconductor substrate such as silicon and germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. In addition, there is a semiconductor substrate having an insulator region inside the above-described semiconductor substrate, for example, a silicon on insulator (SOI) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there is a substrate having a metal nitride, a substrate having a metal oxide, and the like. In addition, there is a substrate provided with a conductor or a semiconductor in the insulator substrate, a substrate provided with a conductor or an insulator in the semiconductor substrate, and a substrate provided with a semiconductor or insulator in the conductor substrate. Alternatively, those provided with elements on these substrates may be used. Examples of elements provided on the substrate include capacitive elements, resistance elements, switching elements, light-emitting elements, and memory elements.

<<insulator>>

Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides having insulating properties.

For example, as transistors are miniaturized and highly integrated, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as the gate insulator, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material having a low relative dielectric constant for an insulator functioning as an interlayer film, it is possible to reduce parasitic capacitance generated between wirings. Therefore, it is better to select a material according to the function of the insulator.

In addition, as an insulator having a high dielectric constant, gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitride having silicon and hafnium, or silicon and hafnium And nitrides having

Insulators with low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with carbon and nitrogen, and silicon oxide with pores. , Or resin.

In addition, a transistor using an oxide semiconductor is surrounded by an insulator (insulator 214, insulator 222, insulator 256, insulator 274, etc.) that has a function of suppressing the transmission of oxygen and impurities such as water or hydrogen. By inexpensive, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium Insulators including, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a laminate. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, Alternatively, metal oxides such as tantalum oxide, aluminum nitride, aluminum nitride titanium, titanium nitride, silicon nitride oxide, or silicon nitride may be used.

Further, the insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, silicon oxide or silicon oxynitride having a region containing oxygen released by heating may be in contact with the oxide 230, thereby compensating for oxygen vacancies in the oxide 230.

<<All>>

Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, It is preferable to use a metal element selected from strontium, lanthanum, or the like, an alloy containing the above-described metal element as a component, or an alloy in which the above-described metal element is combined. For example, tantalum nitride, titanium nitride, tungsten, nitrides including titanium and aluminum, nitrides including tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides including strontium and ruthenium, oxides including lanthanum and nickel, etc. It is desirable to do. In addition, tantalum nitride, titanium nitride, nitride including titanium and aluminum, nitride including tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide including strontium and ruthenium, oxides including lanthanum and nickel are difficult to oxidize, conductive materials, Alternatively, it is preferable because it is a material that maintains conductivity even when oxygen is absorbed. Further, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, and silicide such as nickel silicide may be used.

Further, a plurality of conductive layers formed of the material may be stacked and used. For example, a laminated structure in which a material containing the above-described metal element and a conductive material containing oxygen may be combined. Further, a laminated structure in which a material containing the above-described metal element and a conductive material containing nitrogen may be combined. Further, a laminated structure in which the above-described material containing the metal element, the conductive material containing oxygen, and the conductive material containing nitrogen may be combined.

In addition, when an oxide is used for the channel formation region of a transistor, it is preferable to use a laminated structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined for a conductor functioning as a gate electrode. In this case, it is preferable to provide a conductive material containing oxygen to the channel formation region side. By providing a conductive material containing oxygen to the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed as a conductor functioning as a gate electrode. Further, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium zinc oxide, and indium tin oxide containing silicon are used. Also good. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed can be captured in some cases. Alternatively, there are cases in which hydrogen mixed from an external insulator or the like can be captured.

<<metal oxide>>

As the oxide 230, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor. Hereinafter, a metal oxide applicable to the oxide 230 according to the present invention will be described.

It is preferable that the oxide semiconductor contains at least indium or zinc. It is particularly preferable to contain indium and zinc. Further, in addition to these, it is preferable that aluminum, gallium, yttrium, or tin is contained. In addition, one or more types selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.

Here, the case where the oxide semiconductor is an In-M-Zn oxide containing indium, element M, and zinc is considered. In addition, the element M is made of aluminum, gallium, yttrium, or tin. Other elements that can be applied to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, there are cases where a plurality of the above-described elements may be combined.

In addition, in this specification and the like, a metal oxide having nitrogen is also referred to as a metal oxide in some cases. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

Oxide semiconductors are divided into single crystal oxide semiconductors and non-single crystal oxide semiconductors. As non-single crystal oxide semiconductors, for example, polycrystalline oxide semiconductors and amorphous oxide semiconductors are known.

It is preferable to use a thin film with high crystallinity as the oxide semiconductor used for the semiconductor of the transistor. By using the thin film, the stability or reliability of the transistor can be improved. Examples of the thin film include a single crystal oxide semiconductor thin film or a polycrystalline oxide semiconductor thin film. However, in order to form a thin film of a single crystal oxide semiconductor or a thin film of a polycrystalline oxide semiconductor on a substrate, a process of heat treatment at a high temperature or heat treatment with a laser is required. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.

It is reported in Non-Patent Document 1 and Non-Patent Document 2 that In-Ga-Zn oxide (referred to as CAAC-IGZO) having a CAAC structure was discovered in 2009. Here, it is reported that CAAC-IGZO has c-axis orientation, crystal grain boundaries are not clearly identified, and can be formed on a substrate at low temperatures. Further, it has been reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability.

In addition, in 2013, an In-Ga-Zn oxide (referred to as nc-IGZO) having an nc structure was discovered (see Non-Patent Document 3). Here, it is reported that nc-IGZO has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and that there is no regularity in crystal orientation between the different regions.

In Non-Patent Literature 4 and Non-Patent Literature 5, the transition of the average crystal size by irradiation of electron beams for each thin film of CAAC-IGZO, nc-IGZO, and IGZO having low crystallinity is shown. In the thin film of IGZO having low crystallinity, crystalline IGZO of about 1 nm was observed even before the electron beam was irradiated. Therefore, it is reported here that the existence of a completely amorphous structure was not confirmed in IGZO. In addition, compared to the IGZO thin film having low crystallinity, the CAAC-IGZO thin film and the nc-IGZO thin film have high stability against electron beam irradiation. Therefore, it is preferable to use a thin film of CAAC-IGZO or a thin film of nc-IGZO as the semiconductor of the transistor.

A transistor using an oxide semiconductor has a very small leakage current in a non-conducting state, and specifically, it is shown in Non-Patent Document 6 that the off current per 1 μm channel width of the transistor is in the order of yA/μm (10 ^-24 A/μm). . For example, a low power consumption CPU and the like to which the characteristic that the leakage current of a transistor using an oxide semiconductor is low has been disclosed (see Non-Patent Document 7).

Further, the application of the transistor to a display device using the characteristic that the leakage current of a transistor using an oxide semiconductor is low has been reported (see Non-Patent Document 8). In the display device, the displayed image is switched dozens of times per second. The number of images switching per second is called the refresh rate. Further, the refresh rate is sometimes referred to as a drive frequency. As described above, high-speed screen switching, which is difficult to perceive with the human eye, is thought to be a cause of eye fatigue. Therefore, it has been proposed to reduce the refresh rate of the display device and reduce the number of times the image is rewritten. Further, the power consumption of the display device can be reduced by driving with a lower refresh rate. This driving method is called idling stop (IDS) driving.

The discovery of the CAAC structure and the nc structure contributes to the improvement of the electrical characteristics and reliability of the transistor using the CAAC structure or the oxide semiconductor having the nc structure, and the cost reduction and throughput of the manufacturing process. Further, researches on application of the transistor to a display device and an LSI are being conducted using the characteristic that the leakage current of the transistor is low.

[Composition of metal oxide]

Hereinafter, a configuration of a CAC (Cloud-Aligned Composite)-OS that can be used in the transistor disclosed in one embodiment of the present invention will be described.

In addition, in this specification and the like, it may be described as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). In addition, CAAC represents an example of a crystal structure, and CAC represents an example of a function or a configuration of a material.

CAC-OS or CAC-metal oxide has a function of conductivity in a part of the material, an insulating function in a part of the material, and a function as a semiconductor in the whole material. In addition, when CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the function of conductivity is the function of flowing electrons (or holes) serving as carriers, and the function of insulating property is the function of not flowing electrons serving as carriers. By complementing each of the conductive and insulating functions, a switching function (on/off function) can be given to CAC-OS or CAC-metal oxide. By separating each function from CAC-OS or CAC-metal oxide, both functions can be maximized.

In addition, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In addition, there are cases where the conductive region and the insulating region are separated at the nanoparticle level in the material. In addition, the conductive region and the insulating region may be unevenly located in the material, respectively. In addition, the conductive region may be observed by being connected to the cloud because the surroundings are blurred.

In addition, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material in a size of 0.5 nm or more and 10 nm or less, and preferably 0.5 nm or more and 3 nm or less, respectively.

In addition, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having an inner gap due to a conductive region. In the case of the above configuration, the carrier mainly flows from a component having a gap therein when the carrier flows. In addition, a component having an inner gap acts complementarily to a component having a wide gap, and carriers flow to a component having a wide gap in conjunction with a component having an inner gap. Therefore, when the CAC-OS or CAC-metal oxide is used in a channel formation region of a transistor, a high current driving force, that is, a large ON current and a high field effect mobility can be obtained in the ON state of the transistor.

That is, CAC-OS or CAC-metal oxide may be referred to as a matrix composite or a metal matrix composite.

[Structure of metal oxide]

Oxide semiconductors are divided into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide. Semiconductors, etc.

CAAC-OS has c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction to form a crystal structure having deformation. Further, the deformation refers to a portion in which the direction of the lattice arrangement is changed between a region in which the lattice arrangement is aligned and another region in which the lattice arrangement is arranged in a region where a plurality of nanocrystals are connected.

Nanocrystals are basically hexagonal, but are not limited to regular hexagons, and may be irregular hexagons. In addition, there is a case of having a lattice arrangement such as a pentagon or a heptagon in the deformation. In addition, in CAAC-OS, a clear grain boundary (also referred to as grain boundary) cannot be confirmed even near the deformation. That is, it can be seen that the formation of grain boundaries is suppressed by the deformation of the lattice arrangement. This is considered to be because the CAAC-OS can allow deformation due to the fact that the arrangement of oxygen atoms in the a-b plane direction is not dense, or the bonding distance between atoms is changed due to substitution of metal elements.

In addition, CAAC-OS is a layered crystal structure in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are stacked (also referred to as a layered structure). Have a tendency to have. In addition, indium and element M may be substituted with each other, and when the element M of the (M, Zn) layer is substituted with indium, it may be referred to as an (In, M, Zn) layer. In addition, when indium in the In layer is substituted with the element M, it can also be referred to as an (In, M) layer.

CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, since CAAC-OS cannot confirm a clear grain boundary, it can be said that the decrease in electron mobility due to the grain boundary is unlikely to occur. In addition, since the crystallinity of the oxide semiconductor may decrease due to the incorporation of impurities or generation of defects, CAAC-OS can also be referred to as an oxide semiconductor with few impurities and defects (oxygen defects, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability.

The nc-OS has periodicity in atomic arrangement in a small region (eg, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less). In addition, nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen throughout the film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

The a-like OS is an oxide semiconductor having a structure intermediate between nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than that of nc-OS and CAAC-OS.

Oxide semiconductors take a variety of structures, and each has different properties. The oxide semiconductor of one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[Transistor with oxide semiconductor]

Next, a case where the oxide semiconductor is used in a transistor will be described.

Further, by using the oxide semiconductor as a transistor, a transistor with high field effect mobility can be realized. Further, a highly reliable transistor can be realized.

In addition, it is preferable to use an oxide semiconductor having a low carrier density for the transistor. In the case of lowering the carrier density of the oxide semiconductor film, it is sufficient to lower the impurity concentration in the oxide semiconductor film and lower the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, the oxide semiconductor has a carrier density of less than ⁸ × ^{10 11} /cm ³ , preferably less than 1 × ^{10 11} /cm ³ , more preferably less than 1 × ^{10 10} /cm ³ , and ¹ × ^{10 -9} /cm ³ or more.

Further, since the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low density of defect states, the density of trap states may also be low.

In addition, the charge trapped at the trap level of the oxide semiconductor takes a long time to dissipate, and thus acts like a fixed charge in some cases. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high trap state density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, and silicon.

[impurities]

Here, the influence of each impurity in the oxide semiconductor will be described.

When silicon or carbon, one of the elements of Group 14, is contained in the oxide semiconductor, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor (the concentration obtained by the secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms/cm ³ Hereinafter, preferably, it is 2 Х10 ¹⁷ atoms/cm ³ or less.

In addition, when an alkali metal or an alkaline earth metal is included in the oxide semiconductor, a defect level may be formed to generate a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have a normalion characteristic. Therefore, it is desirable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1 X 10 ¹⁸ atoms/cm ³ or less, preferably 2 X 10 ¹⁶ atoms/cm ³ or less.

In addition, when nitrogen is included in the oxide semiconductor, electrons as carriers are generated and the carrier density increases, so that n-type tends to be formed. As a result, a transistor in which an oxide semiconductor containing nitrogen is used for the semiconductor layer tends to be normally on. Therefore, it is preferable that the nitrogen in the oxide semiconductor is reduced as much as possible, for example, the nitrogen concentration in the oxide semiconductor is less than 5Х10 ¹⁹ atoms/cm ³ in SIMS, preferably 5Х10 ¹⁸ atoms/cm ³ or less, more preferably It is 1 Х10 ¹⁸ atoms/cm ³ or less, more preferably 5 Х10 ¹⁷ atoms/cm ³ or less.

In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons as carriers may be generated. In addition, some of the hydrogen may be bonded to oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have a normal-on characteristic. Therefore, it is desirable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, the hydrogen concentration obtained by SIMS in the oxide semiconductor is less than ¹ Х10 ²⁰ atoms/cm ³ , preferably less than 1 Х10 ¹⁹ atoms/cm ³ , more preferably less than 5 Х10 ¹⁸ atoms/cm ³ , more preferably 1 Х10 ^It should be less than ¹⁸ atoms/cm ³ .

Stable electrical characteristics can be imparted by using an oxide semiconductor having sufficiently reduced impurities in the channel formation region of the transistor.

[Effect of vacuum baking]

Here, a weak Zn-O bond contained in a metal oxide is described, and an example of a method of reducing oxygen atoms and zinc atoms constituting the bonds is shown.

In a transistor using a metal oxide, oxygen vacancies are an example of a defect leading to poor electrical properties of the transistor. For example, in a transistor using a metal oxide containing oxygen vacancies in a film, the threshold voltage is liable to fluctuate in the negative direction, and thus the normally-on characteristic is likely to be obtained. This is because a donor due to oxygen vacancies contained in the metal oxide is generated, and the carrier concentration increases. When the transistor has a normally-on characteristic, various problems arise, such as an operation failure tends to occur during operation or an increase in power consumption during non-operation.

In addition, deterioration of the electrical characteristics of transistors such as fluctuations in threshold voltage and increase in parasitic resistance due to thermal budget in the process of forming connection wiring for manufacturing a module, and electricity due to deterioration of the electrical characteristics There is a problem such as an increase in variation in characteristics. Since these problems directly lead to a decrease in manufacturing yield, it is important to consider countermeasures. In addition, even in a stress test capable of evaluating the change in the characteristics of the transistor (depending on aging) caused by long-term use in a short time, deterioration of the electrical characteristics occurs. The deterioration of the electrical properties is presumed to be due to the deficiency of oxygen in the metal oxide due to the high temperature treatment performed in the manufacturing process or the electrical stress received during the stress test.

In the metal oxide, oxygen atoms that are weakly bonded to metal atoms and tend to become oxygen vacancies exist. In particular, when the metal oxide is an In-Ga-Zn oxide, it is easy to form a weak bond (also referred to as a weak Zn-O bond) between the zinc atom and the oxygen atom. Here, the weak Zn-O bond is a bond formed between a zinc atom and an oxygen atom, bonded with a strength enough to be cleaved due to electrical stress received during a high-temperature treatment performed during a manufacturing process or a stress test. When a weak Zn-O bond is present in the metal oxide, the bond is cleaved by heat treatment or current stress, and oxygen vacancies are formed. As oxygen vacancies are formed, stability of the transistor, such as resistance to heat treatment and resistance to stress tests, decreases.

The bond formed between the zinc atom and the oxygen atom heavily bonded to the zinc atom may be a weak Zn-O bond. Compared to the gallium atom, the zinc atom has a weak bond with the oxygen atom. Therefore, the oxygen atom that is heavily bonded to the zinc atom is liable to be deficient. In other words, it is assumed that the bond formed between the zinc atom and the oxygen atom is weaker than that with other metals.

Further, it is estimated that weak Zn-O bonds tend to be formed when impurities are present in the metal oxide. Examples of impurities in the metal oxide include water molecules and hydrogen. The presence of water molecules or hydrogen in the metal oxide may cause hydrogen atoms to bond with oxygen atoms constituting the metal oxide (also referred to as OH bonds). Oxygen atoms constituting the metal oxide are bonded to four metal atoms constituting the metal oxide when the In-Ga-Zn oxide is a single crystal. However, the oxygen atom bonded to the hydrogen atom may be bonded to two or three metal atoms. By reducing the number of metal atoms bonded to the oxygen atom, the oxygen atom is liable to be deficient. Further, when a zinc atom is bonded to an oxygen atom forming an OH bond, it is assumed that the bond between the oxygen atom and the zinc atom is weak.

In addition, weak Zn-O bonds are sometimes formed in a strain present in a region where a plurality of nanocrystals are connected. Nanocrystals are basically hexagonal, but in the above variant, they have lattice arrangements such as pentagons and heptagons. In the above transformation, it is assumed that weak Zn-O bonds are formed because the bonding distance between atoms is not uniform.

In addition, it is estimated that weak Zn-O bonds are likely to be formed when the crystallinity of the metal oxide is low. When the crystallinity of the metal oxide is high, the zinc atom constituting the metal oxide is bonded to 4 or 5 oxygen atoms. However, when the crystallinity of the metal oxide is lowered, the number of oxygen atoms bonded to the zinc atom tends to decrease. When the number of oxygen atoms bonded to the zinc atom decreases, the zinc atom tends to be deficient. That is, it is assumed that the bond formed between the zinc atom and the oxygen atom is weaker than the bond formed in the single crystal.

By reducing the oxygen atoms and zinc atoms constituting the weak Zn-O bond, it is possible to suppress the formation of oxygen vacancies due to heat treatment or current stress, and improve the stability of the transistor. In addition, when only the oxygen atoms constituting the weak Zn-O bonds are reduced, and the zinc atoms constituting the weak Zn-O bonds are not reduced, supplying oxygen atoms in the vicinity of the zinc atom causes the weak Zn-O bonds to be reformed. There are cases. Therefore, it is desirable to reduce the zinc atoms and oxygen atoms that make up the weak Zn-O bonds.

As one of the methods of reducing the oxygen atoms and zinc atoms constituting the weak Zn-O bond, a method of performing vacuum baking after forming a film of a metal oxide is exemplified. Vacuum baking is a heat treatment performed in a vacuum atmosphere. The vacuum atmosphere is maintained by exhausting it with a turbo molecular pump or the like. In addition, the pressure in the processing chamber may be 1 × 10 ^-2 Pa or less, preferably 1 × 10 ^-3 Pa or less. In addition, the substrate temperature during heat treatment may be 300°C or higher, preferably 400°C or higher.

By performing vacuum baking, oxygen atoms and zinc atoms constituting weak Zn-O bonds can be reduced. In addition, since heat is applied to the metal oxide by vacuum baking, oxygen atoms and zinc atoms constituting the weak Zn-O bond are reduced, and then the atoms constituting the metal oxide are rearranged, thereby bonding with four metal atoms. There are more oxygen atoms. Therefore, while the oxygen atom and the zinc atom constituting the weak Zn-O bond are reduced, it is possible to suppress the formation of the weak Zn-O bond.

In addition, when impurities are present in the metal oxide, vacuum baking is performed to release water molecules or hydrogen in the metal oxide, thereby reducing OH bonds. By reducing the OH bonds in the metal oxide, the proportion of oxygen atoms bonded to the four metal atoms increases. Further, when water molecules or hydrogen are released, the atoms constituting the metal oxide are rearranged, thereby increasing the number of oxygen atoms bonded to the four metal atoms. Thus, it is possible to suppress the formation of weak Zn-O bonds.

As described above, by performing vacuum baking after forming a metal oxide film, oxygen atoms and zinc atoms constituting weak Zn-O bonds can be reduced. Therefore, by the above process, the stability of the transistor can be improved. In addition, as the stability of the transistor is improved, the degree of freedom in selection of materials and formation methods is increased.

<Method of manufacturing semiconductor device>

Next, a method of fabricating a semiconductor device having a transistor 200 according to an embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS. 3 to 10. In addition, in Figs. 3 to 10, (A) of each drawing shows a top view. In addition, (B) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 shown in (A), and is also a cross-sectional view of the transistor 200 in the channel length direction. Incidentally, (C) of each drawing is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in (A), and is also a cross-sectional view of the transistor 200 in the channel width direction. In addition, in the top view of (A) of each drawing, some elements are omitted for clarity of the drawing.

First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The insulator 214 may be formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an atomic vapor deposition (ALD) method. This can be done using the Layer Deposition method.

Further, the CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, and a photo CVD (photo CVD) method using light. In addition, it can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to the raw material gas used.

The plasma CVD method can obtain a high-quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film formation method capable of reducing plasma damage to an object to be processed. For example, wirings, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may be charged up by receiving electric charges from plasma. At this time, the accumulated electric charges may destroy wirings, electrodes, elements, etc. included in the semiconductor device. On the other hand, in the case of a thermal CVD method that does not use plasma, since such plasma damage does not occur, the yield of the semiconductor device can be increased. In addition, the thermal CVD method does not cause plasma damage during film formation, so that a film with few defects can be obtained.

In addition, since the ALD method can deposit atoms layer by layer by using the self-controlling property of the atom, it is possible to form a very thin film, form a film in a structure with a high aspect ratio, and have fewer defects such as pinholes. There are such effects that a film can be formed, a film with excellent coatability can be formed, and a film can be formed at a low temperature. In addition, the ALD method also includes the PEALD (Plasma Enhanced ALD) method, which is a film forming method using plasma. By using a plasma, film formation at a lower temperature becomes possible and it is preferable in some cases. In addition, some of the precursors used in the ALD method contain impurities such as carbon. Therefore, the film provided by the ALD method sometimes contains a large amount of impurities such as carbon as compared to the film provided by other film forming methods. In addition, the quantification of impurities may be performed using X-ray photoelectron spectroscopy (XPS).

The CVD method and the ALD method are film-forming methods in which a film is formed by a reaction on the surface of an object to be treated, unlike a film-forming method in which particles emitted from a target or the like are deposited. Therefore, it is difficult to be affected by the shape of the object to be processed, and is a film forming method having good step coverage. In particular, the ALD method is suitable for covering the surface of an opening having a high aspect ratio because it has excellent step coverage and excellent thickness uniformity. However, since the ALD method has a relatively slow film forming speed, it may be preferable to use it in combination with other film forming methods such as the CVD method having a high film forming speed.

In the CVD method and ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed according to the flow rate ratio of the source gas. In addition, in the CVD method and the ALD method, for example, by changing the flow rate ratio of the source gas while forming the film, a film whose composition is continuously changed can be formed. In the case of forming a film while changing the flow rate ratio of the raw material gas, the time taken for the film formation can be shortened because the time required for conveyance or pressure adjustment is unnecessary compared to the case of forming a film using a plurality of film formation chambers. Therefore, there are cases where the productivity of the semiconductor device can be increased.

In this embodiment, aluminum oxide is formed as the insulator 214 by a sputtering method. Further, the insulator 214 may have a multilayer structure. For example, a structure in which aluminum oxide is formed by a sputtering method and aluminum oxide is formed on the aluminum oxide by an ALD method may be employed. Alternatively, an aluminum oxide film may be formed by the ALD method, and aluminum oxide may be formed on the aluminum oxide by a sputtering method.

Next, a conductive film serving as the conductor 205 is formed on the insulator 214. The conductive film forming the conductor 205 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In addition, the conductive film used as the conductor 205 can be a multilayer film. In this embodiment, tungsten is formed as a conductive film used as the conductor 205.

Next, the conductive film to be the conductor 205 is processed using a lithography method to form the conductor 205.

Further, in the lithography method, first, the resist is exposed through a mask. Next, a resist mask is formed by removing or remaining the exposed area using a developer. Next, by etching through the resist mask, a conductor, a semiconductor, or an insulator can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, a liquid immersion technique in which a liquid (for example, water) is filled and exposed between the substrate and the projection lens may be used. Further, instead of the above-described light, an electron beam or an ion beam may be used. Further, in the case of using an electron beam or an ion beam, a mask is unnecessary. In addition, for removal of the resist mask, dry etching treatment such as ashing may be performed, wet etching treatment may be performed, wet etching treatment may be performed after dry etching treatment, or dry etching treatment may be performed after the wet etching treatment.

Further, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When using a hard mask, an insulating film or a conductive film to be a hard mask material is formed on the conductive film to be a conductor 205, a resist mask is formed thereon, and a hard mask of a desired shape is formed by etching the hard mask material. can do. Etching of the conductive film used as the conductor 205 may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. After etching the conductive film to be the conductor 205, the hard mask may be removed by etching. On the other hand, if the material of the hard mask does not affect the post process or can be used in the post process, it is not necessary to remove the hard mask.

As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having a parallel plate electrode can be used. The capacitively coupled plasma etching apparatus having a parallel plate electrode may be configured to apply a high frequency power to one electrode of the parallel plate electrode. Alternatively, a configuration may be employed in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode. Alternatively, a configuration in which a high-frequency power source of the same frequency is applied to each of the parallel plate electrodes may be employed. Alternatively, a configuration may be employed in which a high frequency power source having a different frequency is applied to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As a dry etching apparatus having a high-density plasma source, an Inductively Coupled Plasma (ICP) etching apparatus or the like can be used, for example.

Next, an insulating film serving as the insulator 216 is formed over the insulator 214 and over the conductor 205. The insulating film is formed to contact the top and side surfaces of the conductor 205. The insulator to be the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, as the insulating film used as the insulator 216, silicon oxide is formed by the CVD method.

Here, it is preferable that the thickness of the insulating film used as the insulator 216 is equal to or larger than the thickness of the conductor 205. For example, if the thickness of the conductor 205 is 1, the thickness of the insulating film used as the insulator 216 is 1 or more and 3 or less. In this embodiment, the thickness of the conductor 205 is set to 150 nm, and the thickness of the insulating film used as the insulator 216 is set to 350 nm.

Next, by performing CMP (Chemical Mechanical Polishing) treatment on the insulating film used as the insulator 216, a part of the insulating film used as the insulator 216 is removed to expose the surface of the conductor 205. Thereby, the conductor 205 and the insulator 216 having a flat top surface and in contact with the side surfaces of the conductor 205 can be formed (see FIG. 3 ). By improving the flatness of the top surfaces of the insulator 216 and the conductor 205, the crystallinity of the CAAC-OS forming the oxide 230b and the oxide 230c can be improved.

In addition, the method of manufacturing the insulator 216 and the conductor 205 is not limited to the above. For example, an insulating film serving as the insulator 216 may be formed over the insulator 214, an opening is provided in the insulating film, and a conductor 205 may be formed so as to be buried in the opening.

Next, an insulator 222 is formed on the insulator 216 and the conductor 205. It is preferable to form an insulator containing oxides of one or both of aluminum and hafnium as the insulator 222. In addition, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) or the like as an insulator containing an oxide of one or both of aluminum and hafnium. Insulators containing oxides of one or both of aluminum and hafnium have barrier properties to oxygen, hydrogen, and water. Since the insulator 222 has a barrier property to hydrogen and water, diffusion of hydrogen and water included in the structure provided around the transistor 200 to the inside of the transistor 200 through the insulator 222 is suppressed. , It is possible to suppress the generation of oxygen vacancies in the oxide 230.

The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, an insulator 224 is formed on the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, it is preferable to perform heat treatment. The heat treatment may be performed at 250°C or more and 650°C or less, preferably 300°C or more and 500°C or less, and more preferably at 320°C or more and 450°C or less. In addition, the heat treatment is performed in a nitrogen or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. In addition, the heat treatment may be performed under reduced pressure. Alternatively, heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the released oxygen after heat treatment in a nitrogen or inert gas atmosphere.

In this embodiment, as a heat treatment, after the film formation of the insulator 224, a treatment for 1 hour is performed at a temperature of 400°C in a nitrogen atmosphere. By the heat treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. Further, the heat treatment may be performed at a timing such as after the insulator 222 is formed.

Here, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use a device having a power source for generating high-density plasma using microwaves, for example. Alternatively, you may have a power supply that applies RF (Radio Frequency) to the substrate side. By using the high-density plasma, oxygen radicals of high density can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, a plasma treatment containing oxygen may be performed to supplement the released oxygen. In addition, by appropriately selecting the conditions for the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In that case, it is not necessary to perform heat treatment.

Next, an oxide film 230A and an oxide film 230B are sequentially formed on the insulator 224 (see FIG. 3). In addition, it is preferable that the oxide film is continuously formed without being exposed to the atmosphere. By forming a film without opening to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be kept clean. have.

The oxide film 230A and the oxide film 230B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and noble gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased. Further, when the oxide film is formed by sputtering, the In-M-Zn oxide target or the like can be used. In addition, an alternating current (AC) power source such as a direct current (DC) power source or a high frequency (RF) power source is connected to the target, and necessary power may be applied according to the electrical conductivity of the target.

Particularly, when the oxide film 230A is formed, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.

In addition, when the oxide film 230B is formed by the sputtering method, when the oxygen-deficient oxide semiconductor is formed by making the ratio of oxygen contained in the sputtering gas 1% or more and 30% or less, preferably 5% or more and 20% or less, Is formed. A transistor in which an oxygen-deficient oxide semiconductor is used in the channel formation region can obtain a relatively high field effect mobility. Further, by forming a film while heating the substrate, the crystallinity of the oxide film can be improved. However, one embodiment of the present invention is not limited thereto. When the oxide film to be the oxide 230b is formed by the sputtering method, when the ratio of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, the oxygen-excessive oxide semiconductor Is formed. A transistor in which an oxygen-excessive oxide semiconductor is used in the channel formation region has relatively high reliability.

In this embodiment, the oxide film 230A is sputtered by In:Ga:Zn=1:1:0.5 [atomic ratio] (2:2:1 [atomic ratio]), or 1:3:4 [atomic ratio] The film is formed using the target of. Further, the oxide film 230B is formed by a sputtering method using a target of In:Ga:Zn=4:2:4.1 [atomic ratio]. Further, each oxide film is preferably formed in accordance with the characteristics required of the oxide 230 by appropriately selecting the film formation conditions and the atomic ratio.

Here, it is preferable to form a film without exposing the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B to the atmosphere. For example, a multi-chamber film forming apparatus may be used.

Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed. In this embodiment, after performing the treatment for 1 hour at a temperature of 400°C in a nitrogen atmosphere, the treatment is continuously performed for 1 hour at a temperature of 400°C in an oxygen atmosphere.

Next, the oxide film 230A and the oxide film 230B are processed into an island shape to form an oxide 230a and an oxide 230b. In addition, in the above process, there is a case where the thickness of the region of the insulator 224 that does not overlap with the oxide 230a becomes thin (see FIG. 4 ).

Here, the oxide 230a and the oxide 230b are formed so that at least a portion of the oxide 230a and the oxide 230b overlap the conductor 205. Further, the angle formed between the side surfaces of the oxide 230a and the oxide 230b and the upper surface of the insulator 222 may be reduced. In that case, the angle between the side surfaces of the oxide 230a and the oxide 230b and the top surface of the insulator 222 is preferably 60° or more and less than 70°. By setting it as such a shape, the covering property of the insulator 256 etc. is improved in a later process, and defects, such as a cavity, can be reduced. Alternatively, the side surface of the oxide 230b may be substantially perpendicular to the upper surface of the insulator 222. By making the side surfaces of the oxide 230a and the oxide 230b substantially perpendicular to the top surface of the insulator 222, when a plurality of transistors 200 are provided, a small area and high density can be achieved.

In addition, it has a curved surface between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter, also referred to as round shape). The curved surface has a radius of curvature of 3 nm or more and 10 nm or less, and preferably 5 nm or more and 6 nm or less, for example at the end of the oxide 230b layer. By not having an angle at the end, the coating property of the film in a subsequent film forming step is improved.

Further, the processing of the oxide film 230A and the oxide film 230B may be performed using a lithography method. In addition, a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing.

Further, by performing a treatment such as dry etching, impurities due to etching gas or the like may adhere or diffuse on the surface or inside of the oxide 230a and the oxide 230b. Examples of impurities include fluorine or chlorine.

Washing is performed to remove the impurities and the like. As a cleaning method, there are wet cleaning using a cleaning liquid or the like, plasma treatment using plasma, or cleaning by heat treatment, and the cleaning may be performed in appropriate combinations.

As wet washing, a washing treatment may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, or hydrofluoric acid with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.

Subsequently, heat treatment may be performed. As the conditions of the heat treatment, the above-described heat treatment conditions can be used. Alternatively, it is preferable to perform heat treatment before forming the insulating film 256A. The heat treatment may be performed at 100°C or higher and 400°C or lower, and may be performed at 200°C, for example. Alternatively, it is preferable to perform it at the same temperature as the film formation temperature of the insulating film 256A. Here, the film formation temperature is not limited to the substrate temperature during film formation, and includes the case of the set temperature of the film formation apparatus. For example, when the insulating film 256A is formed at 200°C, the heat treatment is preferably set at 200°C. The heat treatment is preferably performed under reduced pressure, and for example, may be performed in a vacuum atmosphere. The vacuum atmosphere is maintained by exhausting it with a turbo molecular pump or the like. In a vacuum atmosphere, the pressure in the processing chamber may be 1 × 10 ^-2 Pa or less, preferably 1 × 10 ^-3 Pa or less.

Next, an insulating film 256A is formed by covering the oxide 230a and the oxide 230b (see Fig. 4). The insulating film 256A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

It is preferable to use an insulating film having a function of suppressing diffusion of oxygen or impurities such as hydrogen as the insulating film 256A. For example, it is preferable to form an aluminum oxide film by sputtering. Oxygen can be injected into the insulator 224 by forming an aluminum oxide film using a gas containing oxygen by a sputtering method. That is, the insulator 224 may have excess oxygen. Further, as the insulating film 256A, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an insulator containing aluminum nitride, aluminum nitride titanium, titanium nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, nitride Silicon, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having pores can be used.

Further, as the insulating film 256A, aluminum oxide may be formed while heating the substrate at a high temperature. When the insulating film 256A is formed, the heating temperature of the substrate may be 200°C or higher, preferably 250°C or higher, and more preferably 350°C or higher.

Further, the insulating film 256A may have a laminated structure.

Next, a dummy gate film to be the dummy gate layer 262A is formed on the insulating film 256A.

The dummy gate film used as the dummy gate layer 262A is processed and used as a dummy gate. The dummy gate is a temporary gate electrode. That is, a temporary gate electrode is formed by processing a dummy gate film that becomes the dummy gate layer 262A, and the dummy gate is removed in a later step, and instead, a gate electrode made of a conductive film or the like is formed. Therefore, it is preferable to use a film that can be easily micro-processed and easily removed for the dummy gate film used as the dummy gate layer 262A.

The dummy gate film to be the dummy gate layer 262A may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, an insulator, a semiconductor, or a conductor can be used. Specifically, silicon such as polysilicon, microcrystalline silicon, and amorphous silicon, metal films such as aluminum, titanium, and tungsten may be used. Alternatively, a film containing carbon, a spin on glass (SOG), a resin film, or the like may be formed by using a coating method. Examples include photoresist, polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic. By forming the SOG and resin film by a coating method, the surface of the dummy gate film can be made flat. In this way, by making the surface of the dummy gate film flat, fine processing becomes easy and removal is also easy.

Further, the dummy gate film used as the dummy gate layer 262A may be a multilayer film using different film types. For example, the dummy gate layer to be the dummy gate layer 262A may be a two-layer structure in which a conductive layer and a resin layer are formed on the conductive layer. When the dummy gate film has such a structure, for example, in a subsequent CMP process, the conductive film may function as a stopper film for the CMP process. Alternatively, there may be cases where detection of the end point of the CMP processing is possible, and reduction of processing deviation may be possible.

Next, the dummy gate film used as the dummy gate layer 262A is etched by a lithography method to form the dummy gate layer 262A (see Fig. 5). The dummy gate layer 262A is formed so that at least a portion of the dummy gate layer 262A overlaps the conductor 205 and the oxide 230.

Next, using the dummy gate layer 262A as a mask, a dopant 257 is added to the oxide 230b (see Fig. 5). Accordingly, the layer 253a and the layer 253b including the dopant 257 are formed in a region of the oxide 230b that does not overlap with the dummy gate layer 262A. In addition, in FIG. 5, the dopant 257 is diffused and added from the oxide 230b to a region overlapping the dummy gate layer 262A. Therefore, a portion of the layer 253a and the layer 253b is also formed in a region overlapping the dummy gate layer 262A. In this way, the distance between the layer 253a and the layer 253b, that is, the channel length, can be controlled by the length of the dummy gate layer 262A in the channel length direction.

As a method of adding the dopant 257, an ion implantation method in which the ionized raw material gas is separated by mass and added, an ion doping method in which the ionized raw material gas is added without mass separation, and a plasma immersion ion implantation method can be used. In the case of performing mass separation, the ionic species to be added and their concentration can be strictly controlled. On the other hand, when mass separation is not performed, high concentration of ions can be added in a short time. Further, an ion doping method in which clusters of atoms or molecules are generated and ionized may be used. Further, the dopant may be referred to as ions, donors, acceptors, impurities, or elements.

As the dopant 257, an element forming an oxygen vacancie or an element bonding to an oxygen vacancie may be used. Examples of such an element include boron or phosphorus. Further, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas, or the like may be used. Further, representative examples of rare gases include helium, neon, argon, krypton, and xenon. In addition, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium Any one or a plurality of metal elements selected from metal elements such as and lanthanum may be added. Among the above, boron and phosphorus are preferable as the dopant 257. In the case where boron or phosphorus is used as the dopant 257, equipment in the production line for amorphous silicon or low-temperature polysilicon can be used, so that investment in equipment can be suppressed.

In addition, in FIG. 5, the dopant 257 is added substantially vertically to the top surface of the insulator 214, but the present invention is not limited thereto, and the dopant 257 may be added inclined with respect to the top surface of the insulator 214. By adding a dopant inclined with respect to the upper surface of the insulator 214, it becomes easy to form the layer 253a and the layer 253b in a part of the region overlapping with the dummy gate layer 262A.

In addition, in the manufacturing method of this embodiment, the dopant 257 is added to the oxide 230 via the insulating film 256A. With the above-described preparation method, the dopant 257 is also added to the insulating film 256A. That is, both the oxide 230 and the insulating film 256A have elements included in the dopant 257. In addition, when the insulating film 256A has excess oxygen, the dopant 257 may suppress the diffusion of excess oxygen to the outside.

As described above, by forming the layer 253, the conductor 260 formed in a later process can be self-aligned between the layer 253a and the layer 253b.

Next, an insulating film 280A is formed over the insulating film 256A and the dummy gate layer 262A (see Fig. 6). The insulating film 280A may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the insulating film 280A and a portion of the dummy gate layer 262A are removed until a portion of the dummy gate layer 262A is exposed, thereby forming the insulator 280 and the dummy gate 262 (see FIG. 7 ). ). It is preferable to use CMP processing for the formation of the insulator 280 and the dummy gate 262.

Further, as described above, by using the dummy gate layer 262A as a two-layered film in which a conductive film and a resin film are formed on the conductive film, for example, the conductive film functions as a CMP stopper film in the CMP process. There are cases. Alternatively, the conductive film may be capable of detecting the end point of the CMP process, and in some cases, the variation in height of the dummy gate 262 may be reduced. As shown in FIG. 7B, the upper surface of the dummy gate 262 and the upper surface of the insulator 280 substantially coincide.

Next, a part of the dummy gate 262 and the insulating film 256A overlapping the dummy gate 262 is removed to form the opening 263 (see FIG. 8). The dummy gate 262 and the insulating film 256A may be removed using wet etching, dry etching, or ashing. Alternatively, a plurality of the above treatments may be appropriately combined and performed. For example, after ashing treatment, wet etching treatment or the like can be performed. The insulator 256 is formed by removing a part of the insulating film 256A. By removing the dummy gate 262 and the insulating film 256A, a part of the surface of the oxide 230b is exposed from the opening 263. In this case, a part of the surface of the layer 253 may be exposed from the opening 263.

Next, it is preferable to perform heat treatment before forming the oxide film 230C. The heat treatment may be performed at 100°C or higher and 400°C or lower, and may be performed at 200°C, for example. Alternatively, it is preferable to perform it at the same temperature as the film formation temperature of the oxide film 230C. Here, the film formation temperature is not limited to the substrate temperature during film formation, and includes the case of the set temperature of the film formation apparatus. For example, when the oxide film 230C is formed at 300°C, it is preferable that the heat treatment be 300°C. The heat treatment is preferably performed under reduced pressure, and for example, may be performed in a vacuum atmosphere. The vacuum atmosphere is maintained by exhausting it with a turbo molecular pump or the like. In a vacuum atmosphere, the pressure in the processing chamber may be 1 × 10 ^-2 Pa or less, preferably 1 × 10 ^-3 Pa or less.

Next, an oxide film 230C is formed so as to be buried in the opening 263. Further, after the heat treatment, it is preferable to continuously perform film formation of the oxide film 230C without exposure to the atmosphere. For example, it is preferable to continuously perform the heat treatment and the film formation treatment in different chambers using a multi-chamber type film formation apparatus or the like described later. By performing such a treatment, impurities such as moisture, hydrogen, and carbon adsorbed on the surfaces of the oxide 230a and oxide 230b are removed, and further, the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b are reduced. I can make it. Impurities removed by the heat treatment include impurities having a bond of hydrogen and carbon, impurities having a bond of hydrogen and oxygen, and the like. In addition, by continuously performing heat treatment and film formation without exposure to outside air, impurities such as hydrogen can be prevented from entering the oxide 230 again.

The oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In accordance with the characteristics required for the oxide film 230C, an oxide film to be the oxide film 230C may be formed by using a film forming method such as the oxide film 230A or the oxide film 230B. As the oxide film 230C, an In-Ga-Zn oxide or an oxide not containing In can be used. As the oxide not containing In, Ga-Zn oxide, gallium oxide, or the like can be used. Further, as the oxide film 230C, a laminate structure of an In-Ga-Zn oxide and an oxide not containing In may be used. By sputtering the oxide film 230C, In:Ga:Zn=1:3:4[atomic ratio], 4:2:4.1[atomic ratio], Ga:Zn=2:1[atomic ratio], or Ga:Zn The film is formed using a target of =2:5 [Atomic Ratio]. In this embodiment, as the oxide film 230C, an oxide film serving as the oxide 230c is formed by using a target of 1:3:4 [atomic number ratio] by sputtering.

Further, the oxide film 230C may have a stacked structure consisting of a first oxide film and a second oxide film on the first oxide film, and a first oxide film is formed using the same target as the target used to form the oxide film 230B. , The second oxide film may be formed using the same target as the target used for forming the oxide film 230A.

It is preferable that the oxide film 230C is formed while heating the substrate. At this time, by setting the substrate temperature to 300°C or higher, oxygen vacancies in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. Further, for example, the film may be formed at the same temperature as the film formation temperature of the insulating film 250A described later. Further, by forming a film while heating the substrate in this manner, the crystallinity of the oxide 230a, the oxide 230b, and the oxide film 230C can be improved.

In particular, at the time of forming the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%. Further, by forming a film while heating the substrate, the crystallinity of the oxide film can be improved.

Next, it is preferable to perform heat treatment before forming the insulating film 250A. The heat treatment may be performed at 100°C or higher and 400°C or lower, and may be performed at 200°C, for example. Alternatively, it is preferable to perform it at the same temperature as the film forming temperature of the insulating film 250A. Here, the film formation temperature is not limited to the substrate temperature during film formation, and includes the case of the set temperature of the film formation apparatus. For example, when the insulating film 250A is formed at 350°C, it is preferable that the heat treatment be 350°C. The heat treatment is preferably performed under reduced pressure, and for example, may be performed in a vacuum atmosphere. The vacuum atmosphere is maintained by exhausting it with a turbo molecular pump or the like. In a vacuum atmosphere, the pressure in the processing chamber may be 1 × 10 ^-2 Pa or less, preferably 1 × 10 ^-3 Pa or less.

Next, an insulating film 250A is formed. The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 250A, it is preferable to form a film of silicon oxide, hafnium oxide, gallium oxide, or the like using the ALD method. For example, as the insulating film 250A, a laminated film of silicon oxide and gallium oxide on silicon oxide may be used. Further, the film forming temperature when forming the insulating film 250A is 300°C or more and less than 450°C, preferably 300°C or more and less than 400°C, and particularly preferably around 350°C. For example, by forming the insulating film 250A at 350°C, an insulator with few impurities can be formed.

Further, oxygen can be introduced into the insulating film 250A by exciting oxygen with microwaves to generate a high-density oxygen plasma, and exposing the insulating film 250A to the oxygen plasma.

Further, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, the moisture concentration and the hydrogen concentration of the insulating film 250A can be reduced.

Next, a conductive film 260Aa and a conductive film 260Ab are formed. The conductive film 260Aa and the conductive film 260Ab may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to use the CVD method. In this embodiment, the conductive film 260Aa is formed by using the ALD method, and the conductive film 260Ab is formed by using the CVD method (see Fig. 9).

Next, by polishing the oxide film 230C, the insulating film 250A, the conductive film 260Aa, and the conductive film 260Ab until the insulator 280 is exposed by CMP treatment, the oxide 230c and the insulator 250 ), and a conductor 260 (conductor 260a and conductor 260b) (see Fig. 10).

Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, the moisture concentration and the hydrogen concentration of the insulator 280 may be reduced. Alternatively, it is preferable to perform heat treatment before forming the insulating film to be the insulator 274. The heat treatment may be performed at 100°C or higher and 400°C or lower, and may be performed at 200°C, for example. Alternatively, it is preferable to perform it at the same temperature as the film formation temperature of the insulating film. Here, the film formation temperature is not limited to the substrate temperature during film formation, and includes the case of the set temperature of the film formation apparatus. For example, when the insulating film is formed at 250°C, it is preferable that the heat treatment be 250°C. The heat treatment is preferably performed under reduced pressure, and for example, may be performed in a vacuum atmosphere. The vacuum atmosphere is maintained by exhausting it with a turbo molecular pump or the like. In a vacuum atmosphere, the pressure in the processing chamber may be 1 × 10 ^-2 Pa or less, preferably 1 × 10 ^-3 Pa or less.

Next, an insulating film serving as the insulator 274 is formed on the insulator 280 (see FIG. 10). The insulating film to be the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film used as the insulator 274, it is preferable to form an aluminum oxide film by, for example, sputtering. By forming an aluminum oxide film by a sputtering method, diffusion of hydrogen contained in the insulator 280 into the oxide 230 may be suppressed in some cases.

Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, the moisture concentration and the hydrogen concentration of the insulator 280 may be reduced.

Next, an insulator to be the insulator 281 may be formed over the insulator 274. The insulating film to be the insulator 281 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see Fig. 10).

Next, openings reaching the layers 253a and 252b are formed in the insulator 256, the insulator 280, the insulator 274, and the insulator 281. The formation of the opening may be performed using a lithography method.

Next, an insulating film serving as the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241. The insulating film may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. As the insulating film used as the insulator 241, it is preferable to use an insulating film having a function of suppressing transmission of oxygen. For example, it is preferable to form an aluminum oxide film by the ALD method. Further, a silicon nitride film may be formed by using an ALD method or a CVD method. When a silicon nitride film is formed using the ALD method, a precursor containing silicon and halogen, or a precursor of aminosilanes can be used. As a precursor including silicon and halogen, SiCl ₄ , SiH ₂ Cl ₂ , Si ₂ Cl ₆ , Si ₃ Cl ₈ and the like may be used. Further, as a precursor of aminosilanes, monovalent, divalent, or trivalent aminosilanes can be used. In addition, ammonia or hydrazine can be used as the nitriding gas. In addition, anisotropic etching may be performed by, for example, a dry etching method or the like. By having the sidewall portion of the opening in such a configuration, it is possible to suppress transmission of oxygen from the outside and to prevent oxidation of the next formed conductor 240a and conductor 240b. In addition, it is possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductor 240a and the conductor 240b.

Next, a conductive film to be the conductor 240a and the conductor 240b is formed. It is preferable that the conductor 240a and the conductive film serving as the conductor 240b include a conductor having a function of suppressing diffusion of impurities such as water and hydrogen. For example, it can be laminated with tantalum nitride, titanium nitride, tungsten, molybdenum, copper, or the like. The conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, by performing the CMP treatment, the conductor 240a and a part of the conductive film serving as the conductor 240b are removed to expose the insulator 281. As a result, since the conductive film remains only in the opening, the conductor 240a and the conductor 240b having a flat top surface can be formed (see FIG. 1 ). In addition, a part of the insulator 281 may be removed by the CMP treatment.

As described above, a semiconductor device having the transistor 200 shown in FIG. 1 can be manufactured. As shown in FIGS. 3 to 11, the transistor 200 can be manufactured by using the method of manufacturing the semiconductor device shown in the present embodiment.

According to one embodiment of the present invention, a semiconductor device having a large ON current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high reliability can be provided. Alternatively, a semiconductor device capable of miniaturization or high integration can be provided according to one embodiment of the present invention. Alternatively, according to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having a small off current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high productivity can be provided.

As described above, the configurations, methods, and the like shown in the present embodiment can be used in appropriate combination with the configurations, methods, and the like shown in other embodiments.

(Embodiment 2)

In this embodiment, an embodiment of a semiconductor device will be described with reference to FIGS. 11 and 12.

[Memory 1]

Fig. 11 shows an example of a semiconductor device (storage device) using a capacitive element as an embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200. Further, as the transistor 200, the transistor 200 or the like described in the previous embodiment can be used.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off current, it is possible to maintain the memory contents for a long period by using it in the memory device. That is, since the refresh operation is unnecessary or the frequency of the refresh operation is very small, the power consumption of the memory device can be sufficiently reduced.

In the semiconductor device shown in FIG. 11, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is connected to the transistor 200. ) Is electrically connected to the second gate. The other of the gate of the transistor 300 and the source and drain of the transistor 200 is electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is connected to the other of the electrodes of the capacitor 100. It is electrically connected to the side.

Further, the memory device shown in Fig. 11 is arranged in a matrix, so that a memory cell array can be configured.

<Transistor (300)>

Transistor 300 is provided on the substrate 311, a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 made of a part of the substrate 311, and a source region Alternatively, it has a low resistance region 314a and a low resistance region 314b functioning as a drain region. The transistor 300 may be of a p-channel type and an n-channel type.

Here, in the transistor 300 illustrated in FIG. 11, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so that the conductor 316 is covered with the insulator 315 interposed therebetween. Further, for the conductor 316, a material that adjusts the work function may be used. Such a transistor 300 is also called a FIN transistor because it uses the convex portion of the semiconductor substrate. In addition, you may have an insulator serving as a mask for forming the convex portion by contacting the upper portion of the convex portion. In addition, although the case where the convex part is formed by processing a part of the semiconductor substrate is shown here, the semiconductor film having a convex shape may be formed by processing the SOI substrate.

In addition, the transistor 300 shown in FIG. 11 is an example and is not limited to this structure, and an appropriate transistor may be used according to the circuit configuration and driving method.

<Capacitive element 100>

The capacitive element 100 is provided above the transistor 200. The capacitive element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.

In addition, for example, the conductor 112 and the conductor 110 provided on the conductor 240 may be formed at the same time. In addition, the conductor 112 has a function as a plug or wiring electrically connected to the capacitive element 100, the transistor 200, or the transistor 300.

In Fig. 11, the conductor 112 and the conductor 110 are shown in a single-layer structure, but the structure is not limited to the above configuration, and a stacked structure of two or more layers may be used. For example, a conductor having a barrier property and a conductor having high adhesion to a conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

In addition, the insulator 130 is, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, It is good if hafnium nitride or the like is used, and it can be provided as a laminate or a single layer.

For example, it is preferable to use a laminated structure of a material having a high dielectric strength such as silicon oxynitride and a high-k material for the insulator 130. With the above configuration, the capacitive element 100 can secure sufficient capacity by having a high-k insulator, and the dielectric strength is improved by having an insulator having a large dielectric strength, and the capacitive element 100 Can suppress electrostatic breakdown.

In addition, as an insulator of a high-k material (material with a high relative permittivity), gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, and oxides having silicon and hafnium , Oxynitride having silicon and hafnium, or nitride having silicon and hafnium.

On the other hand, materials with high dielectric strength (materials with low relative dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, and carbon and nitrogen. Silicon oxide, silicon oxide having pores, or resin.

<Wiring layer>

An interlayer film, a wiring, and a wiring layer provided with a plug or the like may be provided between the structures. In addition, a plurality of wiring layers may be provided according to design. Here, a conductor having a function as a plug or wiring may be given the same reference numeral across a plurality of structures. In addition, in this specification and the like, a wiring and a plug electrically connected to the wiring may be integrally formed. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided as an interlayer film on the transistor 300. In addition, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 include a conductor 328 and a conductor 330 that are electrically connected to the capacitor 100 or the transistor 200. Is buried. Further, the conductor 328 and the conductor 330 function as a plug or wiring.

In addition, the insulator functioning as an interlayer film may function as a planarization film covering the uneven shape below it. For example, the upper surface of the insulator 322 may be flattened by a planarization treatment using a chemical mechanical polishing (CMP) method or the like in order to increase the flatness.

A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 11, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked and provided. Further, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring.

Similarly, the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218 and a conductor (conductor 205) constituting the transistor 200. . Further, the conductor 218 has a function as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. In addition, an insulator 150 is provided over the conductor 120 and the insulator 130.

As an insulator that can be used as the interlayer film, there are oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides and the like having insulating properties.

For example, by using a material having a low relative dielectric constant for an insulator functioning as an interlayer film, it is possible to reduce parasitic capacitance generated between wirings. Therefore, it is better to select a material according to the function of the insulator.

For example, it is preferable that the insulator 150, the insulator 212, the insulator 352, and the insulator 354 have an insulator having a low relative dielectric constant. For example, the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with carbon and nitrogen, silicon oxide with pores , Or it is preferable to have a resin or the like. Alternatively, the insulator may include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with carbon and nitrogen, or silicon oxide with pores. , It is preferable to have a laminated structure of resin. Since silicon oxide and silicon oxynitride are thermally stable, when combined with a resin, it is possible to obtain a laminated structure that is thermally stable and has a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

In addition, one or both of the conductor 112 or the insulator 130 and the insulator 150 provided on the conductor 120 has a resistivity of 1.0Х10 ¹² Ωcm or more and 1.0Х10 ¹⁵ Ωcm or less, preferably 5.0Х10 ¹² Ωcm It is preferable to use an insulator that is not less than 1.0 × ^{10 14} Ωcm, more preferably not less than 1.0 × ^{10 13} Ωcm and not more than 5.0 × ^{10 13} Ωcm. By using one or both of the insulator 130 and the insulator 150 as an insulator having a resistivity as described above, the insulator maintains the insulating property and the transistor 200, the transistor 300, the capacitor 100, and the conductor It is preferable that charges accumulated between wirings such as 112 and conductors 120 can be dispersed, and defects in characteristics or electrostatic breakdown of a transistor and a memory device having the transistor due to the charge can be suppressed. As such an insulator, silicon nitride or silicon nitride oxide can be used.

Further, as an insulator having the above-described resistivity, the insulator 140 may be provided in the lower layer of the conductor 112. In this case, an insulator 140 is formed over the insulator 281, and an opening is formed in the insulator 140, the insulator 281, the insulator 274, the insulator 280, the insulator 256, etc., and an insulator in the opening The formation of the 241, or the formation of the conductor 240 electrically connected to the transistor 200, the conductor 218, and the like may be performed. Materials such as the insulator 130 or the insulator 150 may be used for the insulator 140.

In addition, a transistor using an oxide semiconductor can be surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen, thereby stabilizing the electrical characteristics of the transistor. Therefore, for the insulator 210 and the insulator 350, an insulator having a function of suppressing the transmission of impurities such as hydrogen and oxygen may be used.

As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, Insulators including zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or as a laminate. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, Alternatively, a metal oxide such as tantalum oxide, silicon nitride oxide, or silicon nitride may be used.

Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, A material containing one or more types of metal elements selected from beryllium, indium, ruthenium, and the like can be used. Further, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, and silicide such as nickel silicide may be used.

For example, as the conductor 328, the conductor 330, the conductor 356, the conductor 218, and the conductor 112, metal materials, alloy materials, and metal nitrides formed of the above materials A material or a conductive material such as a metal oxide material can be used as a single layer or laminated. It is preferable to use a high melting point material such as tungsten or molybdenum which has both heat resistance and conductivity, and it is particularly preferable to use tungsten. Alternatively, it is preferably formed of a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, wiring resistance can be lowered.

<<Wire or plug in layer provided with oxide semiconductor>>

In addition, when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region in the vicinity of the oxide semiconductor may be provided. In that case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and the conductor provided to the insulator having the excess oxygen region.

For example, in FIG. 11, it is preferable to provide an insulator 241 between the insulator 224 and the conductor 240. In particular, the insulator 241 is preferably provided by holding the insulator 222 and the insulator 256 in which the insulator 224 having an excess oxygen region is sandwiched. Since the insulator 241, the insulator 222, and the insulator 256 are provided in contact with each other, the insulator 224 can be sealed by an insulator having barrier properties. In addition, the insulator 241 is preferably in contact with the insulator 280 and a part of the insulator 281. Since the insulator 241 extends to the insulator 280 and the insulator 281, diffusion of oxygen or impurities can be further suppressed.

That is, by providing the insulator 241, it is possible to suppress the absorption of excess oxygen of the insulator 224 into the conductor 240. Further, by having the insulator 241, it is possible to suppress diffusion of hydrogen, which is an impurity, to the transistor 200 through the conductor 240.

In addition, as the insulator 241, an insulating material having a function of suppressing diffusion of oxygen and impurities such as water or hydrogen is preferably used. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, in addition to this, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide or silicon nitride, etc. can be used. have.

The above is a description of the configuration example. By using this configuration, reliability can be improved while suppressing fluctuations in electrical characteristics in a semiconductor device using a transistor having an oxide semiconductor. Alternatively, a transistor having an oxide semiconductor having a large ON current can be provided. Alternatively, a transistor having an oxide semiconductor having a small off current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

[Memory Device 2]

Fig. 12 shows an example of a memory device using a semiconductor device as one embodiment of the present invention. The memory device shown in FIG. 12 has a transistor 400 in addition to the semiconductor device having the transistor 200, the transistor 300, and the capacitor 100 shown in FIG. 11. Further, as the transistor 200, the transistor 200 or the like described in the previous embodiment can be used.

The transistor 400 may control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 and the second gate of the transistor 200 are connected. When the negative potential of the second gate of the transistor 200 is maintained with the above configuration, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source becomes 0V. In the transistor 400, since the drain current when the second gate voltage and the first gate voltage are 0V is very small, even if power is not supplied to the transistor 200 and the transistor 400, the second gate voltage of the transistor 200 is The negative potential of the gate can be maintained for a long time. Thereby, the memory device including the transistor 200 and the transistor 400 can retain the memory contents for a long period of time.

Accordingly, in FIG. 12, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. In addition, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is It is electrically connected to the back gate. The other of the gate of the transistor 300 and the source and drain of the transistor 200 is electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is connected to the other of the electrodes of the capacitor 100. It is electrically connected to the side. The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, and the wiring 1009 is electrically connected to the back gate of the transistor 400. The wiring 1010 is electrically connected to the drain of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

In addition, the memory device shown in FIG. 12 is arranged in a matrix like the memory device shown in FIG. 11, so that a memory cell array can be configured. In addition, one transistor 400 may control the second gate voltage of the plurality of transistors 200. Therefore, it is preferable to provide a smaller number of transistors 400 than transistors 200.

<Transistor (400)>

The transistor 400 is formed on the same layer as the transistor 200 and is a transistor that can be manufactured in parallel. The transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) that functions as a first gate electrode, and a conductor 405 (conductor 405a) that functions as a second gate electrode. And a conductor 405b), an insulator 222 functioning as a gate insulating layer, an insulator 224, and an insulator 450, an oxide 430c having a region in which a channel is formed, and a layer functioning as a source. 453a, oxide 431a, and oxide 431b, layer 453b functioning as a drain, oxide 432a, and oxide 432b, conductor 440 (conductor 440a and conductive Sieve (440b)).

In transistor 400, conductor 405 is the same layer as conductor 205. The oxide 431a, the oxide 432a, and the oxide 230a are the same layer, and the oxide 431b, the oxide 432b, and the oxide 230b are the same layer. The layers 453a and 453b are layers formed by the same process as the layers 253a and 253b. The oxide 430c is the same layer as the oxide 230c. The insulator 450 is the same layer as the insulator 250. Conductor 460 is the same layer as conductor 260.

In addition, structures formed on the same layer can be formed simultaneously. For example, the oxide 430c can be formed by processing an oxide film that becomes the oxide 230c.

In the oxide 430c functioning as an active layer of the transistor 400, like the oxide 230 or the like, oxygen vacancies are reduced and impurities such as hydrogen or water are reduced. Accordingly, the threshold voltage of the transistor 400 can be made larger than 0V, the off current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0V can be very small.

<<Dicing Line>>

Hereinafter, a dicing line (sometimes called a scribe line, a dividing line, or a cutting line) provided when a plurality of semiconductor devices are obtained in a chip shape by dividing a large-area substrate for each semiconductor element will be described. As a dividing method, for example, a groove (dicing line) for dividing a semiconductor element is first formed on a substrate, and then a dicing line is used to divide it into a plurality of semiconductor devices (dividing).

Here, for example, as shown in FIG. 12, it is preferable to design the area where the insulator 256 and the insulator 222 contact to be a dicing line. That is, an opening is provided in the insulator 224 in the vicinity of a region serving as a dicing line provided at the edge of the memory cell and the transistor 400 having the plurality of transistors 200. In addition, an insulator 256 is provided to cover the side surface of the insulator 224.

That is, the insulator 222 and the insulator 256 come into contact with the opening provided in the insulator 224. For example, at this time, the insulator 222 and the insulator 256 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 256 with the same material and the same method, adhesion can be improved. It is preferred to use aluminum oxide, for example.

By the above structure, the insulator 224, the transistor 200, and the transistor 400 may be surrounded by the insulator 222 and the insulator 256. Since the insulator 222 and the insulator 256 have a function of suppressing the diffusion of oxygen, hydrogen, and water, the substrate is divided into a plurality of chips by dividing the substrate for each circuit region in which the semiconductor element shown in this embodiment is formed. It is possible to prevent impurities such as hydrogen or water from being mixed from the side direction of the substrate and spreading to the transistors 200 and 400.

In addition, due to the above structure, it is possible to prevent excess oxygen in the insulator 224 from diffusing to the outside of the insulator 256 and the insulator 222. Accordingly, excess oxygen in the insulator 224 is efficiently supplied to the transistor 200 or the oxide in which a channel in the transistor 400 is formed. Due to the oxygen, oxygen vacancies of oxides in which channels in the transistor 200 or the transistor 400 are formed may be reduced. Accordingly, the transistor 200 or the oxide in which the channel in the transistor 400 is formed may be an oxide semiconductor having a low density of defect states and stable characteristics. That is, it is possible to improve reliability while suppressing fluctuations in electrical characteristics of the transistor 200 or the transistor 400.

This embodiment can be implemented in appropriate combination with the structures described in other embodiments and the like.

(Embodiment 3)

In this embodiment, using Figs. 13 and 14, a transistor using an oxide semiconductor according to an embodiment of the present invention (hereinafter, sometimes referred to as an OS transistor), and a memory device to which a capacitor is applied (hereinafter, It may be referred to as an OS memory device). The OS memory device is a memory device having at least a capacitive element and an OS transistor that controls charging and discharging of the capacitive element. Since the off current of the OS transistor is very small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

<Configuration example of storage device>

13A shows an example of the configuration of an OS memory device. The memory device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. Further, the wiring is a wiring connected to a memory cell of the memory cell array 1470, and details will be described later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA through the output circuit 1440. Further, the row circuit 1420 has, for example, a row decoder, a word line driver circuit, or the like, and can select a row to be accessed.

A low power supply voltage VSS, a high power supply voltage VDD for the peripheral circuit 1411, and a high power supply voltage VIL for the memory cell array 1470 are supplied to the memory device 1400 as power supply voltages from the outside. In addition, control signals CE, WE, and RE, address signals ADDR, and data signals WDATA are externally input to the memory device 1400. The address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit.

The control logic circuit 1460 processes input signals CE, WE, and RE from the outside to generate a control signal of a row decoder or a column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 1460 is not limited thereto, and a control signal of a row decoder or a column decoder may be generated by processing other input signals as necessary.

The memory cell array 1470 includes a plurality of memory cells MC and a plurality of wirings arranged in a matrix. In addition, the number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined according to the configuration of the memory cells MC, the number of memory cells MC in one column, and the like. Also, the number of wires connecting the memory cell array 1470 and the column circuit 1430 is determined according to the configuration of the memory cells MC, the number of memory cells MC in one row, and the like.

Further, in Fig. 13A, an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane is illustrated, but the present embodiment is not limited thereto. For example, as shown in FIG. 13B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to be superimposed under the memory cell array 1470.

An example of the configuration of a memory cell applicable to the memory cell MC described above in FIG. 14 will be described.

[DOSRAM]

14A to 14C show examples of the circuit configuration of a memory cell of a DRAM. In this specification and the like, a DRAM using one OS transistor and one capacitive element type memory cell is sometimes referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 14A has a transistor M1 and a capacitor CA. Further, the transistor M1 has a gate (which may be referred to as a front gate) and a back gate.

The first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is the wiring WOL. And the back gate of the transistor M1 is connected to the wiring BGL. The second terminal of the capacitive element CA is connected to the wiring CAL.

The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor element CA. It is preferable to apply a low-level potential to the wiring CAL when writing and reading data. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

Further, the memory cell MC is not limited to the memory cell 1471, and a circuit configuration may be changed. For example, the memory cell MC has a configuration in which the back gate of the transistor M1 is connected to the wiring WOL rather than the wiring BGL, like the memory cell 1472 shown in FIG. 14B. You may do it. Further, for example, the memory cell MC may be a memory cell composed of a transistor M1 having a single gate structure, that is, a transistor M1 not having a back gate, like the memory cell 1473 shown in FIG. 14C. .

When the semiconductor device shown in the above embodiment is used in the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor element 100 can be used as the capacitor element CA. By using the OS transistor as the transistor M1, the leakage current of the transistor M1 can be very low. That is, since the recorded data can be held for a long time by the transistor M1, the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leakage current is very low, it is possible to hold multilevel data or analog data for the memory cells 1471, 1472, and 1473.

Further, in the DOSRAM, as described above, if the sense amplifier is provided so as to be superimposed under the memory cell array 1470, the bit line can be shortened. As a result, the bit line capacity is reduced and the storage capacity of the memory cell can be reduced.

[NOSRAM]

14D to 14G show examples of the circuit configuration of a gain cell type memory cell of a two-transistor, one-capacitive element. The memory cell 1474 shown in FIG. 14D has a transistor M2, a transistor M3, and a capacitor element CB. Further, the transistor M2 has a front gate (in some cases simply referred to as a gate) and a back gate. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 is sometimes referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

The first terminal of the transistor M2 is connected to the first terminal of the capacitor element CB, the second terminal of the transistor M2 is connected to the wiring WBL, and the gate of the transistor M2 is connected to the wiring WOL. And the back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the capacitor element CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is the first terminal of the capacitor element CB Is connected with.

The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor element CB. It is preferable to apply a low level potential to the wiring CAL when writing data, holding data, or reading data. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

Further, the memory cell MC is not limited to the memory cell 1474, and the configuration of the circuit can be appropriately changed. For example, the memory cell MC has a configuration in which the back gate of the transistor M2 is connected to the wiring WOL, not the wiring BGL, like the memory cell 1475 shown in FIG. 14E. You may do it. Further, for example, the memory cell MC may be a memory cell composed of a transistor M2 having a single gate structure, that is, a transistor M2 having no back gate, like the memory cell 1476 shown in Fig. 14F. . Further, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into one wiring BIL, like the memory cell 1477 shown in FIG. 14G.

When the semiconductor device shown in the above embodiment is used in the memory cell 1474 or the like, the transistor 200 is used as the transistor M2, the transistor 300 is used as the transistor M3, and the capacitor element CB is used. Capacitive element 100 can be used. By using the OS transistor as the transistor M2, the leakage current of the transistor M2 can be very low. As a result, since the recorded data can be held for a long time by the transistor M2, the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leakage current is very low, multilevel data or analog data can be held in the memory cell 1474. The same is true of the memory cells 1475 to 1477.

Further, the transistor M3 may be a transistor having silicon in the channel formation region (hereinafter, referred to as a Si transistor in some cases). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. Si transistors sometimes have higher field effect mobility than OS transistors. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. Further, by using the Si transistor for the transistor M3, since the transistor M2 can be provided by stacking on the transistor M3, the area occupied by the memory cell can be reduced, and the memory device can be highly integrated.

Further, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, a circuit can be configured using only n-type transistors for the memory cell array 1470.

Further, Fig. 14H shows an example of a gain cell type memory cell of a 3-transistor 1-capacitive element. The memory cell 1478 shown in FIG. 14H has transistors M4 to M6 and a capacitor CC. The capacitive element CC is suitably provided. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The wiring GNDL is a wiring that supplies a low level potential. Further, the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.

The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Further, the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 need not have a back gate.

Further, each of the transistors M5 and M6 may be an n-channel Si transistor or a p-channel Si transistor. Alternatively, the transistors M4 to M6 may be OS transistors, and in this case, a circuit can be configured using only n-type transistors in the memory cell array 1470.

When the semiconductor device shown in the above embodiment is used for the memory cell 1478, the transistor 200 is used as the transistor M4, the transistor 300 is used as the transistors M5 and M6, and the capacitor element CC ), a capacitive element 100 may be used. By using the OS transistor as the transistor M4, the leakage current of the transistor M4 can be very low.

Further, the configurations of the peripheral circuit 1411 and the memory cell array 1470 shown in the present embodiment are not limited to the above. Arrangements or functions of these circuits, wirings connected to the circuits, circuit elements, etc. may be changed, deleted, or added as necessary.

The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments and the like.

(Embodiment 4)

In this embodiment, an example of the chip 1200 on which the semiconductor device of the present invention is mounted is shown using FIG. 15. A plurality of circuits (systems) are mounted on the chip 1200. In this way, a technique for integrating a plurality of circuits (systems) into one chip is sometimes called a system on chip (SoC).

As shown in (A) of Figure 15, the chip 1200 is a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or a plurality of analog calculation unit 1213, one or more A memory controller 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

A bump (not shown) is provided to the chip 1200 and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in FIG. 15B. In addition, a plurality of bumps 1202 are provided on the rear surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.

A memory device such as a DRAM 1221 and a flash memory 1222 may be provided on the motherboard 1203. For example, the DOSRAM shown in the previous embodiment can be used for the DRAM 1221. Further, the NOSRAM shown in the previous embodiment can be used for the flash memory 1222, for example.

It is preferable that the CPU 1211 has a plurality of CPU cores. In addition, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The above-described NOSRAM or DOSRAM can be used for the memory. Further, the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and redefinition calculation. By providing the GPU 1212 with an image processing circuit or redization operation circuit using the oxide semiconductor of the present invention, it is possible to perform image processing and redization operation with low power consumption.

In addition, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, Data transfer between the memory of the CPU 1211 and the GPU 1212, and transfer of the calculation result from the GPU 1212 to the CPU 1211 after the calculation in the GPU 1212 can be performed at high speed.

The analog operation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the above redundant operation circuit may be provided to the analog operation unit 1213.

The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222.

The interface 1215 has an interface circuit for external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, and a game controller. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), or the like can be used.

The network circuit 1216 has a network circuit such as a local area network (LAN). Further, you may have a circuit for network security.

The circuit (system) may be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the chip 1200 can be manufactured at low cost without increasing the manufacturing process.

The PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 may be referred to as a GPU module 1204.

Since the GPU module 1204 has the chip 1200 using SoC technology, its size can be reduced. Further, because of its excellent image processing capability, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (carryable) game machines. In addition, a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a magnetic encoder, a deep Boltzmann machine (DBM), and a deep trust network (DBN) by an integration circuit using the GPU 1212 Since calculations such as can be executed, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in the other embodiments.

(Embodiment 5)

In this embodiment, an application example of a storage device using the semiconductor device according to the above-described embodiment will be described. The semiconductor devices shown in the above-described embodiments include, for example, various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital cameras (including video cameras), recording and playback devices, navigation systems, etc.). ) Can be applied to the memory device. Here, the computer includes a large computer such as a server system in addition to a tablet computer, a notebook computer, and a desktop computer. Alternatively, the semiconductor device shown in the above-described embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and a solid state drive (SSD). Fig. 16 schematically shows some configuration examples of the removable memory device. For example, the semiconductor device shown in the above-described embodiment is processed into a packaged memory chip, and is used in various memory devices and removable memories.

Fig. 16A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device shown in the above-described embodiment can be provided, such as the memory chip 1105 of the substrate 1104.

Fig. 16B is a schematic diagram of the external appearance of the SD card, and Fig. 16C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a board 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By providing the memory chip 1114 on the back side of the substrate 1113 as well, the capacity of the SD card 1110 can be increased. Further, a wireless chip with a wireless communication function may be provided on the substrate 1113. Thereby, it is possible to read and write data in the memory chip 1114 by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above-described embodiment can be provided, such as the memory chip 1114 of the substrate 1113.

FIG. 16D is a schematic diagram of an external appearance of an SSD, and FIG. 16E is a schematic diagram of an internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 also on the rear side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the above-described embodiment can be provided, such as the memory chip 1154 of the substrate 1153.

This embodiment can be implemented in appropriate combination with the structures described in other embodiments and the like.

(Embodiment 6)

The semiconductor device according to one embodiment of the present invention can be used in a processor or chip such as a CPU or GPU. 17 illustrates a specific example of an electronic device including a processor or chip such as a CPU or GPU according to an embodiment of the present invention.

<Electronic devices and systems>

The GPU or chip according to one embodiment of the present invention can be mounted on various electronic devices. Examples of electronic devices include electronic devices having relatively large screens, such as television devices, desktop or notebook personal computers, monitors for computers, digital signage, and large game consoles such as pachinko machines. , Digital cameras, digital video cameras, digital picture frames, mobile phones, portable game consoles, portable information terminals, sound reproduction devices, and the like. In addition, artificial intelligence can be mounted on the electronic device by providing the integrated circuit or chip according to one embodiment of the present invention to the electronic device.

The electronic device of one embodiment of the present invention may have an antenna. By receiving a signal through an antenna, an image or information can be displayed on the display unit. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

Electronic devices of one type of the present invention include sensors (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, It may have a function of measuring current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

The electronic device of one embodiment of the present invention may have various functions. For example, a function to display various information (still images, moving pictures, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to run various software (programs), wireless It may have a communication function, a function of reading a program or data recorded on a recording medium, and the like. 17 shows an example of an electronic device.

[Cell Phone]

Fig. 17A shows a mobile phone (smart phone) which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display portion 5511, and as an input interface, a touch panel is provided on the display portion 5511, and a button is provided on the housing 5510.

The information terminal 5500 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention. As an application using artificial intelligence, for example, an application that recognizes a conversation and displays the content of the conversation on the display unit 5511, the touch panel included in the display unit 5511, recognizes characters, figures, etc. There are applications displayed at 5511, applications that perform biometric authentication such as fingerprints or voiceprints.

[Information terminal 1]

A desktop type information terminal 5300 is shown in FIG. 17B. The desktop type information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

Like the information terminal 5500 described above, the desktop-type information terminal 5300 can execute an application using artificial intelligence by applying a chip of one type of the present invention. Examples of applications using artificial intelligence include design support software, text correction software, and automatic diet generation software. In addition, a new artificial intelligence can be developed by using the desktop-type information terminal 5300.

In addition, although shown in FIGS. 17A and 17B as an example of an electronic device as an electronic device, a smartphone and an information terminal for a desktop can be applied to information terminals other than a smartphone and a desktop information terminal. Examples of information terminals other than information terminals for smartphones and desktops include PDA (Personal Digital Assistant), notebook type information terminals, and workstations.

[Electronic products]

FIG. 17C shows an electric refrigeration refrigerator 5800 which is an example of an electronic product. The electric refrigeration refrigerator 5800 includes a housing 5801, a door 5802 for a refrigerator compartment, a door 5803 for a freezer compartment, and the like.

By applying the chip of one embodiment of the present invention to the electric refrigeration refrigerator 5800, the electric refrigeration refrigerator 5800 having artificial intelligence can be realized. By using artificial intelligence, the electric refrigeration refrigerator 5800 automatically generates a meal based on ingredients stored in the electric refrigeration refrigerator 5800 and the expiration date of the ingredients, or stores them in the electric refrigerator 5800. It can have a function of automatically adjusting the temperature suitable for the food ingredients that are prepared.

In this example, an electric refrigerator has been described as an electronic product, but as other electronic products, for example, vacuum cleaners, microwave ovens, microwave ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners including air conditioners, washing machines, dryers. , An audio visual appliance, and the like.

[Game console]

17D shows a portable game machine 5200 as an example of a game machine. The portable game machine has a housing 5201, a display portion 5202, a button 5203, and the like.

By applying the GPU or chip of one embodiment of the present invention to the portable game machine 5200, the portable game machine 5200 with low power consumption can be realized. In addition, since the power consumption is low, heat generation from the circuit can be reduced, so that the influence on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.

Further, by applying the GPU or chip of one embodiment of the present invention to the portable game machine 5200, a portable game machine 5200 having artificial intelligence can be realized.

Originally, expressions of the progress of the game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program that the game has, but by applying artificial intelligence to the portable game machine 5200, the program of the game Unlimited expression becomes possible. For example, it is possible to express the content that the player asks, the progress of the game, the time of day, and the behavior of a person appearing in the game changes.

In addition, in the case of playing a game that requires a plurality of players with the portable game machine 5200, the game player can be configured artificially by artificial intelligence, so that by making the opponent a game player by artificial intelligence, the game can be played alone. I can.

In Fig. 17D, a portable game machine is shown as an example of the game machine, but the game machine to which the GPU or chip of one embodiment of the present invention is applied is not limited thereto. As a game machine to which the GPU or chip of one embodiment of the present invention is applied, for example, a home stationary game machine, an arcade game machine installed in an amusement facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, etc. I can.

[Move]

The GPU or chip of one embodiment of the present invention can be applied to a mobile vehicle and around a driver's seat of the vehicle.

FIG. 17(E1) shows an automobile 5700 which is an example of a moving body, and FIG. 17(E2) is a view showing a windshield periphery in the interior of the vehicle. In FIG. 17E1, in addition to the display panel 5701, the display panel 5702, and the display panel 5703 provided on the dashboard, a display panel 5704 provided on the pillar is illustrated.

The display panels 5701 to 5703 may provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, a setting of an air conditioner, and the like. In addition, since the display items and layouts displayed on the display panel can be appropriately changed according to the user's taste, design can be improved. The display panels 5701 to 5703 may also be used as lighting devices.

By displaying an image from an imaging device (not shown) provided in the vehicle 5700 on the display panel 5704, the field of view (square) blocked by the filler may be supplemented. That is, by displaying an image from an imaging device provided outside the vehicle 5700, a blind spot can be compensated to increase safety. In addition, by displaying an image that complements the invisible part, safety can be checked more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

Since the GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, the chip can be used, for example, in the automatic driving system of the vehicle 5700. In addition, the chip can be used in a system that performs road guidance and risk prediction. The display panels 5701 to 5704 may be configured to display information such as road guidance and risk prediction.

In addition, although the automobile has been described above as an example of the moving object, the moving object is not limited to the automobile. For example, as a moving object, a train, a monorail, a ship, an air vehicle (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc. may be mentioned, and artificial intelligence is used by applying a chip of one type of the present invention to these moving objects. System can be given.

[Broadcasting system]

The GPU or chip of one embodiment of the present invention can be applied to a broadcasting system.

FIG. 17F schematically shows data transmission in a broadcast system. Specifically, FIG. 17F shows the path until the radio wave (broadcast signal) transmitted from the broadcasting station 5680 is transmitted to the television reception device (TV) 5600 in each home. The TV 5600 includes a reception device (not shown), and a broadcast signal received from the antenna 5650 is transmitted to the TV 5600 through the reception device.

In Fig. 17F, a UHF (Ultra High Frequency) antenna is shown as the antenna 5650, but as the antenna 5650, a BS·110°CS antenna, a CS antenna, or the like can also be applied.

The electric wave 5675A and electric wave 5675B are broadcast signals for terrestrial broadcasting, and the electric wave tower 5670 amplifies the received electric wave 5675A and transmits the electric wave 5675B. In each home, the TV 5600 can watch terrestrial TV broadcasts by receiving the radio wave 5675B from the antenna 5650. Further, the broadcasting system is not limited to the terrestrial broadcasting shown in Fig. 17F, and may be a satellite broadcasting using an artificial satellite or data broadcasting using an optical line.

The above-described broadcasting system may be a broadcasting system using artificial intelligence by applying the chip of one embodiment of the present invention. When broadcasting data is transmitted from the broadcasting station 5680 to the TV 5600 of each home, the broadcasting data is compressed by the encoder, and when the antenna 5650 receives the broadcasting data, it is included in the TV 5600 The broadcast data is restored by a decoder of the receiving device. By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of an encoder, recognition of a display pattern included in a display image can be performed. It can also perform intra-frame prediction using artificial intelligence. In addition, for example, when receiving broadcast data with a low resolution and displaying the broadcast data on a TV 5600 having a high resolution, image interpolation processing such as up-conversion is performed in the restoration of broadcast data by a decoder. I can.

The above-described broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcasting data is increased.

Further, as an application of artificial intelligence to the TV 5600, for example, a recording device having artificial intelligence may be provided for the TV 5600. With such a configuration, it is possible to automatically record a program tailored to the user's taste on the recording device by learning the user's taste with artificial intelligence.

The electronic device described in the present embodiment, the function of the electronic device, an application example of artificial intelligence, its effects, and the like can be appropriately combined with the description of other electronic devices.

This embodiment can be implemented in appropriate combination with the structures described in other embodiments and the like.

200: transistor, 205: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 218: conductor, 222: insulator, 224: insulator, 230: oxide, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230c: oxide, 230C: oxide film, 231: region, 231a: region, 231b: region, 232: region, 232a: region, 232b: region, 234: region, 240: conductor, 240a : Conductor, 240b: conductor, 241: insulator, 241a: insulator, 241b: insulator, 250: insulator, 250A: insulating film, 252: layer, 252b: layer, 253: layer, 253a: layer, 253b: layer, 256 : Insulator, 256A: insulating film, 257: dopant, 260: conductor, 260a: conductor, 260Aa: conductive film, 260Ab: conductive film, 260b: conductor, 262: dummy gate, 262A: dummy gate layer, 263: opening , 274: insulator, 280: insulator, 280A: insulating film, 281: insulator

Claims (5)

As a semiconductor device,
A first oxide,
A second oxide on the first oxide,
A third oxide on the second oxide,
A first insulator on the third oxide,
A conductor on the first insulator,
A second insulator in contact with a part of the upper surface of the second oxide, a part of the side surface of the second oxide, and a part of the side surface of the third oxide,
A third insulator over the second insulator,
A fourth insulator in contact with an upper surface of the third oxide, an upper surface of the first insulator, an upper surface of the conductor, and an upper surface of the third insulator,
The second oxide has a first region, a second region, and a third region positioned between the first region and the second region,
Resistance of the first region and the second region is lower than that of the third region,
The conductor is provided above the third region so as to overlap the third region,
A part of the third oxide, and a part of the first insulator are provided between the side surface of the conductor and the side surface of the third insulator,
The semiconductor device, wherein the second insulator contacts the first region and the second region. The method of claim 1,
The first region and the second region contain one of phosphorus and boron. The method according to claim 1 or 2,
The semiconductor device, wherein the first region and the second region have more oxygen vacancies than the third region. The method according to any one of claims 1 to 3,
The semiconductor device, wherein the first region and the second region contain more hydrogen than the third region. The method according to any one of claims 1 to 4,
The semiconductor device, wherein the third oxide overlaps a part of the first region and a part of the second region.

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