KR20200104561A - Graphics processing unit based on three dimention crossbar network - Google Patents

Abstract

According to an embodiment of an application of the present invention, a graphics processing unit based on a three-dimensional crossbar network includes: a first layer in which a first input wiring formed and which extends to the outside; at least one second layer which is spaced apart from a first layer in parallel and in which a second input wiring is formed; and a monolithic anti-tier via which electrically connects the first and second input wirings perpendicular to the first and second layers, thereby reducing the length of any one of the input wiring and the output wiring to reduce power consumption according to the wiring length.

Description

Graphic processing unit based on 3D crossbar network {GRAPHICS PROCESSING UNIT BASED ON THREE DIMENTION CROSSBAR NETWORK}

The present application relates to a graphic processing unit based on a three-dimensional crossbar network, and more particularly, to a graphic processing unit based on a three-dimensional crossbar network capable of reducing a conventional wiring length.

GPU (Graphics Processing Unit) can run tens of thousands of threads using register files, caches, and shared memory for high data parallelism. . Moreover, the size of the GPU register file is gradually increasing, and accordingly, the power consumption of the register file occupies an important part of the total power consumption of the GPU.

Specifically, the GPU register file may be composed of a register file bank, a crossbar network, an operand collector, and an arbiter. Here, the register file bank may be composed of multiple banks for high throughput of the GPU system.

In particular, the crossbar network can connect the register file bank and the operand collector through massive wires. The power consumption generated by such a large amount of wiring is the largest among the components of the GPU register file, and the length of the large amount of wiring may be an important factor in determining the delay time of the crossbar network.

On the other hand, the TSV-based method, which is a general 3D integration technology, forms an electrode through the TSV by making a hole vertically between two dies. Not suitable for fine-grained architecture.

On the other hand, monolithic 3D integration technology enables high integration density by using very small sized monolithic inter-tier vias (MIVs). In particular, MIVs support much higher alignment precision than TSVs, have low delay, and low dynamic power and leakage power due to excellent electrical characteristics.

Accordingly, in the present application, a graphic processing unit based on a three-dimensional crossbar network using MIVs is provided by simplifying the wiring connection of the crossbar network among the components of the GPU register file and reducing the connection length of the wiring.

An object of the present application is to provide a graphic processing unit based on a three-dimensional crossbar network capable of reducing the power consumption according to the wiring length by reducing the length of any one of the input wiring and the output wiring compared to a two-dimensional crossbar network. For.

In the graphic processing unit based on the 3D crossbar network according to the exemplary embodiment of the present application, a first input wiring is formed, a first layer extending to the outside, spaced apart from the first layer, and a second input wiring is formed. At least one second layer and at least one monolithic anti-tier via electrically connecting the first and second input wires perpendicular to the first and second layers.

In an embodiment, a plurality of tri-state buffers disposed in the same grid pattern are further included in each of the first layer and the at least one second layer.

In an embodiment, further comprising: one input driver positioned at one end along the first input wire and a plurality of output drivers positioned at one end along a plurality of output wires connected to the plurality of tri-state buffers, the One input driver activates a plurality of input wires connected to the plurality of tri-state buffers through the first input wire at a time.

In an embodiment, an external monolithic anti-tier via connecting the plurality of output drivers to each other is further included.

In an embodiment, the number of the at least one monolithic anti-tier via corresponds to the number of the plurality of tri-state buffers.

A graphic processing unit based on a 3D crossbar network according to another exemplary embodiment of the present application includes a first layer on which a first output line is formed, and at least one second layer spaced apart from the first layer in parallel and on which a second output line is formed. And at least one monolithic anti-tier via vertically to the first and second layers and electrically connecting the first and second output wires.

In an embodiment, a plurality of tri-state buffers disposed in the same grid pattern are further included in each of the first layer and the at least one second layer.

In an embodiment, further comprising: one output driver positioned at one end along the first output wiring and a plurality of input drivers positioned at one end along a plurality of input wirings connected to the plurality of three-state buffers, the One output driver activates a plurality of output wires connected to the plurality of tri-state buffers through the first output wire at a time.

In an embodiment, an external monolithic anti-tier via connecting the plurality of input drivers to each other is further included.

In an embodiment, the number of at least one monolithic anti-tier via corresponds to the number of the plurality of tri-state buffers.

The graphic processing unit based on a 3D crossbar network according to the exemplary embodiment of the present application may reduce the power consumption according to the length of the wiring by reducing the length of any one of the input wiring and the output wiring compared to the 2D crossbar network. .

1 is a block diagram of a three-dimensional crossbar network according to an embodiment of the present application.
2 is an embodiment of the 3D crossbar network of FIG. 1.
3 is a plan view of a first layer of FIG. 2.
4 is a plan view of at least one second layer of FIG. 2.
5 is a block diagram of a three-dimensional crossbar network according to another embodiment of the present application.
6 is an embodiment of the 3D crossbar network of FIG. 5.
7 is a plan view of the first layer of FIG. 6.
8 is a plan view of at least one second layer of FIG. 6.
9 is an embodiment of a graphic processing unit based on a 3D crossbar network.

Specific structural or functional descriptions of the embodiments according to the concept of the present application disclosed in the present specification are exemplified only for the purpose of describing the embodiments according to the concept of the present application, and the embodiments according to the concept of the present application are It may be implemented in various forms and is not limited to the embodiments described herein.

Since the embodiments according to the concept of the present application can apply various changes and have various forms, the embodiments will be illustrated in the drawings and described in detail in the present specification. However, this is not intended to limit the embodiments according to the concept of the present application to specific disclosed forms, and includes all changes, equivalents, or substitutes included in the spirit and scope of the present application.

Terms such as first or second may be used to describe various elements, but the elements should not be limited by the terms. The terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of the rights according to the concept of the present application, the first component may be named as the second component, and similarly The second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "just between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

The terms used in this specification are only used to describe specific embodiments, and are not intended to limit the present application. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present specification, terms such as "comprise" or "have" are intended to designate the presence of implemented features, numbers, steps, actions, components, parts, or a combination thereof, but one or more other features or numbers It is to be understood that the possibility of addition or presence of, steps, actions, components, parts, or combinations thereof is not preliminarily excluded.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this specification. Does not.

Hereinafter, the present application will be described in detail by describing a preferred embodiment of the present application with reference to the accompanying drawings.

1 is a block diagram of a 3D crossbar network 100 according to an embodiment of the present application.

Referring to FIG. 1, the 3D crossbar network 100 may include a first layer 110, a second layer 120, and at least one monolithic anti-tier via 130_1_1 to 130_N_1.

First, in the first layer 110, a first input line IW_1_1 extending outward in the X-axis direction may be formed.

Next, at least one second layer 120 may be spaced apart from the first layer 110 in parallel, and a second input wiring IW_1_2 parallel to the first input wiring IW_1_1 may be formed. Here, the at least one second layer 120 is illustrated as one layer for convenience of description, but is not limited thereto, and the at least one second layer 120 is divided into a plurality of identical layers in the Z-axis direction. Can be.

In one embodiment according to the technical idea of the present application, at least one monolithic anti-tier via (130_1_1 to 130_N_1) is perpendicular to the first and second layers (110, 120), the first and second input The wirings IW_1_1 and IW_1_2 may be connected to each other.

Accordingly, compared to a conventional two-dimensional crossbar network in which the first and second input wires IW_1_1 and IW_1_2 are extended to one input wire, the three-dimensional crossbar network 100 has the first and second input wires IW_1_1 and IW_1_2 ) Is electrically connected to each other, and the extension lengths of the first and second input wires IW_1_1 and IW_1_2 are respectively reduced, thereby reducing power consumption according to the wire length.

FIG. 2 is an embodiment of the 3D crossbar network 200 of FIG. 1, FIG. 3 is a plan view of the first layer 210 of FIG. 2, and FIG. 4 is at least one second layer 220_1 to FIG. 2. 220_L-1) is a plan view.

Hereinafter, the input wires, output wires, and a plurality of tri-state buffers 250_11 to 250_NM illustrated in FIG. 2 are omitted for convenience of description, but are not limited thereto, and are illustrated in FIGS. 3 and 4. It will be described with reference to a plan view.

2 to 4, the 3D crossbar network 200 includes a first layer 210, at least one second layer 220_1 to 220_L-1, and a plurality of monolithic anti-tier vias 230_1_1 to 230_N_M. And first to Lth three-state buffers 250_1_1_1 to 250_N_M_L, at least two output drivers 260_1 to 260_L, and one input driver 270.

First, in the first layer 210, a plurality of first input wires IW_1_1 to IW_M_1 extending outward in the X-axis direction may be formed. That is, in the first layer 210, a plurality of first input wires IW_1_1 to IW_M_1 extending to one input driver 270 may be formed.

In addition, the first layer 210 may include a plurality of first output wires OW_1_1 to OW_N_1 extending to the first output driver 260_1.

Next, the at least one second layer 220_1 to 220_L-1 is spaced apart in parallel with the first layer 210, and the second to L-th pluralities parallel to the first plurality of input wires IW_1_1 to IW_M_1. Input wirings IW_1_2 to IW_M_2, IW_1_3 to IW_M_3, ..., IW_1_L to IW_M_L of may be formed. That is, the second to L-th input wires IW_1_2 to IW_M_2, IW_1_3 to IW_M_3, ..., IW_1_L to IW_M_L are different from the first plurality of input wires IW_1_1 to IW_M_1, and one input driver 270 ) May not be extended.

In addition, the at least one second layer 220_1 to 220_L-1 may include second to Lth output wirings OW_1_2 to OW_N_2, OW_1_3 to OW_N_3, ..., OW_1_L to OW_N_L extending outward in the Y-axis direction. ) Can be formed. That is, the at least one second layer 220_1 to 220_L-1 includes the second to Lth plurality of output wirings OW_1_2 to OW_N_2, OW_1_3 to OW_N_3, and the at least two output drivers 260_2 to 260_L. .., OW_1_L to OW_N_L) can be formed.

Next, the plurality of monolithic anti-tier vias 230_1_1 to 230_N_M are perpendicular to the first layer 210 and at least one second layer 220_1 to 220_L-1, and the first plurality of input wires The (IW_1_1 to IW_M_1) and the second to L-th input wires IW_1_2 to IW_M_2, IW_1_3 to IW_M_3, ..., IW_1_L to IW_M_L may be electrically connected. For example, the plurality of monolithic anti-tier vias 230_1_1 to 230_N_M may penetrate a layer positioned between both end layers.

Accordingly, the plurality of monolithic anti-tier vias 230_1_1 to 230_N_M are in the Z-axis direction, the first plurality of input wires IW_1_1 to IW_M_1 and the second to Lth plurality of input wires IW_1_2 to IW_M_2, Since IW_1_3 to IW_M_3, ..., IW_1_L to IW_M_L) can be connected to one input driver 270, power consumption according to a reduction in length of each input wire can be reduced.

Next, the first to Lth three-state buffers 250_1_1_1 to 250_N_M_L may be disposed on the first layer 210 and at least one second layer 220_1 to 220_L-1.

3 and 4, the first plurality of tri-state buffers 250_1_1_1 to 250_N_M_1 are disposed in a grid pattern on the first layer 210, and the second plurality of tri-state buffers 250_1_1_2 to 250_N_M_2 ) Is disposed in a lattice pattern on any one of the at least one second layer 220_1 to 220_L-1 (for example, 220_1), and the Lth tri-state buffers 250_1_1_L to 250_N_M_L are at least one It may be disposed on a layer (eg, 220_L) located at the top of the two layers 220_1 to 220_L-1.

That is, each of the plurality of tri-state buffers 250_1_1 to 250_N_M may be arranged in the same grid pattern for each layer. In this case, the number (N×M) of the plurality of tri-state buffers 250_1_1 to 250_N_M may correspond to the number of the plurality of monolithic anti-tier vias 230_1_1 to 230_N_M.

Specifically, each of the three-state buffers (eg, 250_1_1) can cross one input line (eg, IW_1_1), one output line (eg, OW_1_1), and one monolithic anti-tier via (eg, 230_1_1). have.

For example, each three-state buffer (eg, 250_1_1) is a temporary storage device and may be a logic element that outputs three states of low, high, and high impedance (Hi-Z). have. In addition, one three-state buffer (eg, 250_1_1) may output data by switching one input line (eg, IW_1_1) to one output line (eg, OW_1_1) according to a control signal.

Next, the at least two output drivers 260_1 to 260_L are the first to Lth output wires OW_1_1 to OW_N_1 connected to the first to Lth tristate buffers 250_1_1_1 to 250_N_M_L for each layer. OW_1_2 ~ OW_N_2, ..., OW_1_L ~ OW_N_L) can be located at one end extending along.

In this case, the number of at least two or more output drivers 260_1 to 260_L may correspond to the number of layers L.

Meanwhile, at least two or more output drivers 260_1 to 260_L may be electrically connected to each other through external monolithic anti-tier vias (eg, 231_1 to 231_N). For example, the at least two output drivers 260_1 to 260_L use external monolithic anti-tier vias (eg, 231_1 to 231_N), and the first to Lth three-state buffers 250_11_1 to 250_NM_L ) May be transmitted to the outside through one output driver (eg, 260_1).

Next, one input driver 270 may be located at one end extending from the first layer 210 along the first plurality of input wires IW_1_1, IW_2_1, ..., IW_M_1.

The one input driver 270 according to the embodiment activates the first plurality of input wires IW_1_1, IW_2_1, ..., IW_M_1, so that the first to Lth tristate buffers 250_11_1 to 250_NM_L are Data can be transferred at once.

For example, one input driver 270 activates a plurality of first input wires IW_1_1, IW_2_1, ..., IW_M_1, and a second through a plurality of monolithic anti-tier vias 230_11 to 230_NM. The plurality of L-th input wires IW_1_2 to IW_M_2, ..., IW_1_L to IW_M_L may be activated. That is, one input driver 270 is the first to L-th plurality of input wires IW_1_1 to IW_M_1, IW_1_2 to IW_M_2, ..., IW_1_L through the plurality of monolithic anti-tier vias 230_11 to 230_NM. IW_M_L) can be activated at once.

Accordingly, one input driver 270 simultaneously transmits data to the first to Lth three-state buffers 250_11_1 to 250_NM_L through the first plurality of input wires IW_1_1, IW_2_1, ..., IW_M_1. You can enter it.

5 is a block diagram of a 3D crossbar network 300 according to another embodiment of the present application.

Referring to FIG. 5, the 3D crossbar network 300 may include a first layer 310, a second layer 320, and at least one monolithic anti-tier via 330_1_1 to 330_1_M.

First, in the first layer 310, a first output line OW_1_1 extending outward in the Y-axis direction may be formed.

Next, at least one second layer 320 may be spaced apart in parallel with the first layer 310 and a second output line OW_2_1 parallel to the first output line OW_1_1 may be formed. Here, the at least one second layer 320 is illustrated as one layer for convenience of description, but is not limited thereto, and the at least one second layer 320 is divided into a plurality of identical layers in the Z-axis direction. Can be.

In another embodiment according to the technical idea of the present application, at least one monolithic anti-tier via 330_1_1 to 330_1_M is perpendicular to the first and second layers 310 and 320, and the first and second outputs The wirings OW_1_1 and OW_1_2 may be connected to each other.

Accordingly, compared to a conventional two-dimensional crossbar network in which the first and second output wires OW_1_1 and OW_1_2 are extended to one output wire, the three-dimensional crossbar network 300 has the first and second output wires OW_1_1 and OW_1_2 ) Are electrically connected to each other, and the extension lengths of the first and second output wires OW_11 and OW_21 are reduced, thereby reducing power consumption according to the wire length.

6 is an embodiment of the 3D crossbar network 400 of FIG. 5, FIG. 7 is a plan view of the first layer 410 of FIG. 6, and FIG. 8 is at least one second layer 420_1 to FIG. 6. It is a plan view of 420_L-1).

Hereinafter, the input wires, output wires, and a plurality of tri-state buffers 250_11 to 250_NM illustrated in FIG. 6 are omitted for convenience of description, but are not limited thereto, and are illustrated in FIGS. 7 and 8. It will be described with reference to a plan view.

6 to 8, the 3D crossbar network 400 includes a first layer 410, at least one second layer 420_1 to 420_L-1, and a plurality of monolithic anti-tier vias 430_1_1 to 430_N_M. ) And first to Lth tri-state buffers 450_1_1 to 450_N_M, at least two input drivers 460_1 to 460_L, and one output driver 470.

First, in the first layer 410, a plurality of first output wires OW_1_1 to OW_N_1 extending outward in the Y-axis direction may be formed. That is, in the first layer 410, a plurality of first output wires OW_1_1 to OW_N_1 extending to one output driver 470 may be formed.

Also, in the first layer 410, a plurality of first input wires OW_1_1 to OW_M_1 extending to the first input driver 460_1 may be formed.

Next, at least one of the second layers 420_1 to 420_L-1 is spaced apart from the first layer 410 in parallel, and the second to Lth pluralities parallel to the first plurality of output wires OW_1_1 to OW_N_1 The output wires OW_1_2 to OW_N_2, OW_1_3 to OW_N_3, ..., OW_1_L to OW_N_L of may be formed. That is, the second to Lth output wires OW_1_2 to OW_N_2, OW_1_3 to OW_N_3, ..., OW_1_L to OW_N_L are different from the first plurality of output wires OW_1_1 to OW_N_1, one output driver 470 ) May not be extended.

In addition, the at least one second layer 420_1 to 420_L-1 is a plurality of second to Lth input wires IW_1_2 to IW_M_2, IW_1_3 to IW_M_3, ..., IW_1_L to IW_M_L extending outward in the X-axis direction. ) Can be formed. That is, the at least one second layer 220_1 to 220_L-1 includes the second to L-th plurality of input wires IW_1_2 to IW_M_2, IW_1_3 to IW_M_3, which extend to the at least two or more input drivers 460_2 to 460_L. .., IW_1_L to IW_M_L) may be formed.

Next, the plurality of monolithic anti-tier vias 430_1_1 to 430_N_M are perpendicular to the first layer 410 and at least one second layer 420_1 to 420_L-1, and the first plurality of output wirings The (OW_1_1 to OW_N_1) and the second to Lth output wirings (OW_1_2 to OW_N_2, OW_1_3 to OW_N_3, ..., OW_1_L to OW_N_L) may be electrically connected. For example, the plurality of monolithic anti-tier vias 430_1_1 to 430_N_M may penetrate a layer positioned between both end layers.

Accordingly, the plurality of monolithic anti-tier vias 430_1_1 to 430_N_M are in the Z-axis direction, the first plurality of output wires OW_1_1 to OW_N_1 and the second to L-th output wires OW_1_2 to OW_N_2, Since OW_1_3 to OW_N_3, ..., OW_1_L to OW_N_L) can be connected to one output driver 470, it is possible to reduce power consumption according to a reduction in length of each output wire.

Next, the first to Lth tri-state buffers 450_1_1_1 to 450_N_M_L may be disposed on the first layer 410 and at least one second layer 420_1 to 420_L-1.

7 and 8, the first plurality of three-state buffers 450_1_1_1 to 450_N_M_1 are arranged in a grid pattern on the first layer 410, and the second plurality of three-state buffers 450_1_1_2 to 450_N_M_2 ) Is arranged in a lattice pattern on any one of the at least one second layer 420_1 to 420_L-1 (for example, 420_1), and the Lth tri-state buffers 450_1_1_L to 450_N_M_L are at least one It may be disposed on an upper layer (eg, 420_L) among the two layers 420_1 to 420_L-1.

That is, each of the plurality of tri-state buffers 450_1_1 to 450_N_M may be arranged in the same grid pattern for each layer. In this case, the number (N×M) of each of the plurality of tri-state buffers 450_1_1 to 450_N_M may correspond to the number of the plurality of monolithic anti-tier vias 430_1_1 to 430_N_M.

Specifically, each of the three-state buffers (eg, 450_1_1) can cross one input line (eg, IW_1_1), one output line (eg, OW_1_1), and one monolithic anti-tier via (eg, 430_1_1). have.

For example, each three-state buffer (for example, 450_1_1) is a temporary storage device and may be a logic element that outputs three states of low, high, and high impedance (Hi-Z). have. In addition, one three-state buffer (eg, 450_1_1) may output data by switching one input line (eg, IW_1_1) to one output line (eg, OW_1_1) according to a control signal.

Next, the at least two input drivers 460_1 to 460_L are the first to Lth input wirings IW_1_1 to IW_M_1 and IW_1_2 connected to the first to Lth tristate buffers 450_1_1_1 to 450_N_M_L for each layer. It may be located at one end extending along ~IW_M_2, ..., IW_1_L ~ IW_M_L).

In this case, the number of at least two or more input drivers 460_1 to 460_L may correspond to the number of layers L.

Meanwhile, at least two or more input drivers 460_1 to 460_L may be electrically connected to each other through external monolithic anti-tier vias (eg, 431_1 to 431_N). For example, at least two input drivers 460_1 to 460_L receive input from the outside to any one input driver (e.g., 360_1) using external monolithic anti-tier vias (e.g., 431_1 to 431_N) Data can be shared with the rest of the input drivers (eg, 360_2 to 360_L).

Next, one output driver 470 may be located at one end extending from the first layer 410 along the first plurality of output wires OW_1_1 to OW_N_1.

One output driver 470 according to the embodiment activates the first plurality of output wires OW_1_1 to OW_N_1 to receive data from the first to Lth plurality of tri-state buffers 250_11_1 to 250_NM_L at once. I can.

For example, one output driver 470 activates the first plurality of output wires OW_1_1 to OW_N_1, and the second to Lth plurality of through the plurality of monolithic anti-tier vias 430_1_1 to 430_N_M The output wirings OW_1_2 to OW_N_2, OW_1_3 to OW_N_3, ..., OW_1_L to OW_N_L can be activated. That is, one output driver 470 is the first to Lth output wirings OW_1_1 to OW_N_1, OW_1_2 to OW_N_2, ..., OW_1_L to OW_N_L through the plurality of monolithic anti-tier vias 430_1_1 to 430_N_M. ) Can be activated at once.

Accordingly, one output driver 470 may simultaneously receive data from the first to Lth three-state buffers 450_11_1 to 450_NM_L through the first plurality of output wires OW_1_1 to OW_N_1.

9 is an embodiment of a graphic processing unit 1000 based on a 3D crossbar network.

1 to 9, the graphic processing unit 1000 may include a 3D crossbar network 500, a register file unit 610, an operand collector unit 620, and an arbiter 630.

First, the 3D crossbar network 500 includes first to Lth input wires IW_1_1 to IW_M_1, IW_1_2 to IW_M_2, ..., IW_1_L to IW_M_L, and first to Lth output wires OW_1_1 to OW_N_1, OW_1_2 to OW_N_2, ..., OW_1_L to OW_N_L) may be included.

In the 3D crossbar network 500 according to an embodiment, the first to Lth input wires IW_1_1 to IW_M_1, IW_1_2 to IW_M_2, ..., IW_1_L to IW_M_L may be activated at once. As shown in FIG. 2, the 3D crossbar network 500 includes first to Lth input wires IW_1_1 to IW_M_1, IW_1_2 to IW_M_2, ..., IW_1_L to IW_M_L through one input driver 270. ) Can be activated at once.

In the 3D crossbar network 500 according to another embodiment, the first to L-th output wirings OW_1_1 to OW_N_1, OW_1_2 to OW_N_2,..., OW_1_L to OW_N_L may be activated at once. As shown in FIG. 7, the three-dimensional crossbar network 500 includes first to Lth output wirings OW_1_1 to OW_N_1, OW_1_2 to OW_N_2,..., OW_1_L to OW_N_L through one output driver 470. ) Can be activated at once.

Next, the register file unit 610 may include a plurality of banks 610_1 to 610_N formed in an SRAM memory structure.

Here, the plurality of banks 610_1 to 610_N may store all contexts of a thread corresponding to a series of execution codes. Specifically, the plurality of banks 10_1 to 10_N may store an operand among all contexts of a thread. Here, the operand may mean data or information used to execute an instruction.

As shown in FIG. 2, a plurality of banks 10_1 to 10_N according to an embodiment may simultaneously transmit an operand to a 3D crossbar network 500 activated through one input driver 270. .

Next, as the operand collector unit 620 requests an operand from the register file unit 610, the operand is transmitted from the plurality of banks 10_1 to 10_N through the three-dimensional crossbar network 500. It can be received, stored, and delivered to an execution unit when a thread is executed.

As shown in FIG. 7, the operand collector unit 620 according to the embodiment may receive an operand for the 3D crossbar network 500 activated through one output driver 470 at a time.

At this time, the arbiter 630 can block a request conflict for an operand transmitted from the plurality of banks 610_1 to 610_N to the operand collector unit 620 through the 3D crossbar network 500. , It is possible to control the scheduler function in the three-dimensional crossbar network 500.

The graphic processing unit 1000 based on a three-dimensional crossbar network according to an exemplary embodiment of the present application can reduce the length of each wire of a conventional two-dimensional crossbar network, thereby reducing power consumption according to the wire length. Furthermore, due to the reduced three-dimensional crossbar network 500 compared to the conventional two-dimensional crossbar network area, the graphic processing unit 1000 can relatively increase the area of the plurality of banks 10_1 to 10_N and the operand collector unit 20. It has the effect of making it possible.

Although the present application has been described with reference to an exemplary embodiment illustrated in the drawings, this is only exemplary, and those of ordinary skill in the art will understand that various modifications and equivalent other exemplary embodiments are possible therefrom. Therefore, the true technical protection scope of the present application should be determined by the technical idea of the attached registration claims.

100, 200, 300, 400, 500: three-dimensional crossbar network
110: first layer
120: second layer
130_1_1~130_N_M: at least one monolithic anti-tier via
1000: graphic processing unit

Claims (10)

A first layer on which first input wiring is formed and extending to the outside;
At least one second layer spaced apart from the first layer and having a second input line formed thereon; And
A graphic processing unit based on a three-dimensional crossbar network comprising at least one monolithic anti-tier via vertically to the first and second layers and electrically connecting the first and second input wires. The method of claim 1,
A graphic processing unit based on a three-dimensional crossbar network, further comprising a plurality of three-state buffers arranged in the same grid pattern in each of the first layer and the at least one second layer. The method of claim 2,
One input driver positioned at one end along the first input wiring; And
Further comprising a plurality of output drivers positioned at one end along a plurality of output wires connected to the plurality of tri-state buffers,
The one input driver activates a plurality of input wires connected to the plurality of three-state buffers through the first input wire at one time, a graphic processing unit based on a three-dimensional crossbar network. The method of claim 3,
A graphics processing unit based on a three-dimensional crossbar network, further comprising an external monolithic anti-tier via connecting the plurality of output drivers to each other. The method of claim 2,
A graphic processing unit based on a three-dimensional crossbar network, wherein the number of the at least one monolithic anti-tier via corresponds to the number of the plurality of three-state buffers. A first layer on which first output wiring is formed;
At least one second layer spaced apart from the first layer and having a second output line formed thereon; And
A graphic processing unit based on a three-dimensional crossbar network comprising at least one monolithic anti-tier via vertically to the first and second layers and electrically connecting the first and second output wires. The method of claim 6,
A graphic processing unit based on a three-dimensional crossbar network, further comprising a plurality of three-state buffers arranged in the same grid pattern in each of the first layer and the at least one second layer. The method of claim 7,
One output driver positioned at one end along the first output wiring; And
Further comprising a plurality of input drivers positioned at one end along a plurality of input wires connected to the plurality of tri-state buffers,
The one output driver activates a plurality of output wires connected to the plurality of three-state buffers at a time through the first output wire. 3D crossbar network based graphics processing unit. The method of claim 8,
A graphic processing unit based on a three-dimensional crossbar network, further comprising an external monolithic anti-tier via connecting the plurality of input drivers to each other. The method of claim 7,
A graphic processing unit based on a three-dimensional crossbar network, in which the number of at least one monolithic anti-tier via corresponds to the number of the plurality of three-state buffers.

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