KR20200102337A - Methods and apparatuses for cacheline conscious extendible hashing - Google Patents

Abstract

The present invention relates to a cacheline conscious extendible hashing method and a device therefor capable of minimizing access to a memory cacheline by using a segment including at least one bucket referenced through a directory. According to an embodiment of the present invention, the cacheline conscious extendible hashing method, which is performed by a cacheline conscious extendible hashing device, comprises the following steps of: identifying a segment referenced through a directory by using a first index of a hash key; verifying a bucket to be accessed within the identified segment by using a second index of the hash key; and storing data corresponding to the hash key in the verified bucket.

Description

[Methods and Apparatuses for CACHELINE CONSCIOUS EXTENDIBLE HASHING]

The present invention relates to a method and apparatus for cacheline concierge extendable hashing.

Many conventional data structures are designed to fit on a disk that reads and writes pages of 4KB or 8KB, but recently, in-memory database systems such as SAP HANA databases have been utilized, unlike block-based data structures, 8 bytes (Word ) There is increasing interest in data structures for reading and writing sized data. The hash table data structure has the advantage of being able to read and write data quickly in constant time, unlike the B-tree data structure.

The hash table determines a specific location where data can be stored through a hash function, and a space in which data having a specific hash key value can be stored is called a bucket. Hash tables can be divided into two types. One is a static hash table and the other is a dynamic hash table. Static hash table data structures require one large contiguous memory space. That is, buckets in which data can be stored are consecutively stored in one memory space in order. If the hash key value of some data is K, it is stored in the K-th bucket, and the location of this K-th bucket is determined as (K × bucket size) in the continuous memory space. That is, if the bucket is 4KB and the hash key value is 3, data must be stored in a bucket located at 12KB in the contiguous memory space allocated for the hash table. If a bucket where some data is to be stored is found, and a lot of data is already stored in the bucket and no more new data can be stored, the static hash table allocates a larger contiguous memory space than the current memory space and Copies them to buckets located in a new memory space. This operation is called rehashing, and rehashing is a very overhead operation.

1 is a diagram for explaining a conventional extendable hashing data structure.

A dynamic hash table that dynamically allocates buckets has been developed to reduce such rehashing overhead. The most representative method is the Extendible Hash. The structure of the extendable hash table is composed of two layers as shown in FIG. 1. The upper layer is an array of pointers called directories, and the lower layer is the buckets that store data. The last or first few bits of the hash key of the data to be stored are used to determine which directory entry to read. This number of bits is determined by the size of the directory. As in the example of FIG. 1, if the directory is 4 (2 ² ), only 2 bits are used, and if the directory size is 8 (2 ³ ), 3 bits are used. In the example of FIG. 1, 2 bits are used. Since the least significant bit (LSB), that is, 2 bits is 10 ₍₂₎ , the bucket is searched using the binary number 10 ₍₂₎ out of the 4 directory entries, that is, the 3rd pointer with the array index 2.

In the example of FIG. 1, a bucket B3 is used. The number of bits used to find a directory is called the directory's Global Depth (G). Each bucket has its own Local Depth, because a bucket can be pointed to by multiple directory entries. As shown in the example of FIG. 1, two directory entries point to a bucket B2 having a global depth of 2 and a local depth of 1. If the global depth is 3 and the local depth is 1, the bucket is pointed to by 2 ^(3-1) directory entries.

In FIG. 1, if new data is to be stored in bucket B2, but there is insufficient space, two new buckets must be created and the data must be divided and stored. In Figure 1, since the local depth of the bucket B2 is 1, only one bit marked in dark black is used and stored in the bucket B2. However, if the bucket is divided, the local depth is increased by one and the local depth is 2 Two buckets B4 and B5 are made as shown in FIG. 2.

2 is a diagram for explaining an example of dividing a conventional extendable hash.

Data stored in a bucket with insufficient space is copied to the first new bucket, bucket B4 or the second new bucket, bucket B5 according to the increased local depth, that is, a 2-bit value. Data with the last 2 bits being 01 ₍₂₎ is copied to the first newly created bucket B4, and the data with 11 being copied to the second newly created bucket B5. After completing this partitioning process, the directory entries pointing to bucket B2 are updated. That is, 01 ₍₂₎ directory entry points to the new bucket B4 with data corresponding to 01 ₍₂₎ , and 11 ₍₂₎ directory entry points to the new bucket B5 with data corresponding to 11 ₍₂₎ . Should.

3 is a diagram for describing an example of directory expansion of an extendable hash.

If the local depth is K and the global depth is K, then the bucket is pointing to only one directory entry. In the example of FIG. 2, it is assumed that the bucket B3 is divided. The local depth of the bucket B3 is 2 (Local depth=2), and the global depth of the directory is also 2 (G=2). In this case, when bucket B3 is divided and new buckets B6 and B7 with a local depth of 3 are created, data is copied to B6 or B7 using bits of the local depth. That is, 1101...10001010 ₍₂₎ in bucket B3 is copied to bucket B6 corresponding to 010 ₍₂₎ , which is the least significant 3 bits, and 010...01101110 _{(2) corresponds} to 110 ₍₂₎ . Is copied to bucket B7. However, I cannot store pointers to these new buckets B6 and B7 in the directory. Therefore, if the bucket is divided when the local depth and the global depth are the same, the directory should be made twice as large as shown in FIG. 3. This operation is called Directory Doubling. That is, a directory with a global depth of 3 (2 ³ ) and capable of storing 8 directory entries is created. At this time, pointers are copied to other buckets that are not partitioned so that new directory entries are doubled. That is, Bucket B1, which was pointed to by 00, is pointed not only by 000 ₍₂₎ but also by 100 ₍₂₎ directory entries.

The extendable hashing described above is used in various file systems such as Oracle's ZFS. However, the size of the bucket is set to 4KB or 8KB, so performance is optimized only for disk-based systems. In other words, it is not a data structure suitable for an in-memory system. If this extendable hashing is applied to an in-memory system as it is, the bucket must be searched through the directory and all data in the bucket must be read one by one. In addition, memory that is nonvolatile while being able to access byte units such as Intel 3D crosspoint, STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory), and PCRAM (Phase-change memory), which are recently developed. Even if the data structure is updated with 8-byte operations in order to be used on the computer, the data structure must always maintain consistency, but the conventional extendable hashing has a problem in that it does not maintain consistency for these 8-byte operations. .

Embodiments of the present invention are to provide a method and apparatus for a cache line concierge extendable hashing that can minimize access to a memory cache line by using a segment including at least one bucket referenced through a directory.

Embodiments of the present invention provide fault-atomicity that conventional extendable hashing cannot provide for non-volatile memory, and provides non-volatile memory with fewer cache lines. An object of the present invention is to provide a method and apparatus for cache line concierge extendable hashing that can be used more efficiently.

According to an embodiment of the present invention, in the extendable hashing method performed by a Cacheline Conscious Extendible Hashing device, a directory (Directory) using a first index of a hash key Checking a segment referenced through ); Identifying a bucket to be accessed within the identified segment by using a second index of the hash key; And storing data corresponding to the hash key in the identified bucket. A cache line concierge extendable hashing method may be provided.

The method may further include checking a global depth bit value of the hash key.

The first index of the hash key may include a Most Significant Bit (MSB) of the hash key.

The second index of the hash key may include a least significant bit (LSB) of the hash key.

In the step of confirming the segment, a directory entry corresponding to the first index of the hash key may be searched, and a segment referenced through the searched directory entry may be identified.

The method may further include dividing the segment when a collision occurs when a segment is accessed using the second index of the hash key.

In the dividing of the segment, a new segment having an increased local depth is generated, and data having a preset bit value corresponding to the increased local depth is generated by scanning data of the identified segment. Can be copied to a new segment.

In the step of dividing the segment, a local depth of the segmented segment may be increased and data having a different preset bit value corresponding to the increased local depth may be designated as an invalid key.

The step of dividing the segment may increase the local depth of the identified segment, update a pointer of a directory entry, and increase the local depth of the segmented segment.

The method may further include combining directory entries into pairs of buddies when updating the directory when the segment is divided.

The method may further include identifying a segment in which a system problem has occurred using the global depth and a local depth of the segment, and recovering the segment in which the system problem has occurred using the buddy.

Meanwhile, according to another embodiment of the present invention, there is provided a memory for storing at least one program and for storing a segment including at least one bucket referenced through a directory; And a processor connected through the memory and the cache, wherein the processor executes the at least one program, and thus a segment referenced through a directory using a first index of a hash key. ), and by using the second index of the hash key, a bucket to be accessed within the identified segment is identified, and data corresponding to the hash key is written to or read from the identified bucket. A sears extendable hashing device may be provided.

The processor may further include checking a global depth bit value of the hash key.

The first index of the hash key may include a Most Significant Bit (MSB) of the hash key.

The second index of the hash key may include a least significant bit (LSB) of the hash key.

The processor may search for a directory entry corresponding to the first index of the hash key and check a segment referenced through the searched directory entry.

The processor may divide the segment when a collision occurs when a segment is accessed using the second index of the hash key.

The processor generates a new segment with an increased local depth, scans data of the identified segment, and sends data having a preset bit value corresponding to the increased local depth to the generated new segment. Can be copied.

The processor may increase a local depth of the segmented segment and designate data having another preset bit value corresponding to the increased local depth as an invalid key.

The processor may increase the local depth of the identified segment, update a pointer of a directory entry, and increase the local depth of the segmented segment.

When the identified segment is divided, the processor may bundle directory entries into pairs called buddies when updating a directory.

The processor may identify a segment in which a system problem has occurred using the global depth and a local depth of the segment, and recover a segment in which a system problem has occurred using the buddy.

Meanwhile, according to another embodiment of the present invention, as a non-transitory computer-readable storage medium including at least one program executable by a processor, when the at least one program is executed by the processor, the processor causes: A bucket to be accessed within the identified segment by using the first index of the hash key to check the segment referenced through the directory and by using the second index of the hash key ) And inserting a key value corresponding to the hash key into the identified bucket, a non-transitory computer-readable storage medium may be provided.

Embodiments of the present invention can minimize access to a memory cache line by using a segment including at least one bucket referenced through a directory.

Embodiments of the present invention provide fault-atomicity that conventional extendable hashing cannot provide for non-volatile memory, and provides non-volatile memory with fewer cache lines. It can be used more efficiently.

1 is a diagram for explaining a conventional extendable hashing data structure.
2 is a diagram for explaining an example of dividing a conventional extendable hash.
3 is a diagram for describing an example of directory expansion of an extendable hash.
4 is a configuration diagram illustrating a configuration of a cache line concierge extendable hashing apparatus according to an embodiment of the present invention.
5 to 7 are diagrams for explaining the operation of the cache line concierge extendable hashing apparatus according to an embodiment of the present invention.
8 is a flowchart illustrating a cache line concierge extendable hashing operation according to an embodiment of the present invention.
9 is a diagram for describing a new segment generation operation in a cache line-concierge extendable hashing operation according to an embodiment of the present invention.
10 is a diagram for explaining a separation and slow deletion operation in a cache line-concierge extendable hashing operation according to an embodiment of the present invention.
11 to 13 are diagrams for explaining a tree-shaped segment separation operation in a cache line concierge extendable hashing operation according to an embodiment of the present invention.
14 is a diagram for explaining a pseudo code of a recovery algorithm according to an embodiment of the present invention.
15 is a flowchart for explaining an insert operation operation in a cache line concierge extendable hashing method according to an embodiment of the present invention.
16 is a flowchart illustrating a partition operation operation in a cache line concierge extendable hashing method according to an embodiment of the present invention.
17 is a flowchart illustrating a recovery operation operation in a cache line concierge extendable hashing method according to an embodiment of the present invention.
18A to 18C are diagrams showing experimental results of throughputs having various segment/bucket sizes for an embodiment of the present invention and a prior art.
19A to 19D are diagrams showing time required for insertion while changing the R/W latency of a nonvolatile memory in the embodiment of the present invention and in the prior art.
20A to 20C are diagrams showing simultaneous execution performance for latency CDF and insertion/retrieval throughput for the embodiment of the present invention and the prior art.

Since the present invention can make various changes and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail.

However, this is not intended to limit the present invention to a specific embodiment, it is to be understood to include all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. These terms are used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term and/or includes a combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, but one or more other features. It is to be understood that the presence or addition of elements or numbers, steps, actions, components, parts, or combinations thereof, does not preclude in advance.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. Does not.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In describing the present invention, in order to facilitate an overall understanding, the same reference numerals are used for the same elements in the drawings, and duplicate descriptions for the same elements are omitted.

4 is a configuration diagram illustrating a configuration of a cache line concierge extendable hashing apparatus according to an embodiment of the present invention.

As shown in FIG. 4, the cache line concierge extendable hashing apparatus 100 according to an embodiment of the present invention includes a processor 110, a cache 120, and a memory 130. However, not all of the illustrated components are essential components. The cacheline concierge extendable hashing device 100 may be implemented by more components than the illustrated components, and the cacheline concierge extendable hashing device 100 may be implemented by fewer components.

Hereinafter, a detailed configuration and operation of each component of the cache line concierge extendable hashing apparatus 100 of FIG. 4 will be described.

The memory 130 stores at least one program. The memory 130 may include a file system or a database. The memory 130 stores a segment including at least one bucket referenced through a directory. Here, the memory 130 may be a non-volatile memory (NVM, NVRAM) or a volatile memory.

The processor 110 is connected through the memory 130 and the cache 120. The processor 110 may store data in a bucket in a file system of a memory or read data stored in the bucket through a cache line of the cache 120.

The processor 110, by executing at least one program, identifies a segment referenced through a directory using a first index of a hash key, and determines a second index of the hash key. By using, a bucket to be accessed within the identified segment is identified, and data corresponding to the hash key is stored in the identified bucket. Here, the processor 110 may directly access one of the plurality of buckets in the segment by using the second index of the hash key.

In various embodiments, the processor 110 may check the global depth bit value of the hash key.

In various embodiments, the first index of the hash key may include the Most Significant Bit (MSB) of the hash key.

In various embodiments, the second index of the hash key may include the least significant bit (LSB) of the hash key.

In various embodiments, the processor 110 may search for a directory entry corresponding to the first index of the hash key and check a segment referenced through the searched directory entry.

In various embodiments, the processor 110 may divide the segment when a collision occurs when a segment is accessed using the second index of the hash key.

In various embodiments, the processor 110 generates a new segment with increased local depth, scans data of the identified segment, and retrieves data having a preset bit value corresponding to the increased local depth. You can copy it to a new segment created. For example, the processor 110 may copy data having a bit value of 1 of the second index corresponding to the increased local depth to a new segment and update a pointer of a corresponding directory entry.

In various embodiments, the processor 110 may increase a local depth of a segment to be segmented, and designate data having another preset bit value corresponding to the increased local depth as an invalid key. For example, the processor 110 does not erase data having a bit value of 0 corresponding to the increased local depth of the second index from the segment to be divided, but increases the local depth by 8-byte operation, Can be made into an invalid key. That is, data that has not been erased is considered an invalid key and may be overwritten by other data.

In various embodiments, the processor 110 may increase the local depth of the identified segment, update a pointer of a directory entry, and increase the local depth of the segmented segment. For example, the processor 110 may update a pointer to be updated among pointers of a directory entry from a pointer having a large second index value to a pointer having a small second index value. As another example, the processor 110 may update a pointer to be updated among pointers of a directory entry from a pointer having a small second index value to a pointer having a large second index value. Thereafter, the processor 110 may perform a recovery operation in the opposite direction to the update order to recover.

In various embodiments, when the identified segment is segmented, the processor 110 may group directory entries into pairs called buddies when updating the directory.

In various embodiments, the processor 110 may use the global depth and the local depth of the segment to identify a segment in which a system problem has occurred, and recover a segment in which a system problem has occurred using a buddy.

5 to 7 are diagrams for explaining the operation of the cache line concierge extendable hashing apparatus according to an embodiment of the present invention.

The data transfer unit between the CPU and the memory that can be accessed in byte units is a cache line of 64 bytes in the latest CPU. If a conventional 8KB bucket is used, a bucket consisting of 128 cache lines must be read in order to find one data, so a total of 128 memory is accessed. Unlike disk-based extendable hashing, the in-memory hash table does not require the size of the bucket to match the size of the disk block. If the bucket size is set to 64 bytes, one cache line needs to be read to read one bucket, so one total memory access is required.

However, if the size of a bucket is one cacheline, there is a disadvantage in that the size of the directory becomes very large due to the feature of Extendible Hashing, which requires one directory entry for each 64-byte cache line. .

According to an embodiment of the present invention, it is intended to provide a Cacheline-Conscious Extendible Hashing (CCEH) method suitable for a memory capable of byte unit access by modifying such an extendible hashing method. . The Cacheline-Conscious Extendible Hashing (CCEH) according to an embodiment of the present invention is a modification of Extendible Hashing, and the conventional Extendable Hashing is a nonvolatile memory. This is an extendible hashing method that provides fault-atomicity, which cannot be provided for, and allows more efficient use of nonvolatile memory with fewer cachelines. CCEH can efficiently manage a cacheline by placing a layer called a segment in a two-tier structure consisting of a conventional directory and a bucket.

5 illustrates an example in which a cache line concierge extendable hashing device according to an embodiment of the present invention operates including a file system or a database based on a nonvolatile memory (PM).

As shown in FIG. 5, a cache line concierge extendable hashing apparatus according to an embodiment of the present invention includes a CPU 210, a CPU cache 220, and a nonvolatile memory (PM). Includes 230. Here, the nonvolatile memory 230 may include a PM-based file system 231 or a PM-based database. Instead of the nonvolatile memory 230, a dynamic random-access memory (DRAM) may be used.

The CPU 210 checks the directory entry referenced by the index of the hash key through the cache line of the CPU cache 220 and attempts to access the bucket in the segment indicated by the directory entry.

As shown in FIG. 6, the CPU 210 may check a segment referenced through a directory using the first index of a hash key. That is, the CPU 210 may determine which directory entry to refer to by using the segment index. Here, the segment index may be referred to as a first index. In the example of FIG. 6, it can be confirmed that the directory entry 010 ₍₂₎ is referred to by using the segment index 10 ₍₂₎ corresponding to the most significant 2 bits.

As shown in FIG. 7, the CPU 210 may check a bucket to be accessed within the identified segment by using the second index of the hash key. The CPU 210 may use a bucket index of a hash key to determine which bucket to read in a reference segment. Here, the bucket index may be referred to as a second index. As a result, the CPU 210 may check the segment through the directory entry referenced by the segment index, and check the bucket indicated by the bucket index within the identified segment. Directory [segment index] + bucket index can be the address of the bucket to be accessed. In addition, the CPU 210 may store a key value or data corresponding to the hash key in the identified bucket. Alternatively, the CPU can read or write the key value or data corresponding to the hash key in the identified bucket.

8 is a flowchart illustrating a cache line concierge extendable hashing operation according to an embodiment of the present invention.

The hash table structure according to an embodiment of the present invention has an intermediate layer called a segment between a bucket and a directory. That is, a segment is a contiguous memory space in which at least one bucket is grouped and is used to reduce the size of a directory. That is, the directory does not directly point to the bucket, but points to the start position of the segment, and determines which bucket in the segment, that is, which cache line, is read using different bits of the hash key. In an embodiment of the present invention, a segment is specified by using the most significant bits (MSB) or the least significant bits (LSB) of the hash key, and buckets in the segment are identified by using other bits of the hash key. To be specified.

Referring to FIG. 8 as an example, since the global depth is 2 (G=2), the directory has 4 (2 ² ) entries, i.e. 00 (L=2), 01 (L=2), 10 (L=1) And 11 (L=1). If the given hash key value is 10101010... If 11111110 ₍₂₎ , two bits equal to the global depth are 10 _(2), that is, a segment is searched in a directory using a segment index. In this example, it is assumed that 2 most significant bits are used. 10 ₍₂₎ points to Segment 3. In order to specify the bucket inside the segment, other bits of the hash key, that is, the bucket index, are used. The number of bits is determined by the size of the segment. That is, if a segment has 2 ^S buckets (cache lines), S bits must be used. Since it is assumed that the segment is specified using the most significant bit, the least significant bits (LSB), that is, the bucket index, are used to specify the bucket. For example, suppose a segment consists of 256 (2 ⁸ ) cacheline-sized buckets. In this case, 8 bits are used to specify the bucket. The last 8 bits of the given hash key value are 11111110 _(2), so the 254th cache line becomes the bucket to store or find data. That is, the hash key 10101010... 11111110 ₍₂₎ can be obtained given the ground _{(& Segment (10 (2)} ) + 64 * 11111110 (2)) the memory address of the cache line by the operation stores data at a time, or read. Here, the segment index and bucket index of the hash key are not limited to a specific position.

As described above, the cacheline concierge extendable hashing apparatus 100 according to an embodiment of the present invention may store or read data with only two cacheline accesses. The cache line-concierge extendable hashing apparatus according to an embodiment of the present invention can minimize the number of memory accesses through segments.

9 is a diagram for describing a new segment generation operation in a cache line-concierge extendable hashing operation according to an embodiment of the present invention.

In the next-generation non-volatile memory, data remains in the memory even when the system dies or powers off. When data is stored in such a nonvolatile memory, data can be accessed without problems even if the system is rebooted only by atomically updating the data.

In the conventional disk-based extendible hashing technique, when a bucket is divided or a directory is updated, a large amount of data is redundantly written by performing a logging operation that makes a backup in a separate storage space.

The cache line-concierge extendable hashing device according to an embodiment of the present invention may provide a fault-atomic segment split for a nonvolatile memory.

When a segment is divided, the cache line-concierge extendable hashing apparatus according to an embodiment of the present invention allocates a new segment and scans all data stored in the segment. The local depth of the newly created segment is one greater than the local depth of the segment being segmented. Therefore, while scanning the data of the segment to be divided, one more bit of the hash key is checked. If this bit is 1, it is copied to the new segment, and if it is 0, it is left in the existing segment. Note that even if data is copied to a new segment, it is not deleted from the previous segment. This is to use the previous segment as it is during recovery.

9 shows a state in which a segment 3 having a local depth of 1 in FIG. 8 is divided to create a new segment 4 having a local depth of 2. FIG. Even if the data copied from the previous segment to the new segment 4 are not deleted, the data becomes invalid as soon as the local depth of the segment increases, so there is no problem even if it is not deleted. For example, in FIG. 9, 1101...11111110 ₍₂₎ has been copied to segment 4, but remains in segment 3 as it is. However, such data is regarded as an invalid key when the local depth of the segment increases as shown in FIG. 10, and this space can be used to store other data.

10 is a diagram for explaining a separation and slow deletion operation in a cache line-concierge extendable hashing operation according to an embodiment of the present invention.

As shown in FIG. 10, in FIG. 9, 1110...00000000 ₍₂₎ , 1110...00000001 ₍₂₎ , 1101...111110 ₍₂₎ were copied to Segment 4, but the Segment ) It remains unremoved in 3. This operation is referred to as a lazy deletion operation. As shown in FIG. 10, data copied to segment 4 but not deleted from segment 3 is considered an invalid key when the local depth of segment 3 is increased to 2, and this space can be used to store other data. .

The local depth of the segment segmented from the previous segment must be increased after all new segments have been written. If this order is not followed, consistency problems may arise when the system dies. After increasing the local depth of the previous segment, the pointers of the directory entries are updated and the local depth of the segmented segment is increased. This order must also be followed for recovery. 10 shows a state in which the local depth of the segmented segment is increased and the directory points to a new segment.

11 to 13 are diagrams for explaining a tree-shaped segment separation operation in a cache line concierge extendable hashing operation according to an embodiment of the present invention.

When the segment is divided, the directory must be updated with several directory entries. In one embodiment of the present invention, when updating a directory, directory entries are grouped into pairs called buddies, so that the history of segment splitting can be managed in a tree form. have. In one embodiment of the present invention, when there is a problem in the system, the problem can be found by searching this tree. In this case, in an embodiment of the present invention, a global depth and a local depth are used to determine which part has a problem, and a pair called a buddy may be used as a backup to perform recovery.

11 shows a directory with a global depth of 4 having 16 directory entries. The tree structure shows the history of segmentation. It can be seen that S1 is divided into S1 and S3, and S2 is divided into S2 and S4 in the cache line concierge extendable hashing (CCEH) structure where only two segments S1 and S2 were initially present. In addition, in Level 3, it can be seen that S1 is divided into S1 and S5 again, and S3 is divided into S3 and S6. The current tree structure has a global depth of 4. In this state, consider a situation in which segment S2 is divided.

If S2 is divided into S2 and S11, it must be updated from 9th to 12th entries in the directory. In a situation in which several directory entries are updated, the cache line concierge extendable hashing apparatus 100 according to an embodiment of the present invention first updates the rightmost entry and updates the left entries one by one. As another example, the cacheline concierge extendable hashing apparatus 100 may first update the leftmost entry and then update the right entries one by one in a situation in which several directory entries are updated. As shown in FIG. 12, the cache line concierge extendable hashing apparatus 100 according to an embodiment of the present invention updates the twelfth S2 (L=2) to S11 (L=3). As shown in FIG. 13, the cache line concierge extendable hashing apparatus 100 updates the next 11th entry S2 (L=2) to S11 (L=3). Thereafter, the cache line concierge extendable hashing apparatus 100 increases the local depth of the 10th and ninth entries by one and changes them to S2 (L=3). This order must be observed for restoration.

If the system dies while performing the update while following this order, the directory may be updated through the recovery algorithm shown in FIG. 14 to restore the previously consistent state.

14 is a diagram for explaining a pseudo code of a recovery algorithm according to an embodiment of the present invention.

The recovery algorithm according to an embodiment of the present invention takes advantage of the fact that when segment split occurs, the local depth of the buddy segment must always be the same as the characteristic that occurs because operations are performed in order as described above. I did it. If the local depth of the current segment is smaller than the local depth of the right Buddy segment, it means that the system died while the segment was being divided. Therefore, the right segment is reconstructed using the current node as a backup. If the two local depths are the same, it means that the segmented buddy segment is completely written.

15 is a flowchart for explaining an insert operation operation in a cache line concierge extendable hashing method according to an embodiment of the present invention.

In step S101, the cache line concierge extendable hashing apparatus 100 according to an embodiment of the present invention receives an index of a hash key.

In step S102, the cache line concierge extendable hashing device 100 checks the global depth bit value of the input hash key.

In step S103, the cache line concierge extendable hashing device 100 accesses the corresponding segment in the directory using the index of the hash key.

In step S104, the cache line concierge extendable hashing apparatus 100 accesses the bucket corresponding to the LSB, which is the bucket index of the hash key.

In step S105, the cache line concierge extendable hashing device 100 checks whether a collision occurs.

In step S106, if there is no collision, the cache line concierge extendable hashing device 100 creates a key value corresponding to the hash key.

In step S107, when a collision occurs, the cache line concierge extendable hashing apparatus 100 divides the segment in which the collision occurs.

16 is a flowchart illustrating a partition operation operation in a cache line concierge extendable hashing method according to an embodiment of the present invention.

In step S201, the cacheline concierge extendable hashing apparatus 100 according to an embodiment of the present invention generates a new segment with increased local depth after starting segmentation.

In step S202, the cache line concierge extendable hashing apparatus 100 checks the bit of the hash key and then copies the value to a new segment.

In step S203, the cache line concierge extendable hashing apparatus 100 updates the pointer of the directory entry.

In step S204, the cache line concierge extendable hashing device 100 increases the local depth of the previous segment.

17 is a flowchart illustrating a recovery operation operation in a cache line concierge extendable hashing method according to an embodiment of the present invention.

In step S301, the cache line concierge extendable hashing apparatus 100 according to an embodiment of the present invention starts a recovery operation from the first directory entry.

In step S302, the cache line concierge extendable hashing device 100 checks whether the current location is larger than the directory size.

In step S303, if the current location is less than or equal to the size of the directory, the cache line concierge extendable hashing apparatus 100 checks the local depth of the current location. In step S302, if the current location is larger than the directory size, the cache line concierge extendable hashing apparatus 100 ends the recovery operation.

In step S304, the cache line concierge extendable hashing device 100 checks a stride value. That is, the cache line concierge extendable hashing apparatus 100 obtains a stride value such as Stride = 2 ^{(global depth-current depth)} .

In step S305, the cache line concierge extendable hashing device 100 checks the buddy value. That is, the cache line concierge extendable hashing device 100 checks a buddy value such as buddy = current position + stride.

In step S306, the cache line concierge extendable hashing device 100 checks whether the buddy has reached the current position.

In step S307, when the buddy reaches the current position, the cache line concierge extendable hashing device 100 adds a stride to the current position.

In step S308, if the buddy does not reach the current position, the cache line concierge extendable hashing apparatus 100 checks whether the local depth of the buddy is equal to the current depth.

In step S309, if the local depth of the buddy is not the same as the current depth, the cache line concierge extendable hashing apparatus 100 stores the current depth in the local depth of the buddy. On the other hand, the cache line concierge extendable hashing apparatus performs step S307 if the local depth of the buddy is the same as the current depth.

In step S310, the cache line concierge extendable hashing apparatus 100 stores the current depth in the local depth of the buddy and then decreases the buddy value. In addition, the cache line concierge extendable hashing apparatus 100 performs step S308.

Meanwhile, the experimental settings for the embodiments of the present invention will be described.

For experiments on the embodiments of the present invention, two Intel Xeon Haswell-EX E7-4809 v3 processors are used. The processor used in the experiment has 8 cores, 2.0 GHz, 8 × 32 KB instruction cache, 8 × 32 KB data cache, 8 × 256 KB L2 cache, and 20 MB L3 cache. And 64GB of DDR3 DRAM and DRAM based PM latency emulator, Quartz were used. To emulate write latency, we insert a stall cycle after each clflush command.

18A to 18C are diagrams showing experimental results of throughputs having various segment/bucket sizes for an embodiment of the present invention and a prior art.

The conventional EXTH (LSB) divides the bucket less frequently as the bucket size increases, as shown in FIG. 18B. However, as shown in Figs. 18A and 18C, when searching for an empty slot or record, a larger number of cache lines are read.

The insertion throughput of CCEH (MSB) and CCEH (LSB) according to an embodiment of the present invention increases as the segment size increases to a maximum of 16 KB because segment segmentation is less frequent, whereas as shown in FIGS. 18A and 18C Likewise, the number of cache lines to be read, that is, the missing last level cache (LLC) is not affected by the large segment size.

19A to 19D are diagrams showing time required for insertion while changing the R/W latency of a nonvolatile memory for the embodiment of the present invention and the prior art.

In FIGS. 19A to 19D, a write operation represents a bucket search and write time. Rehash operation represents the rehash time. Cuckoo Displacement refers to the time to move an existing record to another bucket for cuckoo hashing. 19A to 19D, CCEH according to an embodiment of the present invention shows the fastest average insertion time in the whole.

20A to 20C are diagrams showing simultaneous execution performance for latency CDF and insertion/retrieval throughput for the embodiment of the present invention and the prior art.

As shown in FIGS. 20A to 20C, the rest of the implementations except for the CCEH according to the embodiment of the present invention suffer from a total table rehashing overhead. CCEH(C) surpasses CCEH in search throughput, such as CoW (Copy-on-Write) lock free search. As shown in Fig. 20C, the read transaction of CCEH(C) is non-blocking.

The cache line concierge extendable hashing method according to the embodiments of the present invention described above may be implemented as a computer-readable code on a computer-readable recording medium. The cache line concierge extendable hashing method according to the embodiments of the present invention may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable recording medium.

A non-transitory computer-readable storage medium comprising at least one program executable by a processor, wherein when the at least one program is executed by the processor, the processor causes: a first index of a hash key. To check the segment referenced through the directory, check the bucket to be accessed within the identified segment by using the second index of the hash key, and check the identified bucket. A non-transitory computer-readable storage medium may be provided that includes instructions for inserting a key value corresponding to a hash key.

The above-described method according to the present invention may be implemented as a computer-readable code on a computer-readable recording medium. The computer-readable recording medium includes all kinds of recording media in which data that can be decoded by a computer system is stored. For example, there may be read only memory (ROM), random access memory (RAM), magnetic tape, magnetic disk, flash memory, optical data storage device, and the like. In addition, the computer-readable recording medium can be distributed to a computer system connected through a computer communication network, and stored and executed as code that can be read in a distributed manner.

Although described above with reference to the drawings and examples, it does not mean that the protection scope of the present invention is limited by the drawings or examples, and those skilled in the art It will be appreciated that various modifications and changes can be made to the present invention without departing from the spirit and scope.

Specifically, the described features may be implemented in digital electronic circuitry, or computer hardware, firmware, or combinations thereof. Features may be executed in a computer program product implemented in storage in a machine-readable storage device, for example, for execution by a programmable processor. And the features can be performed by a programmable processor executing a program of directives to perform the functions of the described embodiments by operating on input data and generating output. The described features include at least one programmable processor, at least one input device, and at least one output coupled to receive data and directives from the data storage system and to transmit data and directives to the data storage system. It can be executed within one or more computer programs that can be executed on a programmable system including the device. A computer program includes a set of directives that can be used directly or indirectly within a computer to perform a specific action on a given result. Computer programs are written in any form of programming language, including compiled or interpreted languages, and included as modules, elements, subroutines, or other units suitable for use in other computer environments, or as independently operable programs. It can be used in any form.

Suitable processors for execution of a program of directives include, for example, both general and special purpose microprocessors, and either a single processor or multiple processors of a different type of computer. Storage devices suitable for implementing computer program directives and data implementing the described features are, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices, magnetic devices such as internal hard disks and removable disks. Devices, magneto-optical disks, and all types of non-volatile memory including CD-ROM and DVD-ROM disks. The processor and memory may be integrated within application-specific integrated circuits (ASICs) or added by ASICs.

The present invention described above is described on the basis of a series of functional blocks, but is not limited by the above-described embodiments and the accompanying drawings, and various substitutions, modifications and changes within the scope not departing from the technical spirit of the present invention It will be apparent to those of ordinary skill in the art to which this invention pertains.

Combinations of the above-described embodiments are not limited to the above-described embodiments, and combinations of various types as well as the above-described embodiments may be provided according to implementation and/or need.

In the above-described embodiments, the methods are described on the basis of a flow chart as a series of steps or blocks, but the present invention is not limited to the order of steps, and certain steps may occur in a different order or concurrently with the steps described above. I can. In addition, those of ordinary skill in the art understand that the steps shown in the flowchart are not exclusive, other steps are included, or one or more steps in the flowchart may be deleted without affecting the scope of the present invention. You can understand.

The above-described embodiments include examples of various aspects. Although not all possible combinations for representing the various aspects can be described, those of ordinary skill in the art will recognize that other combinations are possible. Accordingly, the present invention will be said to include all other replacements, modifications and changes falling within the scope of the following claims.

100: cacheline concierge extendable hashing device
110: processor
120: cache
130: memory

Claims (23)

In the extendable hashing method performed by a Cacheline Conscious Extendible Hashing device,
Identifying a segment referenced through a directory by using a first index of a hash key;
Identifying a bucket to be accessed within the identified segment by using a second index of the hash key; And
And storing data corresponding to the hash key in the identified bucket. The method of claim 1,
The method further comprising the step of checking a global depth bit value of the hash key. The method of claim 1,
The first index of the hash key,
Including the most significant bit of the hash key (Most Significant Bit, MSB), cache line concierge extendable hashing method. The method of claim 1,
The second index of the hash key,
Including the least significant bit (Least Significant Bit, LSB) of the hash key, cache line concierge extendable hashing method. The method of claim 1,
The step of identifying the segment,
A method of searching for a directory entry corresponding to the first index of the hash key and identifying a segment referenced through the searched directory entry. The method of claim 1,
The method further comprising dividing the segment when a collision occurs when a segment is accessed by using the second index of the hash key. The method of claim 6,
The step of dividing the segment,
A cache that creates a new segment with increased local depth, scans data of the identified segment, and copies data having a preset bit value corresponding to the increased local depth to the created new segment Line concierge extendable hashing method. The method of claim 6,
The step of dividing the segment,
A method of increasing a local depth of the segmented segment and designating data having a different bit value corresponding to the increased local depth as an invalid key. The method of claim 6,
The step of dividing the segment,
A method of increasing the local depth of the identified segment, updating a pointer of a directory entry, and increasing the local depth of the segmented segment. The method of claim 6,
If the segment is divided, the method further comprising the step of grouping the directory entries into a pair of a buddy (buddy) when updating the directory, cacheline concierge extendable hashing method. The method of claim 10,
Using the global depth and the local depth of the segment to identify the segment in which the system problem has occurred, and performing recovery of the segment in which the system problem has occurred by using the buddy, the cacheline concierge extendable hashing method. . A memory storing at least one program and storing a segment including at least one bucket referenced through a directory; And
Including a processor connected through the memory and cache,
The processor, by executing the at least one program,
Check the segment referenced through the directory by using the first index of the hash key,
Using the second index of the hash key, a bucket to be accessed within the identified segment is identified,
A cache line concierge extendable hashing device that writes or reads data corresponding to the hash key in the verified bucket. The method of claim 12,
The processor,
Further comprising the step of checking a global depth bit value of the hash key. The method of claim 12,
The first index of the hash key,
A cache line concierge extendable hashing device including the most significant bit (MSB) of the hash key. The method of claim 12,
The second index of the hash key,
A cache line concierge extendable hashing device including a least significant bit (LSB) of the hash key. The method of claim 12,
The processor,
A cache line concierge extendable hashing device for searching for a directory entry corresponding to the first index of the hash key and identifying a segment referenced through the searched directory entry. The method of claim 12,
The processor,
A cacheline concierge extendable hashing device that divides a segment when a collision occurs when a segment is accessed using the second index of the hash key. The method of claim 17,
The processor,
A cache that creates a new segment with increased local depth, scans data of the identified segment, and copies data having a preset bit value corresponding to the increased local depth to the created new segment Line concierge extendable hashing device. The method of claim 17,
The processor,
A cache line concierge extendable hashing device that increases a local depth of the segmented segment and designates data having another preset bit value corresponding to the increased local depth as an invalid key. The method of claim 17,
The processor,
A cacheline concierge extendable hashing device for increasing the local depth of the identified segment, updating a pointer of a directory entry, and increasing the local depth of the segmented segment. The method of claim 17,
The processor,
When the identified segment is divided, when updating a directory, the directory entries are grouped into a pair called a buddy. The method of claim 21,
The processor,
A cacheline concierge extendable hashing device that checks a segment in which a system problem occurs using the global depth and a local depth of the segment, and recovers a segment in which a system problem occurs using the buddy. A non-transitory computer-readable storage medium comprising at least one program executable by a processor, wherein the at least one program, when executed by the processor, causes the processor to:
Check the segment referenced through the directory by using the first index of the hash key,
Using the second index of the hash key, a bucket to be accessed within the identified segment is identified,
A non-transitory computer-readable storage medium comprising instructions for causing inserting a key value corresponding to the hash key into the identified bucket.

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