KR20200099806A - Semiconductor package - Google Patents

Abstract

The present invention relates to a semiconductor package which can perform packaging to have optimal electrical properties. The semiconductor package comprises: a frame having a through unit; a first semiconductor chip arranged in the through unit of the frame, having a first surface on which a first connection pad is arranged and a second surface on which a second connection pad is arranged, and including a through via connecting the first connection pad and the second connection pad; a second semiconductor chip arranged on the first surface of the first semiconductor ship at the through unit of the frame and disposed to allow an active surface on which a third connection pad is arranged to face the first semiconductor chip; a conductive bonding layer arranged between the first connection pad and the third connection pad; and a connection structure arranged on the second surface of the first semiconductor chip and including a redistribution layer electrically connected to the first connection pad and the third connection pad. The third connection pad is electrically connected to the redistribution layer through the through via.

Description

Semiconductor package {SEMICONDUCTOR PACKAGE}

The present disclosure relates to a semiconductor package, for example a fan-out semiconductor package.

With the recent development of smart electronic devices, the specifications of components used for this are also increasing. For example, the specification of an application processor (AP), which is a core component of smart electronic devices, is rapidly developing. Several methods are applied to improve the performance of the AP, and among them, the recently applied method is the partition method for each function of the AP. For example, by dividing a die for each function and designing and packaging each semiconductor chip according to the optimum process and characteristics, it is possible to implement better performance than a conventional single AP. However, in this case, a high-level packaging method is required. Accordingly, there is a need for a package structure capable of packaging a plurality of divided semiconductor chips to have optimal signal characteristics.

One of the various objects of the present disclosure is to provide a new type of package structure capable of packaging a plurality of semiconductor chips to have optimal electrical characteristics.

One of the various solutions proposed through the present disclosure is to configure a semiconductor package to transmit a signal to an upper semiconductor chip through a through via penetrating the semiconductor chip.

For example, in the semiconductor package according to an example proposed in the present disclosure, a frame having a through part, disposed at a through part of the frame, a first surface on which a first connection pad is disposed, and a second side opposite to the first surface, A first semiconductor chip having a second surface on which a connection pad is disposed and including a through via connecting the first connection pad and the second connection pad, The first surface of the first semiconductor chip at the through part of the frame A second semiconductor chip disposed on the second semiconductor chip and disposed so that the active surface on which the third connection pad is disposed faces the first semiconductor chip, and a third connection between the first connection pad of the first semiconductor chip and the second semiconductor chip A conductive bonding layer disposed between the pads, and disposed on the second surface of the first semiconductor chip, and the first connection pad of the first semiconductor chip and the third connection pad of the second semiconductor chip are electrically And a connection structure including a connected redistribution layer, and a third connection pad of the second semiconductor chip is electrically connected to the redistribution layer through the through via.

As one of the various effects of the present disclosure, a package structure capable of packaging a plurality of semiconductor chips to have optimal electrical characteristics may be provided.

1 is a block diagram schematically showing an example of an electronic device system.
2 is a perspective view schematically showing an example of an electronic device.
3A and 3B are cross-sectional views schematically illustrating a fan-in semiconductor package before and after packaging.
4 is a cross-sectional view schematically illustrating a packaging process of a fan-in semiconductor package.
5 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.
6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.
7 is a schematic cross-sectional view of a fan-out semiconductor package.
8 is a schematic cross-sectional view illustrating a case where a fan-out semiconductor package is mounted on a main board of an electronic device.
9 is a schematic cross-sectional view of an example of a semiconductor package.
10 is a cross-sectional view schematically showing another example of a semiconductor package.
11 is a schematic cross-sectional view of another example of a semiconductor package.
12 is a schematic cross-sectional view of another example of a semiconductor package.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the drawings, the shapes and sizes of elements may be exaggerated or reduced for clearer explanation.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawings, the electronic device 1000 accommodates a main board 1010. A chip-related part 1020, a network-related part 1030, and other parts 1040 are physically and/or electrically connected to the main board 1010. These are also combined with other components to be described later to form various signal lines 1090.

The chip-related parts 1020 include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as a central processor (eg, a CPU), a graphics processor (eg, a GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; Logic chips such as analog-to-digital converters and application-specific ICs (ASICs) are included, but are not limited thereto, and other types of chip-related components may be included in addition to this. Also, of course, these parts 1020 may be combined with each other.

Network-related parts 1030 include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated as such and beyond, including, but not limited to, many other wireless or wired protocols. Any of the standards or protocols may be included. In addition, it goes without saying that the network-related component 1030 may be combined with the chip-related component 1020 with each other.

Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (Electro Magnetic Interference) filters, and MLCC (Multi-Layer Ceramic Condenser). , It is not limited thereto, and in addition, passive components used for various other purposes may be included. In addition, it goes without saying that the other components 1040 may be combined with each other along with the chip-related component 1020 and/or the network-related component 1030.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and/or electrically connected to the main board 1010. For example, the camera 1050, antenna 1060, display 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown), compass ( Not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage device (eg, hard disk drive) (not shown), compact disk (CD) (not shown), and DVD There are (digital versatile disk) (not shown), but are not limited thereto, and other parts used for various purposes may be included depending on the type of the electronic device 1000.

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( computer), a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, the present invention is not limited thereto, and, of course, it may be any other electronic device that processes data in addition to these.

2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, a semiconductor package is applied to various electronic devices as described above for various purposes. For example, a printed circuit board 1110 is accommodated in the body 1101 of the smart phone 1100, and various components 1120 are physically and/or electrically connected to the printed circuit board 1110. In addition, other components that may or may not be physically and/or electrically connected to the printed circuit board 1110 such as the camera 1130 are accommodated in the body 1101. Some of the components 1120 may be chip-related parts, for example, the semiconductor package 1121, but are not limited thereto. It goes without saying that the electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

Semiconductor package

In general, a semiconductor chip is integrated with numerous microelectronic circuits, but cannot itself serve as a finished semiconductor product, and there is a possibility of being damaged by an external physical or chemical impact. Therefore, the semiconductor chip itself is not used as it is, but the semiconductor chip is packaged and used in an electronic device.

The reason why semiconductor packaging is necessary is that there is a difference in circuit width between the semiconductor chip and the main board of the electronic device from the viewpoint of electrical connection. Specifically, in the case of a semiconductor chip, the size of the connection pad and the gap between the connection pads are very small, whereas in the case of a main board used in electronic devices, the size of the component mounting pad and the gap between the component mounting pads are much larger than that of the semiconductor chip. . Therefore, it is difficult to directly mount a semiconductor chip on such a main board, and a packaging technology capable of buffering the difference in circuit width between each other is required.

Semiconductor packages manufactured by such a packaging technology may be classified into a fan-in semiconductor package and a fan-out semiconductor package according to a structure and use.

Hereinafter, a fan-in semiconductor package and a fan-out semiconductor package will be described in more detail with reference to the drawings.

(Fan-In Semiconductor Package)

3A and 3B are cross-sectional views schematically illustrating a fan-in semiconductor package before and after packaging.

4 is a cross-sectional view schematically illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, the semiconductor chip 2220 includes a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc., and aluminum (Al) formed on one surface of the body 2221. For example, including a connection pad 2222 including a conductive material and a passivation film 2223 such as an oxide film or a nitride film formed on one surface of the body 2221 and covering at least a part of the connection pad 2222, It may be an integrated circuit (IC) in a bare state. At this time, since the connection pad 2222 is very small, the integrated circuit (IC) is difficult to be mounted on a main board of an electronic device as well as a printed circuit board (PCB) of an intermediate level.

Accordingly, a connection structure 2240 is formed on the semiconductor chip 2220 according to the size of the semiconductor chip 2220 in order to redistribute the connection pad 2222. In the connection structure 2240, an insulating layer 2241 is formed of an insulating material such as a photosensitive insulating material (PID) on the semiconductor chip 2220, and a via hole 2243h for opening the connection pad 2222 is formed. It may be formed by forming a wiring pattern 2242 and a via 2243. After that, a passivation layer 2250 for protecting the connection structure 2240 is formed, an opening 2251 is formed, and an under bump metal layer 2260 or the like is formed. That is, through a series of processes, for example, a fan-in semiconductor package 2200 including a semiconductor chip 2220, a connection structure 2240, a passivation layer 2250, and an under bump metal layer 2260 is manufactured. do.

As such, the fan-in semiconductor package is in the form of a package in which all connection pads of a semiconductor chip, such as I/O (Input / Output) terminals, are placed inside the device. have. Accordingly, many devices that enter the smartphone are manufactured in the form of fan-in semiconductor packages, and specifically, development is being made in the direction of implementing small and fast signal transmission.

However, the fan-in semiconductor package has many space limitations since all I/O terminals must be placed inside the semiconductor chip. Therefore, this structure has a difficulty in applying to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a small size. In addition, due to this vulnerability, the fan-in semiconductor package cannot be directly mounted and used on the main board of the electronic device. This is because even if the size and spacing of the I/O terminals of the semiconductor chip are enlarged through the rewiring process, they do not have the size and spacing that can be directly mounted on the main board of electronic devices.

5 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

Referring to the drawing, in the fan-in semiconductor package 2200, the connection pads 2222 of the semiconductor chip 2220, that is, the I/O terminals are rewired once again through the interposer substrate 2301, and finally The fan-in semiconductor package 2200 may be mounted on the main board 2500 of the electronic device while the fan-in semiconductor package 2200 is mounted on the interposer substrate 2301. In this case, the solder ball 2270 may be fixed with an underfill resin 2280 or the like, and the outside may be covered with a molding material 2290 or the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pads of the semiconductor chip 2220 by the interposer substrate 2302 in an embedded state. (2222), that is, the I/O terminals are rewired once again, and may be finally mounted on the main board 2500 of the electronic device.

In this way, since the fan-in semiconductor package is directly mounted on the main board of an electronic device and is difficult to use, it is mounted on a separate interposer substrate and then re-packaged to be mounted on the electronic device main board, or It is used by being mounted on an electronic device main board while being embedded in a substrate.

(Fan-out semiconductor package)

7 is a schematic cross-sectional view of a fan-out semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 is protected with a sealing material 2130, and the connection pad 2122 of the semiconductor chip 2120 is a connection structure. The rewiring is performed to the outside of the semiconductor chip 2120 by 2140. In this case, a passivation layer 2202 may be further formed on the connection structure 2140, and an under bump metal layer 2160 may be further formed in the opening of the passivation layer 2202. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, and a passivation layer (not shown). The connection structure 2140 includes an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2241, a via 2143 electrically connecting the connection pad 2122 and the redistribution layer 2142, etc. I can.

As described above, in the fan-out semiconductor package, the I/O terminals are rearranged and arranged to the outside of the semiconductor chip through the connection structure formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip must be placed inside the semiconductor chip, and when the device size is reduced, the ball size and pitch must be reduced, and thus a standardized ball layout cannot be used. On the other hand, the fan-out semiconductor package is a form in which the I/O terminals are rearranged and arranged to the outside of the semiconductor chip through the connection structure formed on the semiconductor chip. Since it can be used as it is, it can be mounted on a main board of an electronic device without a separate printed circuit board as will be described later.

8 is a schematic cross-sectional view illustrating a case where a fan-out semiconductor package is mounted on a main board of an electronic device.

Referring to the drawings, a fan-out semiconductor package 2100 may be mounted on a main board 2500 of an electronic device through a solder ball 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 is a connection structure capable of rewiring the connection pads 2122 on the semiconductor chip 2120 to a fan-out area outside the size of the semiconductor chip 2120 Since the 2140 is formed, a standardized ball layout can be used as it is, and as a result, it can be mounted on the main board 2500 of an electronic device without a separate interposer substrate.

In this way, since the fan-out semiconductor package can be mounted on the main board of an electronic device without a separate interposer substrate, it is possible to achieve a smaller thickness and thinner than a fan-in semiconductor package using an interposer substrate. Do. In addition, it is particularly suitable for mobile products due to its excellent thermal and electrical properties. In addition, it can be implemented more compactly than a general POP (Package on Package) type using a printed circuit board (PCB), and can solve a problem due to the occurrence of warpage.

Meanwhile, the fan-out semiconductor package refers to a package technology for mounting the semiconductor chip on the main board of an electronic device, and for protecting the semiconductor chip from external shocks, and the scale and use thereof are different. It is a different concept from a printed circuit board (PCB) such as an interposer board in which a fan-in semiconductor package is embedded.

Hereinafter, a new type of package structure capable of packaging a plurality of semiconductor chips to have optimum signal characteristics will be described with reference to the drawings.

9 is a schematic cross-sectional view of an example of a semiconductor package.

Referring to the drawings, a semiconductor package 10A according to an example is a POP structure including a first semiconductor package 100 and a second semiconductor package 200 vertically stacked, and is formed on the first semiconductor package 100. The second semiconductor package 200 is stacked. The first semiconductor package 100 is disposed on the frame 110 having the through portion 110H, the through portion 110H of the frame 110, and is disposed on the first connection pad 122 and the non-active surface. The first semiconductor chip 120 having the second connection pad 123 disposed, and the through portion 110H of the frame 110 are stacked and disposed on the first semiconductor chip 120, respectively, and have third and fourth connections, respectively. The second and third semiconductor chips 161 and 162 having pads 161P and 162P, the first connection pad 122 of the first semiconductor chip 120 and the second and third semiconductor chips 161 and 162 The bonding layer 150 including the conductive layer 152 disposed between the third and fourth connection pads 161P and 162P, the frame 110 and the first semiconductor chip 120 1 A first connection structure 140 disposed on an inactive surface of the encapsulant 130, the frame 110 and the first semiconductor chip 120 and including the first redistribution layers 142a, 142b, 142c, and the first A second connection structure 170 disposed on the encapsulant 130 and including a second redistribution layer 172, a first passivation layer 190 disposed on the first connection structure 140, and a first passivation layer The under bump metal layer 160 disposed on the opening of 190, the electrical connection metal 165 disposed on the first passivation layer 190 and connected to the under bump metal layer 160, and the first passivation layer 190 And a passive component 180 disposed thereon. The second semiconductor package 200 includes a wiring board 210, a plurality of fourth semiconductor chips 220 disposed on the wiring board 210, and a second encapsulant 230 sealing the fourth semiconductor chips 220. , And an upper connection terminal 265 under the wiring board 210.

The first semiconductor chip 120 includes a body portion 121, first and second connection pads 122 and 123, and a through via 125. In the first semiconductor chip 120, a surface on which the first connection pad 122 is disposed may be an active surface, and a surface opposite to which the second connection pad 123 is disposed may be an inactive surface, but is not limited thereto. . The through via 125 connects the first and second connection pads 122 and 123, and from the second connection pad 123 to the active surface or a region adjacent to the active surface, the first semiconductor chip 120 It extends through at least a portion. At least a portion of the through via 125 may be electrically connected to semiconductor devices inside the first semiconductor chip 120.

The second and third semiconductor chips 161 and 162 are disposed in the through portion 110H of the frame 110 and are stacked and disposed on the active surface of the first semiconductor chip 120. The second and third semiconductor chips 161 and 162 are disposed so that the active surface on which the third and fourth connection pads 161P and 162P are disposed faces the first semiconductor chip 120, respectively. Accordingly, the first semiconductor chip 120 and the second and third semiconductor chips 161 and 162 are disposed to face each other with active surfaces.

The bonding layer 150 is disposed between the first semiconductor chip 120 and the second and third semiconductor chips 161 and 162 to form the first semiconductor chip 120 and the second and third semiconductor chips 161 and 162. ) Is a bonding layer. The bonding layer 150 is between the first connection pad 122 of the first semiconductor chip 120 and the third and fourth connection pads 161P and 162P of the second and third semiconductor chips 161 and 162. A conductive layer 152 and a dielectric layer 154 surrounding the conductive layer 152 may be included.

Meanwhile, in order to improve the performance of an AP, which is a core component of a smart electronic device, a partition method for each function of the AP can be applied. For example, by dividing the die for each function and designing and packaging each semiconductor chip according to the optimum process and characteristics, it is possible to implement better performance than the existing single AP.

Thus, in the semiconductor package 10A according to an example, the first semiconductor chip 120 and the second and third semiconductor chips 161 and 162 are connected to at least a portion of the first connection pad 122 and the third and fourth connection pads. (161P, 162P) are arranged to face each other, and are connected by a bonding layer 150. Each of the first to third semiconductor chips 120, 161, and 162 may be chips in which the application processor AP is divided for each function. That is, each of the first to third semiconductor chips 120, 161, and 162 may be chips constituting some or all functions of the application processor. The second and third semiconductor chips 161 and 162 may be disposed so that at least a portion of the second and third semiconductor chips 161 and 162 overlap the first semiconductor chip 120 vertically. At this time, at least a portion of the first connection pad 122 is electrically connected to the third and fourth connection pads 161P and 162P vertically in an overlapping area. In this way, the first semiconductor chip 120 and the second and third semiconductor chips 161 and 162 can be connected between signals in a vertical direction. Therefore, since the first to third semiconductor chips 120, 161, 162 are connected with the shortest distance, signal characteristics can be optimized, and at the same time, by using the through via 125, the lower first connection structure 140 and the The connection with the electrical connection metal 165 can be improved.

Hereinafter, each configuration included in the semiconductor package 10A according to an example will be described in more detail.

The frame 110 may further improve the rigidity of the first semiconductor package 100 according to a specific material, and may perform a role of securing uniformity of the thickness of the first encapsulant 130. In addition, the fan-out semiconductor package 10A according to an example may be used as a part of the POP by the frame 110. Frame 110 has a through portion (110H). In the through portion 110H, the first semiconductor chip 120 and the second and third semiconductor chips 161 and 162 are disposed to be spaced apart from the frame 110 by a predetermined distance. The circumferences of side surfaces of the first and third semiconductor chips 120 and 161 and 162 may be surrounded by the frame 110. However, this is only an example and may be variously modified into different forms, and of course, different functions may be performed depending on the form. If necessary, the frame 110 may be omitted, but the case of having the frame 110 may be more advantageous in securing the board level reliability intended in the present disclosure.

The frame 110 includes a core insulating layer 111, a wiring layer 112 disposed on both sides of the core insulating layer 111, and a core via 113 connecting the upper and lower wiring layers 112 through the core insulating layer 111. ). Accordingly, the wiring layers 112 disposed on both sides of the core insulating layer 111 are electrically connected through the core via 113.

An insulating material may be used as the material of the core insulating layer 111, and in this case, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or these resins are inorganic fillers and/or glass fiber. , Glass Cloth, Glass Fabric), etc., an insulating material impregnated into a core material, for example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), etc. may be used. This frame 110 may serve as a support member.

The wiring layer 112 may serve to electrically connect the first and second semiconductor packages 100 and 200. The material for forming the wiring layer 112 is copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or Conductive materials such as alloys of these can be used. The wiring layer 112 may perform various functions according to the design of the corresponding layer. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like may be included. Here, the signal S pattern includes various signals, for example, data signals, excluding the ground (GND) pattern, the power (PWR) pattern, and the like. Here, the pattern is a concept including wiring and pads.

The core via 113 electrically connects the wiring layers 112 formed on different layers, thereby forming an electrical path in the frame 110. The core via 113 may also be formed of a conductive material. The core via 113 may be completely filled with a conductive material, or a conductive material may be formed along the wall surface of the via hole. In addition, all known shapes such as a cylindrical shape as well as a tapered shape can be applied.

Each of the first semiconductor chip 120 and the second and third semiconductor chips 161 and 162 may be an integrated circuit (IC) in which hundreds to millions or more of devices are integrated into one chip. Central processor (e.g., CPU), graphic processor (e.g., GPU), field programmable gate array (FPGA), digital signal processor, encryption processor, microprocessor, processor chips such as microcontrollers, specifically application processor (AP) ), but is not limited thereto. Each of the first semiconductor chip 120 and the second and third semiconductor chips 161 and 162 is a chip in which some functions of the application processor (AP) are divided, for example, a central processor (CPU), a graphic processor (GPU). ), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, and/or a microcontroller, or the like, and may be a divided chip having other functions not illustrated thereto. As a non-limiting example, the first to third semiconductor chips 120, 161, and 162 may be combined to form one complete application processor AP. In this case, the first semiconductor chip 120 may be a main chip, and the second and third semiconductor chips 161 and 162 may be a sub chip. However, the present invention is not limited thereto, and the second and third semiconductor chips 161 and 162 may be memories such as volatile memory (DRAM), non-volatile memory (ROM), and flash memory, respectively.

The first semiconductor chip 120 may be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as a base material forming the body portion 121. . Various semiconductor devices and circuits may be formed in the body portion 121. The first and second connection pads 122 and 123 and the through via 125 are for electrically connecting the first semiconductor chip 120 to other components, and forming materials include aluminum (Al) and copper (Cu ), etc., can be used without special restrictions. A passivation film exposing the first and second connection pads 122 and 123 may be further formed on the body portion 121, and in this case, the passivation film may be an oxide film or a nitride film, or a double layer of an oxide film and a nitride film. . The first semiconductor chip 120 may be a bare die, but if necessary, a packaged die in which a separate redistribution layer is further formed on the surface on which the first connection pad 122 is disposed, that is, the active surface. It could also be (packaged die).

The second and third semiconductor chips 161 and 162 may each be a die formed based on an active wafer, and silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as the base material forming the body. have. Various circuits may be formed in each body. The third and fourth connection pads 161P and 162P are for electrically connecting the second and third semiconductor chips 161 and 162 to other components, and as a forming material, copper (Cu), aluminum (Al ) Can be used. A passivation layer exposing the second and third connection pads 161P and 162P, respectively, may be formed on the body, and the passivation layer may be an oxide layer or a nitride layer, or a double layer of an oxide layer and a nitride layer. An insulating film or the like may be further disposed at other required positions. The second and third semiconductor chips 161 and 162 may also be bare dies, respectively, but if necessary, separate surfaces on which the third and fourth connection pads 161P and 162P are disposed, that is, on the active surface, respectively. It may be a packaged die in which a redistribution layer is further formed.

The bonding layer 150 includes a conductive layer 152 and a dielectric layer 154. The conductive layer 152 may be disposed in a region including a region between the first connection pad 122 and the third and fourth connection pads 161P and 162P. The conductive layer 152 may be, for example, a copper (Cu) layer, and a copper layer on the first connection pad 122 and a copper layer on the third and fourth connection pads 161P and 162P are copper (Cu)- It may be a layer formed by performing copper (Cu) bonding. The first connection pad 122 and the third and fourth connection pads 161P and 162P may be electrically connected through the conductive layer 152. The dielectric layer 154 may be disposed so as to surround the conductive layer 152 on active surfaces of the first semiconductor chip 120 and the second and third semiconductor chips 161 and 162, respectively. The dielectric layer 154 may be a layer formed by performing dielectric-dielectric bonding between a dielectric layer on the first semiconductor chip 120 and a dielectric layer on the second and third semiconductor chips 161 and 162. According to embodiments, the dielectric layer 154 may include at least a portion of the passivation layer of the first semiconductor chip 120 and the second and third semiconductor chips 161 and 162. The dielectric layer 154 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

The first encapsulant 130 may protect the frame 110, the first semiconductor chip 120, the second and third semiconductor chips 161 and 162, and the like. The suture form of the first suture material 130 is not particularly limited. For example, the first encapsulant 130 includes the frame 110, a part of the surface of the first semiconductor chip 120 on which the first connection pad 122 is disposed, and the second and third semiconductor chips 161, The inactive surface of the 162 may be covered, and at least a portion of the through portion 110H may be filled. When the first encapsulant 130 fills the penetrating portion 110H, it is possible to reduce buckling while performing an adhesive role according to a specific material.

The material of the first encapsulant 130 is not particularly limited. For example, an insulating material may be used. In this case, as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or these resins are mixed with an inorganic filler, or glass fiber together with an inorganic filler. , Glass Cloth, Glass Fabric), etc., a resin impregnated into a core material such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), etc. may be used. If necessary, a photosensitive insulating (Photo Imagable Encapsulant: PIE) resin can also be used.

The first connection structure 140 may rearrange the first to fourth connection pads 122, 123, 161P and 162P of the first to third semiconductor chips 120, 161, 162. In addition, the first to fourth connection pads 122, 123, 161P, and 162P may be electrically connected to each other according to functions. Tens of millions of first to fourth connection pads 122, 123, 161P, 162P having various functions can be rewired through the first connection structure 140, and the function can be improved through the electrical connection metal 165. It can be physically and/or electrically connected to the outside. The first connection structure 140 includes a first insulating layer 141a disposed on an inactive surface of the frame 110 and the first semiconductor chip 120, and a first redistribution layer disposed on the first insulating layer 141a (142a), a first via 143a connecting the first redistribution layer 142a and the connection pad 122 of the semiconductor chip 120, a second insulating layer 141b disposed on the first insulating layer 141a ), a second redistribution layer 142b disposed on the second insulation layer 141b, a second redistribution layer 142b, which penetrates the second insulation layer 141b and connects the first and second redistribution layers 142a, 142b, 142c Via 143b, a third insulating layer 141c disposed on the second insulating layer 141b, a third redistribution layer 142c disposed on the third insulating layer 141c, and a third insulating layer 141c And a third via 143c passing through and connecting the second and third redistribution layers 142b and 142c. The first to third redistribution layers 142a, 142b, and 142c are electrically connected to the first to fourth connection pads 122, 123, 161P, and 162P. Each component of the first connection structure 140 may be configured with a greater number of layers than that shown in the drawings. Alternatively, it may be composed of fewer layers than those shown in the drawings.

An insulating material may be used as the material of the insulating layers 141a, 141b, and 141c. In this case, a photosensitive insulating material such as PID resin may be used as the insulating material in addition to the insulating material described above. That is, the insulating layers 141a, 141b, and 141c may be photosensitive insulating layers, respectively. When the insulating layers 141a, 141b, 141c have photosensitive properties, the insulating layers 141a, 141b, 141c can be formed thinner, and a fine pitch of the first connection via 143 can be more easily achieved. I can. The insulating layers 141a, 141b, and 141c may be photosensitive insulating layers each including an insulating resin and an inorganic filler. In the case where the insulating layers 141a, 141b, and 141c are multilayers, the materials thereof may be the same and may be different from each other if necessary. In the case where the insulating layers 141a, 141b, and 141c are multilayers, the materials thereof may be the same and may be different from each other if necessary. In the case where the insulating layers 141a, 141b, and 141c are multilayers, they are integrated according to a process, and the boundary may be unclear by itself, but is not limited thereto.

The redistribution layers 142a, 142b, 142c may substantially perform a role of redistributing the connection pad 122, and forming materials include copper (Cu), aluminum (Al), silver (Ag), and tin (Sn). ), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. For example, the seed metal layer 145a and the plated metal layer 145b constituting the redistribution layers 142a, 142b, 142c are made of copper (Cu) or an alloy thereof, and the bonding metal layers 144a, 144b are titanium (Ti). Or it may be made of an alloy thereof. However, the second bonding metal layer 144b is an optional configuration, and may be omitted according to embodiments. The redistribution layers 142a, 142b, and 142c may perform various functions according to the design of the corresponding layer. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like may be included. Here, the signal S pattern includes various signals, for example, data signals, excluding the ground (GND) pattern, the power (PWR) pattern, and the like.

The vias 143a, 143b, and 143c electrically connect the redistribution layers 142a, 142b, 142c, connection pads 122, etc. formed on different layers, thereby forming an electrical path in the package 10A. The material for each of the vias 143a, 143b, and 143c is copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium. Conductive substances, such as (Ti) or an alloy thereof, can be used. For example, the seed metal layer 145a and the plated metal layer 145b forming the vias 143a, 143b, 143c are made of copper (Cu) or an alloy thereof, and the bonding metal layers 144a, 144b are titanium (Ti) or It can be made of an alloy thereof. Each of the vias 143a, 143b, and 143c may be a field type filled with a metal material, or a conformal type in which a metal material is formed along the wall surface of the via hole. Vias 143a, 143b, and 143c may have a tapered cross-sectional shape.

The second connection structure 170 may include an upper redistribution layer 172 disposed on the first encapsulant 130 and an upper via 173 penetrating the first encapsulant 130. The upper via 173 may connect the upper redistribution layer 172 and the core via 113 of the frame 110. Materials for forming the upper redistribution layer 172 and the upper via 173 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and lead (Pb). ), titanium (Ti), or an alloy thereof may be used. The upper redistribution layer 172 may perform various functions according to a design design. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like may be included. The upper via 173 may have a tapered shape opposite to the vias 143a, 143b, and 143c of the first connection structure 140.

The first passivation layer 190 may protect the first connection structure 140 from external physical and chemical damage. The first passivation layer 190 may have an opening exposing at least a portion of the third redistribution layer 142c of the first connection structure 140. Tens to thousands of such openings may be formed in the first passivation layer 190. The material of the first passivation layer 190 is not particularly limited. For example, an insulating material may be used. In this case, as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or these resins are mixed with an inorganic filler, or glass fiber together with an inorganic filler. , Glass Cloth, Glass Fabric), etc., a resin impregnated into a core material such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), etc. may be used. Alternatively, a solder resist (Solder Resist) may be used. Similar to the first passivation layer 190, the second passivation layer 195 may also be formed on the second connection structure 170.

The under bump metal layer 160 improves the connection reliability of the electrical connection metal 165 and, as a result, improves the board level reliability of the package 10A. The under bump metal layer 160 is connected to the third redistribution layer 142c of the first connection structure 140 exposed through the opening of the first passivation layer 190. The under bump metal layer 160 may be formed in the opening of the first passivation layer 190 by using a known conductive material, that is, a metal, by a known metallization method, but is not limited thereto.

The electrical connection metal 165 physically and/or electrically connects the fan-out semiconductor package 10A to the outside. For example, the fan-out semiconductor package 10A may be mounted on a main board of an electronic device through an electrical connection metal 165. The electrical connection metal 165 may be formed of a conductive material, for example, solder, or the like, but this is only an example, and the material is not particularly limited thereto. The electrical connection metal 165 may be a land, a ball, a pin, or the like. The electrical connection metal 165 may be formed as a multilayer or a single layer. When formed as a multilayer, copper pillars and solder may be included, and when formed as a single layer, tin-silver solder or copper may be included, but the present invention is not limited thereto.

The number, spacing, and arrangement form of the electrical connection metal 165 are not particularly limited, and may be sufficiently modified according to design matters for a person skilled in the art. For example, the number of the electrical connection metal 165 may be tens to thousands, and may have a number of more or less. When the electrical connection metal 165 is a solder ball, the electrical connection metal 165 can cover a side surface formed by extending over one surface of the first passivation layer 190 of the under bump metal layer 160, and the connection reliability is more excellent. can do.

At least one of the electrical connection metals 165 is disposed in the fan-out region of the first semiconductor chip 120. The fan-out package is more reliable than the fan-in package, can implement multiple I/O terminals, and 3D interconnection is easy. In addition, compared to a BGA (Ball Grid Array) package and an LGA (Land Grid Array) package, the package thickness can be made thinner, and the price competitiveness is excellent.

The passive component 180 may be disposed on the lower surface of the first passivation layer 190 and may be disposed between the electrical connection metals 165. The passive component 180 may be electrically connected to the third redistribution layer 142c. The passive component 180 may include, for example, a surface mount (SMT) component including an inductor or a capacitor.

Meanwhile, although not shown in the drawings, if necessary, a metal thin film may be formed on the wall surface of the through portion 110H for heat dissipation and/or electromagnetic wave shielding purposes. In addition, if necessary, a plurality of semiconductor chips performing the same or different functions may be disposed in the through portion 110H. In addition, if necessary, a separate passive component, such as an inductor or a capacitor, may be disposed in the through portion 110H.

The wiring board 210 may be a known printed circuit board (PCB) such as an interposer board. The wiring board 210 includes an insulating layer and a conductive wiring layer formed in the insulating layer. A passivation layer or the like may be formed on both sides of the wiring board 210. The structure and shape of the wiring board 210 may be variously changed in the embodiments. Also, in embodiments, an interposer substrate may be further disposed between the wiring substrate 210 and the first semiconductor package 100.

The fourth semiconductor chip 220 may include a plurality of semiconductor chips 221, 222, 223, and 224 stacked in parallel. The fourth semiconductor chip 220 may be attached to the wiring board 210 or the lower fourth semiconductor chip 220 by the adhesive member 225. The fourth semiconductor chip 220 may be electrically connected to the wiring layer 212 of the wiring board 210 by a conductive wire 240 connected to the connection pad 221P. However, in embodiments, the fourth semiconductor chip 220 may be flip-chip bonded on the wiring board 210.

The fourth semiconductor chip 220 may also be an integrated circuit (IC) in which hundreds to millions of devices are integrated in one chip. The integrated circuit may be, for example, a memory chip such as a volatile memory (eg, DRAM) or a non-volatile memory (eg, ROM, flash memory), but is not limited thereto. In each of the fourth semiconductor chips 220, a surface on which the connection pads 221P are disposed becomes an active surface, and an opposite surface thereof is an inactive surface. However, according to embodiments, the fourth semiconductor chip 220 may be disposed in a face-down form. The fourth semiconductor chip 220 may be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as a base material. Various circuits may be formed in the fourth semiconductor chip 220. The connection pad 221P is for electrically connecting the fourth semiconductor chip 220 to other components, and a conductive material such as aluminum (Al) may be used as a forming material without particular limitation.

The adhesive member 225 may easily attach the inactive surface of the fourth semiconductor chip 220 to the upper surface of the lower fourth semiconductor chip 220 or the wiring board 210, respectively. The adhesive member 225 may be, for example, a tape such as a die attaching film (DAF). The material of the adhesive member 225 is not particularly limited. The adhesive member 225 may include, for example, an epoxy component, but is not limited thereto. Since the fourth semiconductor chip 220 can be more stably mounted through the adhesive member 225, reliability can be improved.

The second encapsulant 230 may protect the fourth semiconductor chip 220. The sealing type is not particularly limited, and any type that surrounds at least a portion of the fourth semiconductor chip 220 may be used. For example, the second encapsulant 230 may cover at least a part of the active surface of the fourth semiconductor chip 220, and may also cover at least a part of the side surface of the fourth semiconductor chip 220. The second encapsulant 230 includes an insulating material. Photo imageable epoxy (PIE), PID, etc. may be used as the insulating material. However, it is not limited thereto, and materials including inorganic fillers and insulating resins, such as thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, or resins containing reinforcing materials such as inorganic fillers therein, specifically ABF, etc. May be used. In addition, it goes without saying that a known molding material such as EMC may be used. If necessary, a material in which a thermosetting resin or a thermoplastic resin is impregnated into a core material such as an inorganic filler and/or glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) may be used.

The upper connection terminal 265 may electrically connect the wiring board 210 and the second connection structure 170. The upper connection terminal 265 may be interposed between the wiring layer 212 of the wiring board 210 and the upper redistribution layer 172 of the second connection structure 170. The upper connection terminal 265 may be formed of a conductive material, for example, solder, or the like, but this is only an example, and the material is not particularly limited thereto. The upper connection terminal 265 may be a land, a ball, or a pin.

In the present embodiment, as an example of a semiconductor package, a POP structure in which the first semiconductor package 100 and the second semiconductor package 200 are stacked is illustrated, but embodiments of the present invention are not limited thereto. For example, the semiconductor package may include only the first semiconductor package 100, and other types of semiconductor devices may be disposed on the first semiconductor package 100.

10 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawings, in the semiconductor package 10B according to another example, the frame 110 includes first and second through portions 110Ha and 110Hb, and one or more passives disposed in the second through portions 110Hb It further includes part 185. Further, the first encapsulant 130a and 130b may be configured to seal the passive component 185 and the first semiconductor chip 120 and the second and third semiconductor chips 161 and 162, respectively.

In one example, the passive component 185 may form a single component embedded structure. The component-embedded structure includes a passive component 185, a frame 110, a first encapsulant 130a, and a component insulating layer 141m, a component redistribution layer 142m, and component vias 142c of the connection structure 140. It may include. According to embodiments, the frame 110 may be omitted from the component-embedded structure. However, according to embodiments, the passive component 185 may be disposed inside the frame 110 to be electrically connected to at least some of the redistribution layers 142a, 142b, and 142c. The passive components 180 and 185 may be of the same type or different types. The number of passive components 180 and 185 is not particularly limited, and may be more or less than those shown in the drawings depending on the design.

The first region 130a of the first encapsulant 130a and 130b fills at least a portion of the second through portion 110Ha and seals at least one passive component 185. The second region 130b is disposed on the inactive surface of the second and third semiconductor chips 161 and 162 and extends on the upper surfaces of the passive component 185 and the frame 110, and the first region 130a It can be disposed on the upper surface of. The first and second regions 130a and 130b may include the same or different materials.

Other configurations are substantially the same as those described for the semiconductor package 10A and the like, and detailed descriptions thereof will be omitted.

11 is a schematic cross-sectional view of another example of a semiconductor package.

Referring to the drawings, in the semiconductor package 10C according to another example, the frame 110 has a different shape. Specifically, the frame 110 has a first core insulating layer 111a in contact with the first connection structure 140, a first wiring layer in contact with the first connection structure 140 and buried in the first core insulating layer 111a ( 112a), the second wiring layer 112b disposed on the opposite side of the side where the first wiring layer 112a of the first core insulating layer 111a is buried, and on the first core insulating layer 111a, the second wiring layer And a second core insulating layer 111b covering 112b, and a third wiring layer 112c disposed on the second core insulating layer 111b. The first to third wiring layers 112a, 112b, and 112c are electrically connected to the first to fourth connection pads 122, 123, 161P, and 162P. The first and second wiring layers 112a and 112b and the second and third wiring layers 112b and 112c are formed with first and second core vias 113a passing through the first and second core insulating layers 111a and 111b, respectively. , 113b). Since the frame 110 has a greater number of wiring layers 112a, 112b, and 112c, the first connection structure 140 can be further simplified.

The first wiring layer 112a may be recessed into the first core insulating layer 111a. As described above, when the first wiring layer 112a is recessed into the first core insulating layer 111a and the lower surface of the first core insulating layer 111a and the lower surface of the first wiring layer 112a have a step difference, the first When encapsulating the first semiconductor chip 120 and the frame 110 with the encapsulant 130, the material forming the first encapsulant 130 may be prevented from bleeding to contaminate the first wiring layer 112a. The thickness of the wiring layers 112a, 112b, and 112c of the frame 110 may be thicker than the thickness of the redistribution layers 142a, 142b, and 142c of the first connection structure 140.

The material of the core insulating layers 111a and 111b is not particularly limited. For example, an insulating material may be used. In this case, as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler, for example, ABF (Ajinomoto Build- up Film), etc. can be used. If necessary, a photosensitive insulating (PID) resin can also be used.

When a hole for the first core via 113a is formed, some pads of the first wiring layer 112a may serve as a stopper, and the width of the upper surface of the first core via 113a is A tapered shape larger than the width can be advantageous in the process. In this case, the first core via 113a may be integrated with the pad pattern of the second wiring layer 112b. In addition, when a hole for the second core via 113b is formed, some pads of the second wiring layer 112b may serve as a stopper, and the width of the upper surface of the second core via 113b is A tapered shape larger than the width of the underside may be advantageous in the process. In this case, the second core via 113b may be integrated with the pad pattern of the third wiring layer 112c.

Other configurations are substantially the same as those described for the semiconductor package 10A and the like, and detailed descriptions thereof will be omitted. Meanwhile, it goes without saying that the above-described characteristic configuration of the semiconductor package 10C can also be applied to the semiconductor package 10B according to another embodiment.

12 is a schematic cross-sectional view of another example of a semiconductor package.

Referring to the drawings, in a semiconductor package 10D according to another example, a frame 110 includes a first core insulating layer 111a, a first wiring layer 112a disposed on both surfaces of the first core insulating layer 111a, and The second core insulating layer 111b is disposed on the second wiring layer 112b and the first core insulating layer 112a and covers the first wiring layer 112a, and the third is disposed on the second core insulating layer 111b. The redistribution layer 112c, the third core insulating layer 111c disposed on the first core insulating layer 111a to cover the second wiring layer 112b, and the fourth disposed on the third core insulating layer 111c It includes a wiring layer 112d. The first to fourth wiring layers 112a, 112b, 112c, and 112d are electrically connected to the first to fourth connection pads 122, 123, 161P, and 162P. Since the frame 110 includes a larger number of wiring layers 112a, 112b, 112c, and 112d, the first connection structure 140 can be further simplified. Accordingly, it is possible to improve a yield decrease due to defects occurring in the process of forming the first connection structure 140. On the other hand, the first to fourth wiring layers 112a, 112b, 112c, and 112d are the first to third core vias 113a, 113b, and 113c passing through the first to third core insulating layers 111a, 111b, and 111c, respectively. ) Can be electrically connected.

The first core insulating layer 111a may be thicker than the second core insulating layer 111b and the third core insulating layer 111c. The first core insulating layer 111a may be relatively thick in order to maintain rigidity, and the second core insulating layer 111b and the third core insulating layer 111c may have a larger number of wiring layers 112c and 112d. It may be introduced to form. The first core insulating layer 111a may include an insulating material different from the second core insulating layer 111b and the third core insulating layer 111c. For example, the first core insulating layer 111a may be, for example, a prepreg including a core material, a filler, and an insulating resin, and the second core insulating layer 111c and the third core insulating layer 111c are It may be an ABF film or a PID film including a filler and an insulating resin, but is not limited thereto. From a similar viewpoint, the first core via 113a penetrating through the first core insulating layer 111a is the second and third core vias 113b and 113c penetrating the second and third core insulating layers 111b and 111c. ) Can be larger than the diameter. Similarly, the thickness of the wiring layers 112a, 112b, 112c, and 112d of the frame 110 may be thicker than the thickness of the redistribution layers 142a, 142b, and 142c of the first connection structure 140.

Other configurations are substantially the same as those described for the semiconductor package 10A and the like, and detailed descriptions thereof will be omitted. Meanwhile, it goes without saying that the above-described characteristic configuration of the semiconductor package 10D can also be applied to the semiconductor package 10B according to another embodiment.

In the present disclosure, the lower side, the lower side, the lower side, etc. are used to mean the direction toward the mounting surface of the fan-out semiconductor package based on the cross section of the drawing for convenience, and the upper side, the upper side, the upper surface, etc. are used in opposite directions. However, this defines a direction for convenience of explanation, and it is of course not to say that the scope of the claims is not specifically limited by the description of such direction.

In the present disclosure, the meaning of connection is a concept including not only direct connection but also indirect connection through an adhesive layer or the like. In addition, the meaning of being electrically connected is a concept that includes both physically connected and unconnected cases. In addition, expressions such as first and second are used to distinguish one component from another, and do not limit the order and/or importance of the corresponding components. In some cases, without departing from the scope of the rights, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component.

The expression example used in the present disclosure does not mean the same embodiment as each other, and is provided to emphasize and describe different unique features. However, the examples presented above are not excluded from being implemented in combination with other example features. For example, even if a matter described in a specific example is not described in another example, it may be understood as a description related to another example unless there is a description contradicting or contradicting the matter in another example.

The terms used in the present disclosure are used only to describe an example, and are not intended to limit the present disclosure. In this case, the singular expression includes a plural expression unless it clearly means differently in the context.

Claims (10)

A frame having a through portion;
It is disposed in the through part of the frame, has a first surface on which a first connection pad is arranged, and a second surface opposite to the first surface and on which a second connection pad is arranged, and the first connection pad and the second connection A first semiconductor chip including a through via connecting the pads;
A second semiconductor chip disposed on a first surface of the first semiconductor chip in the through part of the frame, and disposed such that an active surface on which a third connection pad is disposed faces the first semiconductor chip;
A conductive bonding layer disposed between the first connection pad of the first semiconductor chip and the third connection pad of the second semiconductor chip; And
A connection structure disposed on a second surface of the first semiconductor chip and including a first connection pad of the first semiconductor chip and a redistribution layer electrically connected to the third connection pad of the second semiconductor chip,
A semiconductor package in which a third connection pad of the second semiconductor chip is electrically connected to the redistribution layer through the through via.
The method of claim 1,
The second semiconductor chip is disposed so that the entirety of the second semiconductor chip is vertically overlapped with the first semiconductor chip.
The method of claim 1,
The bonding layer is a two-layer copper (Cu) layer for a copper (Cu)-copper (Cu) bonding semiconductor package.
The method of claim 1,
A semiconductor package further comprising a dielectric layer surrounding the bonding layer and disposed between the first and second semiconductor chips.
The method of claim 1,
Each of the first and second semiconductor chips is a chip constituting some or all functions of an application processor (AP).
The method of claim 1,
A semiconductor package further comprising a passive component disposed on a fourth surface of the connection structure, which is a side opposite to the third surface on which the first semiconductor chip is disposed in the connection structure.
The method of claim 1,
A semiconductor package further comprising a passive component disposed in the through portion of the frame.
The method of claim 1,
The frame includes a first insulating layer in contact with the third surface of the connection structure, a first wiring layer in contact with the third surface of the connection structure and buried in the first insulating layer, and the first wiring layer of the first insulating layer. A second wiring layer disposed on a side opposite to the side of the first insulating layer, a second insulating layer disposed on a side opposite to the side where the first wiring layer of the first insulating layer is buried and covering at least a portion of the second wiring layer, and the second And a third wiring layer disposed on a side opposite to the side where the second wiring layer of the insulating layer is buried,
A surface of the first insulating layer in contact with the third surface of the connection structure has a step difference from a surface of the first wiring layer in contact with the third surface of the connection structure.
The method of claim 1,
The frame includes a first insulating layer, first and second wiring layers disposed on both surfaces of the first insulating layer, and disposed on both surfaces of the first insulating layer, respectively, and covering at least a portion of each of the first and second wiring layers. The second and third insulating layers, a third wiring layer disposed on a side opposite to the side where the first wiring layer of the second insulating layer is buried, and a side opposite to the side where the second wiring layer of the third insulating layer is buried And a fourth wiring layer disposed on,
The first insulating layer is thicker than each of the second and third insulating layers.
A frame having a through part, a first surface disposed at the through part of the frame and on which a first connection pad is disposed, and a second surface opposite to the first surface and on which a second connection pad is disposed, and the first connection pad and A first semiconductor chip including a through via connecting the second connection pad, and an active surface disposed on the first surface of the first semiconductor chip in the through part of the frame and on which the third connection pad is disposed is the first A second semiconductor chip disposed facing a semiconductor chip, a conductive bonding layer disposed between a first connection pad of the first semiconductor chip and a third connection pad of the second semiconductor chip, and a first semiconductor chip of the first semiconductor chip A connection structure disposed on the second surface and including a first redistribution layer electrically connected to a first connection pad of the first semiconductor chip and a third connection pad of the second semiconductor chip, and an inactive surface of the second semiconductor chip A first semiconductor package disposed thereon and including a second redistribution layer electrically connected to the first redistribution layer; And
A second semiconductor package including a wiring board disposed on the first semiconductor package and electrically connected to the second redistribution layer through a connection terminal, and a few third semiconductor chips disposed on the wiring board A semiconductor package comprising a.

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