KR20200087104A - Memory programing method and device performing the same - Google Patents

Abstract

A memory programming device comprises: a memory reading unit reading read data in a plurality of cells associated with a specific address of a programmable memory; and a memory writing unit writing write data to the plurality of cells before the reading and generating a rewrite pattern by comparing the write data with the read data after the reading to correct at least one mismatched cell among the plurality of cells. Therefore, the memory programming device may reduce memory programming process time and increase the yield.

Description

MEMORY PROGRAMING METHOD AND DEVICE PERFORMING THE SAME

The present invention relates to a memory programming method and an apparatus for performing the same, and more particularly, to a multi-bit programming method for a one-time programmable memory and an apparatus for performing the same.

One-time programmable (hereinafter referred to as "OTP") memory includes a plurality of OTP unit cells that are deployed in a row direction and a column direction.

The OTP unit cell is formed in a volatile or nonvolatile memory device such as DRAM, EEPROM, and FLASH, and is used for memory repair. In addition, a mixed-signal chip in which an analog chip and a digital chip are mixed is used for the purpose of internal operating voltage and frequency trimming.

In general, an OTP unit cell includes an anti-fuse made of a metal-oxide-semiconductor field effect transistor (MOSFET) (hereinafter referred to as a MOS transistor) and one or a plurality of MOS transistors. These OTP unit cells are formed in a single (single) or array (array) form in each memory chip is used for repair or trimming.

Korean Registered Patent No. 10-0845407 (2008.07.03.) relates to a one-time-programmable cell and an OTP memory having the same, implemented with fewer MOS transistors, having a small area and short access time, and an inverter type Equipped with a sense amplifier, there is an effect that can be used for leakage current and area consumption.

Korean Registered Patent No. 10-1051673 (2011.07.19.) relates to an antifuse and a method of forming the unit cell of a nonvolatile memory device having the same, and stably destroys an antifuse gate insulating film made of a MOS transistor. Operation reliability can be improved by improving data detection margin during read operation.

1 is a cross-sectional view illustrating a programming method of an OTP memory according to the prior art.

Referring to FIG. 1, programming of an OTP memory applies a high voltage (OTPV) to the antifuse (CMOS antifuse) of the OTP unit cell 100, thereby destroying the CMOS gate insulating layer 103 and gate 104 ) And lowers the resistance value between the substrate 101 to a constant resistance value (for example, several MΩ).

More specifically, the antifuse of the OTP unit cell 100 according to the prior art includes a gate electrode 104 formed on the substrate 101, a junction region 105 formed in the substrate exposed to the sidewalls of the gate electrode 104, and And a gate insulating layer 103 formed with a relatively thin thickness between the gate electrode 104 and the substrate 101.

The junction region 105 and the pick-up region (area for applying bias to the well 102, 106) are interconnected and connected to the ground voltage terminal (VSS). Then, the write voltage OTPV is applied to the gate electrode 104 through the metal wiring. Accordingly, a high electric field is formed between the gate electrode 104 and the substrate 101 to break down the gate insulating layer 103, and the gate electrode 104 and the substrate 101 are electrically shorted.

In the conventional programming method of OTP memory, after the writing process is performed, data recorded in the OTP memory is read and compared with the data to be written repeatedly until all bits (pass) are the same. Perform. For example, if writing is performed on 8-bit unit cells of the OPT memory and all 8 bits have not passed, re-writing of all 8-bit unit cells is performed.

Here, since the energy of the high current is concentrated in the path where the gate insulating film has already been destroyed, the concentration of energy is reduced relative to the unbroken unit cell. Accordingly, there is a problem in that the writing process is lengthened and the yield of the insulating film is not properly broken, so that the yield is reduced.

Korean Registered Patent No. 10-0845407 (2008.07.03.) Korean Registered Patent No. 10-1051673 (2011.07.19.)

The present invention is to provide a memory programming method and an apparatus for performing the same, which can reduce the memory programming process time and increase the yield.

The present invention is to provide a memory programming method capable of controlling a memory programming loop and an apparatus for performing the same.

Among embodiments, a memory programming apparatus includes a memory reading unit for reading read data in a plurality of cells associated with a specific address of a programmable memory; And a memory recording unit which records recording data in advance in the plurality of cells before the reading, and corrects at least one mismatched cell among the plurality of cells by generating a rewriting pattern by comparing the reading data with the reading data after the reading. Includes.

Here, the memory reading unit performs a re-reading operation to re-read data in the plurality of cells through the specific address after the correction, and the memory recording unit updates the re-writing pattern through the re-reading data Accordingly, a re-arrangement operation for re-arranging at least one re-mismatched cell among the at least one mismatched cell may be performed.

In one embodiment, the memory reading unit and the memory recording unit may sequentially repeat the re-reading operation and the redefinition operation until no error occurs in the contents recorded in the plurality of cells.

In one embodiment, the memory recording unit may further include a rewrite pattern storage module for storing the generated rewrite pattern.

In one embodiment, the memory recording unit is a voltage generation module for generating a fusing voltage; And a voltage application module that applies the generated fusing voltage to the at least one mismatched cell based on the rewrite pattern. Here, the voltage application module may include a plurality of switches that are controlled based on the rewrite pattern and can apply the fusing voltage to the plurality of cells.

In one embodiment, the memory programming apparatus may further include a control unit that counts the number of iterations for the re-alignment operation and determines whether or not a specific number is exceeded.

In one embodiment, the memory programming apparatus may further include an address decoding unit that receives programming data from the outside and extracts cell selection information corresponding to a specific address of the memory.

Among embodiments, a memory programming method is performed in a memory programming device. A memory programming method includes writing write data to a plurality of cells associated with a specific address of a programmable memory; Reading read data in the plurality of cells; And comparing the recorded data with the read data to generate a rewrite pattern to correct at least one mismatched cell among the plurality of cells.

Among the embodiments, the memory tester includes a memory accommodating portion accommodating a programmable memory; And a memory programming device that performs programming of the memory, wherein the memory programming device comprises: a memory reading unit that reads read data in a plurality of cells associated with a specific address of a programmable memory; And a memory recording unit which records recording data in advance in the plurality of cells before the reading, and corrects at least one mismatched cell among the plurality of cells by generating a rewriting pattern by comparing the reading data with the reading data after the reading. Includes.

The disclosed technology can have the following effects. However, since a specific embodiment does not mean that all of the following effects should be included or only the following effects are included, the scope of rights of the disclosed technology should not be understood as being limited thereby.

The memory programming technique according to an embodiment of the present invention may reduce memory programming process time and increase yield through generation and update of a rewrite pattern.

The memory programming technique according to an embodiment of the present invention may be capable of controlling a memory programming loop through a comparison operation between write data and read data.

1 is a cross-sectional view illustrating a conventional OTP memory programming method.
2 is a block diagram of a memory programming apparatus according to an embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating the operation of the memory programming device of FIG. 2.
4 is a timing block diagram of a memory programming method.
5 is a flowchart of a memory programming method performed in the memory programming device of FIG. 2.

Since the description of the present invention is only an example for structural or functional description, the scope of the present invention should not be interpreted as being limited by the examples described in the text. That is, since the embodiments can be variously modified and have various forms, it should be understood that the scope of the present invention includes equivalents capable of realizing technical ideas.

Meanwhile, the meaning of terms described in the present invention should be understood as follows.

Terms such as “first” and “second” are for distinguishing one component from other components, and the scope of rights should not be limited by these terms. For example, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is said to be "connected" to another component, it may be understood that other components may exist in the middle, although they may be directly connected to the other component. On the other hand, when a component is said to be "directly connected" to another component, it should be understood that no other component exists in the middle. On the other hand, other expressions describing the relationship between the components, that is, "between" and "immediately between" or "adjacent to" and "directly neighboring to" should be interpreted similarly.

Singular expressions are to be understood as including plural expressions unless the context clearly indicates otherwise, and terms such as “comprises” or “having” refer to the features, numbers, steps, actions, components, parts, or components described. It is to be understood that a combination is intended to indicate the existence, and does not preclude the existence or addition possibility of one or more other features or numbers, steps, operations, components, parts or combinations thereof.

In each step, the identification code (for example, a, b, c, etc.) is used for convenience of explanation. The identification code does not describe the order of each step, and each step clearly identifies a specific order in context. Unless stated, it may occur in a different order than specified. That is, each step may occur in the same order as specified, or may be performed substantially simultaneously, or in the reverse order.

The present invention can be embodied as computer readable code on a computer readable recording medium, and the computer readable recording medium includes all kinds of recording devices in which data readable by a computer system is stored. . Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tapes, floppy disks, optical data storage devices, etc., and are also implemented in the form of carrier waves (eg, transmission over the Internet). Also includes. In addition, the computer-readable recording medium can be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

All terms used herein have the same meaning as generally understood by a person skilled in the art to which the present invention pertains, unless otherwise defined. The terms defined in the commonly used dictionary should be interpreted to be consistent with meanings in the context of related technologies, and cannot be interpreted as having ideal or excessively formal meanings unless explicitly defined in the present invention.

2 is a block diagram of a memory programming apparatus 200 according to an embodiment of the present invention.

Referring to FIG. 2, the memory programming device 200 includes a memory recording unit 220, a memory reading unit 210, an address decoding unit 230, and a control unit 240.

The memory reading unit 210 reads read data in a plurality of cells associated with a specific address of a programmable memory. Here, the programmable memory may correspond to the OTP memory described above, and the read data corresponds to data actually written to a specific address of the memory (Written Data).

In one embodiment, when the write data is recorded in the memory, the memory reading unit 210 may perform a re-reading operation to re-read the read data in a plurality of cells through a specific address of the memory. Here, the re-reading corresponds to reading the recorded data of the same address again.

The memory reading unit 210 may be implemented by sensing a voltage between the CMOS gate and the ground (GND) of each of the OTP memory unit cells described above and comparing the voltage with a reference voltage.

The memory recorder 220 writes write data to a plurality of cells associated with a specific address of a programmable memory, and compares the write data and read data received from the memory readout unit 210 to generate a rewrite pattern to generate the rewrite pattern. Correct at least one mismatched cell.

For example, the memory recording unit 220 receives write data in 8 bits for 8 specific cells in the memory and writes the data to the cells. Thereafter, the memory recording unit 220 compares the read data and the read data received from the memory read unit 210, and if they do not match, generates a rewrite pattern-unrecorded (write failed) write data-for the corresponding cells Records can be redone. Here, rewrite pattern generation can be performed by updating the record data.

In one embodiment, the memory recording unit 220 may perform a re-arrangement operation to re-define at least one re-mismatched cell among at least one mismatched cell by updating the re-write pattern through re-read data.

More specifically, the memory recording unit 220 may compare the rewrite pattern with the re-read data to update only the couple who have not been recorded among the rewrite patterns with the rewrite pattern, and perform rewriting for a corresponding cell in which the rewrite pattern is not recorded.

In one embodiment, the memory reading unit 210 and the memory recording unit 220 may sequentially repeat the re-reading operation and the re-fixing operation until no error occurs in the contents recorded in the plurality of cells.

In other words, the memory reading unit 210 and the memory recording unit 220 may repeatedly perform reading and writing until the first write data is recorded in the memory.

On the other hand, the memory reading unit 210 and the memory recording unit 220 may repeat the re-reading operation and the re-alignment operation sequentially for a specific number of times, and it can be applied differently according to a product application example. Will be self-evident.

The memory programming apparatus 200 according to an embodiment of the present invention can reduce programming time and increase yield compared to the prior art by performing recording of write data only for cells in which no write data is recorded.

In one embodiment, the memory recording unit 220 generates a mask data based on the read data, and performs a logical AND operation between the mask data and the write data to generate a rewrite pattern generating module 222 It can contain.

The rewrite pattern generation module receives the read data from the outside and the read data from the memory reading unit 210, respectively, and compares the write data with the read data to generate a rewrite pattern.

For example, when the write data and read data correspond to [11110000] and [11000000], respectively, as 8-bit binary data, the rewrite pattern generation module uses the read data as mask data and the bit corresponding to [1] passes , Bits corresponding to [0] may retain data and generate a rewrite pattern such as [00110000].

For another example, the rewrite pattern generation module may generate the mask data [00111111] by inverting the read data, and perform a logical AND operation on the mask data [00111111] and the record data [11110000] to rewrite as [00110000] You can create patterns.

In one embodiment, the memory recording unit 220 may further include a rewrite pattern storage module 224 for storing the generated rewrite pattern.

The rewrite pattern storage module 224 temporarily stores the rewrite pattern, and the stored rewrite pattern can be used to generate a rewrite pattern of the next cycle.

Meanwhile, in one embodiment, the rewrite pattern generation module receives the rewrite pattern from the rewrite pattern storage module 224 and the reread data from the memory reading unit 210, respectively, and compares the rewrite pattern with the reread data to rewrite the pattern. Can be updated.

The rewrite pattern generation module may update the rewrite pattern in the same way as the rewrite pattern generation described above.

In other words, the rewrite pattern generation module compares the record data and read data to generate a rewrite pattern corresponding to the updated record data, and after re-recording the memory, the stored rewrite pattern (updated record data) and The rewrite data (data recorded in the memory) can be compared to update the rewrite pattern (renew the updated record data).

In accordance with the repetition of the re-reading operation and the re-alignment operation of the memory recording unit 220 described above, the rewrite pattern generation module repeatedly generates and updates the rewrite pattern.

In one embodiment, the rewrite pattern generation module 222 may further include a record data selection module (not shown).

The rewrite pattern generation module 222 receives a rewrite pattern stored in the rewrite pattern storage module 224 and performs a comparison operation to compare the read data, but when record data is received from the outside, performs a comparison operation between the record data and the read data To do this, it may include a recording data selection module for selecting one of the recording data and the rewrite pattern.

In one embodiment, the memory recording unit 220 further includes a voltage generation module 226 for generating a fusing voltage and a voltage application module 228 for applying the generated fusing voltage to at least one mismatched cell based on the rewrite pattern. can do.

More specifically, the memory recording unit 220 may include a voltage generation module 226 for generating a fusing voltage to be applied to the OTP memory unit cell according to a programming method for the OTP memory and a write data pattern or a rewrite pattern (updated write data). On the basis, a power supply module that applies a fusing voltage to a corresponding cell including data may be included.

Here, the fusing voltage corresponds to about 8 [V], and the fusing voltage applied to the unit cells according to the arrangement (and pass resistance) of the unit cells may correspond to 7.5 to 8 [V].

In one embodiment, the voltage application module 228 may be controlled based on a rewrite pattern (or write data) and include a plurality of switches capable of applying the fusing voltage to the plurality of cells.

Here, each of the plurality of switches may connect the OTP memory unit cells and the power generation module, respectively.

The address decoding unit 230 receives programming data from the outside and extracts cell selection information corresponding to a specific address in memory.

For example, if the memory corresponds to an OTP memory including 8 (row, row) * 16 (column, column) unit cells, the address decoding unit 230 includes address information for specific cells of the memory from the outside. Receiving the programming data (4 bits) to decode the 16-bit cell selection information for selecting the corresponding memory.

The address decoding unit 230 may provide the cell selection information to the memory recording unit 220, and the memory recording unit 220 selects cells of a specific address corresponding to the cell selection information to perform recording of the recording data Can.

The control unit 240 controls the memory reading unit 210, the memory recording unit 220, and the address decoding unit 230 based on the clock signal (Clock) and the rewrite pattern. Here, the clock corresponds to a square wave, and may be received from the outside or generated in the controller 240.

In one embodiment, the control unit 240 may receive the rewrite pattern generated by the memory recorder 220 to determine whether it corresponds to specific data, and if it corresponds to the specific data, may end the recording of the record data for the address. have.

For example, if the 8-bit rewrite pattern generated by the memory recorder 220 corresponds to the control unit 240, the record data (or stored rewrite pattern) and read data are the same, that is, the first record data is OTP The program for the corresponding address can be terminated by determining that it is normally programmed in the corresponding address in the memory.

In one embodiment, if the rewrite pattern generated by the memory recording unit 220 does not correspond to specific data, the control unit 240 causes the memory reading unit 210 and the memory recording unit 220 to repeatedly read and correct operations, respectively. It can be controlled to perform.

In one embodiment, the control unit 240 counts the number of repetitions for the correction operation (or re-arrangement operation) of the memory recording unit 220 and, if it exceeds a certain number of times, may end the recording of the record data for the address. have. Here, the specific number of times may correspond to the number of times set by the user of the memory programming device 200.

Through this, the memory programming apparatus 200 may control a process time that is lengthened by repeating the rereading operation and the redefinition operation until no error occurs in the contents written in the plurality of cells.

In one embodiment, the control unit 240 receives the programming data from the address decoding unit 230 when an error does not occur in the contents recorded in the plurality of cells or the number of repetitive operations exceeds a certain number (max count) By controlling to extract other cell selection information, it is possible to control the memory recorder 220 to update the record data for a specific address.

More specifically, the control unit 240 ends the recording of the record data for the corresponding address when no error occurs in the contents recorded in the plurality of cells or the number of repetitive operations exceeds a certain number, and the record data for other addresses In order to perform the recording, the address decoding unit 230 and the memory recording unit 220 may be controlled.

3 is a circuit diagram illustrating the operation of the memory programming device 200 of FIG. 2.

Referring to FIG. 3, the data recording unit records recording data by fusing unit cells of an OTP memory in 8-bit units, and includes a voltage generation module 226 and a voltage application module 228.

The voltage generation module 226 generates an 8 [V] fusing voltage, and the voltage application module 228 may include eight switches capable of connecting the voltage generation module 226 and eight unit cells one-to-one. Here, the switches operate according to the write data (or rewrite pattern, RD) to be written in each of the unit cells, for example, when the write data to be written to the corresponding unit cell corresponds to [1], the switch is turned on (Turn -On), and when the write data to be written to the corresponding unit cell corresponds to [0], the switch maintains a turn-off state.

In FIG. 3, the voltage application module 228 represents a state in which only a switch connecting the 3rd, 5th and 6th unit cells and the power generation module 226 is turned on.

Through this, the memory programming apparatus 200 updates the rewrite pattern (or write data) and applies a fusing voltage only to the unit cell in which the write data is not written (failure or mismatch), thereby providing high current energy. ) To reduce the number of iterations of the correction operation (or re-arrangement operation) and increase the yield.

4 is a timing block diagram of a memory programming method.

Referring to FIG. 4, the X-axis represents time, and the Y-axis is the address of the OTP memory (OTP_ADD), write data, write pulse of the OTP memory, and the operation pulse (OTP_WR) of the memory recording unit 220, rewrite pattern (or It indicates updated write data, OTP_WDAT, operation pulse OTP_RD of the memory reading unit 210 and read data (or data recorded in the corresponding unit cells, OTP_RDAT).

In the first cycle, the memory recording unit 220 receives a specific address [0] and first recording data [11111111]. The memory reading unit 210 reads the reading data for the corresponding address [0] and provides it to the memory recording unit 220 while the operation pulse corresponds to the high level.

The memory recording unit 220 compares the first recording data [11111111] with [00000000] to generate a rewrite pattern (or update the recording data), and records the recording data.

When the operation of the memory recording unit 220 is finished, the memory reading unit 210 reads data recorded in the corresponding cells, that is, reading data [11010011].

Here, the memory reading unit 210 may perform reading of the reading data at a time just before the end of the first cycle, or at a time immediately after the start of the second cycle, or both.

In the second cycle, the memory recording unit 220 may compare the rewrite pattern [11111111] and the read data [11010011] to update the rewrite pattern to [00101100], and unit cells corresponding to [1] of the rewrite pattern (mismatch) Cells) are recorded (or corrected) only for the rewrite pattern. Here, the mismatched cells correspond to the 3rd, 5th and 6th unit cells.

The memory reading unit 210 reads data recorded in the corresponding cells, that is, reading data [11110111].

In the third cycle, the memory recording unit 220 updates the rewrite pattern to [00001000] in the same way as the other cycles, and performs a re-arrangement operation on the fifth cell. When the read data [11111111] is read by the memory reading unit 210, programming of the corresponding address is ended. Here, the termination of the corresponding program may be determined by the control unit 240 as described above.

In the fourth cycle, the control unit 240 may control to perform programming of the second record data [00010001] for the next specific address [1], as described above.

The memory reading unit 210 reads the reading data in the same manner as the first cycle, and the memory recording unit 220 compares the reading data and the second recording data in the same manner as the first cycle to read the rewrite pattern. Update to to record the second record data for the address.

When the read data [00010001] is read by the memory reading unit 210, programming of the corresponding address [1] ends.

The fifth cycle and the seventh cycle are the processes of programming the third recording data [01101001] for the next specific address [2]. The rewrite pattern and read data are [01101001] -> [01000001] -> [01000000], [ 00101000] -> [00101001] -> It is updated to [01101001], and it can be seen that the re-reading operation and the re-fixing operation for the corresponding address [2] are repeatedly performed.

5 is a flowchart of a memory programming method performed in the memory programming device 200 of FIG. 2.

Referring to FIG. 5, the memory programming apparatus 200 writes write data to a plurality of cells associated with a specific address of the memory (S510).

In one embodiment, the memory programming device 200 may perform a pre-test before recording the write data. Here, the pre-test may correspond to a test for operating parameters (eg, operating frequency, etc.) of the memory programming device 200.

In one embodiment, the memory programming device 200 may retrieve record data after the pre-test. Here, in search of the record data, the record data to be written to the corresponding address may be searched based on cell selection information corresponding to a specific address decoded through the address decoding unit 230.

The memory programming device 200 reads read data in the plurality of cells (S520).

The memory programming device 200 compares the read data with the read data after the read (S530).

When the comparison result is the same, that is, when the write data is written in the plurality of cells without error, the programming operation for the plurality of cells is ended.

If the comparison result is not the same, the memory programming device 200 generates (or updates) a rewrite pattern (S540).

The memory programming apparatus 200 corrects at least one mismatched cell among the plurality of cells based on the rewrite pattern.

The memory programming apparatus 200 may repeatedly perform steps S310 to 340 until no error occurs in the contents written in the plurality of cells.

Accordingly, the memory programming method according to an embodiment of the present invention compares write data (or rewrite pattern) with read data, and repeatedly performs re-write only for a unit cell that has failed to write. It can reduce process time and increase yield than memory programming method.

The programmable memory tester includes a memory accommodating portion accommodating a programmable memory and a memory programming device 200 performing programming of the memory. Here, the memory programming device 200 corresponds to the memory programming device 200 described above.

Although described above with reference to preferred embodiments of the present application, those skilled in the art variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You can understand that you can.

100: OTP memory
200: memory programming device
210: memory reading unit 220: memory recording unit
222: rewrite pattern generation module 224: rewrite pattern storage module
226: voltage generation module 228: voltage application module
230: address decoding unit 240: control unit

Claims (17)

A memory reading unit for reading recorded data in a plurality of cells associated with a specific address of a programmable memory; And
Before the read, record data is previously recorded in the plurality of cells, mask data is generated based on the read data, a rewrite pattern is generated based on the mask data and the record data, and at least one of the plurality of cells is generated. And a memory recording unit that corrects the at least one mismatched cell by recording the rewrite pattern only in the mismatched cell of
The memory recording unit further includes a rewrite pattern storage module for storing the generated rewrite pattern, and after the correction, the memory read unit calculates and updates the reread data generated through the reread process and the rewrite pattern stored in the module Programming device for generating an old rewrite pattern.
The method of claim 1, wherein the memory recording unit
And re-aligning the at least one re-mismatched cell among the at least one mismatched cell based on the updated rewrite pattern.
The memory reading unit and the memory recording unit of claim 2
A memory programming apparatus characterized by sequentially repeating the re-reading process and the redefinition operation until no error occurs in the contents recorded in the plurality of cells.
The method of claim 1, wherein the memory recording unit
And a rewrite pattern generation module generating a rewrite pattern by performing a logical AND operation between the mask data and the write data.
The method of claim 1, wherein the memory recording unit
A voltage generation module that generates a fusing voltage; And
And a voltage application module that applies the generated fusing voltage to the at least one mismatched cell based on the rewrite pattern.
The method of claim 5, wherein the voltage application module
And a plurality of switches controlled based on the rewrite pattern and capable of applying the fusing voltage to the plurality of cells.
According to claim 3,
And a control unit for counting the number of repetitions for the re-arrangement operation to determine whether a certain number of times is exceeded.
The method of claim 7,
And an address decoding unit receiving programming data from the outside and extracting cell selection information corresponding to a specific address of the memory.
The method of claim 8, wherein the control unit
When an error does not occur in the contents recorded in the plurality of cells or the number of repetitions exceeds a specific number, the address decoding unit receives the programming data and extracts cell selection information for cells different from the plurality of cells And controlling and updating the write data for the specific address with the write data for the other cell.
A memory for receiving cell selection information;
A memory reading unit for reading recorded data in a plurality of cells associated with a specific address corresponding to the cell selection information; And
And a memory recording unit for recording recording data in advance to the plurality of cells before the reading,
The memory recording unit may generate a mask data based on the read data, and a rewrite pattern generation module that generates a rewrite pattern based on the mask data and the write data;
A voltage application module correcting the at least one mismatched cell by applying a fusing voltage to at least one mismatched cell among the plurality of cells based on the generated rewrite pattern;
And a rewrite pattern storage module for storing the generated rewrite pattern, wherein the rewrite pattern generation module is updated by calculating the reread data generated through the reread process in the memory reading unit and the stored rewrite pattern after the correction. A memory programming device that generates a rewrite pattern.
The method of claim 10, wherein the memory recording unit
And re-aligning the at least one re-mismatched cell among the at least one mismatched cell based on the updated rewrite pattern.
The method of claim 11, wherein the memory reading unit and the memory recording unit
A memory programming apparatus characterized by sequentially repeating the re-reading process and the redefinition operation until no error occurs in the contents recorded in the plurality of cells.
The method of claim 12,
And counting the number of repetitions for the re-arrangement operation, and further comprising a control unit for terminating the recording of the specific address when the re-reading data and the write data are the same.
The method of claim 10, wherein the rewrite pattern generation module
Generating the mask data by inverting the read data,
And performing a logical AND operation between the mask data and the write data to generate the rewrite pattern.
The method of claim 10,
And an address decoding unit receiving programming data from the outside and extracting the cell selection information into the memory.
The method of claim 10, wherein the memory recording unit
And a voltage generation module generating the fusing voltage.
The method of claim 16, wherein the voltage application module
And a plurality of switches controlled based on the rewrite pattern and capable of applying the fusing voltage to the plurality of cells.

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