KR20200083763A - Scan driver and display device having the same - Google Patents

Abstract

A scan driver includes a plurality of stages each outputting a scan signal. An n^th stage includes: a first driving control unit which controls a voltage of a first node and a voltage of a second node in response to a previous carry signal; a second driving controller which controls a voltage of a first driving node based on a sensing-on signal, a next carry signal, a voltage of a first power source, a voltage of a first node, and a voltage of a sampling node, and controls a voltage of a second driving node based on a voltage of the sampling node and a sensing clock signal; an output buffer unit which outputs the carry signal in response to the voltage of the first node and the voltage of the second node, and output a first scan signal and a second scan signal in response to the voltage of the first driving node and the voltage of the second driving node; and a connection control unit which electrically connects the first node and the first driving node, and the second node and the second driving node respectively in response to a display-on signal. Therefore, the scan signal and/or a sensing signal may be stably outputted by controlling the voltage of the first driving node.

Description

A scan driver and a display device including the same {SCAN DRIVER AND DISPLAY DEVICE HAVING THE SAME}

The present invention relates to a display device, and more particularly, to a scan driver and a display device including the same.

The display device includes a display panel, a scan driver, a data driver, and a timing controller. The scan driver provides a scan signal to the display panel through scan lines. To this end, the scan driver includes stage circuits for sequentially connected scan signal outputs, and each of the stage circuits is composed of a plurality of oxide thin film transistors and operates.

Recently, the display device performs driving to compensate for deterioration or change in characteristics of the driving transistor outside the pixel circuit by sensing the threshold voltage or mobility of the driving transistor included in the pixel circuit. At this time, the scan methods for the display operation, the mobility sensing operation, and the threshold voltage sensing operation are different. A study on a scan driver and a stage circuit thereof to minimize the complexity of the circuit while stably performing various operations of this type is underway.

One object of the present invention is to provide a scan driver that stably outputs a scan signal and/or a sensing signal by controlling the voltage of the first drive node.

Another object of the present invention is to provide a display device including the scan driver.

However, the object of the present invention is not limited to the above-described objects, and may be variously extended without departing from the spirit and scope of the present invention.

The scan driver according to an embodiment of the present invention includes a plurality of stages for outputting a scan signal and a sensing signal, and each stage receives a voltage of a first node and a voltage of a second node in response to a previous carry signal. The first driving control unit controls the voltage of the first driving node based on the sensing on signal, the carry signal thereafter, the voltage of the first power source, the voltage of the first node, and the voltage of the sampling node. The second driving control unit controls the voltage of the second driving node based on the voltage and the sensing clock signal, outputs a carry signal in response to the voltage of the first node and the voltage of the second node, and outputs a carry signal. In response to a voltage and an output buffer unit outputting the scan signal and the sensing signal in response to a voltage of the second driving node and a display-on signal, the first node, the first driving node, the second node, and the It may include a connection control unit for electrically connecting the second drive node, respectively.

In addition, the second driving control unit is connected between the input terminal to which the carry signal is applied afterwards and the sampling node, and a 16th transistor, a third node, and the first driving node through which a gate electrode receives the sensing on signal. A 17th transistor connected to a first sensing clock terminal to which a first sensing clock signal is applied, and a second sensing clock terminal to which a second sensing clock signal is applied, and the third node. , A 18th transistor having a gate electrode connected to the sampling node, a 19th transistor connected between a first power terminal to which the first power is applied and the third node, and a gate electrode connected to the first driving node, and And a third capacitor connected between the second power terminal to which the second power is applied and the sensing node.

In addition, the 17th transistor may be characterized in that when the first sensing clock signal is supplied, the voltage of the first power applied through the 19th transistor is supplied to the first driving node.

In addition, the 19th transistor may be characterized in that the voltage of the first power supply is supplied to the third node in response to the voltage of the first driving node to keep the voltage of the third node constant.

In addition, one frame period includes a display period and a vertical blank period, and in the display period, the sensing on signal may be supplied to at least one selected stage of the stages.

In addition, the at least one selected stage may be characterized by outputting the scan signal and the sensing signal in the vertical blank period following the display period.

In addition, the sensing on signal may be applied in synchronization with the subsequent carry signal in the display period.

In addition, the second driving control unit further includes 14th and 15th transistors connected in series between the third power terminal to which the third power is applied and the second driving node, and the 14th transistor is the second driving node. A gate electrode receiving a sensing clock signal may be included, and the fifteenth transistor may include a gate electrode connected to the sampling node.

In addition, the output buffer unit is connected between a sensing control clock terminal to which a sensing control clock signal is applied and a second output terminal outputting the sensing signal, and a twentieth transistor and a second transistor connected to the first driving node with a gate electrode. It may be characterized in that it comprises a third transistor connected to the third output terminal and the second output terminal to which power is applied, and a gate electrode connected to the second driving node.

In addition, the output buffer unit may further include a fourth capacitor connected between the gate electrode and the second output terminal of the twentieth transistor.

In addition, the first driving control unit is a fourth transistor connected between the first power supply terminal to which the first power is applied and the first node, and the gate electrode receiving the previous carry signal or the scan start signal, the first Fifth and sixth transistors connected in series between one node and a carry output terminal outputting the carry signal, connected between the first node and the carry output terminal, and a gate electrode receiving the subsequent carry signal A ninth transistor, a third terminal connected between a clock terminal to which a clock signal is applied, and the second node, and a gate electrode connected to the first node, a first power terminal to which the first power is applied, and the second And a seventh transistor connected between nodes and a gate electrode connected to the first clock terminal, and an eighth transistor diode-connected between the first power terminal and the second node.

In addition, the first driving control unit may further include a second transistor connected between the gate electrode and the first node of the third transistor, and a gate electrode connected to the first power terminal. have.

In addition, the second driving control unit may further include a fifth capacitor connected between the gate electrode and the sensing node of the sixteenth transistor.

In addition, the second driving control unit may further include a 23rd transistor diode-connected between the first power terminal to which the first power is applied and the sensing node.

In addition, the second driving control unit is connected between the input terminal to which the carry signal is applied afterwards and the sampling node, and a 16th transistor through which a gate electrode receives the sensing-on signal and a sensing clock to which the sensing clock signal is applied. And a third capacitor connected between the terminal and the first driving node, the gate electrode having a 17th transistor connected to the sensing node, and a second power terminal to which a second power is applied and a third capacitor connected to the sensing node. It can be characterized as.

In addition, the output buffer unit is a first transistor connected to a scan control clock terminal to which the scan control clock signal is applied and a first output terminal to output the scan signal, and a gate electrode connected to the first driving node. 3 A second transistor connected between a third power terminal to which power is applied and the first output terminal, a second transistor having a gate electrode connected to the second driving node, a sensing control clock terminal to which a sensing control clock signal is applied, and the sensing signal It is connected between the second output terminal outputting, a gate electrode is connected between the second transistor and the third power supply terminal and the second output terminal connected to the first driving node, the gate electrode is the second driving It may be characterized in that it comprises a twenty-first transistor connected to the node.

Also, in the sensing period, the scan control clock signal and the sensing control clock signal may be applied before the sensing clock signal.

In addition, the second driving control unit is connected between the input terminal to which the carry signal is applied afterwards and the sampling node, and a 16th transistor through which a gate electrode receives the sensing-on signal and a sensing clock to which the sensing clock signal is applied. 17th and 18th transistors connected in series between a terminal and the first driving node, and gate electrodes commonly connected to the sampling node, and a third node and the first between the 17th and 18th transistors It may be characterized in that it comprises a 19th transistor connected between the first power supply terminal to which power is applied, and a gate electrode connected to the first driving node.

In addition, the second driving control unit is connected between an input terminal to which the subsequent signal is applied and the sampling node, a 16th transistor through which a gate electrode receives the sensing on signal, and a clock terminal to which the sensing clock signal is applied. The 17th and 18th transistors connected in series between the first driving node and the gate electrodes commonly connected to the sampling node, and the third node and the carry signal between the 17th and 18th transistors are output. And a 19th transistor diode-connected between the carry output terminal or between the third node and the output terminal outputting the scan signal.

Also, a display device according to an exemplary embodiment of the present invention includes a plurality of pixels connected to first and second scan lines and data lines, respectively, and a scan signal and sensing to the first and second scan lines, respectively. A scan driver including a plurality of stages to supply a signal and a data driver supplying a data signal to the data lines, each of the stages having a voltage and a second voltage at a first node in response to a previous carry signal. Control the voltage of the first driving node based on the first driving control unit for controlling the voltage of the node, the sensing on signal, the carry signal after, the voltage of the first power supply, the voltage of the first node, and the voltage of the sampling node, The second driving control unit controls the voltage of the second driving node based on the voltage of the sampling node and the sensing clock signal, and outputs a carry signal in response to the voltage of the first node and the voltage of the second node. In response to a voltage of a first driving node and a voltage of the second driving node, an output buffer unit outputting the scan signal and the sensing signal and a display on signal, the first node, the first driving node, and the first And a connection controller electrically connecting the two nodes and the second driving node, respectively.

In addition, the second driving control unit is connected between the input terminal to which the carry signal is applied afterwards and the sampling node, and a 16th transistor, a third node, and the first driving node through which a gate electrode receives the sensing on signal. A 17th transistor connected to a first sensing clock terminal to which a first sensing clock signal is applied, and a second sensing clock terminal to which a second sensing clock signal is applied, and the third node. , A 18th transistor having a gate electrode connected to the sampling node, a 19th transistor connected between a first power terminal to which the first power is applied and the third node, and a gate electrode connected to the first driving node, and And a third capacitor connected between the second power terminal to which the second power is applied and the sensing node.

In addition, the 17th transistor may be characterized in that when the first sensing clock signal is supplied, the voltage of the first power applied through the 19th transistor is supplied to the first driving node.

In addition, the 19th transistor may be characterized in that the voltage of the first power supply is supplied to the third node in response to the voltage of the first driving node to keep the voltage of the third node constant.

In addition, the output buffer unit is connected between a sensing control clock terminal to which a sensing control clock signal is applied and a second output terminal outputting the sensing signal, and a twentieth transistor, wherein a gate electrode is connected to the first driving node, 3 Between a third power supply terminal to which power is applied and the second output terminal, and between the gate electrode and the second output terminal of the twenty-first transistor and the twenty-th transistor in which a gate electrode is connected to the second driving node. It may be characterized in that it comprises a fourth capacitor connected to.

In addition, the first driving control unit is a fourth transistor connected between the first power supply terminal to which the first power is applied and the first node, and the gate electrode receiving the previous carry signal or the scan start signal, the first Fifth and sixth transistors connected in series between one node and a carry output terminal outputting the carry signal, connected between the first node and the carry output terminal, and a gate electrode receiving the subsequent carry signal A ninth transistor, a third terminal connected between a clock terminal to which a clock signal is applied, and the second node, and a gate electrode connected to the first node, a first power terminal to which the first power is applied, and the second A seventh transistor connected between a node and a gate electrode connected to the first clock terminal, an eighth transistor diode-connected between the first power terminal and the second node, and the gate electrode and the third transistor It may be characterized in that it comprises a second transistor connected between the first node, the gate electrode is connected to the first power terminal.

In addition, the second driving control unit may further include a fifth capacitor connected between the gate electrode and the sensing node of the sixteenth transistor.

In addition, the second driving control unit may further include a 23rd transistor diode-connected between the first power terminal to which the first power is applied and the sensing node.

In addition, the second driving control unit is connected between the input terminal to which the carry signal is applied afterwards and the sampling node, and a 16th transistor through which a gate electrode receives the sensing-on signal and a sensing clock to which the sensing clock signal is applied. And a third capacitor connected between the terminal and the first driving node, the gate electrode having a 17th transistor connected to the sensing node, and a second power terminal to which a second power is applied and a third capacitor connected to the sensing node. It can be characterized as.

In addition, the output buffer unit is a first transistor connected to a scan control clock terminal to which the scan control clock signal is applied and a first output terminal to output the scan signal, and a gate electrode connected to the first driving node. 3 A second transistor connected between a third power terminal to which power is applied and the first output terminal, a second transistor having a gate electrode connected to the second driving node, a sensing control clock terminal to which a sensing control clock signal is applied, and the sensing signal It is connected between the second output terminal outputting, a gate electrode is connected between the second transistor and the third power supply terminal and the second output terminal connected to the first driving node, the gate electrode is the second driving It may be characterized in that it comprises a twenty-first transistor connected to the node.

Also, in the sensing period, the scan control clock signal and the sensing control clock signal may be applied before the sensing clock signal.

In addition, the second driving control unit is connected between the input terminal to which the carry signal is applied afterwards and the sampling node, and a 16th transistor through which a gate electrode receives the sensing-on signal and a sensing clock to which the sensing clock signal is applied. 17th and 18th transistors connected in series between a terminal and the first driving node, and gate electrodes commonly connected to the sampling node, and a third node and the first between the 17th and 18th transistors It may be characterized in that it comprises a 19th transistor connected between the first power supply terminal to which power is applied, and a gate electrode connected to the first driving node.

In addition, the second driving control unit is connected between an input terminal to which the subsequent signal is applied and the sampling node, a 16th transistor through which a gate electrode receives the sensing on signal, and a clock terminal to which the sensing clock signal is applied. The 17th and 18th transistors connected in series between the first driving node and the gate electrodes commonly connected to the sampling node, and the third node and the carry signal between the 17th and 18th transistors are output. And a 19th transistor diode-connected between the carry output terminal or between the third node and the output terminal outputting the scan signal.

The scan driver according to embodiments of the present invention suppresses excessive rise of the drain-source voltage of transistors connected to the first drive node, stabilizes the voltages of the first drive node and the first node, and leaks the first node at a high temperature. By preventing the current, the scan signal can be stably output even for a long time use.

In addition, the reliability of the display device is improved by including the scan driver in the display device according to embodiments of the present invention, and a problem of insufficient data voltage charging rate of a high resolution display device having a 4k UHD quality or higher can be improved.

However, the effects of the present invention are not limited to the above-described effects, and may be variously extended without departing from the spirit and scope of the present invention.

1 is a diagram illustrating a configuration of a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating a structure of a pixel illustrated in FIG. 1.
3 is a view showing the configuration of a scan driver according to an embodiment of the present invention.
4 is a circuit diagram illustrating a first embodiment of a stage included in the scan driver of FIG. 3.
5 is a timing chart showing an example of the operation of the stage of FIG. 4.
6 is a circuit diagram illustrating a second embodiment of a stage included in the scan driver of FIG. 3.
7 is a circuit diagram illustrating a third embodiment of a stage included in the scan driver of FIG. 3.
8 is a circuit diagram illustrating a fourth embodiment of a stage included in the scan driver of FIG. 3.
9 is a circuit diagram illustrating a fifth embodiment of a stage included in the scan driver of FIG. 3.
10 is a circuit diagram illustrating a sixth embodiment of the stage included in the scan driver of FIG. 3.
11 is a timing diagram showing an example of the operation of the stage of FIG. 10.
12 is a circuit diagram illustrating a seventh embodiment of a stage included in the scan driver of FIG. 3.
13 is a circuit diagram illustrating an eighth embodiment of a stage included in the scan driver of FIG. 3.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions for the same components are omitted.

1 is a diagram illustrating a configuration of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display unit 100 including a plurality of pixels PX, a scan driver 210, a data driver 220, a sensing unit 230, and Timing control unit 240 may be included.

The timing controller 240 may generate a scan driving control signal and a data driving control signal based on signals input from the outside. The scan driving control signal generated by the timing controller 240 may be supplied to the scan driving unit 210, and the data driving control signal may be supplied to the data driving unit 220.

The scan driving control signal may include a plurality of clock signals CLK1 to CLK4, CLK1_SC to CLK4_SC, CLK1_SS to CLK4_SS, and a scan start signal SSP. The scan start signal SSP may control the output timing of the first scan signal.

The plurality of clock signals CLK1 to CLK4, CLK1_SC to CLK4_SC, and CLK1_SS to CLK4_SS supplied to the scan driver 210 include first to fourth clock signals CLK1 to CLK4, and first to fourth scan control clock signals CLK1_SC ~CLK4_SC) and first to fourth sensing control clock signals CLK1_SS to CLK4_SS. The first to fourth clock signals CLK1 to CLK4 may be used to shift the scan start signal SSP. The first to fourth scan control clock signals CLK1_SC to CLK4_SC may be used to output a scan signal corresponding to at least one of the scan start signal SSP and the first to fourth clock signals CLK1 to CLK4. The first to fourth sensing control clock signals CLK1_SS to CLK4_SS may be used to output a sensing signal corresponding to at least one of the scan start signal SSP and the first to fourth clock signals CLK1 to CLK4. In addition, the scan driver 210 may further receive other clock signals in addition to the above-described clock signals CLK1 to CLK4, CLK1_SC to CLK4_SC, and CLK1_SS to CLK4_SS.

The data start control signal may include source start pulse and clock signals. The source start pulse controls the starting point of sampling of data, and clock signals can be used to control the sampling operation.

The scan driver 210 may output scan signals in response to the scan drive control signal. The scan driver 210 may sequentially supply scan signals to the first scan lines SC1 to SCn. Here, the scan signal may be set to a gate-on voltage (eg, a high level voltage) so that the transistor included in the pixels PX can be turned on.

The scan driver 210 may output sensing signals in response to the scan drive control signal. The scan driver 210 may supply a sensing signal to at least one of the second scan lines SS1 to SS2. Here, the sensing signal may be set to a gate-on voltage (eg, a high level voltage) so that the transistor included in the pixels PX can be turned on.

The data driver 220 may supply data signals to the data lines D1 to Dm in response to the data drive control signal. The data signal supplied to the data lines D1 to Dm may be supplied to the pixels PX to which the scan signal is supplied. To this end, the data driver 220 may supply data signals to the data lines D1 to Dm to be synchronized with the scan signal.

The sensing unit 230 may supply initialization power to the pixels supplied with the sensing signal to the sensing lines SL1 to SLm and measure deterioration information of the pixels. In FIG. 1, although the sensing unit 230 is illustrated as having a separate configuration, the sensing unit 230 may be included in the data driving unit 220.

The display unit 100 includes a plurality of pixels connected to the data lines D1 to Dm, the first scan lines SC1 to SCn, the second scan lines SS1 to SSn, and the sensing lines SL1 to SLm. (PX).

The pixels PX may receive first power ELVDD and second power ELVSS from the outside. Each of the pixels PX may receive a data signal from the data lines D1 to Dm when the scan signal is supplied to the first scan lines SC1 to SCn connected to itself. The pixel PX receiving the data signal may control the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS via the light emitting device (not shown) in response to the data signal. At this time, the light emitting device may generate light having a predetermined luminance corresponding to the amount of current. Additionally, the first power supply ELVDD may be set to a higher voltage than the second power supply ELVSS.

In some cases, the pixel PX may be connected to the emission control line in addition to the first scan lines SC1 to SCn and the data lines D1 to Dm. In this case, the emission driver for outputting the emission control signal is further provided. Can be.

FIG. 2 is a diagram illustrating a structure of a pixel illustrated in FIG. 1. In FIG. 2, for convenience of description, a pixel PX connected to the i-th first scan line SCi and the j-th data line Dj is illustrated.

The pixel PX may include a driving transistor M1, a switching transistor M2, a sensing transistor M3, a storage capacitor Cst, and a light emitting device (LED).

The switching transistor M2 may include a first electrode connected to the j-th data line Dj, a gate electrode connected to the i-th first scan line SCi, and a second electrode connected to the first node Na. have.

The switching transistor M2 is turned on when the scan signal is supplied from the i-th first scan line SCi to supply the data signal received from the j-th data line Dj to the storage capacitor Cst. Alternatively, the potential of the first node Na can be controlled. In this case, the storage capacitor Cst including the first electrode connected to the first node Na and the second electrode connected to the second node Nb may charge a voltage corresponding to the data signal.

The driving transistor M1 may include a first electrode connected to the first power supply ELVDD, a second electrode connected to the light emitting device LED, and a gate electrode connected to the first node Na. The driving transistor M1 may control the amount of current flowing through the light emitting element LED in response to the voltage value between the gate and the source.

The sensing transistor M3 may include a first electrode connected to the j-th sensing line SLj, a second electrode connected to the second node Nb, and a gate electrode connected to the i-th second scan line SSi. The sensing transistor M3 is turned on when a sensing signal is supplied to the i-th second scan line SSi to control the potential of the second node Nb. Alternatively, when the sensing signal is supplied to the i-th second scan line SSi, the sensing transistor M3 is turned on to measure the current flowing in the light emitting device LED.

The light emitting device LED may include a first electrode (anode electrode) connected to the second electrode of the driving transistor M1 and a second electrode (cathode electrode) connected to the second power supply ELVSS. The light emitting device LED may generate light corresponding to the amount of current supplied from the driving transistor M1.

In FIG. 2, the first electrodes of the transistors M1 to M3 may be set to one of the source electrode and the drain electrode, and the second electrodes of the transistors M1 to M3 may be set to electrodes different from the first electrode. . For example, when the first electrode is set as the source electrode, the second electrode may be set as the drain electrode.

In addition, the transistors M1 to M3 may be NMOS transistors as illustrated in FIG. 2, but are not limited thereto, and in the modified embodiment, the transistors M1 to M3 may be PMOS transistors.

In one embodiment, while sensing the mobility of the driving transistor M1, the activated scan signal is supplied to the first scan line SCi and the activated sensing signal is supplied to the second scan line SSi. However, it is necessary to turn off the driving transistor M1 and turn on the sensing transistor M3 to sense deterioration information by sensing the current flowing through the light emitting device LED. That is, while sensing a current flowing through the light emitting device LED, an inactive signal is applied to the first scan line SCi and an activated signal is applied to the second scan line SSi. Therefore, the scan signal supplied to the first scan line SCi and the sensing signal supplied to the second scan line SSi need to be supplied separately.

3 is a view showing the configuration of a scan driver according to an embodiment of the present invention.

Referring to FIG. 3, the scan driver 210 may include a plurality of stages ST1, ST2, ST3, ST4, ....

Each of the stages ST1, ST2, ST3, ST4, ST, ... scan signals to the first scan lines SC1, SC2, SC3, SC4, ... in response to the scan start signal SSP (SC(1), SC(2), SC(3), SC(4), ...) is supplied, and the sensing signal is sent to the second scan lines (SS1, SS2, SS3, SS4, ...) Fields (SS(1), SS(2), SS(3), SS(4), ...) can be supplied. For example, the n-th stage may output the n-th scan signal to the n-th scan line. The scan start signal SSP that controls the timing of the first scan signal may be supplied to the first stage ST1.

Each of the stages ST1, ST2, ST3, ST4, ... is a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a fourth input terminal IN4, a clock Terminal CK, first sensing clock terminal S_CK1, second sensing clock terminal S_CK2, sensing control clock terminal SSCK, scan control clock terminal SCCK, first power terminal V1, second power source A terminal V2, a third power terminal V3, a carry output terminal CR, a first output terminal OUT1, and a second output terminal OUT2 may be included.

The first input terminal IN1 may receive a scan start signal SSP or a previous carry signal. In one embodiment, the scan start signal SSP is supplied to the first input terminal IN1 of the first stage ST1, and to the stages other than the first stage ST1, the first input terminal IN1 is provided. The carry signal of the previous stage can be applied. In an embodiment, an n-2 carry signal (n is a natural number of 3 or more) may be applied to the first input terminal IN1 of the n-th stage.

The second input terminal IN2 may receive a sensing on signal SEN_ON. The sensing on signal SEN_ON is a control signal for outputting a scan signal during a sensing period in which the mobility of the driving transistor included in the pixel, the threshold voltage, and the current characteristics of the light emitting device (LED) can be sensed. For example, the gate-on voltage may be stored in the sampling node included in the stage by the sensing-on signal SEN_ON. In one embodiment, the sensing period may be included within a vertical blank period within one frame.

The third input terminal IN3 may receive the display on signal DIS_ON. The display-on signal DIS_ON may have a gate-on voltage in a display period in one frame and a gate-off voltage in a sensing period.

The fourth input terminal IN4 may then receive a carry signal. Thereafter, the carry signal may be one of carry signals supplied a predetermined time after the output of the carry signal of the current stage. In an embodiment, an n+2 carry signal or an n+3 carry signal may be applied to the fourth input terminal IN4 of the n-th stage.

Any one of the first to fourth clock signals CLK1 to CLK4 may be applied to the clock terminal CK of the n-th stage. In one embodiment, when the first clock signal CLK1 is input to the n-th stage, the second clock signal CLK2 is input to the n+1 stage, and the third clock signal CLK3 is input to the n+2 stage. Is input, and the fourth clock signal CLK4 may be input to the n+3 stage. In this embodiment, the first clock signal CLK1 and the third clock signal CLK3 are signals of a half period difference, and the second clock signal CLK2 and the fourth clock signal CLK4 may be signals of a half period difference. .

In one embodiment, the gate-on voltage period of the clock signals CLK1 to CLK4 may be 2 horizontal periods 2H. Also, the gate-on voltage period of the first clock signal CLK1 and the gate-on voltage period of the second clock signal CLK2 may overlap for a quarter horizontal period (1/4H). However, this is an example, and the waveform relationships of the clock signals CLK1 to CLK4 are not limited thereto. In addition, the number of clock signals supplied to one stage is not limited thereto.

The first to fourth clock signals CLK1 to CLK4 may be set as a square wave signal repeating a logic high level and a logic low level. Here, the logic high level may correspond to the gate-on voltage, and the logic low level may correspond to the gate-off voltage.

The first sensing clock terminal S_CK1 and the second sensing clock terminal S_CK2 may receive the first sensing clock signal S_CLK1 and the second sensing clock signal S_CLK2, respectively. The first sensing clock signal S_CLK1 and the second sensing clock signal S_CLK2 may have a gate-on voltage during a sensing period and charge the gate-on voltage to the first driving node. In one embodiment, the gate-off voltage of the first sensing clock signal S_CLK1 and the second sensing clock signal S_CLK2 may be set lower than the gate-off voltage of other signals. For example, the gate-off voltages of the first sensing clock signal S_CLK1 and the second sensing clock signal S_CLK2 may be set to about -15V.

In one embodiment, the first sensing clock signal S_CLK1 has the same waveform as the second sensing clock signal S_CLK2 in the blank period, and may have the same waveform as the predetermined carry signal in the display period.

According to the embodiment. One of the first sensing clock terminal S_CK1 and the second sensing clock terminal S_CK2 may be omitted.

The sensing control clock terminal SSCK may receive any one of the sensing control clock signals CLK1_SS to CLK4_SS. For example, the sensing control clock terminal SSCK may receive a sensing control clock signal synchronized with a clock signal input to the clock terminal CK.

The sensing control clock signals CLK1_SS to CLK4_SS may have a gate-on voltage during the sensing period. The sensing control clock signals CLK1_SS to CLK4_SS may have a gate-on voltage synchronized with the output of the sensing signals SS(1), SS(2), SS(3), SS(4), ...). . In one embodiment, the sensing control clock signals CLK1_SS to CLK4_SS may be configured to have a difference of 1/4 or more periods. In various embodiments of the present invention, the sensing control clock signals CLK1_SS to CLK4_SS may be set to be synchronized with the clock signals CLK1 to CLK4, respectively.

In one embodiment, when the n-th stage receives the first clock signal CLK1 to the clock terminal CK, the sensing control clock terminal SSCK of the n-th stage is synchronized with the third clock signal CLK3. The third sensing control clock signal CLK3_SS is applied, and the fourth sensing control clock signal CLK4_SS synchronized with the fourth clock signal CLK4 may be applied to the sensing control clock terminal SSCK of the n+1 stage. . Further, a first sensing control clock signal CLK1_SS synchronized with the first clock signal CLK1 is applied to the sensing control clock terminal SSCK of the n+2 stage, and a sensing control clock terminal of the n+3 stage ( SSCK) may be applied with a second sensing control clock signal CLK2_SS synchronized with the second clock signal CLK2.

In one embodiment, the gate-on voltage period of the sensing control clock signals CLK1_SS to CLK4_SS may be 2 horizontal periods 2H. Also, the gate-on voltage period of the first sensing control clock signal CLK1_SS and the gate-on voltage period of the second sensing control clock signal CLK2_SS may overlap for a quarter horizontal period (1/4H). However, this is an example, and the waveform relationship of the sensing control clock signals CLK1_SS to CLK4_SS is not limited thereto.

The scan control clock terminal SCCK may receive any one of the scan control clock signals CLK1_SC to CLK4_SC. For example, the scan control clock terminal SCCK may receive a scan control clock signal synchronized with a clock signal input to the clock terminal CK.

The scan control clock signals CLK1_SC to CLK4_SC may have a gate-on voltage during the sensing period. The scan control clock signals CLK1_SC to CLK4_SC may have a gate-on voltage synchronized with the output of the scan signals SC(1), SC(2), SC(3), SC(4), ...). . In one embodiment, the scan control clock signals CLK1_SC to CLK4_SC may be configured to have a difference of half a period or more. In various embodiments of the present invention, scan control clock signals CLK1_SC to CLK4_SC may be set to have the same waveform synchronized with clock signals CLK1 to CLK4, respectively.

In an embodiment, when the n-th stage is supplied with the first clock signal CLK1 to the clock terminal CK, the scan control clock terminal SCCK of the n-th stage is synchronized with the third clock signal CLK3. The third scan control clock signal CLK3_SC is applied, and the fourth scan control clock signal CLK4_SC synchronized with the fourth clock signal CLK4 may be applied to the scan control clock terminal SCCK of the n+1 stage. . In addition, the first scan control clock signal CLK1_SC synchronized with the first clock signal CLK1 is applied to the scan control clock terminal SCCK of the n+2 stage, and the scan control clock terminal of the n+3 stage ( The second scan control clock signal CLK2_SC synchronized with the second clock signal CLK2 may be applied to the SCCK).

In one embodiment, the gate-on voltage period of the first to fourth scan control clock signals CLK1_SC to CLK4_SC may be 2 horizontal periods 2H. Also, the gate-on voltage period of the first scan control clock signal CLK1_SC and the gate-on voltage period of the second scan control clock signal CLK2_SC may overlap for a quarter horizontal period (1/4H). However, this is an example, and the waveform relationship of the scan control clock signals CLK1_SC to CLK4_SC is not limited thereto.

The first power terminal V1 receives the voltage of the first power source VGH, the second power terminal V2 receives the voltage of the second power source VGL1, and the third power source terminal V3 is the third power terminal V1. The voltage of the power supply VGL2 can be received. In one embodiment, the second and third power sources VGL1 and VGL2 may be the same. Also, in one embodiment, the voltage level of the second power source VGL1 may be smaller than the voltage level of the third power source VGL2. For example, the second power supply VGL1 may be set to about -9V, and the third power supply VGL2 may be set to about -6V.

The carry output terminal CR may output a carry signal. The first output terminal OUT1 may output scan signals SC(1), SC(2), SC(3), SC(4), ...). The second output terminal OUT2 may output sensing signals SS(1), SS(2), SS(3), SS(4), ...).

4 is a circuit diagram illustrating a first embodiment of a stage included in the scan driver of FIG. 3.

1 to 4, the k-stage (STk, where k is a natural number) is the first driving control unit 110, the second driving control unit 120, the output buffer units 130A, 130B, 130C and connection It may include a control unit 140.

In an embodiment, the transistors included in the k-th stage STk may be oxide semiconductor transistors. That is, the semiconductor layer (active pattern) of the transistors may be formed of an oxide semiconductor.

The first driving control unit 110 may control the voltage of the first node N1 and the voltage of the second node N2 in response to the scan start signal SSP or the previous carry signal CR(k-2). have. In one embodiment, the previous carry signal CR(k-2) may be the k-2 carry signal CR(k-2). However, this is an example, and the previous carry signal is not limited to the k-2 carry signal CR(k-2). For example, the previous carry signal may be a k-1 carry signal.

The output of the k-th carry signal CR(k) may be controlled based on the voltage of the first node N1 and the voltage of the second node N2. For example, the voltage of the first node N1 is a voltage for controlling the output of the k-th carry signal CR(k).

Meanwhile, in an embodiment, the voltage of the first driving node QN1 is determined by the voltage of the first node N1 in the display period, and the second driving node QN2 is determined by the voltage of the second node N2. The voltage of can be determined. Accordingly, in the display period, the outputs of the k-th scan signal SC(k) and the k-th sensing signal SS(k) are controlled by the voltage of the first node N1 and the voltage of the second node N2. Can. In other words, the first driving control unit 110 is based on a plurality of input signals in the display period. The carry signal CR(k), the scan signal SC(k), and the sensing signal SS(k) An operation for output control can be performed.

In one embodiment, the first driving control unit 110 controls the voltage of the first node N1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9. ) And a third transistor T3, a seventh transistor T7, and an eighth transistor T8 for controlling the voltage of the second node N2.

The fourth transistor T4 may be connected between the first power terminal V1 to which the first power VGH is applied and the first node N1. The gate electrode of the fourth transistor T4 may be connected to the first input terminal IN1 to which the scan start signal SSP or the k-2 carry signal CR(k-2) is applied. The fourth transistor T4 frees the voltage of the first node N1 as the voltage of the first power source VGH in response to the scan start signal SSP or the k-2 carry signal CR(k-2). It can be precharging. In an embodiment, a k-1 carry signal may be applied to the gate electrode of the fourth transistor T4.

The fifth transistor T5 and the sixth transistor T6 may be connected in series between the first node N1 and the carry output terminal CR. The gate electrode of the fifth transistor T5 may be connected to the scan control clock terminal SCCK to which the third scan control clock signal CLK3_SC is applied. The gate electrode of the sixth transistor T6 may be connected to the second node N2. The fifth transistor T5 and the sixth transistor T6 may hold the voltage of the first node N1.

The ninth transistor T9 may be connected between the first node N1 and the carry output terminal CR. The gate electrode of the ninth transistor T9 may be connected to the fourth input terminal IN4 receiving the k+3 carry signal CR(k+3). The ninth transistor T9 may discharge the voltage charged in the first node N1. For example, the voltage of the first node N1 may be discharged in synchronization with the turn-on time of the ninth transistor T9, that is, the rising time of the k+3 carry signal CR(k+3). .

The third transistor T3 may be connected between the clock terminal CK to which the first clock signal CLK1 is applied and the second node N2. The gate electrode of the third transistor T3 may be connected to the first node N1.

The seventh transistor T7 may be connected between the second node N2 and the first power terminal V1. The gate electrode of the seventh transistor T7 may be connected to the clock terminal CK to which the first clock signal CLK1 is applied.

The eighth transistor T8 may be diode-connected between the second node N2 and the first power terminal V1. That is, the gate electrode of the eighth transistor T8 may be connected to the second node N2. That is, the eighth transistor T8 is connected in the form of a diode so that current flows from the second node N2 to the first power terminal V1.

The third transistor T3, the seventh transistor T7, and the eighth transistor T8 may control the voltage of the second node N2 in response to the first clock signal CLK1.

The second driving control unit 120 includes a sensing on signal SEN_ON, a carry signal CR(k+3), a voltage of the first power source VGH, a voltage of the first node N1, and a sampling node SN ), the voltage of the first driving node QN1 connected to the first node N1 is controlled, and the second driving node (based on the voltage of the sampling node SN and the sensing clock signal S_CLK) The voltage of QN2) can be controlled.

The second driving control unit 120 may control the voltage of the first driving node QN1 and the voltage of the second driving node QN2 during the sensing period. In the sensing period, the output of the scan signal SC(k) may be controlled by the voltage of the first driving node QN1 and the voltage of the second driving node QN2. In one embodiment, the sensing period may be a mobility sensing period for sensing the mobility of the driving transistor T1 included in the pixel.

In one embodiment, the second driving control unit 120 controls the voltages of the 16th to 19th transistors T16 to T19 and the second driving node QN2 that control the voltage of the first driving node QN1. The fourteenth transistor T14 and the fifteenth transistor T15 may be included. The second driving control unit 120 may further include a third capacitor C3.

The sixteenth transistor T16 may then be connected between the fourth input terminal IN4 to which the carry signal is applied and the sampling node SN. The gate electrode of the sixteenth transistor T16 may be connected to the second input terminal IN2 to which the sensing on signal SEN_ON is applied. In one embodiment, the carry signal may be the k+3 carry signal CR(k+3) or the k+2 carry signal CR(k+2). The sixteenth transistor T16 may charge the gate node of the carry signal to the sampling node SN in response to the sensing on signal SEN_ON. The sensing on signal SEN_ON may have a gate on voltage in synchronization with the carry signal.

The third capacitor C3 may be connected between the second power terminal V2 to which the second power source VGL1 is applied and the sampling node SN. The gate-on voltage charged in the sampling node SN may be maintained by the third capacitor C3 in response to the sensing-on signal SEN_ON during the display period.

The 17th transistor T17 and the 18th transistor T18 may be connected in series between the second sensing clock terminal S_CK2 to which the second sensing clock signal S_CLK2 is applied and the first driving node QN1. The common node between the 17th transistor T17 and the 18th transistor T18 may be defined as a third node N3.

The gate electrode of the 17th transistor T17 may be connected to the first sensing clock terminal S_CK1 to which the first sensing clock signal S_CLK1 is applied. The gate electrode of the eighteenth transistor T18 may be connected to the sampling node SN.

The 19th transistor T19 may be connected between the third node N3 and the first power terminal V1 to which the first power VGH is applied. The gate electrode of the 19th transistor T19 may be connected to the first driving node QN1.

The 17th to 19th transistors T17 to T19 are configured to hold the voltage of the third node N3 to the voltage of the first power source VGH in response to the voltage of the first driving node QN1. The unnecessary drain-source voltage rise of T17) can be prevented. Therefore, the output of the stable scan signal SC(k) is guaranteed, and the reliability of the display device can be improved.

In addition, in various embodiments of the present invention, the second driving control unit 120 is stable to the first driving node QN1 using the second sensing clock signal S_CLK2 as well as the voltage of the sampling node SN during the sensing period. The gate-on voltage can be charged. For example, a conductive path through the 18th transistor T18 and the 17th transistor T17 may be further formed during the mobility sensing period to further charge the voltage of the first driving node QN1.

In addition, the voltage of the first power supply VGH is applied to the first driving node QN1 through the seventeenth transistor T17 by turning on the seventeenth transistor T17 in synchronization with the first sensing clock signal S_CLK1. Can be. That is, the second driving control unit 120 may charge a stable gate voltage to the first driving node QN1 using the first power source VGH as well as the voltage of the first node N1 during the display period. For example, a conductive path through the 19th transistor T19 and the 17th transistor T17 is further formed during the display period, and the second driving control unit 120 assists charging the voltage at the first driving node QN1. (Supplement) can do it.

In an embodiment, the operation of the first sensing clock signal S_CLK1 in the display period may be changed according to the ambient temperature. When the display device operates at a high temperature, the second driving control unit 120 does not need to assist in charging the first driving node QN1 during the display period. Therefore, at or above the predetermined threshold temperature, the first sensing clock signal S_CLK1 may maintain the gate-off voltage during the display period. Only when the display device is lower than the threshold temperature, the first sensing clock signal S_CLK1 may have a gate-on voltage in synchronization with the scan start signal SSP or the k-2 carry signal CR(k-2). .

Meanwhile, the first sensing clock signal S_CLK1 may be a global signal. Accordingly, in order to assist the voltage charging of the first driving node QN1 in stages corresponding to the plurality of pixel rows, the first sensing clock signal S_CLK1 may have a gate-on voltage multiple times during the display period. .

As described above, the scan driver according to the embodiments of the present invention prevents unnecessary drain-source voltage rise of the 17th transistor T17 by holding the voltage of the third node N3 at a predetermined voltage, and the display period And the gate-on voltage may be stably charged in the first driving node QN1 during the sensing period. Therefore, the reliability of the output of the scan signal SC(k) can be further improved.

The fourteenth transistor T14 and the fifteenth transistor T15 may be connected in series between the second driving node QN2 and the third power terminal V3 to which the third power source VGL2 is applied. The gate electrode of the fourteenth transistor T14 may be connected to the second sensing clock terminal S_CK2 to which the second sensing clock signal S_CLK2 is applied. The gate electrode of the fifteenth transistor T15 may be connected to the sampling node SN. In the sensing period, the 14th transistor T14 and the 15th transistor T15 are turned on, and the voltage of the third power source VGL2 may be applied to the second driving node QN2.

The output buffer units 130A, 130B, and 130C output the carry signal CK(k) in response to the voltage of the first node N1 and the voltage of the second node N2, and the output of the first driving node QN1. The scan signal SC(k) and the sensing signal SS(k) may be output in response to the voltage and the voltage of the second driving node QN2.

The first output buffer unit 130A may include a tenth transistor T10 and an eleventh transistor T11. The first output buffer unit 130A may further include a first capacitor C1 and a second capacitor C2.

The tenth transistor T10 may be connected between the scan control clock terminal SCCK to which the third scan control clock signal CLK3_SC is applied and the carry output terminal CR. The gate electrode of the tenth transistor T10 may be connected to the first node N1. The tenth transistor T10 may supply a gate-on voltage to the carry output terminal CR in response to the voltage of the first node N1. For example, the tenth transistor T10 may function as a pull-up buffer.

The eleventh transistor T11 may be connected between the carry output terminal CR and the second power terminal V2 to which the second power source VGL1 is applied. The gate electrode of the eleventh transistor T11 may be connected to the second node N2. The eleventh transistor T11 may supply a gate-off voltage to the carry output terminal CR in response to the voltage of the second node N2. For example, the eleventh transistor T11 may maintain the voltage of the carry output terminal CR at the gate-off voltage level (ie, the logic low level).

The first capacitor C1 may be connected between the first node N1 and the carry output terminal CR. The first capacitor C1 may function as a boosting capacitor. Accordingly, the tenth transistor T10 can stably maintain the turn-on state for a predetermined period. The second capacitor C2 may be connected between the second node N2 and the carry output terminal CR.

In one embodiment, since the k-th carry signal CR(k) is used as an input signal of another stage, the voltage of the second power source VGL1 is lower than the voltage of the first power source VGH for stable scan signal output. Can.

The second output buffer unit 130B may include a first transistor T1 and a second transistor T2.

The first transistor T1 may be connected between the scan control clock terminal SCCK to which the third scan control clock signal CLK3_SC is applied and the first output terminal OUT1 outputting the scan signal SC(k). have. The gate electrode of the first transistor T1 may be connected to the first driving node QN1. The first transistor T1 may supply a gate-on voltage to the first output terminal OUT1 in response to the voltage of the first driving node QN1.

The second transistor T2 may be connected between the first output terminal OUT1 and the third power terminal V3 to which the third power source VGL2 is applied. The gate electrode of the second transistor T2 may be connected to the second driving node QN2. The second transistor T2 may supply a gate-off voltage to the first output terminal OUT1 in response to the voltage of the second driving node QN2.

The third output unit 130C may include a twentieth transistor T20 and a twenty-first transistor T21.

The 20th transistor T20 may be connected between the sensing control clock terminal SSCK to which the third sensing control clock signal CLK3_SS is applied and the second output terminal OUT2 outputting the sensing signal SS(k). have. The gate electrode of the twentieth transistor T20 may be connected to the first driving node QN1. The twentieth transistor T20 may supply a gate-on voltage to the second output terminal OUT2 in response to the voltage of the first driving node QN1. For example, the twentieth transistor T20 may function as a pull-up buffer.

The 21st transistor T21 may be connected between the second output terminal OUT2 and the third power terminal V3 to which the third power source VGL2 is applied. The gate electrode of the 21st transistor T21 may be connected to the second driving node QN2. The twenty-first transistor T21 may supply a gate-off voltage to the second output terminal OUT2 in response to the voltage of the second driving node QN2.

The connection control unit 140 electrically connects the first node N1 and the first driving node QN1 and the second node N2 and the second driving node QN2 in response to the display-on signal DIS_ON, respectively. Can. The display-on signal DIS_ON may have a gate-on voltage in the display period, and may have a gate-off voltage in the sensing period (eg, mobility sensing period).

In an embodiment, the output buffer units 130A, 130B, and 130C are carried by the connection control unit 140 according to the operation of the first driving control unit 110 during the display period, and the carry signal CR(k) and the scan signal ( SC(k)) and a sensing signal SS(k) may be output. That is, during the display period, the second driving control unit 120 does not affect the output of the output buffer units 130A, 130B, and 130C. Similarly, by the connection control unit 140, during the sensing period, the output buffer units 130A, 130B, and 130C are driven by the operation of the second driving control unit 120, and carry signals CR(k) and scan signals SC(k )) and a sensing signal SS(k). That is, during the sensing period, the first driving control unit 110 does not affect the output of the output buffer units 130A, 130B, and 130C.

In one embodiment, the connection control unit 140 may include a twelfth transistor T12 and a thirteenth transistor T13.

The twelfth transistor T12 may be connected between the first node N1 and the first driving node QN1. The gate electrode of the twelfth transistor T12 may be connected to the third input terminal IN3 to which the display on signal DIS_ON is applied.

The thirteenth transistor T13 may be connected between the second node N2 and the second driving node QN2. The gate electrode of the thirteenth transistor T13 may be connected to the third input terminal IN3 to which the display on signal DIS_ON is applied.

5 is a timing chart showing an example of the operation of the stage of FIG. 4. In FIG. 5, the operation of the k-th stage STk will be mainly described. In addition, the position, width, height, etc. of the waveform shown in FIG. 5 are exemplary only, and the present invention is not limited thereto.

1 to 5, one frame period may include a display period DP and a vertical blank period VBP.

In the display period DP, scan signals SC(k) may be sequentially provided to pixel lines. Also, during the display period DP, the sensing signal SS(k) may be provided to the pixel lines.

In the display period DP, the sensing-on signal SEN_ON may be supplied to at least one of the plurality of stages (in the present embodiment, the k-th stage STk). Only the stage receiving the sensing on signal SEN_ON may output the scan signal SC(k) and the sensing signal SS(k) in the subsequent sensing period SP. During the sensing period SP, sensing of pixels receiving the scan signal SC(k) and the sensing signal SS(k) output from at least one selected stage may be performed.

In the display period DP, the display-on signal DIS_ON may have a gate-on voltage and the second sensing clock signal S_CLK2 may have a gate-off signal. Accordingly, during the display period DP, the twelfth transistor T12 and the thirteenth transistor T13 maintain the turn-on state, and the fourteenth transistor T14 and the seventeenth transistor T17 turn-off state. To maintain.

In the first period t1, the scan start signal SSP or the k-2 carry signal CR(k-2) is applied in synchronization with the first clock signal CLK1 applied to the clock terminal CK. Then, the fourth transistor T4 is turned on and the first power terminal V1 and the first node N1 are electrically connected. Accordingly, the voltage of the first node N1 and the voltage of the first driving node QN1 may be precharged.

Meanwhile, as the voltages of the first node N1, the second node N2, the first driving node QN1, and the second driving node QN2 rise, the first transistor T1 and the second transistor T2 ), the tenth transistor T10, the eleventh transistor T11, the twentieth transistor T20, and the twenty-first transistor T21 are turned on, but the third scan control clock signal CLK3_SC and the third sensing control clock Since the signal CLK3_SS has a gate-off voltage, the k-th carry signal CR(k), the k-th scan signal SC(k), and the k-th sensing signal SS(k) are not output.

In various embodiments of the present invention, the first sensing clock signal S_CLK1 is further supplied during the first period t1. The 17th transistor T17 is turned on as the first sensing clock signal S_CLK1 has a gate-on voltage. In addition, since the first driving node QN1 is precharged, the 19th transistor T19 maintains the turn-on state. Then, the voltage of the first power supply VGH is supplied to the first driving node QN1 to assist (supplement) voltage charging in the first driving node QN1.

In an embodiment, when the display device operates at a high temperature, the first sensing clock signal S_CLK1 may not be supplied during the display period DP. That is, at a threshold temperature or higher, the first sensing clock signal S_CLK1 may maintain the gate-off voltage during the display period DP. Only when the display device is lower than the threshold temperature, the first sensing clock signal S_CLK1 may have a gate-on voltage in synchronization with the scan start signal SSP or the k-2 carry signal CR(k-2). .

In the second period t2, the third scan control clock signal CLK3_SC has a gate-on voltage. Then, the voltages of the first node N1 and the first driving node QN1 may be boosted by the first capacitor C1.

Also, the gate-off voltage of the first clock signal CLK1 is supplied to the second node N2 and the second driving node QN2 through the third transistor T3 in the turn-on state. Accordingly, the second transistor T2, the eleventh transistor T11, and the twenty-first transistor T21 are turned off. Then, the k-th carry signal CR(k) is output in synchronization with the third scan control clock signal CLK3_SC, the k-th scan signal SC(k) is output, and the kth sensing control clock signal CLK3_SS. In synchronization with, the kth sensing signal SS(k) may be output.

The voltage of the first power source VGH is supplied to the third node N3 through the 19th transistor T19 maintaining the turn-on state during the second period t2. Then, the voltage of the third node N3 is held at a predetermined voltage, unnecessary drain-source voltage rise of the 17th transistor T17 is prevented, and the gate-on voltage is stably charged to the first driving node QN1. Can. The driving characteristics may be equally applied to the period in which the first sensing clock signal S_CLK1 is not supplied.

In the third period t3, the k+3 carry signal CR(k+3) and the sensing on signal SEN_ON may be simultaneously applied. Then, the sixteenth transistor T16 is turned on to supply the gate-on voltage of the k+3 carry signal CR(k+3) to the sensing node SN. Accordingly, the sensing node SN may be charged with the gate-on voltage. At this time, when the ninth transistor T9 is turned on in response to the k+3 carry signal CR(k+3), the voltages of the first node N1 and the first driving node QN1 are discharged. The gate-on voltage may be charged and maintained in the sampling node SN in response to the sensing on signal SEN_ON.

The stage STk receiving the sensing on signal SEN_ON may output the scan signal SC(k) and the sensing signal SS(k) in the vertical blank period VBP. That is, if the first and second sensing clock signals S_CLK1 and S_CLK2 have a gate-on voltage during the vertical blank period VBP, and the display-on signal DIS_ON has a gate-off voltage, the first and second sensing clock signals The voltages of the first driving node QN1 may be charged in response to the charging voltage of the sensing node SN by (S_CLK1, S_CLK2).

Meanwhile, as the first node N1 and the first driving node QN1 are set to the gate-off voltage, the first transistor T1, the twelfth transistor T12, and the twentieth transistor T20 are turned on. During the third period t3, the first clock signal CLK1 has a gate-on voltage and the second node N2 and the second driving node QN2 are formed by the seventh transistor T7 and the eighth transistor T8. It is set to the gate-on voltage. Then, the second transistor T2, the eleventh transistor T11, and the twenty-first transistor T21 are turned on so that the voltage of the second power source VGL1 is output to the carry output terminal CR and the third power source VGL2. ) Is output to the first output terminal OUT1 and the second output terminal OUT2. As a result, the carry signal CR(k), the scan signal SC(k), and the sensing signal SS(k) are deactivated.

The vertical blank period VBP may include a sensing period SP and a reset period RP. However, this is an example, and the reset period RP may be included in the display period DP. In one embodiment, the sensing period SP may include a first sensing period SP1 in which mobility and a threshold voltage are sensed, and a second sensing period SP2 in which a current characteristic of the light emitting diode LED is sensed. Also, the sensing period SP may include a pixel reset period PRP.

During the sensing period SP, the k-th stage STk may output the scan signal SC(k) in synchronization with the third scan control clock signal CLK3_SC applied to the scan control clock terminal SCCK. In one embodiment, during the vertical blank period VBP, the scan signal SC(k) may be output at least twice. The first scan signal SC(k) is output in the first sensing period SP1, and when the first scan signal SC(k) is output, the mobility and threshold voltage sensing of the driving transistor provided in the pixel are sensed. The voltage for this may be applied to the pixel. The second scan signal SC(k) is output in the pixel reset period PRP, and when the second scan signal SC(k) is output, the data voltage applied to the corresponding pixel in the previous display period DP is Can be re-applied.

Also, in the sensing period SP, the k-th stage STk may output the sensing signal SS(k) in synchronization with the third sensing control clock signal CLK3_SS applied to the sensing control clock terminal SSCK. . In one embodiment, the sensing signal SS(k) may be output in the first sensing period SP1, the second sensing period SP2, and the pixel reset period PRP. While the sensing signal SS(k) is output in the first sensing period SP1, a sensing current for sensing the mobility and threshold voltage of the driving transistor provided in the pixel may be applied to the pixel. While the sensing signal SS(k) is output in the second sensing period SP2, a sensing current for sensing the current characteristic of the light emitting diode LED provided in the pixel may be applied to the pixel.

In the sensing period SP, the display-on signal DIS_ON has a gate-off voltage and the first and second sensing clock signals S_CLK1 and S_CLK2 may have a gate-on signal. Accordingly, during the sensing period SP, the twelfth transistor T12 and the thirteenth transistor T13 maintain the turn-off state, and the fourteenth transistor T14 and the seventeenth transistor T17 are the first and second transistors. It may be turned off in response to the sensing clock signals S_CLK1 and S_CKL2.

During the fourth period t4, the first sensing clock signal S_CLK1 and the second sensing clock signal S_CLK2 are supplied together. When the first sensing clock signal S_CLK1 has a gate-on voltage, the 17th transistor T17 is turned on. Since the sensing node SN of the corresponding stage STk selected during the display period DP is charged with a gate-on voltage, the 18th transistor T18 maintains a turn-on state. Accordingly, the gate-on voltage of the second sensing clock signal S_CLK2 may be transmitted to the first driving node QN1 via the 17th transistor T17 and the 18th transistor T18. When the first driving node QN1 is set to the gate-on voltage, the first transistor T1 and the twentieth transistor T20 are turned on.

During the fifth period t5, when the third scan control clock signal CLK3_SC is supplied, the third scan control clock signal CLK3_SC to the first output terminal OUT1 via the turned-on first transistor T1 The gate-on voltage of is supplied. Accordingly, the scan signal SC(k) is activated.

In addition, when the third sensing control clock signal CLK3_SS is supplied, the gate-on voltage of the third sensing control clock signal CLK3_SS is supplied to the second output terminal OUT2 via the turned-on 20th transistor T20. do. Accordingly, the sensing signal SS(k) is activated.

When supply of the third scan control clock signal CLK3_SC is stopped in the sixth period t6, the gate-off voltage of the third scan control clock signal CLK3_SC is supplied to the first output terminal OUT1. Accordingly, the scan signal SC(k) is deactivated.

When supply of the second sensing clock signal S_CLK2 is stopped in the seventh period t7, the gate-off voltage of the second sensing clock signal S_CLK2 is removed via the 17th transistor T17 and the 18th transistor T18. It may be transmitted to one driving node (QN1). Accordingly, the first driving node QN1 is initialized with a gate-off voltage.

In the eighth period t8, that is, the reset period RP, the sensing on voltage SEN_ON may have a gate on voltage. At this time, since the k+3 carry signal CR(k+3) has a gate-off voltage, the voltage of the sampling node SN may be reset to the gate-off voltage.

6 is a circuit diagram illustrating a second embodiment of a stage included in the scan driver of FIG. 3.

In FIG. 5, the same reference numerals are used for the components described with reference to FIG. 4, and duplicate description of these components will be omitted. In addition, the stage STka of FIG. 6 may have a configuration substantially the same as or similar to the stage STk of FIG. 4 except for the configuration of the third output buffer unit 131C.

3, 4 and 6, the k-stage STka includes a first driving control unit 110, a second driving control unit 120, an output buffer unit 130A, 130B, 131C, and a connection control unit 140 ).

In the second embodiment of the present invention, the third output buffer unit 131C may further include a fourth capacitor C4. The fourth capacitor C4 may be connected between the first driving node QN1 and the second output terminal OUT2 outputting the sensing signal SS(k). In the second embodiment of the present invention, as the fourth capacitor C4 is provided, the stage STka may be more robust to the threshold voltage negative condition. Also, as the fourth capacitor C4 is provided, the voltage of the first driving node QN1 may be boosted during the display period DP.

Since the driving method of the stage STka shown in FIG. 6 is the same as that shown in FIG. 5, a detailed description thereof will be omitted.

7 is a circuit diagram illustrating a third embodiment of a stage included in the scan driver of FIG. 3.

In FIG. 7, the same reference numerals are used for the components described with reference to FIG. 4, and duplicate description of these components will be omitted. In addition, the stage STkb of FIG. 7 may have a configuration substantially the same as or similar to the stage STk of FIG. 4 except for the configuration of the first driving control unit 111. therefore,

3, 4 and 7, the k-th stage STkb includes a first driving control unit 111, a second driving control unit 120, an output buffer unit 130A, 130B, 130C, and a connection control unit 140 ).

In the third embodiment of the present invention, the first driving control unit 111 may further include a second transistor T22. The 22nd transistor T22 may be connected between the gate electrode of the third transistor T3 and the first node N1. The gate electrode of the 22nd transistor T22 may be connected to the first power terminal V1 that receives the first power VGH. The 22nd transistor T22 may always be turned on by the voltage of the first power source VGH. Therefore, the 22nd transistor T22 does not significantly affect the operation of the first node N1 and/or the first driving node QN1.

The 22nd transistor T22 may stabilize the gate voltage of the third transistor T3. For example, when the voltage of the first node N1 is boosted by the first capacitor C1, the gate voltage of the third transistor T3 by the 22nd transistor T22 is not affected by the boosted voltage. Does not. Therefore, when the third transistor T3 is turned on, the gate-source voltage Vgs of the third transistor T3 can be prevented from being unintentionally raised, and the third transistor T3 is stably It can work. As a result, accordingly, the reliability of the scan driver 210 can be improved.

Since the driving method of the stage STkb shown in FIG. 7 is the same as that shown in FIG. 5, a detailed description thereof will be omitted.

8 is a circuit diagram illustrating a fourth embodiment of a stage included in the scan driver of FIG. 3.

In FIG. 8, the same reference numerals are used for the components described with reference to FIG. 4, and duplicate description of these components will be omitted. In addition, the stage STkc of FIG. 8 may have a configuration substantially the same as or similar to the stage STk of FIG. 4 except for the configuration of the second driving control unit 121.

3, 4 and 8, the k-th stage STkc includes a first driving control unit 110, a second driving control unit 121, an output buffer unit 130A, 130B, 130C, and a connection control unit 140. ).

In the fourth embodiment of the present invention, the second driving control unit 121 may further include a fifth capacitor C5. The fifth capacitor C5 may be connected between the gate electrode of the sixteenth transistor T16 and the sampling node SN.

In the fourth embodiment of the present invention, as the fifth capacitor C5 is provided, the leakage current generated by the supply of the sensing on signal SEN_ON can be blocked.

Since the driving method of the stage STkc shown in FIG. 8 is the same as that shown in FIG. 5, a detailed description thereof will be omitted.

9 is a circuit diagram illustrating a fifth embodiment of a stage included in the scan driver of FIG. 3.

In FIG. 9, the same reference numerals are used for the components described with reference to FIG. 4, and duplicate description of these components will be omitted. In addition, the stage STkd of FIG. 9 may have a configuration substantially the same as or similar to the stage STk of FIG. 4 except for the configuration of the second driving control unit 122.

3, 4 and 9, the k-th stage STkd includes a first driving control unit 110, a second driving control unit 122, an output buffer unit 130A, 130B, 130C, and a connection control unit 140 ).

In the fifth embodiment of the present invention, the second driving control unit 122 may further include a 23rd transistor T23.

The 23rd transistor T23 may be diode-connected between the first power terminal V1 receiving the first power VGH and the sensing node SN. The 23 transistor T23 is turned on according to the voltage of the sensing node SN to supply the voltage of the first power source VGH to the sensing node SN.

As described above, after the gate-on voltage is charged to the sensing node SN, the 23rd transistor T23 can stably maintain the voltage of the sensing node SN as the gate-on voltage.

Since the driving method of the stage STkd shown in FIG. 9 is the same as that shown in FIG. 5, a detailed description thereof will be omitted.

In the above-described second to fifth embodiments of FIGS. 6 to 9, one or at least two or more may be combined. That is, in various embodiments of the present invention, the stage STk of the first embodiment shown in FIG. 4 is one of the components added according to the second to fifth embodiments shown in FIGS. 6 to 9 or It may further include two or more.

10 is a circuit diagram illustrating a sixth embodiment of the stage included in the scan driver of FIG. 3.

In FIG. 10, the same reference numerals are used for the components described with reference to FIG. 4, and duplicate description of these components will be omitted. In addition, the stage STke of FIG. 10 may have a configuration substantially the same as or similar to the stage STk of FIG. 4 except for the configuration of the second driving control unit 123.

3, 4 and 10, the k-th stage STke includes a first driving control unit 110, a second driving control unit 123, an output buffer unit 130A, 130B, 130C, and a connection control unit 140 ).

In the sixth embodiment of the present invention, the second driving control unit 123 includes the 17a transistors T17a instead of the 17th to 19th transistors T17 to T19 compared to the first embodiment of FIG. 4. . The 17a transistor T17a is connected between the third node N3 and the first power terminal V1. The gate electrode of the 17a transistor T17a is connected to the first driving node QN1.

11 is a timing diagram showing an example of the operation of the stage of FIG. 10.

1, 3, 10 and 11, one frame period may include a display period DP and a vertical blank period VBP.

In the display period DP, scan signals SC(k) may be sequentially provided to pixel lines. Also, during the display period DP, the sensing signal SS(k) may be provided to the pixel lines.

In the display period DP, the sensing-on signal SEN_ON may be supplied to at least one of the plurality of stages (in the present embodiment, the k-th stage STk). Only the stage receiving the sensing on signal SEN_ON may output the scan signal SC(k) and the sensing signal SS(k) in the subsequent sensing period SP. During the sensing period SP, sensing of pixels receiving the scan signal SC(k) and the sensing signal SS(k) output from at least one selected stage may be performed.

In the display period DP, the display-on signal DIS_ON may have a gate-on voltage and the second sensing clock signal S_CLK2 may have a gate-off signal. Accordingly, during the display period DP, the twelfth transistor T12 and the thirteenth transistor T13 maintain the turn-on state, and the fourteenth transistor T14 and the seventeenth transistor T17 turn-off state. To maintain.

Since the driving method in the display period DP is the same as that described with reference to FIG. 5, a detailed description is omitted.

During the sensing period SP, the k-th stage STk may output the scan signal SC(k) in synchronization with the third scan control clock signal CLK3_SC applied to the scan control clock terminal SCCK. In one embodiment, during the vertical blank period VBP, the scan signal SC(k) may be output at least twice. The first scan signal SC(k) is output in the first sensing period SP1, and when the first scan signal SC(k) is output, the mobility and threshold voltage sensing of the driving transistor provided in the pixel are sensed. The voltage for this may be applied to the pixel. The second scan signal SC(k) is output in the pixel reset period PRP, and when the second scan signal SC(k) is output, the data voltage applied to the corresponding pixel in the previous display period DP is Can be re-applied.

Also, in the sensing period SP, the k-th stage STk may output the sensing signal SS(k) in synchronization with the third sensing control clock signal CLK3_SS applied to the sensing control clock terminal SSCK. . In one embodiment, the sensing signal SS(k) may be output in the first sensing period SP1, the second sensing period SP2, and the pixel reset period PRP. While the sensing signal SS(k) is output in the first sensing period SP1, a sensing current for sensing the mobility and threshold voltage of the driving transistor provided in the pixel may be applied to the pixel. While the sensing signal SS(k) is output in the second sensing period SP2, a sensing current for sensing the current characteristic of the light emitting diode LED provided in the pixel may be applied to the pixel.

In the sensing period SP, the display-on signal DIS_ON may have a gate-off voltage and the second sensing clock signal S_CLK2 may have a gate-on signal. Accordingly, during the sensing period SP, the twelfth transistor T12 and the thirteenth transistor T13 maintain a turn-off state, and the fourteenth transistor T14 turns in response to the second sensing clock signal S_CKL2. -Can be turned off.

The operation in the sensing period SP will be mainly described for differences from those described in FIG. 5.

In an embodiment of the present invention, the third scan control clock signal CLK3_SC and the third sensing control clock signal CLK3_SS are first supplied in the first period t1, and thereafter the second sensing in the second period t2 The clock signal S_CLK2 is supplied. In FIG. 5, compared to a case in which the second sensing clock signal S_CLK2 is first supplied in the sensing period SP and the third scan control clock signal CLK3_SC and the third sensing control clock signal CLK3_SS are supplied thereafter, The voltage of the first driving node QN1 is prevented from being boosted. Accordingly, the voltage of the first driving node QN1 during the second period t2 when the scan signal SC(k) and the sensing signal SS(k) are output together is the fifth period t5 in FIG. 5. It is lower than the voltage during.

As the boosting of the first driving node QN1 is suppressed, excessive drain-source voltage Vds and gate-source voltage Vgs of the 17a transistor T17a may be prevented, and the 17a transistor ( The stress applied to T17a) is reduced and damage can be prevented.

12 is a circuit diagram illustrating a seventh embodiment of a stage included in the scan driver of FIG. 3.

In FIG. 12, the same reference numerals are used for the components described with reference to FIG. 10, and duplicate description of these components will be omitted. In addition, the stage STkf of FIG. 12 may have a configuration substantially the same as or similar to the stage STke of FIG. 10 except for the configuration of the second driving control unit 124.

3, 10 and 12, the k-th stage STkf includes a first driving control unit 110, a second driving control unit 124, an output buffer unit 130A, 130B, 130C, and a connection control unit 140 ).

In the seventh embodiment of the present invention, the second driving control unit 124 may include a 17b transistor T17b, a 18b transistor T18b, and a 19b transistor T19b.

The 17b transistor T17b and the 18b transistor T18b may be connected in series between the second sensing clock terminal S_CK2 to which the second sensing clock signal S_CLK2 is applied and the first driving node QN1. The gate electrodes of the 17b transistor T17b and the 18b transistor T18b may be commonly connected to the sampling node SN. The 17b transistor T17b and the 18b transistor T18b may transmit the second sensing clock signal S_CLK2 to the first driving node QN1 based on the voltage of the sampling node SN. In an embodiment, the second sensing clock signal S_CLK2 may have a gate-on voltage in a sensing period (eg, mobility sensing period).

The 19th transistor T19b may be connected between the third node N3 and the first power terminal V1 to which the first power VGH is applied. The 19th transistor T19b may include a gate electrode connected to the first driving node QN1.

The 17b to 19b transistors T17b to T19b are the 17b transistors by holding the voltage of the third node N3 to the voltage of the first power source VGH in response to the voltage of the first driving node QN1. The unnecessary drain-source voltage rise of (T17b) can be prevented. Therefore, the output of the stable scan signal SC(k) is guaranteed, and the reliability of the display device can be improved.

Since the driving method of the stage STkf shown in FIG. 12 is the same as that shown in FIG. 11, a detailed description thereof will be omitted.

13 is a circuit diagram illustrating an eighth embodiment of a stage included in the scan driver of FIG. 3.

In FIG. 13, the same reference numerals are used for the components described with reference to FIG. 12, and duplicate description of these components will be omitted. In addition, the stage STkg of FIG. 13 may have a configuration substantially the same as or similar to the stage STkf of FIG. 12 except for the configuration of the second driving control unit 125.

3, 12, and 13, the k-th stage STkg includes a first driving control unit 110, a second driving control unit 125, an output buffer unit 130A, 130B, 130C, and a connection control unit 140 ).

In the eighth embodiment of the present invention, the second driving control unit 125 may include a 19c transistor T19c.

The 19th transistor T19c outputs between the third node N3 and the carry output terminal CR outputting the carry signal CR(K) or the third node N3 and the scan signal SC(k). A diode may be connected between the first output terminal OUT1. Accordingly, the 19th transistor T19c may carry the carry signal CR(K) or the scan signal SC() to the third node N3 in response to the carry signal CR(K) or the scan signal SC(k). k)). That is, the 17b, 18b, and 19c transistors T17b, T18b, and T19c determine the voltage of the third node N3 in response to the carry signal CR(K) or the scan signal SC(k). By holding at the voltage of, the unnecessary drain-source voltage rise of the 17b transistor T17b can be prevented. Therefore, the output of the stable scan signal SC(k) is guaranteed, and the reliability of the display device can be improved.

Since the driving method of the stage STkg shown in FIG. 13 is the same as that shown in FIG. 11, a detailed description thereof will be omitted.

Although described above with reference to the embodiments of the present invention, those skilled in the art may variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that you can.

PX: Pixel
100: display unit
210: scan driver
220: data driver
230: sensing unit
240: timing control

Claims (32)

It includes a plurality of stages for outputting a scan signal and a sensing signal,
Each stage,
A first driving control unit controlling the voltage of the first node and the voltage of the second node in response to the previous carry signal;
Based on the sensing on signal, the carry signal, the voltage of the first power source, the voltage of the first node, and the voltage of the sampling node, the voltage of the first driving node is controlled, and the voltage of the sampling node and the sensing clock signal are used. A second driving control unit controlling the voltage of the second driving node;
A carry signal is output in response to the voltage of the first node and the voltage of the second node, and the scan signal and the sensing signal are output in response to the voltage of the first driving node and the voltage of the second driving node. An output buffer unit; And
And a connection control unit electrically connecting the first node, the first driving node, and the second node and the second driving node, respectively, in response to the display-on signal. The method of claim 1, wherein the second driving control unit,
A 16th transistor connected between the input terminal to which the carry signal is applied and the sampling node, and a gate electrode receiving the sensing on signal;
A 17th transistor connected between a third node and the first driving node, the gate electrode being connected to a first sensing clock terminal to which a first sensing clock signal is applied;
An 18th transistor connected between a second sensing clock terminal to which a second sensing clock signal is applied and the third node, and a gate electrode connected to the sampling node;
A 19th transistor connected between a first power terminal to which the first power is applied and the third node, and a gate electrode connected to the first driving node; And
And a third capacitor connected between a second power terminal to which a second power is applied and the sensing node. The method of claim 2, wherein the 17th transistor,
When the first sensing clock signal is supplied, a scan driver that supplies the voltage of the first power applied through the 19th transistor to the first driving node. The method of claim 2, wherein the 19th transistor,
And a scan driving unit maintaining the voltage of the third node constant by supplying the voltage of the first power supply to the third node in response to the voltage of the first driving node. The method of claim 2, wherein one frame period includes a display period and a vertical blank period,
In the display period, the sensing-on signal is supplied to at least one selected stage among the stages. The scan driver of claim 5, wherein the at least one selected stage outputs the scan signal and the sensing signal in the vertical blank period following the display period. The scan driver according to claim 5, wherein the sensing on signal is applied in synchronization with the subsequent carry signal in the display period. According to claim 2, The second drive control unit,
The 14th and 15th transistors connected in series between the third power terminal to which the third power is applied and the second driving node are further included.
The fourteenth transistor includes a gate electrode receiving the second sensing clock signal,
The 15th transistor includes a gate electrode connected to the sampling node. According to claim 2, The output buffer unit,
A twentieth transistor connected between a sensing control clock terminal to which a sensing control clock signal is applied and a second output terminal outputting the sensing signal, and a gate electrode connected to the first driving node; And
And a second transistor connected between a third power terminal to which a third power is applied and the second output terminal, and a gate electrode connected to the second driving node. The method of claim 9, wherein the output buffer unit,
And a fourth capacitor connected between the gate electrode of the twentieth transistor and the second output terminal. The method of claim 2, wherein the first driving control unit,
A fourth transistor connected between a first power terminal to which the first power is applied and the first node, and a gate electrode receiving the previous carry signal or scan start signal;
Fifth and sixth transistors connected in series between the first node and a carry output terminal outputting the carry signal;
A ninth transistor connected between the first node and the carry output terminal, the gate electrode receiving the carry signal after the gate electrode;
A third transistor connected between a clock terminal to which a clock signal is applied and the second node, and a gate electrode connected to the first node;
A seventh transistor connected between a first power terminal to which the first power is applied and the second node, and a gate electrode connected to the first clock terminal; And
And an eighth transistor diode-connected between the first power terminal and the second node. The method of claim 11, wherein the first driving control unit,
And a second transistor connected between the gate electrode of the third transistor and the first node, the gate electrode being connected to the first power terminal. According to claim 2, The second drive control unit,
And a fifth capacitor connected between the gate electrode and the sensing node of the sixteenth transistor. According to claim 2, The second drive control unit,
And a 23rd transistor diode-connected between the first power terminal to which the first power is applied and the sensing node. The method of claim 1, wherein the second driving control unit,
A 16th transistor connected between the input terminal to which the carry signal is applied and the sampling node, and a gate electrode receiving the sensing on signal;
A 17th transistor connected between the sensing clock terminal to which the sensing clock signal is applied and the first driving node, and a gate electrode connected to the sensing node; And
And a third capacitor connected between a second power terminal to which a second power is applied and the sensing node. The method of claim 15, wherein the output buffer unit,
A first transistor connected between a scan control clock terminal to which a scan control clock signal is applied and a first output terminal outputting the scan signal, and a gate electrode connected to the first driving node;
A second transistor connected between a third power terminal to which third power is applied and the first output terminal, and a gate electrode connected to the second driving node;
A twentieth transistor connected between a sensing control clock terminal to which a sensing control clock signal is applied and a second output terminal outputting the sensing signal, and a gate electrode connected to the first driving node; And
And a 21st transistor connected between the third power terminal and the second output terminal, and having a gate electrode connected to the second driving node. The method of claim 16,
In the sensing period, the scan control clock signal and the sensing control clock signal are applied to the scan driver before the sensing clock signal. The method of claim 1, wherein the second driving control unit,
A 16th transistor connected between the input terminal to which the carry signal is applied and the sampling node, and a gate electrode receiving the sensing on signal;
17th and 18th transistors connected in series between the sensing clock terminal to which the sensing clock signal is applied and the first driving node, wherein gate electrodes are commonly connected to the sampling node; And
And a 19th transistor connected between a third node between the 17th and 18th transistors and a first power terminal to which the first power is applied, and a gate electrode connected to the first driving node. Scan driver to do. The method of claim 1, wherein the second driving control unit,
A 16th transistor connected between an input terminal to which the subsequent signal is applied and the sampling node, and a gate electrode receiving the sensing on signal;
17th and 18th transistors connected in series between the clock terminal to which the sensing clock signal is applied and the first driving node, wherein gate electrodes are commonly connected to the sampling node; And
And a 19th transistor diode-connected between a third node between the 17th and 18th transistors and a carry output terminal outputting the carry signal, or between an output terminal outputting the scan signal and the third node. Scan drive unit characterized in that. A plurality of pixels connected to the first and second scan lines and data lines, respectively;
A scan driver including a plurality of stages to supply scan signals and sensing signals to the first and second scan lines, respectively; And
It includes a data driver for supplying a data signal to the data lines,
Each of the stages,
A first driving control unit controlling the voltage of the first node and the voltage of the second node in response to the previous carry signal;
Based on the sensing on signal, the carry signal, the voltage of the first power source, the voltage of the first node, and the voltage of the sampling node, the voltage of the first driving node is controlled, and the voltage of the sampling node and the sensing clock signal are used. A second driving control unit controlling the voltage of the second driving node;
A carry signal is output in response to the voltage of the first node and the voltage of the second node, and the scan signal and the sensing signal are output in response to the voltage of the first driving node and the voltage of the second driving node. An output buffer unit; And
And a connection control unit electrically connecting the first node, the first driving node, and the second node and the second driving node, respectively, in response to the display-on signal. The method of claim 20, wherein the second drive control unit,
A 16th transistor connected between the input terminal to which the carry signal is applied and the sampling node, and a gate electrode receiving the sensing on signal;
A 17th transistor connected between a third node and the first driving node, the gate electrode being connected to a first sensing clock terminal to which a first sensing clock signal is applied;
An 18th transistor connected between a second sensing clock terminal to which a second sensing clock signal is applied and the third node, and a gate electrode connected to the sampling node;
A 19th transistor connected between a first power terminal to which the first power is applied and the third node, and a gate electrode connected to the first driving node; And
And a third capacitor connected between a second power terminal to which second power is applied and the sensing node. The method of claim 21, wherein the 17th transistor,
And when the first sensing clock signal is supplied, supply the voltage of the first power applied through the 19th transistor to the first driving node. The method of claim 21, wherein the 19th transistor,
And supplying the voltage of the first power supply to the third node in response to the voltage of the first driving node to keep the voltage of the third node constant. The method of claim 21, wherein the output buffer unit,
A twentieth transistor connected between a sensing control clock terminal to which a sensing control clock signal is applied and a second output terminal outputting the sensing signal, and a gate electrode connected to the first driving node;
A twenty-first transistor connected between a third power terminal to which third power is applied and the second output terminal, and a gate electrode connected to the second driving node; And
And a fourth capacitor connected between the gate electrode of the twentieth transistor and the second output terminal. The method of claim 21, wherein the first drive control unit,
A fourth transistor connected between a first power terminal to which the first power is applied and the first node, and a gate electrode receiving the previous carry signal or scan start signal;
Fifth and sixth transistors connected in series between the first node and a carry output terminal outputting the carry signal;
A ninth transistor connected between the first node and the carry output terminal, the gate electrode receiving the carry signal after the gate electrode;
A third transistor connected between a clock terminal to which a clock signal is applied and the second node, and a gate electrode connected to the first node;
A seventh transistor connected between a first power terminal to which the first power is applied and the second node, and a gate electrode connected to the first clock terminal;
An eighth transistor diode-connected between the first power terminal and the second node; And
And a 22th transistor connected between the gate electrode of the third transistor and the first node, and a gate electrode connected to the first power terminal. The method of claim 21, wherein the second drive control unit,
And a fifth capacitor connected between the gate electrode and the sensing node of the sixteenth transistor. The method of claim 21, wherein the second drive control unit,
And a 23rd transistor diode-connected between the first power terminal to which the first power is applied and the sensing node. The method of claim 20, wherein the second drive control unit,
A 16th transistor connected between the input terminal to which the carry signal is applied and the sampling node, and a gate electrode receiving the sensing on signal;
A 17th transistor connected between the sensing clock terminal to which the sensing clock signal is applied and the first driving node, and a gate electrode connected to the sensing node; And
And a third capacitor connected between a second power terminal to which second power is applied and the sensing node. The output buffer unit of claim 28,
A first transistor connected between a scan control clock terminal to which a scan control clock signal is applied and a first output terminal outputting the scan signal, and a gate electrode connected to the first driving node;
A second transistor connected between a third power terminal to which third power is applied and the first output terminal, and a gate electrode connected to the second driving node;
A twentieth transistor connected between a sensing control clock terminal to which a sensing control clock signal is applied and a second output terminal outputting the sensing signal, and a gate electrode connected to the first driving node; And
And a twenty-first transistor connected between the third power terminal and the second output terminal and a gate electrode connected to the second driving node. The method of claim 29,
In the sensing period, the scan control clock signal and the sensing control clock signal are applied before the sensing clock signal. The method of claim 20, wherein the second drive control unit,
A 16th transistor connected between the input terminal to which the carry signal is applied and the sampling node, and a gate electrode receiving the sensing on signal;
17th and 18th transistors connected in series between the sensing clock terminal to which the sensing clock signal is applied and the first driving node, wherein gate electrodes are commonly connected to the sampling node; And
And a 19th transistor connected between a third node between the 17th and 18th transistors and a first power terminal to which the first power is applied, and a gate electrode connected to the first driving node. Display device. The method of claim 20, wherein the second drive control unit,
A 16th transistor connected between an input terminal to which the subsequent signal is applied and the sampling node, and a gate electrode receiving the sensing on signal;
17th and 18th transistors connected in series between the clock terminal to which the sensing clock signal is applied and the first driving node, wherein gate electrodes are commonly connected to the sampling node; And
And a 19th transistor diode-connected between a third node between the 17th and 18th transistors and a carry output terminal outputting the carry signal, or between an output terminal outputting the scan signal and the third node. Display device characterized in that.

Images