KR20200077383A - Comparator curcuit, adc citcuit, semiconductor device and mobile device - Google Patents

Abstract

Provided is a comparator circuit capable of low voltage driving. A comparator circuit includes an input differential stage, a load circuit, a first current source, a first bias voltage supply, a third connection portion, and a fourth connection portion. An input differential stage has a first transistor to which a first input signal is supplied and a second transistor to which a second input signal is supplied. The load circuit includes a third transistor connected to the first transistor via a first connection portion, and the fourth transistor is connected to the second transistor through the second connection portion, wherein the fourth transistor has a gate connected to the third transistor. The gates of the third transistor and the fourth transistor are connected to the first connection portion through a third capacitor. A first bias voltage supply unit supplies a first bias voltage between the gates of the third transistor and the fourth transistor and the third capacitor.

Description

Comparator circuit, ADC circuit, semiconductor device and mobile device {COMPARATOR CURCUIT, ADC CITCUIT, SEMICONDUCTOR DEVICE AND MOBILE DEVICE}

The present invention relates to comparator circuits, ADC circuits, semiconductor devices and mobile devices.

Recently, a large scale integration (LSI) of an image sensor for a mobile device such as a smart phone strongly demands low power consumption. The ADC (Analog to Digital Converter) mounted in the image sensor LSI is the main factor of power consumption in the image sensor LSI. Therefore, it is effective to realize low power consumption of the image sensor LSI to achieve low power consumption of the ADC.

However, there are several proposals for ADC. For example, the patent document proposes a differential amplification circuit that suppresses the variation of the output operating point with respect to the variation of the common-mode input voltage. The related differential amplification circuit includes a pair of push-pull complementary metal oxide semiconductor (CMOS) inverting amplifiers. Here, between the common source and ground of the pair of NMOS transistors, an NMOS transistor is arranged, with a gate connected to the output terminal.

The present invention has been made to solve such a problem, and an object thereof is to provide a comparator circuit capable of driving a low power voltage.

The comparator circuit according to the present invention includes a differential amplifier for comparing a first input signal and a second input signal in the form of a differential signal to output a comparison result, and an output stage amplifier for outputting an amplification signal based on the comparison result. The differential amplifier includes an input differential stage, a load circuit, a first current source, a first bias voltage supply, a third connection, and a fourth connection. The input differential stage includes a first transistor in which the first input signal is supplied to the gate through the first capacitor, and a second transistor in which the second input signal is supplied to the gate through the second capacitor. The load circuit is provided at the input differential stage. The load circuit includes a third transistor connected to the first transistor via the first connection, and a fourth transistor connected to the second transistor via the second connection and a gate connected to the third transistor and each other. The gates of the third transistor and the fourth transistor are connected to the first connection part via the third capacitor. The first current source is a current source of the input differential stage and is connected to the first transistor and the second transistor. The first bias voltage supply unit supplies a first bias voltage between the gates of the third and fourth transistors and the third capacitor. The third connection part connects the gate of the first transistor and the first connection part. The fourth connection portion connects the gate of the second transistor and the second connection portion. The output stage amplifier includes a fifth transistor, a second current source, a sixth connection portion, and an output portion. The signal based on the comparison result is supplied to the gate of the fifth transistor via the fourth capacitor. The second current source is connected to the fifth transistor via the fifth connection. The sixth connecting portion connects the gate of the fifth transistor and the fifth connecting portion.

The output unit is disposed on the fifth connection unit and outputs an amplified signal.

By the above configuration, the present invention can provide a comparator circuit or the like capable of driving a low power voltage.

In the comparator circuit, the first bias voltage supply unit includes a first switch that adjusts the timing for supplying the first bias voltage, and the third connection unit is configured to control the timing of connecting the gate of the first transistor and the first connection unit. It may include 2 switches.

The fourth connection portion includes a third switch for adjusting the timing of connecting the gate of the second transistor and the second connection portion, and the sixth connection portion is a fourth switch for adjusting the timing of connecting the gate of the fifth transistor and the fifth connection portion. It may include. Thereby, the comparator circuit can set the operating point of each transistor.

In the comparator circuit, the differential amplifier may further include a second bias voltage supply unit supplying a second bias voltage to the first connection unit, and a fifth switch path adjusting timing of supplying a second bias voltage to the first connection unit. . Thereby, the comparator circuit can supply a bias voltage very suitable for the load circuit.

In the comparator circuit, the first switch is turned on before the second switch, the third switch, the fourth switch and the fifth switch are turned on, and the fifth switch is turned on simultaneously with the second switch, the third switch and the fourth switch , The second switch, the third switch, and the fourth switch are preferably turned off after the first switch and the fifth switch are turned off. Thereby, the operation point can be set very appropriately for each transistor.

In the comparator circuit, the differential amplifier may further include a buffer circuit between the first capacitor and the gate of the first transistor. The buffer circuit includes a constant current supply, a buffer transistor, a second bias voltage supply, and a sixth switch. The constant current supply unit supplies a preset current. One of the source or drain of the buffer transistor is connected to the constant current supply, the other is connected to ground, and the gate is supplied with a first input signal and a second bias voltage. The second bias voltage supply unit supplies the second bias voltage. The sixth switch adjusts the timing at which the second bias voltage is supplied to the gate of the buffer transistor. Thereby, the load of the 2nd bias voltage supply part can be reduced.

In the comparator circuit, the second switch, the third switch, and the fourth switch are turned on after the first switch and the sixth switch are turned on, while they can be turned off after the first switch and the sixth switch are turned off. As a result, the comparator circuit having the buffer circuit can set the operating point very appropriately for each transistor.

In the comparator circuit, the first current source and the second current source each include a current source transistor, and a third bias voltage may be supplied to the gate of the current source transistor. In this case, the first current source and the second current source may include a current source switch that adjusts the supply timing of the third bias voltage. In addition, the current source switch can be turned off simultaneously with the first switch being turned off. With this configuration, the comparator circuit can reduce the influence of each other with the surrounding configuration.

The ADC circuit according to the present invention includes a plurality of the comparator circuits.

The semiconductor device according to the present invention includes the ADC circuit and a plurality of photoelectric conversion elements arranged on a matrix, and the ADC circuit discretes the analog signal generated by the photoelectric conversion element. Moreover, the mobile device according to the present invention includes the semiconductor device and a lens for imaging an image of a subject, and the semiconductor device performs processing for generating image data captured through a lens. With this configuration, the ADC circuit, the semiconductor device, and the mobile device can reduce power consumption.

According to the present invention, a comparator circuit or the like capable of suppressing the driving voltage is provided.

1 is a circuit diagram of a comparator circuit according to the first embodiment.
2 is a timing chart of a switch in the comparator circuit according to the first embodiment.
3 is a circuit diagram of a comparator circuit according to the second embodiment.
4 is a timing chart of a switch in the comparator circuit according to the second embodiment.
5 is a circuit diagram of a comparator circuit according to the third embodiment.
6 is a timing chart of a switch in the comparator circuit according to the third embodiment.

For clarity of explanation, the following description and drawings will be appropriately omitted, and simplified. In addition, the same reference numerals are assigned to the same elements in each drawing, and duplicate descriptions will be omitted if necessary.

<Example 1>

Hereinafter, Example 1 will be described with reference to the drawings. 1 is a circuit diagram of a comparator circuit according to the first embodiment. The illustrated comparator circuit 10 can be used, for example, in an ADC or the like.

The comparator circuit 10 compares the first input signal IN1 and the second input signal IN2 in the form of a differential signal to output a comparison result VV in response to the differential amplifier 11 and a comparison result. An output stage amplifier 12 may be included. In addition, the output signal VOUT is also called an amplified signal.

The differential amplifier 11 will be described below. The differential amplifier 11 includes an input differential stage 111, a load circuit 112, a first current source 113, a first bias voltage supply 114, a second bias voltage supply 115, and a third connection W3. And a fourth connecting portion W4.

The input differential stage 111 includes a first transistor T1 in which a first input signal IN1 is supplied to a gate through a first capacitor C1, and a second input signal IN2 in a second capacitor C2. And a second transistor T2 supplied to the gate via. In the present embodiment, the first transistor T1 and the second transistor T2 are N-type metal-oxide-semiconductor field-effect transistors (MOSFETs). In addition, N-type MOSFET is also called NMOS.

The load circuit 112 configures a load differential transistor stage corresponding to the input differential stage 111. The load circuit 112 includes a third transistor T3 and a fourth transistor T4. The third transistor T3 and the fourth transistor T4 are P-type MOSFETs. In addition, P-type MOSFET is also called PMOS.

The source of the third transistor T3 is connected to the first power supply V1, and the drain is connected to the drain of the first transistor T1 through the first connection portion W1. The source of the fourth transistor T4 is connected to the second power supply V2, and the drain is connected to the drain of the second transistor T2 through the second connecting portion W2. Further, the gates of the third transistor T3 and the fourth transistor T4 are connected to each other. Further, the gates of the third transistor T3 and the fourth transistor T4 are connected to the first connection W1 through the third capacitor C3. That is, the third transistor T3 and the fourth transistor T4 constituting the load circuit 112 constitute a current mirror circuit diode-connected to the first transistor T1 side. However, the third capacitor C3 is added to the configuration of the diode connection.

Further, the load circuit 112 is connected to the first bias voltage supply unit 114. The first bias voltage supply unit 114 supplies a first bias voltage Vb1 between the gates of the third transistor T3 and the fourth transistor T4 and the third capacitor C3. The first bias voltage supply unit 114 includes a first switch SW1 that adjusts timing for supplying the first bias voltage Vb1. By adjusting the first switch SW1, the load circuit 112 receives the first bias voltage Vb1, and correspondingly, the operating point of the load circuit 112 is set.

The first current source 113 is a current source of the input differential stage 111 and is connected to the first transistor T1 and the second transistor T2. The first current source 113 has a sixth transistor T6 that is an NMOS. The drain of the sixth transistor T6 is connected to the sources of the first transistor T1 and the second transistor T2, and the source is connected to ground (GND). Further, a third bias voltage Vb3 is supplied to the gate of the sixth transistor T6.

The third connection part W3 connects the gate of the first transistor T1 and the first connection part W1. That is, the gate and drain of the first transistor T1 are short-circuited by the third connection portion W3.

Further, the third connecting portion W3 includes the second switch SW2. The second switch SW2 adjusts the timing of connecting the gate of the first transistor T1 and the first connection portion W1. By adjusting the second switch SW2, the operating point of the first transistor T1 is set.

The fourth connection portion W4 connects the gate of the second transistor T2 and the second connection portion W2. That is, the gate and drain of the second transistor T2 are short-circuited by the fourth connecting portion W4.

Further, the fourth connecting portion W4 includes the third switch SW3. The third switch SW3 adjusts the timing of connecting the gate of the second transistor T2 and the second connection portion W2. By adjusting the third switch SW3, the operating point of the second transistor T2 is set.

The second bias voltage supply unit 115 is connected to the first connection unit W1 and supplies the second bias voltage Vb2 to the first connection unit W1. In addition, the second bias voltage supply unit 115 includes a fifth switch SW5. The fifth switch SW5 adjusts the timing of supplying the second bias voltage Vb2 to the first connection portion W1. The voltage Vds between the drain and the source of the third transistor T3 is set by adjusting the fifth switch SW5.

By the above-described configuration, the differential amplifier 11 receives the first input signal IN1 and the second input signal IN2, generates a signal resulting from comparing the two transmitted signals, and generates the generated signal. It is supplied to the output stage amplifier 12.

Next, the output stage amplifier 12 will be described. The output stage amplifier 12 receives a signal supplied from the differential amplifier 11 and outputs an output signal VOUT in response to this signal. The output stage amplifier 12 has a main configuration, and includes a fifth transistor T5, a second current source 121, a sixth connection portion W6, and an output portion 122.

The fifth transistor T5 is a PMOS, and the source is connected to the power supply V3. The signal of the comparison result output from the differential amplifier 11 is supplied to the gate of the fifth transistor T5 via the fourth capacitor C4. Furthermore, the drain of the fifth transistor is connected to the second current source 121 via the fifth connection portion W5. The output of the differential amplifier 11 is supplied to the fifth transistor T5 via the fourth capacitor C4, thereby separating the voltages of the differential amplifier 11 and the output stage amplifier 12, and the differential amplifier ( 11) can be prevented from being affected by the output stage amplifier (12).

The second current source 121 is connected to the fifth transistor T5 through the fifth connecting portion W5.

The second current source 121 includes a seventh transistor T7 that is an NMOS. The drain of the seventh transistor T7 is connected to the drain of the fifth transistor T5 through the fifth connecting portion W5. Further, the source of the seventh transistor T7 is connected to ground (GND). Further, a third bias voltage Vb3 is supplied to the gate of the seventh transistor T7. In addition, as shown in FIG. 1, the third bias voltage Vb3 supplied to the gate of the seventh transistor T7 and the third bias voltage Vb3 supplied to the gate of the sixth transistor T6 are the same power supply. Is supplied from.

The sixth connection portion W6 connects the gate of the fifth transistor T5 and the fifth connection portion W5. That is, the gate and drain of the fifth transistor T5 are shorted by the sixth connection W6.

Further, the sixth connection portion W6 includes a fourth switch SW4. The fourth switch SW4 adjusts the timing of connecting the gate of the fifth transistor T5 and the fifth connection W5. By adjusting the fourth switch SW4, the operating point of the fifth transistor T5 is set.

The output unit 122 is disposed on the fifth connection unit W5 and outputs the output signal VOUT generated by the output stage amplifier 12.

Next, with reference to FIG. 2, the operation timing of the switches of the comparator circuit 10 according to this embodiment will be described. 2 is a timing chart of a switch in the comparator circuit according to the first embodiment. The horizontal axis in Fig. 2 is time t, and the vertical axis represents the switch state (on or off). For example, the first switch SW1 is turned on before time t0, and turns from on to off at time t1. The fifth switch SW5 changes from off to on at time t0, and changes from on to off at time t1. The second switch SW2, the third switch SW3, and the fourth switch SW4 all change from off to on at time t0, and change from on to off at time t2.

As shown in FIG. 2, the first switch SW1 in the comparator circuit 10 includes a second switch SW2, a third switch SW3, a fourth switch SW4, and a fifth switch SW5. It came before it came. In addition, the fifth switch SW5 is turned on simultaneously with the second switch SW2, the third switch SW3 and the fourth switch SW4, and is turned off simultaneously with the first switch SW1. The second switch SW2, the third switch SW3, and the fourth switch SW4 are turned off after the first switch SW1 and the fifth switch SW5 are turned off. The comparator circuit 10 sets each operating point of each transistor by adjusting each switch at the timing described above.

The comparator circuit 10 according to the first embodiment has been described above. As described above, the comparator circuit 10 according to the first embodiment is configured to set the operation points of each transistor separately. Further, in the comparator circuit 10, the gate of each transistor is provided with the above-described capacitor, so that each DC component is separately set and configured so that the AC component can propagate. Accordingly, for example, the first bias voltage Vb1 supplied to the gate of the third transistor T3 and the second bias voltage Vb2 supplied to the drain of the third transistor T3 are set to different values. Can be. Therefore, the first bias voltage Vb1 is set such that the gate source-to-gate voltage Vgs is greater than the threshold voltage Vth of the third transistor T3. Meanwhile, the second bias voltage Vb2 is a different voltage from the first bias voltage Vb1, and based on the second bias voltage Vb2, between the drain sources where the third transistor T3 can normally operate in the saturation region. The voltage Vds can be set.

More specifically, the comparator circuit 10 may set the second bias voltage Vb2 to a voltage higher than the first bias voltage Vb1, for example. Therefore, the transistor of the comparator circuit 10 can set the voltage (Vds) between the drain sources to a value suitable for constant voltage driving. Thereby, the comparator circuit 10 can reduce the drive voltage.

The above-described comparator circuit 10 may be used in an apparatus or device requiring low power consumption. For example, the comparator circuit 10 can be used in a mobile device having a camera function. Such a mobile device has an image sensor that generates image data obtained by imaging a subject using a lens. In the image sensor, a plurality of photoelectric conversion elements (ie, imaging elements) arranged in a matrix form an analog signal, and a single slope ADC receiving the analog signal performs discrete processing. Therefore, the mobile device using the comparator circuit 10 can reduce power consumption.

As described above, according to the first embodiment, a comparator circuit or the like capable of driving low voltage can be provided. In addition, by using the comparator circuit according to the first embodiment, power consumption of the ADC circuit, the semiconductor device, or the mobile device can be reduced.

<Example 2>

Next, Example 2 will be described. The comparator circuit according to the second embodiment is different from the first embodiment in that it has a buffer circuit for reducing the load current of the second bias voltage.

The comparator circuit according to the second embodiment will be described with reference to FIG. 3. 3 is a circuit diagram of a comparator circuit according to the second embodiment. Incidentally, the configuration already described in the description of Example 1 below is appropriately omitted.

The comparator circuit 20 shown in FIG. 3 has a first input signal IN1 and a buffer circuit 21 connected to the input terminal of the second bias voltage. In other words, the differential amplifier 11 of FIG. 1 further includes a buffer circuit between the gate of the first capacitor C1 and the first transistor T1. The buffer circuit 21 has a main configuration, and includes a constant current supply unit A1 and a buffer transistor T8.

The constant current supply unit A1 is a constant current source capable of supplying a predetermined current, and is connected to the power source V4 and the source of the buffer transistor T8. In addition, the constant current supply unit A1 connects to the gate of the first transistor T1 and supplies a predetermined signal to the first transistor T1 in response to the switching operation of the buffer transistor T8.

The buffer transistor T8 is a PMOS, and the source is connected to the constant current supply unit A1, and the drain is connected to ground (GND). Further, the gate of the buffer transistor T8 is connected to the first capacitor C1 and to the second bias voltage supply unit 211. The second bias voltage supply unit 211 supplies the second bias voltage Vb4 to the gate of the buffer transistor T8. In addition, the second bias voltage supply unit 211 has a sixth switch SW6. The sixth switch SW6 adjusts timing of supplying the second bias voltage Vb4 to the gate of the buffer transistor T8.

Next, the operation timing of each switch of the comparator circuit 20 according to the second embodiment will be described with reference to FIG. 4. 4 is a timing chart of a switch in the comparator circuit according to the second embodiment.

The comparator circuit 20 according to the present embodiment is different from the first embodiment in that it has a sixth switch SW6. The sixth switch SW6 is turned on before time t0, and changes from on to off at time t21.

4, the second switch SW2, the third switch SW3, and the fourth switch SW4 are turned on after the first switch SW1 and the sixth switch SW6 are turned on, and the first switch SW1 is turned on. The switch SW1 and the sixth switch SW6 are turned off and then off. Also, the sixth switch SW6 is turned off before the first switch SW1 is turned off.

The comparator circuit 20 sets the operating point of each transistor by adjusting each switch at the timing described above.

With the above configuration, the comparator circuit 20 according to the second embodiment can receive a signal from the constant current supply unit A1 to the first connection unit W1. Therefore, the comparator circuit 20 can receive the second bias voltage Vb4 with low impedance. The second bias voltage supply unit 211 may be configured to operate at a low load.

As described above, according to the second embodiment, a comparator circuit or the like capable of low-voltage driving can be provided. Further, the comparator circuit 20 according to the second embodiment can reduce the load current to the bias voltage generating circuit during self-biasing. Therefore, the comparator circuit 20 according to the second embodiment can reduce power consumption of the bias voltage generation circuit. Therefore, by using the comparator circuit according to the second embodiment, power consumption of the ADC circuit, semiconductor device, or mobile device can be reduced.

<Example 3>

Next, Example 3 will be described with reference to FIG. 5. Embodiment 3 differs from the configuration of Embodiment 1 in that the first current source 113 has a first current source switch SW31 and the second current source 121 has a second current source switch SW32. In addition, since other structures are the same as those of Embodiment 1, differences from Embodiment 1 will be described below.

In the comparator circuit 30 according to the present embodiment, the first current source 113 and the second current source 121 include a sixth transistor T6 and a seventh transistor T7, respectively. 3 bias voltages Vb3 are respectively supplied. In addition, the first current source 113 includes a first current source switch SW31, and the second current source 121 includes a second current source switch SW32.

The first current source switch SW31 connects to the gate of the sixth transistor T6 and adjusts the supply timing of the third bias voltage Vb3 to the sixth transistor T6. The second current source switch SW32 is connected to the gate of the seventh transistor T7 and adjusts the supply timing of the third bias voltage Vb3 to the seventh transistor T7.

Referring to Fig. 6, the operation timing of each switch of the comparator circuit 30 according to the third embodiment will be described. 6 is a timing chart of a switch in the comparator circuit according to the third embodiment.

The timing chart shown in FIG. 6 is different from the timing chart according to Embodiment 1 in that the current source switches SW31 and SW32 are added. The current source switches SW31 and SW32 are turned on before time t0, and are switched from on to off at time t1. That is, the current source switches SW31 and SW32 are turned off simultaneously with the first switch SW1 being turned off.

With the above configuration, the comparator circuit 30 according to the third embodiment can reduce the influence of each other between adjacent circuits by switching off the current source after determining the bias voltage. With this configuration, the comparator circuit 30 including a plurality of switches is less susceptible to noise caused by the switching operation of the switch. Therefore, according to the third embodiment, it is possible to reduce a malfunction caused by noise and, on the other hand, provide a comparator circuit or the like capable of low voltage driving.

In addition, the present invention is not limited to the above-described embodiments, and it is possible to appropriately change the scope without departing from the spirit.

10 Comparator circuit
11 Differential Amplifier
12 output stage amplifier
20 comparator circuit
21 buffer circuit
30 comparator circuit
111 input differential stage
112 load circuit
122 outputs
A1 constant current supply
SW1 first switch
SW2 second switch
SW3 third switch
SW4 4th switch
SW5 fifth switch
SW6 sixth switch
SW31 first current source switch
SW32 second current source switch
T1 first transistor
T2 second transistor
T3 third transistor
T4 fourth transistor
T5 fifth transistor
T6 sixth transistor
T7 seventh transistor
T8 buffer transistor

Claims (12)

In the comparator circuit including a differential amplifier for comparing the first input signal and the second input signal in the form of a differential signal to output a comparison result, and an output stage amplifier for outputting an amplified signal based on the comparison result,
The differential amplifier is:
An input differential stage including a first transistor to which the first input signal is supplied to a gate via a first capacitor, and a second transistor to which the second input signal is supplied to a gate via a second capacitor;
The third transistor is provided as a load to the input differential stage, and is connected to the third transistor via a first connecting portion and connected to the second transistor via a second connecting portion, and the third transistor is connected to each other. A load circuit including a fourth transistor to which the gate of the gate is connected, and the gates of the third transistor and the fourth transistor to be connected to the first connecting portion via a third capacitor;
A first current source connected to the first transistor and the second transistor, the current source of the input differential stage;
A first bias voltage supply unit disposed between the gates of the third transistor and the fourth transistor and the third capacitor and supplying a first bias voltage;
A third connection portion connecting the gate of the first transistor and the first connection portion; And
And a fourth connection part connecting the gate of the second transistor and the second connection part,
The output stage amplifier:
A fifth transistor through which a signal based on the comparison result is supplied to the gate via a fourth capacitor;
A second current source connected to the fifth transistor via a fifth connection portion;
A sixth connection portion connecting the gate of the fifth transistor and the fifth connection portion; And
A comparator circuit including an output unit disposed on the fifth connection unit and outputting the amplified signal.
The method according to claim 1,
The first bias voltage supply unit includes a first switch for adjusting the timing for supplying the first bias voltage,
The third connection portion includes a second switch for adjusting the timing of connecting the gate of the first transistor and the first connection portion,
The fourth connection portion includes a third switch for adjusting the timing of connecting the gate of the second transistor and the second connection portion,
And the sixth connection portion includes a fourth switch that adjusts a timing for connecting the gate of the fifth transistor and the fifth connection portion.
The method according to claim 2,
The differential amplifier is:
A second bias voltage supply unit supplying a second bias voltage to the first connection unit; And
And a fifth switch for adjusting timing of supplying the second bias voltage to the first connection.
The method according to claim 3,
The first switch is turned on before the second switch, the third switch, the fourth switch, and the fifth switch are turned on,
The fifth switch is turned on simultaneously with the second switch, the third switch and the fourth switch,
And the second switch, the third switch, and the fourth switch are turned off after the first switch and the fifth switch are turned off.
The method according to claim 2,
The differential amplifier is:
Further comprising a buffer circuit between the first capacitor and the gate of the first transistor,
The buffer circuit:
A constant current supply unit supplying a preset current;
One of the source or drain is connected to the constant current supply, the other is connected to ground, a buffer transistor to which the gate is supplied with the first input signal and the second bias voltage;
A second bias voltage supply unit supplying the second bias voltage; And
And a sixth switch for adjusting timing of supplying the second bias voltage to the gate of the buffer transistor.
The method according to claim 5,
The second switch, the third switch and the fourth switch are turned on after the first switch and the sixth switch are turned on, and the comparator circuit is turned off after the first switch and the sixth switch are turned off.
The method according to claim 2,
The first current source and the second current source each include a current source transistor, and a comparator circuit to which a third bias voltage is supplied to the gate of the current source transistor.
The method according to claim 7,
Each of the first current source and the second current source comprises a comparator circuit including a current source switch that adjusts the supply timing of the third bias voltage.
The method according to claim 8,
The current source switch is a comparator circuit that is turned off simultaneously with the first switch.
An ADC circuit comprising a plurality of the comparator circuits according to claim 1.
The ADC circuit of claim 10; And
A plurality of photoelectric conversion elements arranged on a matrix,
The ADC circuit is a semiconductor device for discrete analog signals generated by the photoelectric conversion elements.
The semiconductor device according to claim 11; And
Includes a lens for imaging the image of the subject,
The semiconductor device is a mobile device for generating and processing image data captured through the lens.

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