KR20200073264A - Silicon block quality determination method, silicon block quality determination program and silicon single crystal manufacturing method - Google Patents

Abstract

The quality determination method of a silicon block for determining the quality of a plurality of silicon blocks cut out from a silicon single crystal drawn by the Czochralski method acquires a quality evaluation result of a sample wafer cut out from each end of the plurality of silicon blocks Process (S2), process of obtaining impression performance data of the silicon single crystal (S3), and process of setting the impression management margin in each silicon block according to the quality evaluation result of each sample wafer (S6, S7) Then, a process (S8, S9) of checking the quality of each silicon block is performed by checking the acquired impression performance data against the set impression management margin.

Description

Silicon block quality determination method, silicon block quality determination program and silicon single crystal manufacturing method

The present invention relates to a method for determining the quality of a silicon block, a program for determining the quality of a silicon block, and a method for manufacturing a silicon single crystal.

In the case of manufacturing a semiconductor wafer such as a conventional silicon wafer, for example, after performing an outer peripheral grinding of an ingot of a silicon single crystal pulled up by the Czochralski method, a top and tail portion that cannot be used as a product are cut. Thereafter, a silicon single crystal ingot is cut into a plurality of silicon blocks by a cutting device such as a wire saw.

At this time, the sample wafer is cut out from the end of the silicon block, and grown-in such as resistivity, oxygen concentration, Oxidation Induced Stacking Fault ring (OSF), void (void, cavity) defect, and large dislocation loop (L/DL defect) By evaluating defects and the like, quality evaluation of the silicon block is performed.

However, in recent years, there has been a strong demand for wafers having no grown-in defects or only very low-density grown-in defects on the entire wafer surface, and accordingly, there are no grown-in defects or very low-density grown-in defects. The demand for a single crystal of silicon has become stronger.

As a method of pulling the silicon single crystal, for example, there is a method of improving the temperature distribution in the furnace of the pulling apparatus and performing pulling of the silicon single crystal while adjusting the pulling speed.

However, because the management margin of the pulling speed is very narrow, even if the crystal quality at the end of the silicon block passes, if the pulling speed fluctuates in the middle of the block, there may be a case where a grown-in defect occurs in the silicon block. There is a problem of causing defects.

Here, the defects based on the detection result of the L/DL defect among the defects are referred to as the defects of the L/DL defect and the defect based on the detection result of the void defect.

In Patent Document 1, impression data is loaded into a computer along the growth axis of an ingot of a silicon single crystal, and when the difference between the impression data and the target value becomes more than a predetermined value, the ingot of the silicon single crystal is cut at a position that is more than a predetermined position. And a technique for obtaining a silicon block free of grown-in defects.

Japanese Patent Publication 2007-99556

However, in the technique disclosed in Patent Document 1, since the difference between the impression data and the target value is managed to be a predetermined value, the quality evaluation result of the actual sample wafer does not necessarily match. Accordingly, in the next step, when the silicon block is cut and the quality is re-evaluated by excluding the silicon block determined to be defective, there is a problem that the frequency of quality check increases because it is unknown where the defect occurred.

An object of the present invention is to provide a method for determining the quality of a silicon block, a program for determining the quality of a silicon block, and a method for manufacturing a silicon single crystal capable of reducing the frequency of quality confirmation in the next step.

The method for determining the quality of a silicon block of the present invention is a quality determination method of a silicon block for determining the quality of a plurality of silicon blocks cut out from a silicon single crystal pulled by the Czochralski method, from each end of the plurality of silicon blocks. The process of acquiring the quality evaluation result of the cut sample wafer, the process of acquiring the impression performance data of the silicon single crystal, and setting the impression management margin in each silicon block according to the quality evaluation result of each sample wafer The process is characterized by performing a process of confirming the quality of each silicon block by checking and confirming the acquired impression performance data and the set impression management margin.

Here, the quality evaluation of the sample wafer refers to the quality evaluation in the Pv region, the Pv region, and the Pi region of the silicon single crystal in which there are no grown-in defects, and in the Pi region.

The impression management margin means a range of acceptable performance values for the target value of the impression, and is set according to the quality evaluation result of the sample wafer.

According to the present invention, according to the quality evaluation result of the sample wafer, the impression management margin for each silicon block is set, and the impression management margin for each silicon block is compared with the impression performance data. For this reason, impression performance data outside the impression management margin can be judged with high precision, and the frequency of quality confirmation in the next step can be reduced.

In the present invention, when a result indicating a large dislocation loop (L/DL) defect is obtained among the quality evaluation results of the sample wafer prior to the process of setting the impression management margin, a process of excluding a silicon block indicating the result is performed. It is desirable to do.

According to the present invention, if the sample wafer exhibits L/DL defects, it is highly likely that all of the silicon blocks from which the sample wafer has been cut out are L/DL defects. Can be reduced more.

In the present invention, it is preferable to perform a process of excluding a silicon block showing the result when a result indicating a void defect is obtained in the quality evaluation result of the sample wafer before the setting of the impression management margin.

According to the present invention, as in the case of L/DL defects, the frequency of quality check in the next process can be further reduced by excluding silicon blocks that are void defects.

The silicon block quality determination program of the present invention is characterized by causing the computer to execute the above-described silicon block quality determination method.

According to the present invention, automation can be promoted by running on a computer, so that the burden of the quality control process itself can be reduced.

The method for manufacturing a silicon single crystal of the present invention is based on a process of executing the above-described quality determination program of a silicon block on a computer and calculating an impression management margin at the time of pulling the silicon single crystal, and the calculated impression management margin. It is characterized by controlling the impression of the silicon single crystal.

According to the present invention, by controlling the impression of the silicon single crystal based on the impression management margin set for each silicon block, it is possible to prevent occurrence of a rejected product by preventing generation of a silicon block that fails to be quality.

1 is a schematic view showing a silicon single crystal pulling device according to an embodiment of the present invention.
2 is a flowchart showing a method for determining the quality of a silicon single crystal in the above embodiment.
3 is a schematic diagram for explaining a management margin in the above embodiment.
4 is a schematic diagram for describing a management margin in the above embodiment.
5 is a graph showing the results of quality determination in Examples.
6 is a graph showing the results of quality determination in Examples.

[1] Structure of silicon single crystal pulling device (1)

1 is a schematic diagram showing an example of the structure of a silicon single crystal pulling apparatus 1 to which a method of manufacturing a silicon single crystal 10 according to an embodiment of the present invention can be applied. The pulling device 1 is a device for pulling the silicon single crystal 10 by the Czochralski method, and includes a chamber 2 constituting the outer periphery and a crucible 3 disposed at the center of the chamber 2.

The crucible 3 is a double structure composed of a quartz crucible 3A on the inside and a graphite crucible 3B on the outside, and is fixed to the upper end of the support shaft 4 capable of rotating and elevating.

On the outer side of the crucible 3, resistance-heating heaters 5A and 5B surrounding the crucible 3 are provided, and on the outer side, an insulating material 6 is provided along the inner surface of the chamber 2.

On the upper side of the crucible 3, there is provided an impression shaft 7 such as a wire that rotates at a predetermined speed in the opposite direction or the same direction on the support shaft 4 and the same axis. A seed crystal (8) is attached to the lower end of the pulling shaft (7).

A cylindrical heat shield 12 is disposed in the chamber 2.

The heat shield 12 blocks high temperature radiant heat from the silicon melt 9 in the crucible 3 or the sidewalls of the heaters 5A, 5B or the crucible 3 with respect to the silicon single crystal 10 being grown. In the vicinity of the solid-liquid interface, which is the crystal growth interface, it suppresses the diffusion of heat to the outside and plays a role of controlling the temperature gradient in the direction of the pulling axis in the center of the single crystal and the outer circumference of the single crystal.

The heat shield 12 also has a function as a rectifying cylinder that exhausts the evaporation portion from the silicon melt 9 out of the furnace by an inert gas introduced from above the furnace.

A gas inlet 13 for introducing an inert gas such as argon gas (hereinafter referred to as Ar gas) into the chamber 2 is provided on the upper portion of the chamber 2. The lower part of the chamber 2 is provided with an exhaust port 14 which sucks and discharges gas in the chamber 2 by driving a vacuum pump (not shown).

The inert gas introduced from the gas inlet 13 into the chamber 2 descends between the silicon single crystal 10 being grown and the heat shield 12, and the lower surface of the heat shield 12 and the liquid level of the silicon melt 9 After passing through the gap therebetween, it flows toward the outside of the heat shield 12, and further toward the outside of the crucible 3, after which the outside of the crucible 3 is lowered and discharged from the exhaust port 14.

When manufacturing the silicon single crystal 10 using the pulling device 1, a solid raw material such as polycrystalline silicon filled in the crucible 3 in a state where the inside of the chamber 2 is maintained under an inert gas atmosphere under reduced pressure (heater ( 5A and 5B) are melted by heating to form a silicon melt (9). When the silicon melt 9 is formed in the crucible 3, the impression shaft 7 is lowered to immerse the seed crystal 8 in the silicon melt 9, and the crucible 3 and the impression shaft 7 are predetermined. While rotating in the direction, the pulling shaft 7 is gradually pulled up, and accordingly, the silicon single crystal 10 connected to the seed crystal 8 is grown.

[2] Crystal defects generated in the silicon single crystal 10

It is known that crystal defects (Grown-in defects) formed during crystal growth exist in the silicon single crystal 10 pulled by the Czochralski method.

Usually, the silicon single crystal 10 includes Vacancy and Interstitial Si, which are intrinsic point defects.

The saturation concentration of these intrinsic point defects is a function of temperature, and a supersaturation state of the point defects occurs as the temperature rapidly decreases during crystal growth.

The supersaturated point defect proceeds in a direction to alleviate the supersaturation state due to mass extinction, outward diffusion, and diffusion of slopes. In general, it is not possible to completely eliminate this supersaturation state, and ultimately, either the Vacancy (Baconcy, the public, or the vacant point) or the Interstitial Si (Interstitial Si, interstitial Si) dominates. Remains as point defects.

It is known that when the crystal growth rate is fast, Vacancy tends to become supersaturated, whereas when the crystal growth rate is slow, Interstitial Si tends to become supersaturated.

When the concentration of the supersaturated state becomes more than a certain level, they aggregate and form crystal defects (Grown-in defects) during crystal growth.

As a grow-in defect in the region where the vacancy is dominant (V region), an OSF nucleus or a void defect is known. When the OSF nucleus heat-treats a sample cut from the crystal at a high temperature of about 1100°C in a wet oxygen atmosphere, interstitial Si is injected from the surface, and lamination defects (SF) grow around the OSF nucleus, and this sample is This defect is observed as a lamination defect when selectively etched while swinging in a selective etching solution.

It is called OSF (Oxygen induced Stacking Fault) because stacking defects are grown by oxidation treatment.

Void defect is a void-shaped defect formed by the collection of vacancy, and it is known that an oxide film called an inner wall oxide film is formed on the inner wall. There are several names for this defect depending on how it is detected.

It is called COP (Crystal Originated Pattern Defect) when it is observed by a particle counter that irradiates a laser beam onto a wafer surface and detects reflected light, scattered light, or the like.

It is called FPD (Flow Pattern Defect) when it is observed as a flow pattern after being left for a relatively long time without shaking the sample in the selective etching solution.

When the infrared laser beam is incident from the surface of the wafer and observed by an infrared scattering tomograph that detects the scattered light, it is called LSTD (Laser Scattering Tomography Defect). Although they have different detection methods, they are all considered to be void defects.

DSOD (Direct Surface Oxide Defect) is one of the void defects. DSOD is a microscopic void defect and is present in the OSF region. Since it is a micro void defect, it cannot be observed by selective etching or the like.

The DSOD evaluation detects defects by growing an oxide film on the wafer and performing Cu decoration thereon.

On the other hand, when the interstitial Si is dominant, crystal defects in which the interstitial Si is aggregated are formed. Although the identity of this is not clear, it is considered to be a dislocation loop or the like, and a large one is observed by TEM (Transmission Electron Microscopy) as a dislocation loop cluster.

The Grown-in defect of this interstitial Si is observed as a large pit in the form of a clamshell by leaving the sample in the same etching method as FPD, i.e., without shaking the sample in a selective etching solution for a relatively long time. This is called LEP (Large Etch Pit).

These dislocation loops, dislocation loop clusters, and LEPs are collectively called L/DL (Large Dislocation Loop).

[3] How to judge the quality of silicon blocks

The method for determining the quality of the silicon block of this embodiment will be described based on the flowchart shown in FIG. 2. The quality determination program of the silicon block in this embodiment can be executed by installing a quality determination program of the silicon block on the computer.

When the silicon single crystal 10 is manufactured by the pulling device 1 (process S1), after the outer circumferential grinding of the silicon single crystal 10 is performed, it is cut into a plurality of silicon blocks 10A, 10B, 10C by wire sawing, etc. (See FIG. 4, although the case of dividing into three blocks is illustrated, four or more blocks may be used, and two or fewer blocks may be used). At that time, at the same time, the sample wafers SW1, SW2, SW3, and SW4 are cut out from both ends of the silicon blocks 10A, 10B, and 10C, and the quality evaluation for each sample wafer SW1, SW2, SW3, and SW4 is evaluated. To perform. In addition, the sample wafer SW2 is a common sample of the silicon block 10A and the silicon block 10B, and the sample wafer SW3 is a common sample of the silicon block 10B and the silicon block 10C.

When the quality evaluation is finished, the quality evaluation results of each of the sample wafers SW1, SW2, SW3, and SW4 are loaded into the computer (process S2).

In addition, manufacturing performance data at the time of raising the silicon single crystal 10 is also loaded into a computer (process S3).

The computer determines whether or not sample wafers SW1, SW2, SW3, and SW4 indicating L/DL defects or void defects are present in the quality evaluation result (process S4). The L/DL defect is judged to be L/DL defective if L/DL has occurred in any one of the sample wafers SW1, SW2, SW3, and SW4. The determination as to whether or not the void is defective is determined as a defect when there are a predetermined number of void defects detected on the sample wafers SW1, SW2, SW3, and SW4, for example, 100 or more. If there is no L/DL defect or void defect, the process proceeds to step S6.

If there are sample wafers SW1, SW2, SW3, and SW4 indicating L/DL defects or void defects, the silicon blocks 10A, 10B, 10C from which the sample wafers SW1, SW2, SW3, SW4 are cut are next. It is excluded from the silicon block to be sent to the process (process S5).

The computer calculates an impression management margin capable of obtaining a target quality from the quality evaluation result (step S6). Here, the quality of the sample wafers SW1, SW2, SW3, and SW4 changes according to the pulling speed, as shown in FIG. Specifically, when the pulling speed is high, voids, which are hollow aggregates, are generated. On the other hand, when the pulling rate is slow, interstitial silicon atoms become excessive, and L/DL, which is an aggregate of interstitial silicon, is generated.

The pulling speed in the present embodiment is a moving average of the pulling speeds, and is referred to as a moving average speed having the highest correlation with the defect distribution in the right figure of FIG. 3. For example, a temporal moving average speed in the range of 50 minutes to 200 minutes can be employed. Conversely, there is generally a temporal moving average velocity with the highest correlation within the range of 50 minutes to 200 minutes.

In this embodiment, the pulling rate is used as an index of the management margin, but is not limited thereto, and the present invention can also be applied when detecting the linear diameter of the silicon single crystal 10 and controlling it constantly. .

There are two defect-free regions, a Pv region and a Pi region, between the region where the void occurs and the region where the L/DL occurs.

The Pv region contains oxygen precipitation nuclei in an as-grown state, and oxygen precipitates are generated when two stages of heat treatment are performed at low and high temperatures (for example, 800°C and 1000°C). It is an easy area. The Pi region is a region that hardly contains precipitation nuclei in the acid in an as-grown state, and does not easily generate oxygen precipitates even after heat treatment.

In the determination of the region of the Pv region or the Pi region, since the precipitation state of the oxygen precipitate after heat treatment is evaluated, the determination result of the Pv region or the Pi region is affected by the oxygen concentration. As a result, the defect-free margins described later and the new control line will be affected by the oxygen concentration.

The defect-free region is formed by the crystal growth rate between the crystal growth rate dominated by the OSF region and the crystal growth rate dominated by the L/DL region, and the void dominant region (Pv region) and the interstitial silicon dominant region ( Pi area).

The defect-free crystals, which are impressed by the growth rate of crystals in the defect-free region, can be said to be high-quality silicon single crystals with no or very few grown-in defects such as COP or dislocation clusters. Therefore, it is important to secure the quality of the silicon single crystal by performing pulling control of the silicon single crystal by the crystal growth rate in the defect-free region.

In this embodiment, as shown in Fig. 3, the Pv region, Pi region, that is, the defects of the sample wafers SW1, SW2, SW3, and SW4 taken between the region where the void occurs and the region where the L/DL occurs Depending on the existence of the area, an impression speed margin, which will be an impression management margin, is set.

In the case of Fig. 3, the pulling speed margin to be a defect-free area is 5% of the pulling speed in the center of the defect-free area (target value of the ideal pulling speed).

Specifically, defect distribution evaluation of the sample wafers SW1, SW2, SW3, and SW4 is performed, and the pattern formed by the Pv region and the Pi region in these wafer surfaces, and the defect distribution and pulling rate shown on the left side in FIG. By checking the relationship by contrast, the margin for the impression speed of the actual defect rate upper limit (the boundary between the OSF area and the Pv area) (hereinafter referred to as the upper defect-free margin) and the lower limit of the defect area of the actual impression rate ( It is possible to grasp the margin (hereinafter referred to as a lower defect-free margin) for the pulling speed of the boundary between the Pi region and the L/DL region.

That is, when the actual pulling speed is close to the upper limit of the defect-free area (the boundary between the OSF area and the Pv area), the upper defect-free margin is set smaller and the lower defect-free margin is set larger. On the other hand, when it is close to the lower limit of the defect-free region (the boundary between the Pi region and the L/DL region), the upper defect-free margin is set large and the lower defect-free margin is set small.

For example, in the present embodiment, in the case of the sample wafer SW1 only in the Pv region, the upper defect-free margin is 0.5% with respect to the target value of the pulling speed, and the lower defect-free margin is 4.5% with respect to the target value of the pulling speed. Is set.

Similarly, for the sample wafer SW2, the upper defect-free margin is set to 2.5%, and the lower defect-free margin is set to 2.5%, and for the sample wafer SW3, the upper defect-free margin is 3% and the lower defect-free margin is It is set to 2%, and for the sample wafer SW4, the upper defect-free margin is set to 4.8%, and the lower defect-free margin is set to 0.2%.

When the sample wafers SW1, SW2, SW3, and SW4 have more than a predetermined number of voids, and when L/DL occurs, the silicon blocks 10A, 10B, and 10C generated are excluded as defective products without setting an impression management margin. .

Next, returning to FIG. 2, a new management line is set based on the impression management margin (step S7). Specifically, the upper defect defect margin and the lower defect defect margin in the actual pulling speed are grasped from the defect distribution evaluation results of the sample wafers at both ends of the silicon block. Next, the pulling speed (target value of the ideal speed) corresponding to the center of the defect-free area is grasped.

For the interior of the silicon block, a line connecting the upper limit of the defect-free areas at both ends of the silicon block is set as a new management line on the upper side, and a line connecting the lower-limit areas of the silicon block ends as the new management line on the lower side. Is set. In FIG. 4B, the new management line of the upper limit and the new management line of the lower limit are set in a straight line, but are not limited thereto.

Next, returning to FIG. 2, the computer performs verification of the impression performance data and the impression management margin (step S8).

As shown in Fig. 4(A), the management line of the conventional pulling rate is set equally in the Void-side area and the L/DL-side area with respect to the target value of the pulling rate, and this conventional management line is the pulling rate performance value. In this case, the silicon blocks 10A, 10B, and 10C were judged as defective products.

On the other hand, the new management line of the pulling speed of the present embodiment changes the management line of the pulling speed according to the evaluation results of the obtained sample wafers SW1, SW2, SW3, and SW4, as shown in Fig. 4B. I made it.

As a result, as shown in Fig. 4(B), it is determined that the silicon block 10B, which was judged as a good product in the conventional management line, has a risk of defects in the new management line of the pulling speed of this embodiment (step S9).

When it is determined that there is a risk of defect, except for the silicon block 10B, in the next step, the excluded silicon block 10B is divided into a plurality of wafers and reevaluation is performed (step S10). In addition, the silicon block 10B determined to be defective may be discarded as it is.

When it is determined that there is no defect risk, the silicon block 10B is discharged to the next process.

When the method for determining the quality of the silicon blocks 10A, 10B, and 10C by the computer is finished, the impression of the silicon single crystal 10 is controlled based on the new management line of the calculated pulling rate when the next silicon single crystal 10 is pulled. To perform.

[4] Effects and Effects of Embodiments

As described above, according to the present embodiment, a new line for managing the pulling rate is calculated according to the sample wafers SW1, SW2, SW3, and SW4 that have undergone quality evaluation. Therefore, even if the silicon block 10B, which was previously determined to be non-defective, is judged to be defective, the possibility of sending the defective silicon block 10B to the next process is reduced, and the frequency of quality check in the next process is reduced. can do.

Controlling the pulling rate Since the obviously defective silicon blocks (10A, 10B, 10C) can be discharged in advance by performing L/DL judgment and void judgment prior to the calculation of a new line, the defective product is excluded beforehand in the next step. The frequency of quality checks can be further reduced.

Since automation can be promoted by executing the method for determining the quality of a silicon block according to a series of flow charts shown in FIG. 2 as a program on a computer, the burden of the quality control process itself can be reduced.

By controlling the impression of the silicon single crystal 10 based on the new management line of the pulling rate set for each of the silicon blocks 10A, 10B, and 10C, the quality of the silicon blocks 10A, 10B, and 10C, which are to be rejected, is prevented from failing. It can reduce the occurrence of.

(Example)

Next, embodiments of the present invention will be described. In addition, the present invention is not limited to the examples.

When the discharged silicon block 10B was divided into a plurality of wafers to evaluate each wafer, results as shown in Fig. 5 were obtained.

In the case of management by a conventional management ship, quality evaluation was performed in cases where the impression performance peaks on the Void side and peaks on the L/DL side, and judgments of good and bad products are performed.

On the other hand, when managed by the new management line, the quality and defective products were judged on the wafers W1 in the A1 area and the A2 area where the impression results exceed the new management line.

In the map of the void of the wafer W1 in the A1 region, it was confirmed that a void was generated in the form of a ring around the wafer W1.

In the map of the void of the wafer W1 in the area A2, it was confirmed that the void was generated in the form of a ring around and around the center of the wafer W2.

When other portions were judged, as shown in Fig. 6, L/DL occurred in the A3 region, and Void occurred in the A4 region and the A5 region.

Table 1 shows the results of the quality evaluation of the silicon block 10B. In the case of the conventional method, it was not possible to extract the defective portion without evaluating all the qualities of the wafer taking the peak of the impression performance.

On the other hand, in the case of the embodiment, it was decided to perform only wafers in areas A1 to A5 where the impression results exceeded the new management line. Table 1 shows the results.

Funga content Sample longevity Number of defects Conventional law Void occurrence 609 18 L/DL generation 200 4 Example Void occurrence 286 18 L/DL generation 90 4

In the conventional method, quality evaluation of 809 samples was performed, and 22 defective products were found.

On the other hand, in the embodiment, quality evaluation of 376 samples was performed, and 22 defective items identical to those of the conventional method were found.

From this result, in the silicon block 10B discharged by performing the quality determination method by the new management line of the present embodiment, the number of wafers to be subjected to quality evaluation can be significantly reduced, and in the next step. It was confirmed that the frequency of quality evaluation can be reduced.

One… Impression device, 2... Chamber, 3... Crucible, 3A... Quartz crucible, 3B... Graphite crucible, 4... Support shaft, 5A… Heater, 5B… Heater, 6… Insulation, 7... Impression axis, 8… Seed crystal, 9... Silicone melt, 10... Silicon single crystal, 10A... Silicon block, 10B… Silicon block, 10C… Silicon block, 12... Heat shield, 13... Gas inlet, 14… Exhaust port, SW1… Sample wafer, SW2… Sample wafer, SW3… Sample wafer, SW4… Sample wafer, W1… wafer.

Claims (5)

A method for determining the quality of a silicon block, which determines the quality of a plurality of silicon blocks cut out from a silicon single crystal drawn by the Czochralski method,
Obtaining a quality evaluation result of the sample wafer cut out from each end of the plurality of silicon blocks;
The process of acquiring the impression performance data of the silicon single crystal,
The process of setting the impression management margin for each silicon block according to the quality evaluation result of each sample wafer,
A method of determining the quality of a silicon block, characterized in that a process of determining the quality of each silicon block is performed by checking the acquired impression performance data and the set impression management margin. In the method for determining the quality of the silicon block according to claim 1,
If a result indicating a large dislocation loop (L/DL) defect is obtained among the quality evaluation results of the sample wafer prior to the process of setting the management margin, a process of excluding a silicon block indicating the result is performed. Method for determining the quality of silicon blocks. In the method for determining the quality of the silicon block according to claim 1 or claim 2,
If a result indicating a void defect is obtained in the quality evaluation result of the sample wafer prior to the process of setting the management margin, a method of determining the quality of the silicon block is characterized in that a process of removing the silicon block indicating the result is performed. The silicon block quality determination program characterized by causing the computer to execute the method for determining the quality of the silicon block according to any one of claims 1 to 3. A step of executing a quality determination program of the silicon block according to claim 4 on a computer and setting an impression management margin at the time of pulling the silicon single crystal;
A method for manufacturing a silicon single crystal, characterized in that a process of controlling the impression of the silicon single crystal is performed based on a set impression management margin.

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