KR20200072153A - Data Driver Integrated Circuit And Display Device Including The Same And Driving Method Thereof - Google Patents

Abstract

A display device according to an embodiment of the present invention includes: a display panel including a plurality of gate lines, a plurality of data lines, and pixels arranged in an intersection region thereof; a timing controller for supplying an image data signal; and a data drive IC which converts the image data signal into a grayscale voltage according to a gamma reference voltage and outputs a data voltage to the data lines. The data drive IC includes a plurality of amplifiers which output the grayscale voltage as the data voltage, and the plurality of amplifiers have different delay times and output the data voltage according to the variation amount of the data voltages written to each gate line. Accordingly, it is possible to prevent the occurrence of ripples in the data voltage by controlling the amplifiers (AMP) outputting the data voltage to output the data voltage with a time difference.

Description

Data driver IC, display device including same, and driving method therefor{Data Driver Integrated Circuit And Display Device Including The Same And Driving Method Thereof}

The present invention relates to a data drive IC, a display device including the same, and a driving method thereof.

The active matrix type organic light emitting display device includes self-emission organic light emitting diodes (hereinafter, referred to as "light emitting devices"), and has a fast response speed, high light emission efficiency, high brightness, and a wide viewing angle.

The display device includes a panel including subpixels connected to a data line and a gate line, a gate driver, a data drive IC, and a timing controller. The timing controller supplies control signals for processing and outputting image data and image data to the data drive IC side.

The data drive IC converts digital RGB data into analog data voltage and supplies it to the display panel. The data voltage output terminal of the data drive IC is composed of a plurality of amplifiers (AMPs). A number of amplifiers AMP use an analog power voltage AVDD as a reference voltage to output an analog data voltage for image display to a panel.

However, when the data voltage between adjacent data lines in the same gate line changes abruptly, the analog power voltage AVDD may momentarily shake due to the amplifier switching current and load. The shaking of the analog power supply voltage (AVDD), that is, ripple causes an overcharge or uncharge of the data voltage, which causes a line crosstalk in which white horizontal lines are recognized on the screen. There is a problem.

An object of the present invention is to provide a data drive IC capable of preventing line crosstalk by reducing the ripple of an analog power voltage (AVDD) caused by a difference in day voltage between adjacent data lines, a display device including the same, and a driving method thereof Has to do.

In order to solve the above problems, a display device according to an exemplary embodiment of the present invention includes: a display panel including a plurality of gate lines, a plurality of data lines, and pixels arranged in a crossing area; A timing controller that supplies an image data signal; And a data drive IC that converts the image data signal to a gradation voltage according to a gamma reference voltage and outputs it as data voltages to the data lines, wherein the data drive ICs output a plurality of gradation voltages as the data voltages. It includes an amplifier of, and the plurality of amplifiers have different delay times according to the variation of the data voltages written to each gate line and output the data voltage.

The timing control unit may detect the amount of change in data voltages written to each gate line and provide it to the data drive IC.

The data drive IC includes: an analog-to-digital converter for receiving the gamma reference voltage and outputting the gradation voltage corresponding to the image data signal; A delay unit which stores the gradation voltage and outputs the gradation voltage to the amplifier according to an output selection signal; And a delay selection unit controlling an output point of time of the delay unit according to a variation amount of data voltages written to each gate line.

The delay unit may delay the output time of the gradation voltage input to at least one of an amplifier outputting R data voltage, an amplifier outputting G data voltage, and an amplifier outputting B data voltage.

The delay unit may delay the output time of at least one of an amplifier outputting the R data voltage and an amplifier outputting the G data voltage.

The delay selector may control the data voltage to be output in the order of an amplifier outputting the B data voltage, an amplifier outputting the R data voltage, and an amplifier outputting the G data voltage.

The delay unit may include a latch that stores the gradation voltage and outputs the gradation voltage to the amplifier according to an output selection signal.

The delay selection unit may control the output time of the delay unit to be delayed as the amount of variation of data voltages written to each gate line increases.

When the variation of the data voltages is included in a certain section, the timing controller may provide digital bit data set in the section to the data driver.

The delay selection unit inputs at least one of an amplifier outputting an R data voltage, an amplifier outputting a G data voltage, and an amplifier outputting a B data voltage according to the digital bit data received from the timing controller. It is possible to delay the output time of the gradation voltage.

The plurality of amplifiers may receive an analog power voltage AVDD as a reference voltage and reflect the gradation voltage to the analog power voltage to output the data voltage.

A data drive IC according to an embodiment of the present invention comprises: an analog-to-digital converter for receiving a gamma reference voltage and outputting a gradation voltage corresponding to a video data signal; A delay unit which stores the gradation voltage and outputs the gradation voltage according to an output selection signal; An amplifier that receives an analog power voltage (AVDD) as a reference voltage and reflects the gradation voltage to the analog power voltage to output the data voltage; And a delay selection unit controlling an output point of time of the delay unit according to a variation amount of data voltages written to each gate line.

The delay unit may include a latch for delaying the output time of the grayscale voltage input to at least one of an amplifier outputting R data voltage, an amplifier outputting G data voltage, and an amplifier outputting B data voltage. have.

The delay selector may control the data voltage to be output in the order of an amplifier outputting the B data voltage, an amplifier outputting the R data voltage, and an amplifier outputting the G data voltage.

A control method of a display device according to an exemplary embodiment of the present invention includes: a control method of a display device including a display panel including a plurality of gate lines, a plurality of data lines, and pixels arranged in a crossing area; Converting the image data signals corresponding to the gate lines into gradation voltages according to the gamma reference voltage; Outputting the gradation voltages at different time points according to a variation in the data voltage of the image data signals corresponding to the one gate line; And outputting the gradation voltages output at different times as data voltages to the data lines.

The step of outputting the gradation voltage at different time points may include outputting the gradation voltage so that an output time point between the amplifiers outputting the data voltage is delayed as the variation of the data voltage is larger.

In the step of outputting the gradation voltage at different times, the gradation voltage is output to output the data voltage in the order of the amplifier outputting the B data voltage, the amplifier outputting the R data voltage, and the amplifier outputting the G data voltage. It may include the steps.

The data drive IC according to the present invention, a display device including the same, and a driving method thereof, allow the amplifiers AMPs outputting the data voltage to output the data voltages with a time difference, so that the analog power supply voltage AVDD changes due to the amplifier switching current. Can be prevented. When the analog power voltage AVDD is maintained stably, the stability of the data voltage is also ensured, so that line crosstalk or quality deterioration can be prevented.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.
2 is a schematic circuit diagram of a subpixel.
3 is a diagram schematically showing a configuration of a data drive IC according to an embodiment of the present invention.
FIG. 4 is a diagram showing the configuration of the output control unit of FIG. 3.
5 is a view showing in detail a portion of a data drive IC and a panel according to an embodiment of the present invention.
6 is a graph for explaining the principle of crosstalk generation in a display device according to a comparative example.
7 is a graph for explaining the principle of crosstalk removal of a display device according to an exemplary embodiment of the present invention.
8 and 9 are simulation results of a method of driving a display device according to an exemplary embodiment of the present invention.

Advantages and features of the present specification, and a method of achieving them will be apparent with reference to embodiments described below in detail together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present specification to be complete, and common knowledge in the art to which this specification belongs It is provided to completely inform the person having the scope of the invention, and this specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present specification are exemplary, and the present specification is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. When'include','have','consist of', etc. mentioned in this specification are used, other parts may be added unless'~ only' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, if the positional relationship of the two parts is described as'~ on','~ on top','~ on the bottom','~ next to', etc.,'right' Alternatively, one or more other parts may be located between the two parts unless'direct' is used.

The first, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, the first component mentioned below may be the second component within the technical spirit of the present specification.

Throughout the specification, the same reference numerals refer to substantially the same components.

Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that a detailed description of known functions or configurations related to the present specification may unnecessarily obscure the subject matter of the present specification, the detailed description is omitted.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention. The display device according to an exemplary embodiment of the present invention may include any display device that sequentially supplies gate pulses (or scan pulses) to gate lines (or scan lines) to write digital video data to pixels by line sequential scanning. have. For example, a display device according to an embodiment of the present invention includes a liquid crystal display (LCD), an organic light emitting diode (OLED), a field emission display (FED) , Electrophoresis display (Electrophoresis, EPD) can be implemented in any one. Although the present invention mainly exemplifies that the display device is implemented as an organic light emitting diode display device in the following embodiments, it should be noted that the display device of the present invention is not limited to the organic light emitting diode display device.

Referring to FIG. 1, the display device includes an image processing unit 110, a timing control unit 120, a gate driver 130, a data drive IC 140, and a display panel 150.

The image processing unit 110 outputs a driving signal including an image data signal DATA supplied from the outside, a data enable signal DE, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal to the timing controller 120. .

The timing control unit 120 controls the operation timing of the gate timing control signal GDC and the data drive IC 140 for controlling the operation timing of the gate driving unit 130 based on the driving signal received from the image processing unit 110. A data timing control signal (DDC) is generated. The timing controller 120 outputs a gate timing control signal GDC to the gate driver 130. In addition, the timing controller 120 outputs the image data signal DATA together with the data timing control signal DDC to the data drive IC 140. The image data signal DATA may include a digital format R data signal, a G data signal, and a B data signal.

The gate driver 130 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120. The gate driver 130 may output a scan signal composed of a scan high voltage and a scan low voltage through the gate lines GL1 to GLm. The gate driver 130 is formed in the form of an integrated circuit (IC) or a gate in panel method on the display panel 150.

The data drive IC 140 samples and latches the digital format image data signal DATA in response to the data timing control signal DDC supplied from the timing control unit 120, and then the analog format grayscale based on the gamma reference voltage. Convert it to a gray scale voltage. The data drive IC 140 reflects the gradation voltage to the analog power voltage AVDD and supplies the data voltages to the data lines DL1 to DLn of the display panel 150 as data voltages. The data drive IC 140 according to an embodiment of the present invention outputs data by a predetermined delay time between the data lines DL1 to DLn according to the variation of data voltages written to the gate lines GL1 to GLm. The data voltage can be output by delay. For example, R data voltage, G data voltage, and B data voltage can be output at different timings. Here, the amount of variation of the data voltages written to each of the gate lines GL1 to GLm may be detected by the timing controller 120 and provided to the data drive IC 140.

A plurality of data lines DL1 to DLn and a plurality of gate lines GL1 to GLm cross each other on the display panel 150, and subpixels SP are arranged in a matrix form for each intersection area. The subpixels SP may include an R subpixel, a G subpixel, and a B subpixel, and may further include a W subpixel. The display panel 150 displays an image by emitting sub-pixels according to the scan signal and data voltage supplied from the data drive IC 140 and the gate driver 130.

As shown in FIG. 2, one subpixel SP includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED.

The switching transistor SW operates to switch the data voltage supplied through the first data line DL1 as the data voltage to the capacitor Cst in response to the scan signal supplied through the first gate line GL1. The driving transistor DR operates to flow driving current between the first power line EVDD and the second power line EVSS according to the data voltage stored in the capacitor Cst. The organic light emitting diode OLED operates to emit light according to the driving current formed by the driving transistor DR.

The compensation circuit CC is a circuit added in the subpixel to compensate for the threshold voltage of the driving transistor DR. The compensation circuit CC may be configured in various forms including one or more transistors.

3 is a diagram schematically showing the configuration of a data drive IC 140 according to an embodiment of the present invention.

The data drive IC 140 converts the digital format image data signal DATA supplied from the timing control unit 120 into an analog format data voltage to provide one horizontal period during which scan signals are supplied to the gate lines GL1 to GLm. Data voltage for each horizontal line is supplied to the data lines DL1 to DLn. In particular, the data drive IC 140 according to an embodiment of the present invention stores data for a predetermined delay time between each data line DL1 to DLn according to the variation of data voltages written to each gate line GL1 to GLm. The data voltage can be output by delaying the output. A plurality of data drive ICs 140 may be provided.

Referring to FIG. 3, the data drive IC 140 includes a sampling unit 210, a digital to analog converter (hereinafter referred to as DAC) 220, an output control unit 230, and an output unit 240 It includes.

The gamma unit 250 may generate gamma reference voltages VG having various voltage levels corresponding to each gray level, as many as the number of gray levels that can be expressed by the number of bits of digital video data RGB. When the data signal is an r-bit digital signal, the gradation from 0 to (2 ^r- 1) can be displayed. For example, in the case of an 8-bit digital signal, the data signal can display a total of 256 gradations from 0 to 255 gradations. Accordingly, the gamma unit 250 may generate gamma reference voltages VG of levels VG1 to VG256.

The power supply unit 260 may generate an analog power voltage AVDD.

The gamma unit 250 and the power supply unit 260 are configured to generate a gamma reference voltage (VG) and an analog power supply voltage (AVDD), and may be provided outside or embedded in the data drive IC 140.

The sampling unit 210 samples and latches the digital format image data signal DATA, aligns it with an R data signal, a G data signal, and a B data signal according to a position to be output to the display panel 150 and outputs the data.

The DAC 220 receives the gamma reference voltage VG from the gamma compensation voltage generator 123, and the R data signal, the G data signal, and the B data signal output from the sampling unit 210 correspond to the corresponding gradation value. Output as gradation voltage. The DAC 220 selects the corresponding gamma reference voltage VG among the gamma reference voltages VG1 to VG256 according to the R data signal, the G data signal, and the B data signal input in a digital format, and the R gray voltage and G gray level are selected. Voltage and B gradation voltages can be output.

The output control unit 230 controls the output timing of the gradation voltages output from the DAC 220. The output control unit 213 may control the data voltages output to adjacent data lines to be output to the display panel with a time difference. The output control unit 213 may delay one or more of the R, G, and B signals, and may adjust the delay time according to the variation of the data voltages of one gate line input for each scan period.

The output unit 240 outputs the gradation voltage applied from the output control unit 230 as a data voltage capable of driving the subpixel SP. The output unit 240 receives the analog power voltage AVDD as a reference voltage and outputs the gradation voltage input from the output control unit 230 as a data voltage. The data voltage has a different value depending on the gradation voltage with the analog power voltage AVDD being the maximum value. The data voltage is supplied to the subpixels connected to the data lines DL1 to DLn.

As described above, the data drive IC 140 according to an embodiment of the present invention may selectively delay the data voltage output from the output unit 240 using the output control unit 230.

FIG. 4 is a diagram showing the configuration of the output control unit 230 of FIG. 3 in detail, and is a diagram mainly showing components required to drive one sub-pixel SP.

The DAC 220 receives the image data signal DATA and outputs a gamma reference voltage VG corresponding to the corresponding grayscale value as a grayscale voltage. The DAC 220 may select a gamma reference voltage VG corresponding to the input image data signal DATA among the gamma reference voltages VG1 to VG256 and output the gamma reference voltage VG.

The output unit 240 includes a plurality of amplifiers AMPs connected to each of the data lines DL1 to DLn, but only one amplifier AMP is illustrated because this embodiment illustrates one sub-pixel SP. City. The amplifier AMP of the output unit 240 receives the analog power voltage AVDD as a reference voltage and outputs the gradation voltage output from the DAC 220 as a data voltage to the data line DL of the corresponding channel C. To supply.

The output control unit 230 controls the output timing of the gradation voltage output from the DAC 220. The output control unit 213 may adjust the delay time according to the variation amount of data voltages written to the gate line. To this end, the output control unit 230 includes a data detection unit 310 that detects the data voltage written to the gate line, a delay unit 330 that delays output of a signal, and a delay unit 330 according to the detection results of the data detection unit 310. It includes a delay selection unit 320 for selecting the delay time.

The data detector 310 detects a variation in data voltages written to each gate line. The data detector 310 may provide the delay selection unit 320 with a variation amount of the detected data voltage. The function of the data detection unit 310 may be performed by the timing control unit 120 or may be performed by a configuration provided inside or outside the data drive IC 140. The function of the data detection unit 310 will be described later in detail in the embodiment with reference to FIG. 5.

The delay unit 330 receives and stores the gray level voltage output from the DAC 220 and outputs the gray level voltage to the amplifier AMP of the output unit 240 when a control signal is input from the delay selection unit 320. The delay unit 330 may include a latch, and various circuits capable of storing and outputting data may be applied.

The delay selection unit 320 may apply a control signal instructing the delay unit 330 to output data according to the detection result of the data detection unit 310. The delay selection unit 320 may control the data of the delay unit 330 to be output after a preset delay time has elapsed. If a delay is not required, the gradation voltage output from the DAC 220 is an amplifier (AMP). It can be controlled to be input.

In the above embodiment, only one amplifier AMP required to supply a data voltage to one sub-pixel SP is shown, but the amplifier AMP of the output unit 240 is provided for each channel C and corresponding data The data voltage is output to the lines DL1 to DLn. Therefore, the delay unit 330 may also be provided for each amplifier AMP, and when there are multiple delay units 330, the delay selection unit 320 may apply a control signal to each delay unit 330. have. A method of controlling a plurality of delay units will be described in detail with reference to FIG. 5.

FIG. 5 is a view showing in detail a portion of the data drive IC 140 and the display panel 150 according to an exemplary embodiment of the present invention. The data line connected to the R subpixel of the display panel 150 is connected to the G subpixel. Configurations for outputting the data voltage to the data line and the data line connected to the B subpixel are shown.

The DAC 220 is provided for each data line, and receives digital data R data signals R_DATA, G data signals G_DATA, and B data signals B_DATA, respectively. The DAC 220 outputs a gradation voltage corresponding to a corresponding gradation value according to the R data signal R_DATA, the G data signal G_DATA, and the B data signal B_DATA. When the data signal is an r-bit digital signal, the gradation from 0 to (2 ^r- 1) can be displayed. For example, in the case of an 8-bit digital signal, the data signal can display a total of 256 gradations from 0 to 255 gradations. Accordingly, the DAC 220 receives the gamma reference voltage VG of the VG1 to VG256 level and outputs a gradation voltage corresponding to the corresponding bit. The DAC receiving the R data signal R_DATA outputs the gamma reference voltage VG corresponding to the number of bits of the R data signal R_DATA as the R gray voltage. The DAC receiving the G data signal G_DATA outputs the gamma reference voltage VG corresponding to the number of bits of the G data signal G_DATA as the G gradation voltage. The DAC receiving the B data signal B_DATA outputs the gamma reference voltage VG corresponding to the number of bits of the B data signal B_DATA as the B gradation voltage.

The delay unit 230 may include latches that store and output data. The delay unit 230 is provided to allow the amplifiers AMPs of the output unit 240 to output the data voltage with a time difference, and thus latches at one or more of the output lines of R, G, and B gradation voltages. ). Although the embodiment of FIG. 5 shows a case where a latch is provided in the R data line and the G data line, only one of R, G, and B lines has a latch, or R, It is also possible to provide a latch in both the G and B data lines. As shown in FIG. 5, when latches are provided only on the R data line and the G data line, the data voltage of the B data line is immediately output without delay, and the latches on the remaining R data line and the G data line are latched. By controlling the output timing of (Latch), R, G, and B data voltages can be controlled to be output at different times. In general, the B data voltage has the largest data range, and then the data range decreases in the order of R data voltage and G data voltage. When the output of the B data voltage having a large data range is delayed, it may be advantageous to delay the output of the R data voltage and the G data voltage having a relatively small data range because the data charging time may be insufficient.

The data detector 310 may detect a data variation amount of data signals of each gate line and provide the detection result to the delay selector 320 in n-bit data format. When the data fluctuation amount of the data signals of the gate line is large, the size of the data signal is rapidly changed between adjacent data lines in the corresponding gate line, which increases the possibility of ripple in the data voltage output from the amplifier. For example, when displaying data of white gradation only in a certain section on a horizontal line displaying black gradation, an amplifier switching current is used as an amplifier switching current in a section where an amplifier outputting a data signal of black gradation and an amplifier outputting a data signal of white gradation are adjacent. Causes analog power supply voltage (AVDD) ripple. The ripple of the analog power supply voltage AVDD causes a change in the data voltage output from the amplifier AMP, and as a result, line crosstalk can be generated. The amount of change in the data signal of each gate line may be calculated by the timing controller 120. Accordingly, the data detection unit 310 may be provided in the timing control unit 120 to provide the detected amount of data fluctuation to the delay selection unit 320.

The data detector 310 may output the detection result of the amount of data variation for each data line as n-bit data. For example, in the case of outputting the detection result as 2 bit data, any one of four data of 00, 01, 10, and 11 can be output. When the detection results are displayed as four data, the entire range of the data fluctuation amount is divided into four sections, and four data sets of 00, 01, 10, and 11 are assigned to each section to indicate the detection result of the data change amount. have. The function of the data detection unit 310 may be performed by the timing control unit 120 or may be performed by a configuration provided inside or outside the data drive IC 140.

The delay selector 320 may apply a data output signal to the latch so that the R gradation voltage, the G gradation voltage, and the B gradation voltage are output with a mutual time difference according to the detection result of the data detection unit 310. The larger the amount of data fluctuation between data lines, the larger the ripple when data voltage is output. Accordingly, the delay selector 320 applies a control signal so that each latch has a time difference and outputs data when the amount of data variation is greater than or equal to a reference value. Here, the size of the delay time can be controlled differently according to the amount of data variation. That is, as the amount of data fluctuation decreases, the output delay time between latches decreases, and as the amount of data fluctuation increases, the output delay time increases. When the amount of data fluctuation is less than or equal to the reference value, the gradation voltage output from the DAC 220 can be controlled to be directly input to the amplifier AMP without delay.

The output unit 240 includes a plurality of amplifiers (AMPs), and each of the amplifiers (AMPs) receives a gradation voltage applied from the output control unit 230 and outputs it as a data voltage. The data voltage output from the amplifier AMP is supplied to the corresponding data line of the display panel 150. The subpixel SP of the display panel 150 receives a scan signal from the gate driver 130 and switches to receive the data voltage output from the amplifier AMP.

The amplifier switching current occurs at the time when the data voltage is output, and the amplifier switching current may cause ripple of the data voltage. Accordingly, the present invention can prevent the ripple from occurring in the data voltage by controlling the amplifiers AMPs that output the data voltage to output the data voltage with a time difference.

6 and 7 are diagrams for explaining a line crosstalk improvement effect of a display device according to an exemplary embodiment of the present invention. FIG. 6 is a result of measuring the data voltage of the display device according to a comparative example, and FIG. It is a result of measuring the data voltage of a display device according to an embodiment of the invention.

6 illustrates a screen of a display device according to a comparative example, and illustrates a case where a horizontal strip of black color is displayed at a predetermined interval on a background of white color. Looking at the color change of each horizontal line in the scan direction of the gate line, the horizontal line of the white color continues, and in the area where the black strip is displayed, the black color is displayed on both sides of the horizontal line and the white color is displayed on the center area. do. In the following description, the region where the horizontal line of the black color starts will be referred to as A region and the region where the white color is maintained will be referred to as the B region.

In the A area, the data voltage is changed from white to black, so that the R data voltage, G data voltage, and B data voltage are changed at the same time as the graph in the A area. As a result, the amplifier switching current is generated and the load is also changed, causing an instantaneous analog power supply voltage (AVDD) variation. Specifically, as in the waveform diagrams of AVDD(A) and AVDD(V), the current value increases instantaneously and the voltage decreases instantaneously. When the analog power voltage (AVDD) fluctuates, the dip of the supply voltages of the amplifiers AMP outputting the R data voltage, the G data voltage, and the B data voltage also drops instantaneously. As a result, as in the graph of the B region, the dip of the R data voltage, the G data voltage, and the B data voltage of the B region in which the data voltage should be maintained is instantaneously dip, resulting in a luminance change. In the display device according to the comparative example, since all amplifiers AMP simultaneously output the data voltage, the dip of the data voltage is deepened. When dip occurs in the data voltage, uncharge of the sub-pixel occurs, so that the luminance appears bright, and this phenomenon is called line crosstalk.

7 illustrates a screen of a display device according to an exemplary embodiment of the present invention, and displays the same screen as the comparative example of FIG. 6.

In the display device according to the present invention, the amplifiers AMP outputting the R data voltage, the G data voltage, and the B data voltage, as shown in the graph in the A area, respectively output a data voltage with a time difference. Accordingly, the amplifier switching current and the load are reduced, such that the fluctuation range of the analog power supply voltage AVDD, such as the AVDD(A) and AVDD(V) waveform diagrams, can be reduced. As the variation width of the analog power voltage AVDD decreases, the variation of the supply voltage of the amplifiers AMPs outputting the R data voltage, the G data voltage, and the B data voltage also decreases. As a result, dip of the R data voltage, the G data voltage, and the B data voltage of the B region where the data voltage should be maintained is also reduced, such as a graph of the B region, to prevent line crosstalk.

8 and 9 are results of simulating data ripple that occurs when the general display device to which the present invention is not applied, that is, the amplifiers AMP outputting data voltages operate simultaneously. The same pattern as in Fig. 7 is displayed while the screen is set to the area B where data is retained as the measurement point, and the pattern of area A is changed from gray to gray to AVDDH ripple voltage in the measurement point area, R, G, It is the result of simulating the voltage of B pixel and the total amount of data fluctuation in the line.

FIG. 8 graphically shows the measured voltages of EVDD, AVDD, and R/B pixels when the gray level of the measurement point is gray and the gray level of the A area is on the screen. Looking at the measurement results of the A region sampled during the 4us sampling period, it can be seen that the AVDD fluctuated by 287 mV and the voltage of the R/B pixel also fluctuated as the AVDD fluctuated. Unlike the A area, the measurement point is an area in which the data voltage must be kept constant. Since the voltage of the R/B pixel fluctuates greatly, the change can be recognized even on the screen.

The change in voltage is changed as shown in the table in FIG. 9 according to the color of the region A. The table of FIG. 9 measures the ripple of AVDDH, the voltages of R, G, and B pixels and the data fluctuation amount of each gate line when A region changes to black, white, red, green, blue, cyan, magenta, and yellow. One result. As can be seen from the table of FIG. 9, when the area A is black, it can be seen that the total data fluctuation amount is the largest at 7.22 mV, and the data fluctuation amount is differently measured as the color of the area A changes.

When the amount of data fluctuation is large, it is possible to reduce the amount of data fluctuation by setting the output delay time between the amplifiers (AMPs) long. Can be prevented. Accordingly, the present invention can set the output delay time between the amplifiers AMP based on the total amount of data variation for each horizontal line.

For example, when the data fluctuation amount is 7.0V or more, after outputting the B data signal, the R data signal may be delayed by 0.5us and the G data signal may be delayed by 1us. When the data fluctuation amount is within 5.0V to 7.0V, after outputting the B data signal, the R data signal may be delayed by 0.25us, and the G data signal may be delayed by 0.5us. When the amount of data fluctuation is within 3.0V to 5.0V, the B data signal and the R data signal are simultaneously output, and only the G data signal can be delayed by 0.25us. When the amount of data fluctuation is within 1.0V to 3.0V, since the image quality is not significantly affected, the B data signal, the R data signal and the G data signal can be simultaneously output without delay.

As described above, according to the present invention, ripples can be prevented from occurring in the data voltage by controlling the amplifiers AMPs that output the data voltage to output the data voltage with a time difference.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the technical configuration of the present invention described above is in other specific forms without changing the technical spirit or essential features of the present invention by those skilled in the art to which the present invention pertains. It will be understood that it can be practiced. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive. In addition, the scope of the invention is indicated by the claims below, rather than the detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be construed as being included in the scope of the present invention.

110: image processing unit 120: timing control unit
130: scan driver 140: data drive IC
150: display panel 210: sampling unit
DAC: 220 230: Output control unit
240: output unit 330: delay unit
320: delay selector

Claims (17)

A display panel including a plurality of gate lines, a plurality of data lines, and pixels arranged in a crossing area;
A timing controller that supplies an image data signal; And
And a data drive IC that converts the image data signal to a gradation voltage according to a gamma reference voltage and outputs the data lines as a data voltage.
The data drive IC,
A display device including a plurality of amplifiers outputting the gradation voltage as the data voltages, and outputting the data voltages with a plurality of amplifiers having different delay times according to variations in data voltages written to each gate line. According to claim 1,
The timing control unit,
A display device that detects a variation in data voltages written to each gate line and provides it to the data drive IC. According to claim 2,
The data drive IC,
An analog-to-digital converter that receives the gamma reference voltage and outputs the gradation voltage corresponding to the image data signal;
A delay unit which stores the gradation voltage and outputs the gradation voltage to the amplifier according to an output selection signal; And
A delay selection unit controlling an output point of time of the delay unit according to a variation amount of data voltages written to each gate line;
Display device comprising a. According to claim 3,
The delay unit,
A display device that delays the output time of the gradation voltage input to at least one of an amplifier outputting R data voltage, an amplifier outputting G data voltage, and an amplifier outputting B data voltage. According to claim 3,
The delay unit,
A display device that delays the output time of at least one of an amplifier outputting the R data voltage and an amplifier outputting the G data voltage. According to claim 3,
The delay selector,
A display device for controlling such that the data voltage is output in the order of an amplifier outputting the B data voltage, an amplifier outputting the R data voltage, and an amplifier outputting the G data voltage. According to claim 3,
The delay unit,
And a latch that stores the gradation voltage and outputs the gradation voltage to the amplifier according to an output selection signal. According to claim 3,
The delay selector,
A display device that controls the output time of the delay unit to be delayed as the amount of variation of the data voltages written to each gate line increases. According to claim 3,
The timing control unit,
A display device that provides digital bit data set in a corresponding section when the amount of variation of the data voltages is included in a predetermined section. The method of claim 9,
The delay selector,
Output of a gradation voltage input to at least one of an amplifier outputting an R data voltage, an amplifier outputting a G data voltage, and an amplifier outputting a B data voltage according to the digital bit data received from the timing controller. A display device that delays viewpoint. According to claim 1,
The plurality of amplifiers,
A display device that receives an analog power voltage (AVDD) as a reference voltage and reflects the gradation voltage to the analog power voltage to output the data voltage. An analog-to-digital converter for receiving a gamma reference voltage and outputting a gradation voltage corresponding to the image data signal;
A delay unit which stores the gradation voltage and outputs the gradation voltage according to an output selection signal;
An amplifier that receives an analog power voltage (AVDD) as a reference voltage and reflects the gradation voltage to the analog power voltage to output the data voltage; And
A delay selection unit controlling an output point of time of the delay unit according to a variation amount of data voltages written to each gate line;
Data drive IC comprising a. The method of claim 12,
The delay unit,
A data drive IC including a latch for delaying the output time of a gradation voltage input to at least one of an amplifier outputting R data voltage, an amplifier outputting G data voltage, and an amplifier outputting B data voltage. The method of claim 12,
The delay selector,
A data drive IC that controls the data voltage to be output in the order of an amplifier outputting a B data voltage, an amplifier outputting an R data voltage, and an amplifier outputting a G data voltage. In the control method of a display device including a display panel including a plurality of gate lines and a plurality of data lines and pixels arranged in the crossing area,
Converting image data signals corresponding to one gate line into gradation voltages according to a gamma reference voltage;
Outputting the gradation voltages at different time points according to a variation in the data voltage of the image data signals corresponding to the one gate line; And
Outputting the gradation voltages output at different times as data voltages to the data lines;
Control method of a display device comprising a. The method of claim 15,
The step of outputting the gradation voltage at different times,
And outputting the gradation voltage so that an output time between amplifiers outputting the data voltage is delayed as the variation of the data voltage is larger. The method of claim 16,
The step of outputting the gradation voltage at different times,
And outputting the gradation voltage so as to output the data voltage in the order of an amplifier outputting a B data voltage, an amplifier outputting an R data voltage, and an amplifier outputting a G data voltage.

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