KR20200069896A - Appratus for detecting circuit failure - Google Patents

Abstract

According to an embodiment of the present invention, provided is a circuit fault detection apparatus, which comprises: a signal amplification unit amplifying a detection signal having a first frequency received from an interlock circuit in accordance with a predetermined ratio; a potential difference adjusting unit generating an offset voltage for the signal amplification unit and applying the offset voltage to the signal amplification unit; a reverse voltage blocking unit dropping the voltage magnitude of the amplified detection signal by a predetermined magnitude and blocking a reverse voltage applied to the signal amplification unit; and an output unit generating an output voltage by repeatedly charging and discharging charges corresponding to a frequency of the amplified detection signal in accordance with a preset time constant.

Description

Circuit fault detection device {APPRATUS FOR DETECTING CIRCUIT FAILURE}

The embodiment relates to a circuit fault detection device.

An electric vehicle is a vehicle that obtains the driving energy of the vehicle from electric energy, not from fossil fuel combustion. These electric vehicles have no exhaust gas and very little noise, so they are environmentally friendly and pollution-free. However, the electric vehicle requires a battery that is a source of energy, and the practical use of the electric vehicle is delayed due to the light weight/miniaturization of the battery and a short charging time.

Meanwhile, in order to build the infrastructure of the electric vehicle, it is necessary to install a charging station nationwide. The charging station can supply a power source to a battery that is an energy source of an electric vehicle, like a gas station used by a conventional vehicle, and recently, many charging stations have been installed together with the rapid supply of electric vehicles.

At this time, when the electric vehicle is connected to a charging station to perform charging or discharging, a charging closed loop generated during charging or discharging may be formed. Through the charging closed loop, the charging station may supply power to the electric vehicle, and may discharge the electric vehicle to the charging station.

However, in the process of charging or discharging the electric vehicle at the charging station, various failure modes such as short, short, open, short, battery, and ground (body) may be generated. Accordingly, there is a need for a method capable of detecting various failure modes of an electric vehicle.

An embodiment of the present invention is to provide a circuit failure detection device that detects a failure of an interlock circuit by detecting a frequency of a signal of an interlock circuit of an electric vehicle.

An embodiment of the present invention is to provide a circuit failure detection device for determining whether an interlock circuit has a failure and a type of failure using a signal of an interlock circuit of an electric vehicle.

The problem to be solved in the embodiment is not limited to this, and it will be said that the object or effect that can be grasped from the solution means or the embodiment of the problem described below is also included.

The circuit fault detection apparatus according to an embodiment of the present invention generates a signal amplification unit for amplifying a detection signal having a first frequency received from an interlock circuit according to a preset ratio, and generates an offset voltage for the signal amplification unit to generate the signal. The potential difference adjusting unit applied to the amplifying unit, the voltage level of the amplified detection signal is dropped by a predetermined amount, and the reverse voltage blocking unit blocking the reverse voltage applied to the signal amplifying unit, and the amplified according to a preset time constant And an output unit which generates an output voltage by repeatedly charging and discharging charges corresponding to the frequency of the detection signal.

The output voltage may be a DC voltage having different magnitudes according to the frequency of the detection signal.

When the magnitude of the output voltage is different from a preset value, a control unit determining that an error has occurred in the interlock circuit may be further included.

The signal amplification unit includes a first resistor element having a first terminal connected to the interlock circuit, a second resistor element having a first terminal connected to a second terminal of the first resistor element, and a first input terminal having the first resistor element. It may include an amplifier element connected to the second terminal of the 1 resistor, the second input terminal is connected to the potential difference adjustment unit, the output terminal is connected to the second terminal of the second resistance element.

In the amplifier element, the first input terminal may be a non-inverting terminal, and the second input terminal may be an inverting terminal.

The potential difference adjusting unit may include a third resistor element having a first terminal connected to the signal amplifying unit and a second terminal connected to a ground terminal.

The reverse voltage blocking unit may include a diode element having a first terminal connected to the signal amplifying unit and a second terminal connected to an output unit.

The output part is connected to the reverse terminal of the reverse voltage, the fourth terminal is connected to the ground terminal, the first terminal is connected to the first terminal of the fourth resistance element, the second The terminal may include a capacitor element connected to the ground terminal.

The detection signal is compared with the first reference voltage and the second reference voltage to generate a first comparison signal and a second comparison signal, and the first comparison signal and the second comparison signal are combined with a counting signal having a second frequency. In addition, it may further include an error detection unit for generating a first combined signal and a second combined signal.

The control unit may determine that the interlock circuit operates normally when the first combined signal and the second combined signal are greater than or equal to a preset value and the output voltage is equal to a preset value.

The first frequency may be a lower frequency than the second frequency.

According to an embodiment of the present invention, it is possible to detect whether the electric vehicle interlock circuit has failed.

According to an embodiment of the present invention, it is possible to improve the accuracy of the failure determination by determining whether the electric vehicle interlock circuit has failed through two processes.

According to an embodiment of the present invention, it is possible to determine the type of failure of the electric vehicle interlock circuit.

According to an embodiment of the present invention, when the frequency of the interlock circuit signal is detected, frequency monitoring can be performed even if the duty and edge of the signal are not detected.

According to an embodiment of the present invention, by simplifying the circuit configuration for frequency detection, it is robust to failure and has high detection accuracy.

Various and beneficial advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1 relates to an embodiment of an electric vehicle failure mode prevention circuit.
2 is a view showing the configuration of a circuit failure detection device and an electric vehicle according to an embodiment of the present invention.
3 is a block diagram of a circuit fault detection apparatus according to a first embodiment of the present invention.
4 is a circuit diagram of a circuit fault detection apparatus according to an embodiment of the present invention.
5 is a simulation result of the output voltage of the output unit according to an embodiment of the present invention.
6 is a configuration diagram of a circuit fault detection apparatus according to a second embodiment of the present invention.
7 is a block diagram of an error detection unit according to a second embodiment of the present invention.
8 is a circuit diagram of a circuit fault detection apparatus according to a second embodiment of the present invention.
9 is a view for explaining the output signal of the detection unit according to an embodiment of the present invention.
10 is a view showing the output signal of the detection unit according to the failure mode of the interlock circuit.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, the technical spirit of the present invention is not limited to some embodiments described, but may be implemented in various different forms, and within the technical spirit scope of the present invention, one or more of its components between embodiments may be selectively selected. It can be used by bonding and substitution.

In addition, the terms used in the embodiments of the present invention (including technical and scientific terms), unless specifically defined and described, can be generally understood by those skilled in the art to which the present invention pertains. It can be interpreted as meaning, and commonly used terms, such as predefined terms, may interpret the meaning in consideration of the contextual meaning of the related technology.

In addition, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention.

In the present specification, a singular form may also include a plural form unless specifically stated in the phrase, and is combined with A, B, and C when described as "at least one (or more than one) of A and B, C". It can contain one or more of all possible combinations.

In addition, in describing the components of the embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used.

These terms are only for distinguishing the component from other components, and the term is not limited to the nature, order, or order of the component.

And, when a component is described as being'connected','coupled' or'connected' to another component, the component is not only directly connected to, coupled to, or connected to the other component, but also to the component It may also include the case of'connected','coupled' or'connected' due to another component between the other components.

Further, when described as being formed or disposed in the "top (top) or bottom (bottom)" of each component, the top (top) or bottom (bottom) is one as well as when the two components are in direct contact with each other It also includes a case in which another component described above is formed or disposed between two components. In addition, when expressed as "up (up) or down (down)", it may include the meaning of the downward direction as well as the upward direction based on one component.

1 relates to an embodiment of an electric vehicle failure mode prevention circuit.

According to an embodiment of the present invention, in detecting an electric vehicle failure mode, a one-way loop interrupts detection method may be used.

In addition, referring to FIG. 1, the electric vehicle may further include a fuse between internal control parts (eg, ECU), so as to detect a failure by disconnecting the fuse when a failure mode occurs due to overcurrent.

However, in the case of the failure mode processing method, since a fuse is blown when a failure mode occurs, inconvenience of replacing the fuse may occur every time, and a failure mode cannot be detected when an overcurrent sufficient to blow the fuse does not flow. This can happen. In addition, even if an in-house defect of the High-Voltage Inter Lock (HVIL) module occurs, a problem in which a defect cannot be diagnosed may occur.

2 is a view showing the configuration of a circuit failure detection device and an electric vehicle according to an embodiment of the present invention.

2, when the electric vehicle 210 is connected to the charging station 220 to perform charging or discharging, various parts (inverter, motor, PDU, insulation protection device, charging) included in the electric vehicle 210 Battery), the power or voltage supplied from the charging station 220 is applied as it is. Particularly, since the components included in the electric vehicle 210 are composed of complex and various circuits, the overall operation of the electric vehicle 210 may be stopped when overvoltage or overcurrent is applied, which is dangerous.

The circuit fault detection apparatus 100 according to an embodiment of the present invention quickly detects a malfunction of the interlock circuit 10 inside the electric vehicle in order to eliminate the above risk. Specifically, the circuit fault detection apparatus 100 may determine whether the interlock circuit has failed by generating a DC voltage corresponding to the frequency of the detection signal generated from the interlock circuit, and comparing the generated DC voltage with a set value. . The circuit failure detection device 100 may be embedded in an electric vehicle, and when a failure is detected, an interlock circuit may be opened through control of the electric vehicle charging controller 211 to protect parts of the electric vehicle 210.

3 is a block diagram of a circuit fault detection apparatus according to a first embodiment of the present invention.

Referring to FIG. 3, the circuit fault detection device 100 according to the first embodiment of the present invention includes a signal amplification unit 110, a potential difference adjustment unit 120, a reverse voltage blocking unit 130 and an output unit 140. It includes, it may further include a control unit 150.

The signal amplifying unit 110 amplifies the detection signal having the first frequency received from the interlock circuit 10 according to a preset ratio.

The electric vehicle 210 may have various failure modes, such as movement of the vehicle, an abnormality of the charging station, and breakage of the internal circuit of the vehicle while connected to the charging station, in order to prevent loss of the electric vehicle caused by the failure mode. Interlock circuit 10 may be included.

At this time, the interlock circuit 10 may detect the states of various parts of the electric vehicle and generate a detection signal having a first frequency. In addition, the detection signal is composed of a PWM (Pulse Width Modulation) signal, and can be represented by modulating various states by converting a period. More specifically, the detection signal may be composed of a square wave having a first frequency of 88 Hz and a period of 50%.

The signal amplifying unit 110 may include at least one operational amplifier (Op-Amp) and a plurality of resistors to amplify the detection signal according to a preset ratio. The signal amplifying unit 110 may adjust a preset ratio through the size and arrangement of a plurality of resistance elements. The preset ratio can be changed by a person skilled in the art and can be set differently according to the size of the detection signal.

The potential difference adjusting unit 120 generates an offset voltage for the signal amplifying unit 110 and applies it to the signal amplifying unit 110.

As described above, the signal amplifying unit 110 amplifies the detection signal using at least one amplifier element. However, in the case of the amplifier element, the output does not become 0 [V] even though there is no signal being input. This is because the amplifier element is sensitive to temperature, and various components having different characteristics such as transistors and resistors are combined. The above phenomenon causes an error in the output of the amplifier element, and this error causes a larger problem as the signal size is smaller.

In order to eliminate the above phenomenon, the potential difference adjusting unit 120 applies an offset voltage to the signal amplifying unit 110 so that the output becomes 0 [V] when there is no signal input to the amplifier element included in the signal amplifying unit 110. Approve. The magnitude of the offset voltage may be set differently depending on the amplifier element of the signal amplifying unit 110.

The reverse voltage blocking unit 130 drops the voltage level of the amplified detection signal by a predetermined amount, and blocks the reverse voltage applied to the signal amplifying unit 110.

Specifically, in the case of the amplified detection signal received from the signal amplification unit 110, a voltage of an unexpected size may be generated due to noise, etc. in the driving process. By driving the voltage level of the amplified detection signal by a predetermined amount, it is possible to stabilize driving of the circuit defect detection apparatus according to the embodiment of the present invention.

In addition, the reverse voltage blocking unit 130 blocks the application of the reverse voltage generated by the output unit 140 to the signal amplifying unit 110 in the process of driving the circuit fault detection apparatus 100 according to the embodiment of the present invention. Can be.

The output unit 140 generates an output voltage by repeatedly charging and discharging charges corresponding to the frequency of the detection signal amplified according to a preset time constant.

Since the detection signal can be implemented in the form of a square wave, the amplified detection signal can also be implemented in the form of a square wave. The output unit 140 charges the electric charge according to the time constant while the pulse is generated among the amplified detection signals, and discharges the charged electric charge according to the time constant while the pulse is not generated among the amplified detection signals.

The output unit 140 repeats charge charging and discharging according to the amplified detection signal, and has a large amount of charge compared to the amount of charge discharged at the beginning of charge charge, but after a certain period of time, the charge amount and the discharge amount are the same. The output voltage of a certain size is generated.

The output voltage is a DC voltage, and may have different voltage levels depending on the frequency of the detection signal. For example, the higher the frequency of the detection signal, the higher the output voltage, and the lower the frequency of the detection signal, the lower the output voltage. This is because the higher the detection signal frequency, the more pulses the detection signal has.

The controller 150 determines an error of the interlock circuit 10 based on the output voltage.

Specifically, the controller 150 has a preset value for comparing with the output voltage, and when the magnitude of the output voltage is different from the preset value, it is determined that an error has occurred in the interlock circuit 10. The preset value may be set differently according to the interlock circuit 10. The control unit 150 may be implemented as a micro controller unit (MCU).

4 is a circuit diagram of a circuit fault detection apparatus according to an embodiment of the present invention.

First, as described above, the interlock circuit 10 may detect the states of various parts of the electric vehicle and generate a detection signal having a first frequency.

The interlock circuit 10 may include a power supply device for supplying power and four switching elements. In the interlock circuit 10, four switching elements perform a switching operation according to a predetermined order, so that if any one device connected to the circuit fails, all devices connected to the interlock circuit 10 do not operate. Can be controlled. Since the interlock circuit 10 of the electric vehicle is obvious to those skilled in the art, detailed descriptions thereof will be omitted.

Referring to FIG. 4, the device connection configuration of the signal amplifying unit 110 will be described in detail.

The signal amplifying unit 110 includes a first resistor element R1, a second resistor element R2, and an amplifier element OP1.

In the first resistor element R1, the first terminal is connected to the interlock circuit 10, and the second terminal is connected to the first terminal of the second resistor element R2.

In the second resistor element R2, the first terminal is connected to the second terminal of the first resistor element R1, and the second terminal is connected to the output terminal of the amplifier element OP1.

In the amplifier element OP1, the first input terminal is connected to the second terminal of the first resistor, the second input terminal is connected to the potential difference adjusting unit 120, and the output terminal is connected to the second terminal of the second resistor element R2. Connected. Further, the positive driving power terminal is connected to the amplifier driving power V1, and the negative driving power terminal is connected to the ground terminal.

Here, the first input terminal may be a non-inverting input terminal, and the second input terminal may be an inverting input terminal. In this case, the output voltage of the output unit 140 may be output as a DC voltage having a positive (+) potential. Conversely, the first input terminal may be an inverting input terminal, and the second input terminal may be a non-inverting input terminal. In this case, the output voltage of the output unit 140 may be output as a DC voltage having a negative potential.

Referring to the circuit driving process of the signal amplifying unit 110 with reference to FIG. 4, when the detection signal input from the interlock circuit 10 is input to the first end of the first resistor element R1, the amplifier element OP1 Is amplified at a ratio according to the resistance values of the first resistance element R1 and the second resistance element R2. At this time, the maximum value of the amplified detection signal may be limited to be less than the voltage value of the amplifier driving power supply, and the minimum value of the amplified detection signal may not be greater than 0 [v] of the ground power supply.

Referring to Figure 4 to look at in detail the device connection configuration of the potential difference adjustment unit 120.

The potential difference adjusting unit 120 includes a third resistor element R3.

The first terminal of the third resistor element R3 is connected to the signal amplifying unit 110, and more specifically, the second terminal of the amplifier element OP1. The second terminal of the third resistor element R3 is connected to the ground terminal. At this time, the resistance value of the third resistance element R3 may be the same as the value obtained by parallelly combining the resistance values of the first resistance element R1 and the second resistance element R2.

Referring to the circuit driving process of the potential difference adjusting unit 120 with reference to FIG. 4, the third provision element is formed with an offset voltage having a predetermined size as it is connected between the amplifier element OP1 and the ground terminal. At this time, the offset voltage may have a polarity opposite to the voltage applied to the parallel combined resistance of the first resistor element R1 and the second resistor element R2. The offset voltage generated through the third resistor element R3 is applied to the second input terminal of the amplifier element OP1, and the output offset voltage of the amplifier element OP1 may be canceled.

Referring to FIG. 4, the device connection configuration of the reverse voltage blocking unit 130 will be described in detail.

The reverse voltage blocking unit 130 includes a diode element D1.

In the diode device D1, the first terminal is connected to the signal amplifying unit 110, and the second terminal is connected to the output unit 140. Specifically, the first terminal of the diode element D1 is connected to the second terminal of the second resistor element R2 and the output terminal of the amplifier element OP1, and the second terminal of the diode element D1 is the fourth resistor It is connected to the first end of the element R4 and the first end of the capacitor element C1. At this time, the first terminal may be an anode terminal, and the second terminal may be a cathode terminal.

Referring to the circuit driving process of the reverse voltage blocking unit 130 with reference to FIG. 4, the first terminal of the diode element D1, that is, the anode terminal is connected to the signal amplifying unit 110, and the first element of the diode element D1 is connected. Since the second stage, that is, the cathode terminal, is connected to the output unit 140, only the current can flow from the signal amplification unit 110 to the output unit 140, and the current from the output unit 140 to the signal amplification unit 110 Cannot flow Therefore, the reverse voltage generated by the output unit 140 cannot be applied to the signal amplification unit 110.

In addition, the diode element D1 operates only when a voltage equal to or higher than its own threshold voltage is applied, and accordingly serves to drop or lower the voltage of the amplified detection signal. Therefore, the reverse voltage blocking unit 130 outputs the amplified detection signal having a safe size range through a voltage drop even if a sudden high voltage is applied due to an abnormal voltage of the detection signal or an abnormal voltage generated during amplification. ).

Referring to FIG. 4, the device connection configuration of the output unit 140 will be described in detail.

The output unit 140 includes a fourth resistor element R4 and a capacitor element C1.

In the fourth resistor element R4, the first terminal is connected to the reverse voltage blocking unit 130, and in detail, the first terminal is connected to the second terminal of the diode element D1. In addition, the second terminal of the fourth resistance element is connected to the ground terminal.

In the capacitor element C1, the first terminal is connected to the first terminal and the control unit 150 of the fourth resistor element R4, and the second terminal is connected to the ground terminal.

Looking at the circuit driving process of the output unit 140 with reference to Figure 4, the output unit 140 is implemented in a parallel connection configuration of the fourth resistor element (R4) and the capacitor element (C1), the output voltage is a capacitor element It is the same as the voltage at both ends of (C1). Therefore, the output voltage is generated according to the amount of charge charged in the capacitor element C1. The detection signal is a square wave, and accordingly, the amplified detection signal applied to the output unit 140 is also a square wave. Therefore, the capacitor element C1 performs charge charging on the pulse portion of the square wave and discharges on the zero potential portion. The rate at which charge is charged and discharged in the capacitor element C1 depends on the time constant based on the capacitor element C1. During charging and discharging, since the charging speed is faster than the discharging speed at the beginning, the magnitude of the output voltage increases, but after a certain period of time, the magnitude of the output voltage stabilizes as the charging speed and the discharging speed become the same. At this time, the level of the stabilized output voltage may vary depending on the size of the first frequency of the detection signal. This is because as the frequency increases, the number of pulses generated during the same time increases. As the frequency increases, the amount of charge charged in the capacitor element C1 increases during the same time. That is, the magnitude of the output voltage varies depending on the frequency of the detection signal.

5 is a simulation result of the output voltage of the output unit according to an embodiment of the present invention.

Figure 5 shows the magnitude of the output voltage when the frequency of the detection signal is 30Hz, 60Hz, 90Hz, 120Hz and 150Hz.

Referring to FIG. 5, it can be seen that the output voltage at all frequencies is increased and the voltage level increases while charging and discharging in a sawtooth wave form from start to stabilization. In addition, it can be seen that at the time when charging and discharging become the same, each frequency has a different voltage that is stabilized.

Specifically, a 30 Hz frequency detection signal outputs a DC voltage of 1.52 [V] as an output voltage, a 60 Hz frequency detection signal outputs a 2.20 [V] DC voltage as an output voltage, and a 90 Hz frequency detection signal is 2.80. A DC voltage of [V] is output as an output voltage, a detection signal of 120 Hz frequency outputs a DC voltage of 3.30 [V] as an output voltage, and a detection signal of 150 Hz frequency outputs a DC voltage of 3.85 [V] as an output voltage. Is outputting.

That is, it can be seen that DC voltages of different magnitudes are output as output voltages according to the magnitude of the frequency, and it can be seen that the higher the magnitude of the frequency, the higher the DC voltage of the higher magnitude is formed.

6 is a configuration diagram of a circuit fault detection apparatus according to a second embodiment of the present invention.

Referring to FIG. 6, the circuit fault detection device 100 includes a signal amplification unit 110, a potential difference adjustment unit 120, a reverse voltage blocking unit 130, an output unit 140, and a control unit 150 as shown in FIG. 3. It includes, and may further include an error detection unit 160.

The signal amplification unit 110, the potential difference adjustment unit 120, the reverse voltage blocking unit 130, and the output unit 140 are the same as those described with reference to FIG. 3 in the first embodiment, and thus detailed description will be omitted.

The error detection unit 160 detects a signal for use in determining the type of error in the interlock circuit 10. Specifically, the error detection unit 160 compares the detection signal with the first reference voltage and the second reference voltage, respectively, to generate a first comparison signal and a second comparison signal. In addition, the error detection unit 160 combines the first comparison signal and the second comparison signal with a counting signal having a second frequency to generate a first combined signal and a second combined signal.

At this time, the first frequency may be a lower frequency than the second frequency.

Then, the control unit 150 determines whether the interlock circuit 10 operates normally through the first combined signal, the second combined signal, and the output voltage.

First, the control unit 150 determines that the interlock circuit 10 operates normally when the first combined signal and the second combined signal are greater than or equal to a preset value and the output voltage of the output unit 140 is equal to a preset value. do.

Next, even if the first combined signal and the second combined signal are greater than or equal to a preset value, the control unit 150 indicates that a failure occurs in the interlock circuit 10 when the output voltage of the output unit 140 is different from the preset value. Judge.

Next, the control unit 150, if at least one of the first combined signal and the second combined signal is less than a preset value, and the output voltage of the output unit 140 is equal to the preset value, the interlock circuit 10 It is judged that a malfunction has occurred.

7 is a configuration diagram of an error detection unit according to a second embodiment of the present invention, and FIG. 8 is a circuit diagram of a circuit fault detection apparatus according to a second embodiment of the present invention.

7 and 8, the error detection unit 160 according to the second embodiment of the present invention includes an input terminal 161, a correction circuit 162, a first comparator 163, a second comparator 164, and counting. It includes a signal generator 165, a first combiner 166 and a second combiner 167.

The input terminal 161 may receive a detection signal having a first frequency from the interlock circuit 10.

The detection unit 160 and the control unit 150 are in a bad mode through a signal output as the detection signal input to the input terminal 161 passes through the correction circuit 162, the comparators 163, 164, and the combiners 166, 167. Can judge.

The correction circuit 162 may correct the voltage of the input detection signal. When the detection signal is used as it is, since the comparator 163 or 164 or the control unit 150 cannot properly measure the error for the detection signal, the correction circuit 162 of the present invention determines the voltage of the detection signal as a circuit failure. It should be corrected for easy detection.

Specifically, the correction circuit 162 of the present invention can be corrected by adding an offset voltage to the voltage of the input detection signal. In the case of a battery included in the electric vehicle in which the circuit defect detector of the present invention is installed, the battery voltage swings between 9 and 16 V, so that the detection signal can be corrected using the battery voltage. Accordingly, the correction circuit 162 of the present invention can be offset by a battery voltage or an arbitrary set voltage to correct the input detection signal with a predetermined square wave.

The correction circuit 162 of the present invention includes an operational amplifier that receives a battery voltage adjusted to a constant value according to the voltage distribution, an operational amplifier that receives an output value of the operational amplifier and a detection signal applied from the input terminal 161, and other voltages It can include a number of resistors to adjust the value and a capacitor to eliminate noise, and stabilize the circuit.

A comparator is a circuit that compares one voltage with another voltage. It receives an input voltage and compares it with a reference voltage to detect whether the input exceeds the reference voltage, and the results are mainly digital (low, high). ) It is a device that outputs as a value. In addition, the comparator of the present invention may compare the magnitude of the input voltage and the reference voltage and output one of the two.

The first comparator 163 of the present invention may compare the corrected detection signal with the first reference voltage and output a high voltage signal or a low voltage signal. In addition, the second comparator 164 of the present invention may invert the corrected detection signal, compare the inverted detection signal with the second reference voltage, and output a high voltage signal or a low voltage signal.

Specifically, the first comparator 163 and the second comparator 164 of the present invention receives the corrected detection signal and the first reference voltage to compare the operational amplifier, and generates a voltage adjusted to a constant value according to the voltage distribution. It can include multiple resistors, capacitors for charging, noise cancellation and circuit stabilization.

At this time, the first comparator 163 and the second comparator 164 respectively receive signals inverted from each other and compare them with a reference voltage. Referring to FIG. 4, the corrected detection signal input to the first comparator 163 is applied to the (+) input terminal 161 of the operational amplifier, while the corrected detection signal input to the second comparator 164 is calculated. It is applied to the (-) input terminal 161 of the amplifier. Therefore, the signals output from the first comparator 163 and the second comparator 164 have inverted values, and the output signal values can be used to effectively classify circuit faults having different failure modes. do.

In addition, the first reference voltage of the first comparator 163 of the present invention may be lower than the second reference voltage of the second comparator 164. In the present invention, since the detection signal applied to the first comparator 163 is inverted and applied to the second comparator 164, an output signal can be generated using a second reference voltage lower than the first reference voltage. .

For example, the first reference voltage of the present invention may constitute a resistor connected to the operational amplifier to have 2/3 the magnitude of the battery voltage, and the second reference voltage may be connected to the operational amplifier to have a magnitude of 1/3 of the battery voltage. Resistance can be configured.

In addition, when the corrected detection signal is higher than the first reference voltage, the first comparator 163 of the present invention may output a corrected detection signal. Further, the second comparator 164 of the present invention may output an inverted detection signal when the inverted detection signal is lower than the second reference voltage.

In addition, the comparators 163 and 164 of the present invention may output a high voltage signal (high) or a low voltage signal (low) according to + and-of the compared value when compared with the reference voltage, but higher or lower than the reference voltage In this case, the corresponding input signal may be output as it is. Accordingly, the first comparator 163 and the second comparator 164 of the present invention can output a corrected detection signal input after comparison with a reference voltage.

The counting signal generator 165 may generate a counting signal having a second frequency.

The counting signal is combined with the detection signal by a coupler described later, so that the controller detects a circuit failure through the final output signal. A circuit defect may be detected using only the detection signal, but in this case, since the output signal outputs only a high or low voltage state value, various states cannot be distinguished and judged. Therefore, the circuit defect detector of the present invention further includes a counting signal generator 165, so that it is possible to effectively detect a circuit defect through a detection signal combined with the counting signal.

At this time, the second frequency generated by the counting signal may be a higher frequency than the first frequency. For example, the second frequency of the present invention may have a frequency of about 10 kHz, and the first frequency may have 88 Hz.

The first combiner 166 may combine the output signal of the first comparator 163 and the counting signal, and the second combiner 167 may combine the output signal of the second comparator 164 and the counting signal. As described above, a final output signal having a first frequency and a second frequency may be generated by combining the signal output from the comparators 330 and 340 and the counting signal. At this time, the couplers 166 and 167 may include an AND gate element.

9 is a view for explaining the output signal of the detection unit according to an embodiment of the present invention.

9(a) and 9(b), it is possible to check the final output signal of the detection signal combined with the counting signal. Looking at the scale of the horizontal axis (time) of FIG. 9(a), the 1/0/1/0 state alternates with the second frequency of the counting signal even during a high period of the first frequency of the detection signal. You can confirm that.

The controller 150 may detect a circuit failure based on the output signal of the first coupler 166 and the output signal of the second coupler 167. Specifically, the output signal of the first coupler 166 and the output signal of the second coupler 167 are respectively detected, and the state of the corresponding output signal is checked to determine whether the circuit is defective. At this time, the output signal of the first coupler 166 is high, and the output signal of the second coupler 167 is low, thereby detecting a circuit failure.

Referring to (a) of FIG. 9, the control unit 150 includes an output signal of the first combiner 166 and an output signal of the second combiner 167 (ex> pulse count, FIG. 9(b)). When it is greater than or equal to the set value, it can be detected that the interlock circuit 10 is in a normal state. When the charging closed loop of the electric vehicle is in a normal state, the input detection signal normally appears in alternating high and low states, so that the controller 150 outputs the output signal of the first coupler 166 and the second coupler 167. It can be confirmed that the output signal normally outputs a certain abnormal value (high value), and it is possible to detect that the interlock circuit 10 is in a normal state.

Referring to (b) of FIG. 9, the controller 150 can see that the signals of higher frequencies are combined and counted to confirm that the high and low signals of FIG. 9(a) alternate.

The results of 0 to 6.3 hours in FIG. 9(a) are enlarged, and it can be seen that the high frequency signals are combined as in FIG. 9(b). The control unit 150 counts the output signal of the first combiner 166 (high side pulse of FIG. 9(b)) and counts the output signal of the second combiner (low side pulse of FIG. 9(b)). Circuit faults. By counting the number of pulses, it is possible to check whether an input signal of a normal cycle comes in.

10 is a view showing the output signal of the error detection unit according to the failure mode of the interlock circuit.

10A is a graph of an output signal of an error detection unit in an open state of an electric vehicle according to another embodiment of the present invention.

Referring to (a) of FIG. 10, when the interlock circuit 10 is in an open state, it is possible to check the output signal state of the first coupler and the output signal of the second coupler 167.

When the output signal of the first coupler 166 and the output signal of the second coupler 167 are low voltage signals, as shown in (a) of FIG. 10, the control unit 150 displays the interlock circuit 10 in an open state. It is possible to detect that the circuit is defective.

When the interlock circuit 10 is in an open state, it may mean that the detection signal applied from the interlock circuit 10 is not connected to either end of the input terminal 161.

In the open state, since no more detection signal input 400 can enter the input terminal 161 in the interlock circuit 10, the low voltage signal (0) is applied to both the first coupler 166 and the second coupler 167. Will print. Therefore, the control unit 150 of the present invention can detect that all output signals output a low voltage signal, and detect that the parts of the electric vehicle 210 are open.

10B is a graph of the output signal of the error detection unit in the battery-short state of the electric vehicle according to the embodiment of the present invention.

When the output signal of the first coupler 166 is greater than or equal to a preset value and the output signal of the second coupler 167 is a low voltage signal, the control unit 150 displays a battery-short state. It is possible to detect that the circuit is defective.

Since the interlock circuit 10 is located inside the electric vehicle, a battery-short state in which the power input node of the battery and the interlock circuit 10 are short-circuited may occur.

This means that the power input node of the battery is connected to either end of the input terminal 161. Accordingly, it can be said that among various components included in the electric vehicle 210, a defective mode in a battery-short state in which a portion detected by the circuit defect detector of the present invention is short-circuited with the battery has occurred.

Referring to FIG. 10B, when the interlock circuit 10 is in a battery-short state, it is possible to check the output signal state of the first coupler and the second combiner 167 of the present invention. In the battery-short state, a high state that is higher than a preset value is output to the first coupler 166, and a low voltage signal 0 is output from the second coupler. Accordingly, the control unit 150 of the present invention may detect that the output signals of the first coupler and the second coupler 167 are output, thereby detecting that the parts of the electric vehicle 210 are in a battery-short state.

10(c) is a graph of the output signal of the error detection unit in the ground-short state of the electric vehicle according to the embodiment of the present invention.

When the output signal of the first coupler 166 is a low voltage signal and the output signal of the second coupler 167 is greater than or equal to a preset value, the control unit 150 sets the interlock circuit 10 to a ground-short (GND-Shrot) state. It is possible to detect that the circuit is defective.

Since the interlock circuit 10 is located inside the electric vehicle, a ground-short state in which the ground and the interlock circuit are short-circuited may occur. Particularly, in the case of a vehicle, since the vehicle body itself made of metal serves as a ground, this failure mode may occur when a part of the interlock circuit 10 contacts the vehicle body.

This means that the ground is connected to either end of the input terminal 161. Therefore, it can be said that among various components included in the electric vehicle 210, a failure mode in a ground-short state in which a portion detected by the error detection unit of the present invention is shorted to the ground has occurred.

Referring to (c) of FIG. 10, when the interlock circuit 10 is in the ground-short state, it is possible to check the output signal state of the first coupler 166 and the output signal of the second coupler 167. In the ground-short state, the first combiner 166 outputs a low voltage signal 0, and the second combiner 167 outputs a predetermined value or higher. Accordingly, the controller 150 may detect that the output signals of the first coupler and the second coupler 167 are output, thereby detecting that the parts of the electric vehicle are in the ground-short state.

In addition, the control unit 150 of the present invention, if the second frequency of the output signal of the first combiner 166 or the output signal of the second combiner 167 is out of a preset range, the interlock circuit 10 It can detect that it is defective. The detection signal input to the input terminal 161 of the present invention may generate the final output signal in combination with the counting signal. In the normal state, the second frequency of the final output signal as shown in FIG. 10(b) is constant. Should be printed.

However, when an abnormality occurs in the component included in the electric vehicle 210 or the counting signal generator itself, an abnormality may occur in the second frequency. More specifically, in the high state of the first frequency, 55 high/low may alternate. However, when there is an abnormality in the component or counting signal generator, frequency abnormalities such as 40 or 100 high/low alternating currents may occur. The controller of the present invention, by detecting the second frequency, it is possible to check the failure mode of the electric vehicle 210.

In addition, the circuit defect detector of the present invention may further include an arbitrary detection signal generator. The random detection signal generator may generate an arbitrary detection signal having a first frequency, and input an arbitrary detection signal to the input terminal 161. At this time, the controller of the present invention can detect a circuit failure based on the output signal of the first combiner 166 or the second combiner 167 generated by an arbitrary detection signal.

In the case of the above-described detection signal, the circuit defect detector of the present invention is not generated, and is input from the interlock circuit. However, in another embodiment, the error detection unit of the present invention generates its own detection signal to detect a failure mode when the detection signal of the input terminal 161 is damaged. Further, by using an arbitrary detection signal without receiving a signal from the vehicle, it is possible to detect a defective mode of an efficient vehicle component.

Meanwhile, the circuit defect detector of the present invention may be used in an electric vehicle charging controller, and may also be included in an electric vehicle.

The term'~ unit' used in this embodiment means software or a hardware component such as a field-programmable gate array (FPGA) or an ASIC, and the'~ unit' performs certain roles. However,'~ wealth' is not limited to software or hardware. The'~ unit' may be configured to be in an addressable storage medium or may be configured to reproduce one or more processors. Thus, as an example,'~ unit' refers to components such as software components, object-oriented software components, class components and task components, processes, functions, attributes, and procedures. , Subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, database, data structures, tables, arrays, and variables. The functions provided within components and'~units' may be combined into a smaller number of components and'~units', or further separated into additional components and'~units'. In addition, the components and'~ unit' may be implemented to play one or more CPUs in the device or secure multimedia card.

The embodiments have been mainly described above, but this is merely an example and does not limit the present invention, and those of ordinary skill in the art to which the present invention pertains have not been exemplified above in a range that does not depart from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be implemented by modification. And differences related to these modifications and applications should be construed as being included in the scope of the invention defined in the appended claims.

100: circuit failure detection device
110: signal amplification unit
120: potential difference adjustment unit
130: reverse voltage blocking unit
140: output unit
150: control unit
160: error detection unit

Claims (11)

Signal amplification unit for amplifying the detection signal having the first frequency received from the interlock circuit according to a predetermined ratio,
A potential difference adjusting unit that generates an offset voltage for the signal amplifying unit and applies it to the signal amplifying unit,
Reverse voltage blocking unit for dropping the voltage level of the amplified detection signal by a predetermined amount, blocking the reverse voltage applied to the signal amplification unit, and
A circuit fault detection apparatus including an output unit for generating an output voltage by repeatedly charging and discharging charges corresponding to the frequency of the amplified detection signal according to a preset time constant. According to claim 1,
The output voltage,
A circuit fault detection device that is a DC voltage having different magnitudes according to the frequency of the detection signal. According to claim 1,
If the magnitude of the output voltage is different from a predetermined value, the circuit fault detection device further comprising a control unit for determining that an error has occurred in the interlock circuit. According to claim 1,
The signal amplification unit,
A first resistor element having a first terminal connected to the interlock circuit,
A second resistance element having a first end connected to a second end of the first resistance element, and
A circuit failure comprising an amplifier element having a first input terminal connected to the second terminal of the first resistor, a second input terminal connected to the potential difference adjusting unit, and an output terminal connected to the second terminal of the second resistor element Detection device. The method of claim 4,
The amplifier element,
A circuit fault detection device in which the first input terminal is a non-inverting terminal and the second input terminal is an inverting terminal. According to claim 1,
The potential difference adjustment unit,
A circuit fault detection apparatus comprising a third resistor element having a first terminal connected to the signal amplifying unit and a second terminal connected to a ground terminal. According to claim 1,
The reverse voltage blocking unit,
A circuit fault detection apparatus comprising a diode element having a first terminal connected to the signal amplifying unit and a second terminal connected to an output unit. According to claim 1,
The output unit
A fourth resistor element having a first terminal connected to the reverse voltage blocking unit and a second terminal connected to a ground terminal, and
A circuit fault detection apparatus comprising a capacitor element having a first terminal connected to a first terminal of the fourth resistor element and a second terminal connected to a ground terminal. According to claim 3,
The detection signal is compared with the first reference voltage and the second reference voltage to generate a first comparison signal and a second comparison signal, and the first comparison signal and the second comparison signal are combined with a counting signal having a second frequency. The circuit fault detection device further comprises an error detector for generating a first combined signal and a second combined signal. The method of claim 9,
The control unit,
The first combined signal and the second combined signal are greater than or equal to a preset value,
When the output voltage is equal to a preset value, the circuit fault detection device determines that the interlock circuit is operating normally. The method of claim 9,
The first frequency is a circuit fault detection device having a lower frequency than the second frequency.

Images