KR20200066435A - Vertical pin diodes with improving breakdown voltage and manufacturing method for the same - Google Patents

Abstract

The present invention relates to a GaN-based photodiode capable of suppressing an electric field of a mesa gradient while maximizing electric field intensity inside an active region. As an avalanche photodiode for detecting ultraviolet light, the photo diode comprises: a GaN-based substrate doped with a first dopant; a GaN-based intrinsic layer doped with the same dopant as the substrate and disposed on an upper part of the substrate; a GaN-based low concentration layer doped with a second dopant and disposed on an upper part of the intrinsic layer; a GaN-based high concentration layer doped with a second dopant, disposed on an upper part of the low concentration layer, and having a higher doping concentration than the low concentration layer; and a pair of electrodes providing ohmic contact and including a first electrode disposed on a lower part of the substrate and a second electrode disposed on an upper part of the high concentration layer, wherein a first mesa isolation surface is formed from a portion of the substrate to the low concentration layer, and a second mesa isolation surface is formed on the high concentration layer to expose a part of a surface of the low concentration layer. In the present invention, the high concentration layer is additionally mesa-isolated to expose a part of the surface of the low concentration layer, and thus, a remarkable voltage drop effect occurs outside the active region to suppress the electric field at the mesa isolation surface, thereby increasing gains with an increased breakdown voltage and a higher electric field inside the active region.

Description

Vertical PIN diode with improved breakdown voltage and its manufacturing method{VERTICAL PIN DIODES WITH IMPROVING BREAKDOWN VOLTAGE AND MANUFACTURING METHOD FOR THE SAME}

The present invention relates to a structure for improving breakdown voltage of a vertical PIN diode, and more particularly, to a structure for improving breakdown voltage in a wide energy bandgap semiconductor-based avalanche photodiode.

In general, avalanche photodiodes (APDs) are high-speed, high-sensitivity photodiodes that use an internal gain mechanism that functions by applying a reverse voltage. Compared to PN or PIN photodiodes, APD can measure even low-level light and can be used in a variety of different applications requiring high sensitivity. Silicon can be used for APD due to the high gain bandwidth product and the high ionization coefficient ratio resulting in very low excess noise. However, in the case of silicon, the range of wavelengths that can be detected is limited because the energy band gap is low, so the detection efficiency in the short-wavelength ultraviolet region is not high, the dark current is high, and high-temperature operation is impossible.

Suitable materials for detecting ultraviolet rays are semiconductors with a wide energy bandgap, including gallium nitride (GaN), silicon carbide (SiC), gallium oxide (Ga2O3), and manganese oxide (ZnO), due to their very low intrinsic carrier concentration. Low dark current and high temperature operation are possible. In particular, gallium nitride (GaN) has a wide energy band gap of 3.45 eV and a very low intrinsic carrier concentration of 1.9×10 ^-10 cm ^-3 at 300K, and the energy band gap is adjusted by adjusting the Al _x Ga _1-x N composition. Because of this, GaN-based UV detectors have small size, high signal-to-noise ratio, and excellent temperature stability.

GaN APD is made of a PIN structure, and it is common to apply an inclined mesa structure to the side for reasons such as device separation, and it is preferable that the angle of the inclined surface is small to suppress a high electric field at the side wall of the junction.

Republic of Korea Patent Publication 10-2004-0050865

The present invention is to solve the problems of the prior art described above and has an object to provide a GaN-based vertical PIN diode capable of suppressing the electric field of the mesa inclined surface while maximizing the electric field strength inside the active region.

The vertical PIN diode according to the present invention for achieving the above object, a substrate of a GaN-based material doped with a first dopant; An intrinsic layer of GaN-based material doped with the same dopant as the substrate and disposed on the substrate; A low concentration layer of GaN-based material doped with a second dopant and disposed on the intrinsic layer; A high concentration layer made of a GaN-based material doped with a second dopant, disposed above the low concentration layer, and having a higher doping concentration than the low concentration layer; And a pair of electrodes that provide ohmic contact and include a first electrode disposed under the substrate and a second electrode disposed over the high concentration layer, wherein the first mesa from a portion of the substrate to the low concentration layer is provided. A separation surface is formed, and a second mesa separation surface is formed on the high concentration layer so that the surface of the low concentration layer is partially exposed.

At this time, the effect of suppressing the electric field on the inclined surface is improved by the two-step configuration, and the same effect can be obtained even if the inclined surface angle of the first mesa separation surface is made larger than before, and the inclination angle of the first mesa separation surface is 4 to 15 ° range. In addition, the angle of the inclined surface of the second mesa separation surface added in the present invention does not significantly affect characteristics, and the inclination angle of the second mesa separation surface may be in the range of 4 to 80°.

In addition, the doping concentration of the high concentration layer is 10 times higher than the doping concentration of the low concentration layer, and the doping concentration of the low concentration layer is doped in the intrinsic layer so that the low concentration layer exposed by the second mesa separation surface has a sufficient voltage drop. It is higher than the concentration by 10 times or more, and the thickness of the exposed portion of the surface in the low concentration layer is preferably 50 nm or more.

According to another aspect of the present invention, a method of manufacturing a vertical PIN diode includes: a substrate preparation step of preparing a substrate of a GaN-based material doped with a first dopant; An intrinsic layer forming step of forming an intrinsic layer of GaN-based material doped with the same dopant as the substrate on top of the substrate; A low concentration layer forming step of forming a low concentration layer of GaN-based material doped with a second dopant on top of the intrinsic layer; A high concentration layer forming step of forming a high concentration layer of a GaN-based material doped with a second dopant and having a higher doping concentration than the low concentration layer on top of the low concentration layer; Forming a first mesa separation surface to form a first mesa separation surface by mesa separation from a portion of the substrate to the high concentration layer; And forming a second mesa separation surface to form a second mesa separation surface by performing mesa separation on the high concentration layer so that a portion of the low concentration layer is exposed.

According to another aspect of the present invention, a method of manufacturing a vertical PIN diode includes: a substrate preparation step of preparing a substrate of a GaN-based material doped with a first dopant; An intrinsic layer forming step of forming an intrinsic layer of GaN-based material doped with the same dopant as the substrate on top of the substrate; Forming a low concentration layer of a GaN-based material doped with a second dopant on the intrinsic layer; A high-concentration layer forming step of forming a high-concentration layer of a GaN-based material doped with a second dopant and having a higher doping concentration than the low-concentration layer; Forming a second mesa separation surface to form a second mesa separation surface by performing mesa separation on the high concentration layer so that a portion of the low concentration layer is exposed; And forming a first mesa separation surface to form a first mesa separation surface by mesa separation from a portion of the substrate to the low concentration layer.

In the step of forming the first mesa separation surface, the first mesa separation surface is to be an inclined inclined surface, but the inclination angle may be in the range of 4 to 15°, and the same effect can be obtained even if the angle is made larger than in the prior art.

The method further includes forming a first electrode to form a first electrode on a lower portion of the substrate, and further comprising forming a second electrode to form a second electrode on a high concentration layer. The process of can be applied.

The doped concentration of the high-concentration layer is formed to be 10 times higher than the doping concentration of the low-concentration layer, and the doping concentration of the low-concentration layer is intrinsic, so that the low-concentration layer exposed by the second mesa separation surface can have sufficient voltage drop It is formed so as to be 10 times higher than the doping concentration of, it is preferable that the thickness of the portion of the surface exposed in the low concentration layer is 50 nm or more.

In the present invention configured as described above, a significant voltage drop effect can be obtained outside the active region by additionally mesa separating the high concentration layer so that a part of the surface of the low concentration layer is exposed.

In addition, because the electric field at the mesa separation surface is suppressed by a voltage drop outside the active region, a higher voltage can be applied, so that the breakdown voltage is higher.

Finally, the higher the breakdown voltage, the higher the electric field may be applied inside the active region under the avalanche bias condition, thereby improving the gain of the GaN-based avalanche photodiode.

1 is a schematic view for explaining a cross-sectional structure of a vertical PIN diode according to an embodiment of the present invention.
2 is a schematic view for explaining the cross-sectional structure of a vertical PIN diode according to a comparative example.
Figure 3 is a result showing the yield characteristics of the vertical PIN diode according to an embodiment and a comparative example of the present invention.
4 is a view showing a potential and an electric field distribution in a yield condition for a vertical PIN diode according to an embodiment and a comparative example of the present invention.
5 is a graph comparing the electric field distribution in the PN junction for the vertical PIN diode according to the embodiment of the present invention and a comparative example.
6 is a result of simulating dark current characteristics, photocurrent characteristics, and gain characteristics for a vertical PIN diode according to an embodiment of the present invention.
7 is a result of simulating dark current characteristics, photocurrent characteristics, and gain characteristics for a vertical PIN diode according to a comparative example.
8 is a result of simulating quantum efficiency characteristics for a vertical PIN diode according to an embodiment and a comparative example of the present invention.

An embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

However, the embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited only to the embodiments described below. The shape and size of elements in the drawings may be exaggerated for clarity, and elements indicated by the same reference numerals in the drawings are the same elements.

And throughout the specification, when a part is said to be "connected" to another part, this includes not only "directly connected" but also "electrically connected" with other elements in between. In addition, when a part is said to "include" or "equipment" a component, this means that other components may be further included or provided, rather than excluding other components unless otherwise specified. do.

In addition, terms such as “first” and “second” are for distinguishing one component from other components, and the scope of rights should not be limited by these terms. For example, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

1 is a schematic view for explaining a cross-sectional structure of a vertical PIN diode according to an embodiment of the present invention.

The vertical PIN diode of the present embodiment is a GaN-based avalanche photodiode, in which the substrate 100, the intrinsic layer 200, the low-concentration layer 300, and the high-concentration layer 400 are sequentially stacked on the substrate 100. A first electrode (not shown) that is in contact with the anode and a second electrode (not shown) that is in contact with the high concentration layer 400 are formed in a pair, and the mesa separated from a part of the substrate 100 to the low concentration layer 300 A second mesa separation surface 600 is formed in which the high concentration layer is mesa separated so that a portion of the surfaces of the 1 mesa separation surface 500 and the low concentration layer 300 are exposed.

The substrate 100 is made of a GaN-based material doped with an N-type dopant for the PIN structure.

The intrinsic layer 200 is made of a GaN-based material exhibiting intrinsic properties by doping a small amount of an N-type dopant such as the substrate 100.

The low concentration layer 300 is made of a GaN-based material doped with a P-type dopant different from the substrate 100.

The high-concentration layer 400 is doped with a P-type dopant, such as the low-concentration layer 300, and is made of a GaN-based material doped at a higher concentration than the low-concentration layer 300.

The first mesa separating surface 500 is a surface formed by mesa separating from a part of the substrate 100 to the low concentration layer 300, and as in the general mesa separating, a predetermined field to suppress the electric field in the side wall of the junction Construct an inclined slope at an angle.

The second mesa separation surface 600 is a structure specially applied in the present invention, unlike the conventional GaN-based avalanche photodiode, by separately mesa separating only the high concentration layer 400 so that the surface of the low concentration layer 300 is partially exposed. It is formed, and is composed of an inclined surface inclined at a predetermined angle.

The second mesa separation surface 600 of this embodiment, compared to the conventional GaN-based avalanche photodiode shown in Figure 2, the mesa separation surface 700 was formed as a single layer up to a high concentration layer, the substrate 100 ), it can be seen that the two-layer mesa separation structure including the first stage from the low concentration layer 300 and the second stage separately formed in the high concentration layer 400 is applied.

The GaN-based avalanche photodiode according to the present embodiment shown in FIG. 1 and the GaN-based avalanche photodiode of the comparative example shown in FIG. 2 were prepared.

The doping concentration and thickness of each layer are as shown in Table 1, and the inclination angle of the mesa separation surface was formed at 10°.

Doping concentration (cm ^-3 ) Thickness (㎛) High concentration layer 1×10 ¹⁹ 0.15 Low concentration layer 5×10 ¹⁷ 0.15 True layer 1×10 ¹⁶ 1.3 Board 1×10 ¹⁸ 1.4

A simulation experiment was performed on the fabricated GaN avalanche photodiode.

Figure 3 is a result showing the yield characteristics of the GaN-based avalanche photodiode according to the Examples and Comparative Examples of the present invention.

As a result of confirming the breakdown voltage by simulation, the GaN-based avalanche photodiode according to this example was evaluated to be 495V and the GaN-based avalanche photodiode of the comparative example was 436V. It can be seen that the breakdown voltage 495V confirmed in the GaN-based avalanche photodiode of this embodiment is almost the same as the value for the GaN-based avalanche photodiode in an ideal structure.

4 is a view showing the electric potential and electric field distribution in the yield condition, and FIG. 5 is a graph comparing the electric field distribution in the PN junction.

As a result of confirming the two-dimensional potential and electric field distribution under the breakdown voltage condition, it can be seen that the electric field strength (~ 3.5 MV/cm) in the breakdown voltage condition is the same in both the Examples and Comparative Examples. Consequently, it can be confirmed that the breakdown voltage is determined by the peak electric field strength at the PN junction.

On the other hand, according to the electric field distribution in the aa' cross-section (PN junction cross-section) of FIG. 4 shown in FIG. 5, it can be confirmed that the electric field strength in the active region is significantly different in Examples and Comparative Examples. Under breakdown voltage conditions, the GaN-based avalanche photodiode of the comparative example exhibited an electric field strength of ~2.2 MV/cm inside the active region, while the GaN-based avalanche photodiode of the example showed an electric field strength of -2.6 MV/cm.

According to the dislocation distribution for the GaN-based avalanche photodiode of this embodiment shown on the right side of FIG. 4, a portion of the high concentration layer doped at a high concentration at the edge of the active region is formed to form a second mesa separation surface having a two-layer structure. By removing, a voltage drop of about 315 V occurred along the low concentration layer where the surface was exposed. The voltage drop is determined by the resistance value of the low-concentration layer exposed on the surface, and has a concentration of at least 10 times lower than the doping of the upper high-concentration layer and a concentration of at least 10 times higher than the doping of the lower intrinsic layer for sufficient voltage drop. It is preferred to have. At this time, the voltage drop is determined according to the length of the surface of the low-concentration layer exposed by the second mesa separation surface, and the position of the second mesa separation surface is defined to expose the length as necessary in the design process. In addition, in the process of forming the second mesa separation surface, the surface of the low-concentration layer 300 may be shaved, so that the thickness may be reduced, and the thickness of the remaining low-concentration layer should be at least 50 nm. Therefore, by applying the two-layer mesa separation structure as in the present embodiment, the electric field at the sidewall of the PN junction interface can be alleviated, and eventually a higher voltage can be applied until breakage occurs. That is, in the structure of the GaN-based avalanche photodiode of this embodiment, the electric field strength inside the active region may be higher than the electric field strength under the yield condition for a typical single mesa structure.

6 is a result of simulating dark current characteristics and photocurrent characteristics and gain characteristics for a GaN-based avalanche photodiode according to an embodiment of the present invention, and FIG. 7 is a dark current characteristic for a GaN-based avalanche photodiode according to a comparative example. It is a result of simulating photocurrent characteristics and gain characteristics.

1 and 2, assuming that incident photons having a wavelength of 340 nm were absorbed only in the active region, dark current characteristics, photo current characteristics, and gain characteristics were simulated. .

In the low bias region, the GaN-based avalanche photodiode of Examples and Comparative Examples showed similar characteristics, but it was confirmed that a significantly higher gain was achieved in the GaN-based avalanche photodiode of this example near the breakdown voltage.

In a conventional structure such as the comparative example, a sufficient multiplication process cannot be generated because the electric field inside the active region is relatively low, which limits the APD gain. On the other hand, the GaN-based avalanche photodiode of the present embodiment can achieve much higher gain because the electric field inside the active region is sufficiently high, as described above. Consequently, the mesa-separated structure of the second layer of this embodiment can effectively suppress the electric field at the sidewalls, thereby allowing a higher electric field strength to be formed in the active region under avalanche conditions, and a higher electric field in the active region. Leads to higher impact ionization coefficients and higher APD gain characteristics.

8 is a result of simulating quantum efficiency characteristics for a GaN-based avalanche photodiode according to Examples and Comparative Examples of the present invention.

As a result of simulating the quantum efficiency characteristics at the unity gain state of 5 V, there is no difference in the quantum efficiency characteristics in the two structures because the avalanche process is not generated under the unity gain condition.

The method of manufacturing a GaN-based avalanche photodiode of the present invention shown in FIG. 1 is conventional in that the substrate 100, the intrinsic layer 200, the low-concentration layer 300, and the high-concentration layer 400 are sequentially stacked. It is the same as the general method of manufacturing a GaN-based avalanche photodiode, and various methods can be applied without detracting from the features of the present invention.

However, the conventional method of manufacturing a general GaN avalanche photodiode differs in the mesa separation process from performing only one mesa separation to form only the mesa separation surface 700 corresponding to the first mesa separation surface 500. have. The method of manufacturing a GaN-based avalanche photodiode of the present invention is performed by dividing a step of forming a first mesa separation surface and a step of forming a second mesa separation surface to form a first mesa formed from a part of the substrate to a low concentration layer. The second mesa separation surface 600 formed on the high concentration layer is formed so that the surface of the separation surface 500 and the low concentration layer are partially exposed.

At this time, it is possible to form a first mesa separation surface by mesa separation from a portion of the substrate to the high concentration layer, and then additionally perform mesa separation for the high concentration layer to form a second mesa separation surface.

Alternatively, first mesa separation may be performed on a high concentration layer to form a second mesa separation surface, followed by mesa separation from a portion of the substrate to a low concentration layer to form a first mesa separation surface.

Electrodes must be formed on the lower surface of the substrate and the upper surface of the high-concentration layer, and the order and method of forming the electrodes are not particularly limited, and a detailed description thereof will be omitted since all conventional methods can be applied.

The GaN avalanche photodiode has been described above, but the breakdown voltage improvement by the mesa separation structure of the two layers may be applied to the vertical PIN diode for other purposes.

The present invention has been described through preferred embodiments, but the above-described embodiments are merely illustrative of the technical idea of the present invention, and various changes are possible within the scope of the present invention. Anyone with ordinary knowledge will understand. Therefore, the protection scope of the present invention should be interpreted by the matters described in the claims, not by specific embodiments, and all technical ideas within the equivalent range should be interpreted as being included in the scope of the present invention.

100: substrate
200: true layer
300: low concentration layer
400: high concentration layer
500: first mesa separation surface
600: second mesa separation surface

Claims (19)

A GaN-based substrate doped with a first dopant;
An intrinsic layer of GaN-based material doped with the same dopant as the substrate and disposed on the substrate;
A low concentration layer of GaN-based material doped with a second dopant and disposed on the intrinsic layer;
A high concentration layer made of a GaN-based material doped with a second dopant, disposed above the low concentration layer, and having a higher doping concentration than the low concentration layer; And
It provides a ohmic contact and includes a pair of electrodes including a first electrode disposed on the lower portion of the substrate and a second electrode disposed on the high concentration layer,
A first mesa separation surface is formed from a portion of the substrate to the low concentration layer,
A vertical PIN diode characterized in that a second mesa separation surface is formed on the high concentration layer so that the surface of the low concentration layer is partially exposed.
The method according to claim 1,
Vertical PIN diode, characterized in that the first mesa separation surface is an inclined surface inclined at a predetermined angle.
The method according to claim 2,
Vertical PIN diode, characterized in that the inclination angle of the first mesa separation surface is in the range of 4 ~ 15 °.
The method according to claim 1,
Vertical PIN diode characterized in that the second mesa separation surface is an inclined surface inclined at a predetermined angle.
The method according to claim 4,
Vertical PIN diode characterized in that the inclination angle of the second mesa separation surface is in the range of 4 ~ 80 °.
The method according to claim 1,
The vertical PIN diode characterized in that the doping concentration of the high concentration layer is 10 times higher than the doping concentration of the low concentration layer.
The method according to claim 1,
The vertical PIN diode characterized in that the doping concentration of the low concentration layer is 10 times higher than the doping concentration of the intrinsic layer.
The method according to claim 1,
Vertical PIN diode, characterized in that the thickness of the portion of the surface exposed in the low concentration layer is 50nm or more.
A substrate preparation step of preparing a GaN-based substrate doped with a first dopant;
An intrinsic layer forming step of forming an intrinsic layer of GaN-based material doped with the same dopant as the substrate on top of the substrate;
Forming a low concentration layer of a GaN-based material doped with a second dopant on the intrinsic layer;
A high-concentration layer forming step of forming a high-concentration layer of a GaN-based material doped with a second dopant and having a higher doping concentration than the low-concentration layer;
Forming a first mesa separation surface to form a first mesa separation surface by mesa separation from a portion of the substrate to the high concentration layer; And
And a second mesa separation surface forming step of forming a second mesa separation surface by performing mesa separation on the high concentration layer so that a portion of the low concentration layer is exposed.
A substrate preparation step of preparing a GaN-based substrate doped with a first dopant;
An intrinsic layer forming step of forming an intrinsic layer of GaN-based material doped with the same dopant as the substrate on top of the substrate;
Forming a low concentration layer of a GaN-based material doped with a second dopant on the intrinsic layer;
A high-concentration layer forming step of forming a high-concentration layer of a GaN-based material doped with a second dopant and having a higher doping concentration than the low-concentration layer;
Forming a second mesa separation surface to form a second mesa separation surface by performing mesa separation on the high concentration layer so that a portion of the low concentration layer is exposed; And
And forming a first mesa separation surface to form a first mesa separation surface by mesa separation from a portion of the substrate to the low concentration layer.
The method according to claim 9 or claim 10,
In the step of forming the first mesa separation surface, a method of manufacturing a vertical PIN diode, characterized in that the first mesa separation surface to be an inclined inclined surface.
The method according to claim 11,
Method of manufacturing a vertical PIN diode characterized in that the inclination angle of the first mesa separation surface is in the range of 4 ~ 15 °.
The method according to claim 9 or claim 10,
In the step of forming the second mesa separation surface, the method of manufacturing a vertical PIN diode, characterized in that the second mesa separation surface to be an inclined inclined surface.
The method according to claim 13,
Method of manufacturing a vertical PIN diode, characterized in that the inclination angle of the second mesa separation surface is in the range of 4 ~ 80 °.
The method according to claim 9 or claim 10,
And forming a first electrode under the substrate, further comprising forming a first electrode.
The method according to claim 9 or claim 10,
A method of manufacturing a vertical PIN diode, further comprising a second electrode forming step of forming a second electrode on the high concentration layer.
The method according to claim 9 or claim 10,
In the step of forming the high concentration layer, a method of manufacturing a vertical PIN diode, characterized in that the doping concentration of the high concentration layer is 10 times higher than the doping concentration of the low concentration layer.
The method according to claim 9 or claim 10,
In the step of forming the low-concentration layer, a method of manufacturing a vertical PIN diode characterized in that the doping concentration of the low-concentration layer is 10 times higher than the doping concentration of the intrinsic layer.
The method according to claim 9 or claim 10,
In the step of forming the second mesa separation surface, the method of manufacturing a vertical PIN diode, characterized in that the thickness of the portion of the surface exposed in the low concentration layer is 50 nm or more.

Images