KR20200059636A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present technology may comprise a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an etch stop pattern disposed on a stacked body; an insulation film extending to cover an upper surface of the etch stop pattern and a sidewall of the etch stop pattern, and having a sidewall formed with a depression; and contact plugs penetrating the insulation film. According to the present invention, the etch stop pattern can be protected by vertical parts, thereby improving stability of processes.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF}

The present invention relates to a semiconductor device and its manufacturing method, and more particularly, to a three-dimensional semiconductor device and its manufacturing method.

The semiconductor device may include a memory cell array including a plurality of memory cells. The memory cell array may include memory cells arranged in various structures. To improve the degree of integration of semiconductor devices, three-dimensional semiconductor devices have been proposed. During manufacturing of a 3D semiconductor device, process failure may occur due to various reasons. Process defects degrade operation reliability of a semiconductor device or cause an operation failure of a semiconductor device, and thus a method for improving a process defect of a 3D semiconductor device is required.

Embodiments of the present invention provide a semiconductor device and a method of manufacturing the semiconductor device that can improve operational reliability.

A semiconductor device according to an embodiment of the present invention includes an etch stop pattern; A gate stack including interlayer insulating films and conductive patterns alternately stacked under the etch stop pattern; Channel structures penetrating the etch stop pattern and the gate stack; An insulating film extending to cover the upper surface of the etch stop pattern and sidewalls of the etch stop pattern, and having a side wall formed with depressions; And contact plugs penetrating the insulating layer so as to be connected to the channel structures, respectively.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a stack including alternately stacked first material films and second material films; Forming an etch stop film on the laminate; Forming an insulating film including vertical portions penetrating the etch stop film; Forming a slit extending through the etch stop layer between the adjacent vertical portions and extending through the stack; And replacing the second material layers with line patterns through the slits.

The present technology can perform a manufacturing process of a semiconductor device so that the insulating film disposed on the etch stop film may include vertical portions penetrating the etch stop film. The vertical portions of the insulating film may protect the etch stop film during the manufacturing process of the semiconductor device, and recesses may be formed on the sidewalls of the insulating film by the vertical parts of the insulating film.

The etch stop film, which is protected by the vertical portions and remains, may increase the stability of the process even if a misalignment occurs while forming a contact plug penetrating the insulating film. Accordingly, the present technology can reduce process defects and improve operational reliability of the semiconductor device.

1A and 1B are block diagrams schematically illustrating semiconductor devices according to embodiments of the present invention.
2 is a cross-sectional view schematically showing a peripheral circuit structure.
3A to 3E are perspective views schematically illustrating semiconductor devices according to embodiments of the present invention.
FIG. 4 is an enlarged view of the area X shown in FIG. 3C.
5A and 5B show various cross-sections of a semiconductor device according to an embodiment of the present invention.
6 is a plan view showing a layout of vertical portions and etch stop patterns of an upper insulating film according to an embodiment of the present invention.
7 is an enlarged cross-sectional view of the Y region shown in FIGS. 5A and 5B, respectively.
8, 9A, 9B, 10A, 10B, 11A to 11C, 12A, and 12B are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
13 is a block diagram showing the configuration of a memory system according to an embodiment of the present invention.
14 is a block diagram showing the configuration of a computing system according to an embodiment of the present invention.

The technical idea of the present invention can be made of various modifications and embodiments that can have various aspects. Hereinafter, the technical idea of the present invention will be described through some embodiments so that those skilled in the art to which the present invention pertains can easily practice it.

In the exemplary embodiment of the present invention, terms such as first and / or second may be used to describe various components, but the components should not be limited by the terms. The above terms are only for the purpose of distinguishing one component from another component, for example, without departing from the scope of rights according to the concept of the present invention, the first component may be referred to as the second component, and similarly The second component may also be referred to as the first component.

When an element is said to be "connected" or "connected" to another component, it is understood that other components may be directly connected to or connected to the other component, but there may be other components in between. It should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that no other component exists in the middle. Other expressions that describe the relationship between the components, such as "between" and "immediately between" or "neighboring" and "directly neighboring to" should be interpreted as well.

The terms used in the present invention are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as “include” or “have” are intended to indicate that a described feature, number, step, action, component, part, or combination thereof exists, one or more other features or numbers. It should be understood that it does not preclude the presence or addition possibilities of, steps, actions, components, parts or combinations thereof.

1A and 1B are block diagrams schematically illustrating semiconductor devices according to embodiments of the present invention.

1A and 1B, each of the semiconductor devices according to embodiments of the present invention may include a peripheral circuit structure (PC) and a cell array (CAR) disposed on a substrate (SUB).

The substrate SUB may be a single crystal semiconductor film. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an optional It may be an epitaxial thin film formed through a selective epitaxial growth method.

The cell array CAR may include a plurality of memory blocks. Each of the memory blocks may include multiple cell strings. Each of the cell strings is electrically connected to bit lines, source lines, word lines and select lines. Each of the cell strings may include memory cells and select transistors connected in series. Each of the select lines is used as a gate electrode of a corresponding select transistor, and each of the word lines is used as a gate electrode of a corresponding memory cell.

The peripheral circuit structure PC may include NMOS transistors and PMOS transistors, resistors, and capacitors electrically connected to the cell array CAR. NMOS and PMOS transistors, registers, and capacitors can be used as the elements that make up the row decoder, column decoder, page buffer and control circuitry.

As shown in FIG. 1A, the peripheral circuit structure PC may be disposed on a portion of the substrate SUB not overlapping the cell array CAR.

Alternatively, as illustrated in FIG. 1B, the peripheral circuit structure PC may be disposed between the cell array CAR and the substrate SUB. In this case, since the peripheral circuit structure PC overlaps the cell array CAR, the area of the substrate SUB occupied by the cell array CAR and the peripheral circuit structure PC can be reduced.

2 is a cross-sectional view schematically showing a peripheral circuit structure. The peripheral circuit structure PC shown in FIG. 2 may be included in the peripheral circuit structure shown in FIG. 1A or may be included in the peripheral circuit structure shown in FIG. 1B.

Referring to FIG. 2, the peripheral circuit structure PC includes peripheral gate electrodes PG, peripheral gate insulating layer PGI, junctions Jn, peripheral circuit wirings PCL, and peripheral contact plugs PCP, And a peripheral circuit insulating layer (PIL).

The peripheral gate electrodes PG may be used as NMOS transistors of the peripheral circuit structure PC and gate electrodes of the PMOS transistors. The peripheral gate insulating layer PGI is disposed between each of the peripheral gate electrodes PG and the substrate SUB.

Junctions Jn are regions defined by injecting n-type or p-type impurities into the active region of the substrate SUB, and are disposed on both sides of each of the peripheral gate electrodes PG to be used as a source junction or a drain junction. . The active region of the substrate SUB may be partitioned by an isolation layer (ISO) formed inside the substrate SUB. The device isolation layer ISO is formed of an insulating material.

The peripheral circuit wirings PCL may be electrically connected to circuits of the peripheral circuit structure PC through the peripheral contact plugs PCP.

The peripheral circuit insulating layer PIL may cover circuits of the peripheral circuit structure PC, peripheral circuit wirings PCL, and peripheral contact plugs PCP. The peripheral circuit insulating layer PIL may include insulating layers stacked in multiple layers.

3A to 3E are perspective views schematically illustrating semiconductor devices according to embodiments of the present invention. 3A to 3E, illustration of insulating films is omitted.

3A to 3E, a semiconductor device according to an exemplary embodiment of the present invention may include a plurality of memory strings CST. The memory strings CST may include memory cells and select transistors arranged along the channel structures CH. For example, each of the memory strings CST may include memory cells and select transistors connected in series by a corresponding channel structure CH. The memory cells of each of the memory strings CST may be arranged in a three-dimensional structure to improve the degree of integration of the semiconductor device.

Each of the channel structures CH extends in the first direction I and may be electrically connected to a bit line BL corresponding thereto. The bit line BL may extend in a second direction II in a horizontal plane intersecting the first direction I. The bit line BL may be connected to a channel structure CH corresponding to the contact plug DCT. The contact plug DCT may directly contact the bit line BL and extend toward the corresponding channel structure CH.

The gates of the memory cells and the gates of the select transistors may be spaced apart in the first direction I and connected to the stacked conductive patterns CP1 to CPn. The conductive patterns CP1 to CPn may be used as word lines WL, source select lines SSL and drain select lines DSL. The conductive patterns CP1 to CPn may be sequentially stacked in the first direction I and disposed on the n-th layer from the first layer spaced apart from each other. The first layer is defined as the layer disposed farthest from the bit line BL, and the n-th layer is defined as the layer disposed closest to the bit line BL.

The channel structures CH protrude toward the bit line BL than the n-th patterns CPn disposed on the n-th layer.

3A to 3D, at least n-th patterns CPn of the conductive patterns CP1 to CPn may be used as drain select lines DSL. The present invention is not limited to this, and conductive patterns disposed on two or more layers may be used as drain select lines DSL. As an example, the n-th patterns CPn and the n-1th patterns CPn-1 disposed on the n-1th layer may be used as drain select lines DSL.

The first patterns CP1 disposed on at least the first layer of the conductive patterns CP1 to CPn may be used as source select lines SSL. The present invention is not limited to this, and conductive patterns disposed on two or more layers may be used as source select lines SSL. As an example, the first patterns CP1 and the second patterns CP2 disposed on the second layer may be used as source select lines SSL.

Conductive patterns (for example, CP3 to CPn-2) disposed between the drain select lines DSL and the source select lines SSL may be used as word lines WL.

The conductive patterns CP1 to CPn may be separated from each other by a first slit SI1 in each layer. The drain select lines DSL may be separated from each other by the second slits SI2 as well as the first slits SI1 in each layer. The present invention is not limited to this. Although not shown in the drawing, as an embodiment, the source select lines SSL may be separated from each other by the third slit as well as the first slit SI1 in each layer. Although not shown in the drawing, as an embodiment, the second slit SI2 may be omitted.

The above-described second slits SI2 and the third slits may overlap each layer of the word lines WL, and may be formed to a depth not penetrating the word lines WL.

The first slits SI1 and the second slits SI2 may extend in a third direction (III) in a horizontal plane. The third direction (III) is defined as a direction intersecting the first direction (I) and the second direction (II).

The channel structures CH shared in each of the word lines WL may be divided into two or more groups controlled by different drain select lines DSL. As an embodiment, the drain select lines DSL may include a first drain select line and a second drain select line separated from each other by the second slit SI2. In this case, the channel structures CH shared in each of the word lines WL may be divided into a first group controlled by the first drain select line and a second group controlled by the second drain select line. .

Each of the word lines WL, the drain select lines DSL, and the source select lines SSL may commonly wrap one or more channel structures CH.

The arrangement of the channel structures CH may form a zigzag shape. The embodiment of the present invention is not limited to this. As an embodiment, the channel structures CH may be arranged side by side in the second direction (II) and the third direction (III).

The drain select lines DSL disposed on the same layer may be separated from each other by the first slit SI1 and the second slit SI2. Each of the word lines WL is not penetrated by the second slit SI2, but may be extended to overlap the second slit SI2. Although not shown in the drawing, the source select lines SSL disposed on the same layer may be separated from each other by the third slits as well as the first slits SI1. In this case, each of the word lines WL is not penetrated by the third slit, but may be extended to overlap the third slit.

3A, 3B, and 3D, each of the channel structures CH may pass through the drain select lines DSL, word lines WL, and source select lines SSL. Referring to FIG. 3C, each of the channel structures CH may pass through the drain select lines DSL and word lines WL.

3A and 3B, the channel structures CH may be directly connected to the source layer SL disposed under the conductive patterns CP1 to CPn. The source film SL may be formed in various structures.

Referring to FIG. 3A, the source layer SL may contact the bottom surface of each of the channel structures CH. The source film SL may be formed of a doped semiconductor film including a source dopant. The source dopant may include n-type impurities. As an example, the source layer SL may be formed by injecting a source dopant from the surface of the substrate SUB described with reference to FIG. 1A toward the inside of the substrate SUB. As an example, the source film SL may be formed by depositing a doped semiconductor film on the substrate SUB described with reference to FIG. 1B. In this case, an insulating film may be disposed between the substrate SUB and the doped semiconductor film. As an embodiment, the doped semiconductor film may include doped silicon.

Each of the channel structures CH may contact the top surface of the source layer SL, penetrate the conductive patterns CP1 to CPn, and extend in the first direction I toward the bit line BL. The sidewalls of each of the channel structures CH may be surrounded by a multilayer film ML. The multilayer film ML may extend along sidewalls of the corresponding channel structure CH. The top and bottom surfaces of each of the channel structures CH may be opened without being blocked by the multilayer film ML.

Referring to FIG. 3B, the channel structures CH may pass through the conductive patterns CP1 to CPn and extend into the source layer SL. A portion of the sidewalls of each of the channel structures CH may contact the source layer SL.

The source layer SL may include a first source layer SL1 and a contact source layer CTS. The source layer SL may further include a second source layer SL2. The channel structures CH may pass through the second source layer SL2 and the contact source layer CTS, and may extend into the first source layer SL1.

The first source layer SL1 may cover the bottom of each of the channel structures CH. The first source film SL1 may be formed of a doped semiconductor film including a source dopant. The source dopant may include n-type impurities. As an example, the first source layer SL1 may be formed by injecting a source dopant from the surface of the substrate SUB described with reference to FIG. 1A toward the inside of the substrate SUB. As an example, the first source film SL1 may be formed by depositing a doped semiconductor film on the substrate SUB described with reference to FIG. 1B. In this case, an insulating film may be disposed between the substrate SUB and the doped semiconductor film. As an embodiment, the doped semiconductor film may include doped silicon.

The contact source layer CTS is disposed on the first source layer SL1 and may contact the top surface of the first source layer SL1. The contact source layer CTS is in contact with a part of the sidewalls of each of the channel structures CH and surrounds the channel structures CH.

The multi-layer film extending along the sidewalls of each of the channel structures CH may be separated into a first multi-layer pattern ML1 and a second multi-layer pattern ML2 by a contact source film CTS. The first multi-layer pattern ML1 is defined as a pattern surrounding the top of each of the channel structures CH, and the second multi-layer pattern ML2 is disposed between the first source layer SL1 and each channel structure CH. Is defined as a pattern.

The second source layer SL2 may be disposed between the contact source layer CTS and the source select line SSL. The second source layer SL2 may be formed to surround the first multi-layer pattern ML1. The second source layer SL2 may be omitted in some cases. The second source layer SL2 may be penetrated by the first slit SI1.

Each of the contact source film CTS and the second source film SL2 described above may be formed of a doped semiconductor film including a source dopant. The source dopant may include n-type impurities. As an embodiment, the doped semiconductor film may include a doped silicon film.

FIG. 4 is an enlarged view of the area X shown in FIG. 3C.

3C and 4, each of the channel structures CH may be connected to a corresponding lower channel structure LPC.

The lower channel structure LPC is connected under the corresponding channel structure CH. Each channel structure CH may be surrounded by a multilayer film ML. The multilayer film ML may extend along sidewalls of the corresponding channel structure CH. The top and bottom surfaces of the channel structure CH are not blocked by the multilayer film ML, but are opened.

The lower channel structure LPC penetrates at least one source select line SSL disposed under the word lines WL. The sidewall of the lower channel structure LPC may be surrounded by a gate insulating layer GI. The gate insulating layer GI may extend along sidewalls of the lower channel structure LPC. The top and bottom surfaces of the lower channel structure LPC may be opened without being blocked by the gate insulating layer GI.

The source film SL may contact the bottom surface of the lower channel structure LPC. The source film SL may be formed of the same material as the source film SL described with reference to FIG. 3A.

Referring to FIG. 3D, each of the channel structures CH includes pillars PL passing through the conductive patterns CP1 to CPn and a horizontal portion HP extending in a horizontal direction from the pillars PL. Can be. The horizontal portions HP of the channel structures CH may extend in parallel to the lower surfaces of the first patterns CP1. The horizontal parts HP may be separated from each other by a slit extension SIE extending from the first slit SI1. The doped area DA may be disposed under the horizontal parts HP. In other words, the horizontal parts HP may be disposed between the doped area DA and the first patterns CP1.

As an example, the doped region DA may be formed of a doped semiconductor film including a well dopant. The well dopant may contain p-type impurities. As an example, the doped region DA may be formed by injecting a well dopant with a partial thickness from the surface of the substrate SUB described with reference to FIG. 1A. As an example, the doped region DA may be formed by depositing a doped semiconductor film on the substrate SUB described with reference to FIG. 1B. In this case, an insulating film may be disposed between the substrate SUB and the doped semiconductor film. As an embodiment, the doped semiconductor film may include doped silicon.

The side walls of each of the pillar parts PL may be surrounded by a multilayer film ML. The multilayer film ML may extend between the horizontal portion HP and the first pattern CP1 corresponding thereto. The multilayer film ML may extend between the horizontal portion HP and the doped region DA corresponding thereto.

Referring to FIG. 3E, the conductive patterns CP1 to CPn may be divided into source-side conductive patterns CP_S and drain-side conductive patterns CP_D by the first slit SI1.

The source-side n-th pattern CPn disposed on at least the n-th layer among the source-side conductive patterns CP_S may be used as the source select line SSL. The present invention is not limited thereto, and each of the conductive patterns disposed on two or more layers may be used as a source select line (SSL). As an example, among the source-side conductive patterns CP_S, the source-side n-th pattern CPn and the source-side n-1 pattern CPn-1 disposed on the n-th layer and the n-1-th layer, respectively, respectively. It can be used as a source select line (SSL). Among the source-side conductive patterns CP_S, conductive patterns (for example, CP1 to CPn-2) disposed under the source select line SSL may be used as source-side word lines WL_S.

The drain-side n-th pattern CPn disposed on at least the n-th layer of the drain-side conductive patterns CP_D may be used as a drain select line DSL. The present invention is not limited to this, and each of the conductive patterns disposed on two or more layers may be used as the drain select line DSL. As an example, among the drain-side conductive patterns CP_D, the drain-side n-th pattern CPn and the drain-side n-1 pattern CPn-1 disposed on the n-th layer and the n-1-th layer, respectively, respectively. It can be used as a drain select line (DSL). The conductive patterns (for example, CP1 to CPn-2) disposed under the drain select line DSL among the drain-side conductive patterns CP_D may be used as word lines WL_D.

The common source line CSL may be disposed on the source-side conductive patterns CP_S. The common source line CSL is disposed on a different layer from the bit line BL. The common source line CSL and the bit line BL are formed of a conductive material and are spaced apart from each other. For example, the common source line CSL may be disposed between the bit line BL and the source-side conductive patterns CP_S.

Each of the channel structures CH may include a source side pillar S_PL, a drain side pillar D_PL, and a horizontal portion HP. The drain-side pillar D_PL may be electrically connected to the bit line BL. The drain-side pillar D_PL extends through the drain-side conductive patterns CP_D and is connected to the horizontal portion HP. The source side pillar S_PL may be electrically connected to the common source line CSL. The source side pillar S_PL extends through the source side conductive patterns CP_S and is connected to the horizontal portion HP. The horizontal portion HP is embedded in the pipe gate PG. The source side pillar S_PL and the drain side pillar D_PL extend from the horizontal portion HP along the first direction I. The pipe gate PG is disposed under the source-side conductive patterns CP_S and the drain-side conductive patterns CP_D, and may be formed to surround the horizontal portion HP. The pipe gate PG may be used as a gate of the pipe transistor. The pipe transistor may electrically connect the source-side pillar S_PL and the drain-side pillar D_PL according to the signal transmitted to the pipe gate PG through the horizontal portion HP.

The outer walls of each of the channel structures CH may be surrounded by a multilayer film ML. The multilayer film ML extends along the outer walls of the drain-side pillar D_PL, the horizontal portion HP, and the source-side pillar S_PL of the corresponding channel structure CH.

The first slit SI1 is disposed between the source-side conductive patterns CP_S and the drain-side conductive patterns CP_D adjacent to each other in the second direction II and may extend along the third direction III. have. Each of the source-side conductive patterns CP_S, the drain-side conductive patterns CP_D, and the common source line CSL may be formed in a line shape extending along the third direction III.

The word lines WL, WL_D or WL_S described above with reference to FIGS. 3A to 3E are used as gates of memory cells, and each of the drain select lines DSL is used as a gate of a drain select transistor, and source select Each of the lines SSL is used as a gate of a source select transistor. The multilayer layer ML, ML1, or ML2 may include a data storage layer that stores data.

Each of the channel structures CH illustrated in FIGS. 3A to 3E includes an upper end protruding toward the bit line BL than the n-th patterns CPn. The separation distance between the contact plug DCT and the corresponding n-th pattern CPn is proportional to the upper length of each channel structure CH. The upper length of each channel structure CH may be variously designed according to the design rules of the semiconductor device, and may be designed in consideration of a process margin.

Poor process due to misalignment of the contact plug (DCT) can be prevented by an etch stop pattern formed to surround the top of each channel structure (CH). Hereinafter, an etch stop pattern surrounding the upper end of each channel structure CH will be described with reference to FIGS. 5A and 5B.

5A and 5B show various cross-sections of a semiconductor device according to an embodiment of the present invention.

5A and 5B, a semiconductor device according to an exemplary embodiment of the present invention includes gate stacks GST. The gate stacks GST may be disposed under the etch stop patterns ES. In other words, the etch stop patterns ES may be disposed on the gate stacks GST. Each of the gate stacks GST may include interlayer insulating layers ILD and conductive patterns CPk to CPn stacked alternately in the first direction I. 5A and 5B respectively show interlayer insulating layers ILD and conductive patterns CPk to CPn constituting the upper portion of each of the gate stacks GST. The conductive patterns CPk to CPn shown in each of FIGS. 5A and 5B are the kth patterns CPk to nth pattern CPn among the conductive patterns CP1 to CPn shown in FIGS. 3A to 3E, respectively. Correspond. The k-th pattern CPk is a pattern disposed on the k-th layer among the conductive patterns CP1 to CPn shown in FIGS. 3A to 3E, respectively. Each of the gate stacks GST according to an embodiment of the present invention is first from the k-1 pattern disposed on the k-1th layer among the conductive patterns CP1 to CPn shown in each of FIGS. 3A to 3E. Patterns CPk-1 to CP1 may be further included.

The conductive patterns CPk to CPn may include a gate conductive layer. For example, the gate conductive film may include at least one of a doped silicon film, a metal silicide film, and a metal film. For example, the metal film may include a low-resistance metal such as tungsten, nickel, or cobalt for the low-resistance gate conductive film. The gate conductive layer may further include a barrier layer. The barrier film is a film for preventing diffusion of metal from the metal film, and may include, for example, a metal nitride film. For example, the metal nitride film may include titanium nitride, tantalum nitride film, and the like.

The interlayer insulating layers ILD may include oxide, for example, silicon oxide.

Gate stacks GST adjacent to each other in the second direction II may be separated from each other by slits SI. The second direction (II) is a direction parallel to the horizontal plane intersecting the first direction (I). Each of the interlayer insulating layers ILD and the conductive patterns CPk to CPn may extend in the second direction (II) and the third direction (III). The third direction (III) is a direction parallel to the horizontal plane intersecting the first direction (I), and is a direction intersecting the second direction (II).

The etch stop patterns ES and the gate stacks GST may be penetrated by the channel structures CH. Each of the channel structures CH is surrounded by a corresponding etch stop pattern ES and a corresponding gate stack GST. Each of the channel structures CH protrudes from the n-th pattern CPn and has an upper end surrounded by an etch stop pattern ES corresponding thereto.

The gate stacks GST may protrude toward the lateral direction than the etch stop patterns ES. That is, the gate stacks GST may protrude toward the slit SI rather than the etch stop patterns ES. For example, each of the interlayer insulating layers ILD and the conductive patterns CPk to CPn may protrude toward the slit rather than the etch stop patterns ES.

The etch stop patterns ES may be surrounded by an upper insulating layer UD. The upper insulating layer UD may include oxide. For example, the oxide may include silicon oxide. The etch stop patterns ES may include a material having a different etch rate from the interlayer insulating layers ILD and the upper insulating layer UD. For example, the etch stop patterns ES may include nitride. For example, the nitride may include silicon nitride.

The upper insulating layer UD extends to cover the top surface and sidewalls of each of the etch stop patterns ES. The upper insulating layer UD may include sidewalls facing the slits SI. Depressions DP are formed on sidewalls of the upper insulating layer UD. The recessed portions DP overlap the upper ends of the channel structures CH passing through the etch stop patterns ES.

The upper insulating layer UD may include vertical portions P1 and horizontal portions P2. The vertical portions P1 of the upper insulating layer UD are respectively disposed on sidewalls of the etch stop patterns ES facing the slits SI. The horizontal parts P2 extend from the vertical parts P1 to cover the top surface of the etch stop patterns ES.

The horizontal parts P2 and the gate stacks GST may protrude from the vertical parts P1 toward the slit SI. In other words, the horizontal parts P2 may protrude from the vertical parts P1 and the gate stacks GST toward the lateral direction intersecting the first direction I. According to this structure, the concave portions DP of the upper insulating layer UD may be respectively defined on the side surfaces of the vertical portions P1.

The semiconductor device may further include a first blocking insulating layer BI1. The first blocking insulating layer BI1 extends along interfaces between the interlayer insulating layers ILD and the conductive patterns CPk to CPn. The first blocking insulating layer BI1 extends to cover sidewalls of the conductive patterns CPk to CPn facing the channel structures CH. The first blocking insulating layer BI1 extends to cover the surface of each of the horizontal portions P2 protruding from the vertical portions P1, and extends to cover the side surfaces of the vertical portions P1.

The first blocking insulating layer BI1 may include an insulating material having a high dielectric constant. For example, the first blocking insulating layer BI1 may include metal oxide. For example, the metal oxide may include aluminum oxide. The first blocking insulating layer BI1 may be omitted in some cases.

The slit SI may be filled with a vertical structure VS. The vertical structure VS extends to cover sidewalls of the gate stacks GST and sidewalls of the upper insulating layer UD, and may include protrusions protruding toward the recesses DP.

As an embodiment, the vertical structure VS may include an insulating material that completely fills the inside of the slit SI. As an example, the vertical structure VS may include a sidewall insulating film and a vertical conductive pattern. The sidewall insulating film may extend to cover the sidewall of the slit SI, and the vertical conductive pattern may be formed to fill the central region of the slit SI opened by the sidewall insulating film.

When the first blocking insulating layer BI1 is formed, the vertical structure VS may be formed on the first blocking insulating layer BI1.

The horizontal portions P2 of the upper insulating layer UD may be penetrated by the contact plugs CT. Each of the contact plugs CT may correspond to the contact plug DCT shown in each of FIGS. 3A to 3E. The contact plugs CT may be respectively connected to the channel structures CH. The contact plugs CT may include a conductive material.

Each of the channel structures CH may include a core insulating film CO, a semiconductor film SE, and a capping pattern CAP. The core insulating film CO may include an insulating material, for example, oxide. The semiconductor film SE extends along the sidewalls of the core insulating film CO to surround the core insulating film CO. The semiconductor film SE may be used as a channel through which charges are transferred. For example, the semiconductor film SE may include silicon. The core insulating film CO is formed to a lower height than the semiconductor film SE, and the semiconductor film SE protrudes in the first direction I from the core insulating film CO. The capping pattern CAP is disposed on the core insulating film CO and is surrounded by the upper end of the semiconductor film SE protruding from the core insulating film CO. The capping pattern CAP is in contact with the semiconductor film SE. The capping pattern CAP includes a doped semiconductor film doped with a dopant. For example, the doped semiconductor film may include doped silicon. The capping pattern CAP may include an n-type dopant. The contact plugs CT may be connected to a capping pattern CAP corresponding thereto. The capping pattern CAP may be used as a junction.

The multilayer film ML surrounding each of the channel structures CH may extend along sidewalls of the corresponding channel structure CH.

When aligning the contact plugs CT, as shown in FIG. 5A, the center axis of the contact plugs CT may coincide with the center axis of the channel structures CH without alignment error. Alternatively, when the contact plugs CT are aligned, as shown in FIG. 5B, due to a misalignment, the contact plugs CT may be biased on one side of the channel structures CH.

During the manufacture of the semiconductor device, the slit SI is opened and the etch stop film for the etch stop patterns ES is exposed by the slit SI. A portion of the etch stop film exposed by the slit SI may be removed while manufacturing the semiconductor device, and concave portions DP may be formed. Even if a part of the etch stop film is removed while the slit SI is opened, the remaining parts of the etch stop film protected by the vertical portions P1 of the upper insulating layer UD may remain as etch stop patterns ES. .

During the etching of the upper insulating layer UD to form the contact plugs CT, the exposure of the nth pattern CPn using the difference in the etch rate between the etch stop patterns ES and the upper insulating layer UD Can be prevented. For example, as illustrated in FIG. 5B, when a misalignment of the contact plugs CT occurs, while etching the upper insulating layer UD, a part of each of the etch stop patterns ES may be etched. Can be. However, since the etch stop patterns ES have high etch resistance to an etch material for etching the upper insulating layer UD, it is difficult to completely penetrate the contact plugs CT. Accordingly, an embodiment of the present invention can reduce the punch phenomenon according to the misalignment of the contact plugs CT.

6 is a plan view illustrating a layout of vertical portions P1 and etch stop patterns ES of an upper insulating layer UD according to an embodiment of the present invention. FIG. 6 shows a cross-sectional view of the semiconductor device taken along line A-A 'shown in FIG. 5A or line B-B' shown in FIG. 5B.

Referring to FIG. 6, each of the etch stop patterns ES may extend in a second direction (II) and a third direction (III) intersecting each other in a horizontal plane intersecting the first direction (I). Each of the vertical portions P1 and the vertical structure VS may extend in a line shape along the third direction III. The vertical parts P1 face each other with the vertical structure VS interposed therebetween. The first blocking insulating layer BI1 may extend along the interface between each of the vertical portions P1 and the vertical structure VS.

The channel structures CH passing through each of the etch stop patterns ES may be arranged in a zigzag manner in the second direction (II) and the third direction (III). The embodiment of the present invention is not limited to this. For example, the channel structures CH passing through each of the etch stop patterns ES may be arranged side by side in the second direction (II) and the third direction (III).

Each of the channel structures CH may have a circular cross section. The embodiment of the present invention is not limited to this. For example, the cross section of each of the channel structures CH may be variously changed, such as a triangle, a square, a polygon, or an oval. Each of the channel structures CH includes a capping pattern CAP surrounded by the semiconductor film SE, and is surrounded by a multilayer film ML.

7 is an enlarged cross-sectional view of the Y region shown in FIGS. 5A and 5B, respectively.

Referring to FIG. 7, the multilayer film ML may extend along an interface between each of the channel structures CH and the gate stack GST. The multilayer film ML includes a tunnel insulating film TI surrounding the corresponding channel structure CH, a data storage film DL surrounding the tunnel insulating film TI, and a second blocking insulating film BI2 surrounding the data storage film DL. ).

The data storage layer DL may be formed of a charge trap film, a material film containing conductive nanodots, or a phase change material film.

The data storage layer DL is a Fowler node-heim tunneling caused by a voltage difference between the corresponding channel structure CH and the word lines among the conductive patterns CPk to CPn shown in FIGS. 5A or 5B. -Nordheim tunneling) can be used to store the changed data. To this end, the data storage layer DL may be formed of silicon nitride capable of charge trapping.

The data storage layer DL may store data based on an operating principle other than Fowler node Heim tunneling. For example, the data storage layer DL is formed of a phase change material film and may store data according to the phase change.

The second blocking insulating layer BI2 may include an oxide capable of blocking charge. The tunnel insulating layer TI may include silicon oxide capable of charge tunneling.

One of the first blocking insulating layer BI1 and the second blocking insulating layer BI2 may be omitted in some cases.

Although not shown in the drawing, at least one of the tunnel insulating layer TI and the data storage layer DL has an interface between the first blocking insulating layer BI1 and the interlayer insulating layer ILD, and a channel structure CH and the first blocking layer. It may extend along the interface between the insulating films BI1.

8, 9A, 9B, 10A, 10B, 11A to 11C, 12A, and 12B are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

8 shows channel structures 129 penetrating the preliminary stack ST and the etch stop layer 111.

Referring to FIG. 8, the preliminary stack ST is formed by alternately stacking the first material films 101 and the second material films 103. The first material layers 101 may be an insulating material for the interlayer insulating layers ILD shown in FIGS. 5A or 5B. The second material layers 103 have different etch rates from the first material layers 101. For example, each of the first material films 101 may include an oxide such as a silicon oxide film, and each of the second material films 103 may include a nitride such as a silicon nitride film. The uppermost layer of the first material layers 101 may be disposed on the uppermost layer of the preliminary laminate ST.

The etch stop layer 111 is formed on the preliminary laminate ST. The etch stop layer 111 has a different etch rate from the first material layers 101. For example, the etch stop layer 111 may include the same material as the second material layers 103. For example, each of the etch stop layer 111 and the second material layers 103 may include nitride.

Forming the channel structures 129 may include forming holes H passing through the preliminary stack ST and filling the holes H with channel structures 129, respectively. Before forming the channel structures 129, a step of forming a multilayer film 121 on each sidewall of each of the holes H may be further included. In this case, each of the channel structures 129 may be formed on the multilayer film 121.

The step of forming the multi-layer film 121 may include sequentially stacking a blocking insulating film, a data storage film, and a tunnel insulating film from the sidewalls of the holes H toward the center region of each of the holes H. The blocking insulating layer may include an insulating material capable of blocking electric charges. For example, the blocking insulating film may include oxide. The data storage film may be formed of a charge trap film, a material film containing conductive nanodots, or a phase change material film. For example, the data storage layer may include silicon nitride. The tunnel insulating layer may include an insulating material capable of charge tunneling. For example, the tunnel insulating layer may include silicon oxide.

Each of the channel structures 129 may include a semiconductor film 123, a core insulating film 125, and a capping pattern 127. The semiconductor film 123 is conformally formed along the sidewalls of each of the holes H. For example, the semiconductor film 123 may be formed by depositing a silicon film. The central region of each of the holes H opened by the semiconductor layer 123 is filled with the core insulating layer 125 and the capping pattern 127.

The core insulating layer 125 may include oxide. The height of the core insulating film 125 may be controlled to be lower than the height of each of the holes H. In order to control the height of the core insulating film 125, a part of the core insulating film 125 inside the holes H may be removed.

The capping pattern 127 is disposed on the core insulating film 125 and may be surrounded by an upper end of the semiconductor film 123. The capping pattern 127 may include a doped semiconductor film. For example, the capping pattern 127 may include doped silicon. The capping pattern 127 may include an n-type dopant. As an example, the top of the semiconductor film 123 in contact with the capping pattern 127 may be recrystallized together with the capping pattern 127 by a process such as laser annealing.

9A and 9B show trenches 131 penetrating the etch stop layer. 9A is a plan view showing the layout of the channel structures 129 and the trenches 131, and FIG. 9B shows a cross-section taken along line C-C 'shown in FIG. 9A.

9A and 9B, trenches 131 are formed to penetrate through the etch stop layer 111 illustrated in FIG. 8. Thus, the etch stop layer may be separated into etch stop patterns 111P1 and a first dummy pattern 111P2A. Each of the etch stop patterns 111P1 may wrap the channel structures 129 for each group. For example, the channel structures 129 may be divided into a plurality of groups GR. Each group GR is surrounded by an etch stop pattern 111P1 corresponding thereto.

The trenches 131 extend side by side at the boundary between the groups GR formed by the channel structures 129. The first dummy pattern 111P2A is a partial region of the etch stop layer remaining between the trenches 131 adjacent to each other at the boundary between the groups GR formed by the channel structures 129.

The trenches 131 may be formed using a photolithography process. As an embodiment, the process of forming the trenches 131 may be formed using a process of forming the second slits SI2 illustrated in each of FIGS. 3A to 3D. Although not shown in the drawing, the second slits SI2 may be formed to have a wider width than each of the trenches 131, and etch stop patterns 111P1 and between channel structures 129 of each group GR. A portion of the preliminary laminate ST may be penetrated. As an embodiment, the process of forming the trenches 131 may be performed as a separate process separate from the process of forming the second slit SI2.

10A and 10B show the slit 141 and the upper insulating film 133. 10A is a plan view showing the layout of the slits 141, vertical portions 133P1 of the upper insulating film, and etch stop patterns 111P1. FIG. 10B shows a cross-section taken along line C-C 'shown in FIG. 10A.

10A and 10B, an upper insulating layer 133 is formed so that the trenches 131 illustrated in FIGS. 9A and 9B are filled. The upper insulating layer 133 may be divided into vertical portions 133P1 and horizontal portions 133P2. The vertical portions 133P1 are a part of the upper insulating layer 133 filling the trenches 131. The horizontal portion 133P2 is another part of the upper insulating layer 133 extending from the vertical portions 133P1 to cover the upper surface of the etch stop patterns 111P1 and the channel structures 129. The horizontal portion 133P2 extends to cover the top surface of the first dummy pattern 111P2A shown in FIGS. 9A and 9B.

The upper insulating layer 133 has a different etch rate from the etch stop layer 111 and the second material layers 103 described above with reference to FIG. 8. For example, the upper insulating film 133 may include an oxide such as a silicon oxide film.

The upper insulating film 133 is penetrated by the slit 141. The slits 141 penetrate the horizontal portions 133P2 of the upper insulating layer 133 between the adjacent vertical portions 133P1. The slit 141 extends through the first dummy pattern 111P2A shown in FIGS. 9A and 9B. Accordingly, the first dummy pattern 111P2A may be separated into second dummy patterns 111P2B by the slits 141. The second dummy patterns 111P2B may remain between the vertical portions 133P1 and the slit 141. The slit 141 is extended to penetrate the preliminary stack ST superimposed on the first dummy pattern 111P2A shown in FIGS. 9A and 9B. The slits 141 may be formed in a line shape extending parallel to the vertical portions 133P1. The slit 141 may be formed using a photolithography process.

11A to 11C are cross-sectional views illustrating steps of replacing the second material layers 103 shown in FIG. 10B with line patterns through the slit 141.

Referring to FIG. 11A, the second material layers 103 shown in FIG. 10B are removed through the slit 141. As a result, as shown in FIG. 11A, the first material layers 101 and the second material layers 103 adjacent to each other in the stacking direction of the first material layers 101 shown in FIG. Fields 143 are defined. As described above with reference to FIG. 8, since the second material layers 103 have different etch rates from the first material layers 101, the first material layers 103 are selectively removed while the first material layers 103 are selectively removed. The loss of the material films 101 can be minimized.

While selectively etching the second material layers 103, the second dummy patterns 111P2B exposed through the slit 141 illustrated in FIG. 10B may be simultaneously removed. As a result, as illustrated in FIG. 11A, vertical portions 133P1 of the upper insulating film 133 may be exposed, and an undercut region UC may be defined on the side of the upper insulating film 133 facing the slit 141. have. The undercut region UC may be defined by a horizontal portion 133P2 and a top layer first material film T that protrude toward the slit 141 rather than each vertical portion 133P1.

As described above with reference to FIGS. 10A and 10B, the upper insulating layer 133 has an etch rate different from that of the second material layers 103. Accordingly, even when the vertical portions 133P1 of the upper insulating layer 133 are exposed while selectively removing the second material layers 103, loss of the vertical portions 133P1 may be minimized. In addition, while selectively removing the second material layers 103, the etch stop patterns 111P1 may be protected by vertical portions 133P1 as illustrated in FIG. 11A.

Referring to FIG. 11B, the opening regions 143 shown in FIG. 11A are filled with a conductive film 151. Before forming the conductive layer 151, a blocking insulating layer 145 extending along the surfaces of the opening regions 143 may be further formed. The blocking insulating layer 145 may be extended to cover the sidewalls of each of the first material layers 101 facing the slits 141 and the surface of the undercut region UC shown in FIG. 11A. The blocking insulating layer 145 may include an insulating material that blocks electric charges. For example, the blocking insulating layer 145 may include metal oxide. For example, the metal oxide may include an aluminum oxide film.

When the above-described blocking insulating film 145 is formed, the conductive film 151 is formed on the blocking insulating film 145 to fill each of the opening regions 143 shown in FIG. 11A. The conductive film 151 may include at least one of a doped silicon film, a metal silicide film, and a metal film. For example, the metal film may include low-resistance metals such as tungsten, nickel, and cobalt. The conductive layer 151 may further include a barrier layer formed conformally on the blocking insulating layer 145. The barrier film may include a metal nitride film. For example, the metal nitride film may include titanium nitride, tantalum nitride film, and the like.

Referring to FIG. 11C, the conductive layer 151 illustrated in FIG. 11A is etched to separate the conductive layer 151 into line patterns 151P. As a result, gate stacks GST as illustrated in FIGS. 5A and 5B may be formed.

The line patterns 151P may correspond to the conductive patterns CPk to CPn shown in FIG. 5A or 5B. Some regions of the blocking insulating layer 145 not covered by the line patterns 151P may be exposed by an etching process of the conductive layer 151. At this time, a portion of the blocking insulating layer 145 disposed on the undercut region UC may be exposed.

12A and 12B are cross-sectional views showing the vertical structure 155 and the contact holes 161A and 161B. 12A is a cross-sectional view showing an embodiment in which the contact holes 161A are aligned without error in the channel structures 129, and FIG. 12B shows one side of the channel structures 129 in which the contact holes 161B are within an error range. It is a cross-sectional view showing an embodiment biased.

12A and 12B, the inside of the slit 141 illustrated in FIG. 11C may be filled with a vertical structure 155. As an example, the vertical structure 155 may be formed by completely filling the inside of the slit 141 with an insulating material. As an embodiment, forming the vertical structure 155 may include forming a sidewall insulating film on the sidewall of the slit 141 so as to cover the blocking insulating film 145 and of the slit 141 exposed by the sidewall insulating film. And filling the central region with a conductive material.

The contact holes 161A and 161B may be formed by etching the horizontal portion 133P2 of the upper insulating layer using a photolithography process.

12A, when the central axes of the contact holes 161A coincide with the central axes of the channel structures 129, the capping pattern 127 is caused by the corresponding contact hole 161A. Can be exposed. At this time, the capping pattern 127 may serve as an etch stop layer.

12B, when the contact holes 161B are disposed on one side of the channel structures 129, the capping pattern 127 as well as the sidewalls of the semiconductor film 123 correspond to the contact holes. (161B). At this time, the capping pattern 127 and the etch stop patterns 111P1 may serve as an etch stop film.

As a comparative example, when the etch stop patterns 111P1 are not formed, the gate stack GST may be exposed while forming the contact holes 161B passing through the first upper insulating layer 133. In this case, a punch failure may occur in which the insulation distance between the line patterns 151P and the contact plugs to be disposed inside the contact holes 161B is not secured. To prevent this, the upper length of each of the channel structures 129 protruding from the gate stack GST may be increased. In this case, it may be difficult to uniformly control the etch amount of the core insulating layer 125 for each hole in the step of removing a portion of the core insulating layer 125 inside the holes described above with reference to FIG. 8. In this case, since it is difficult to uniformly form the capping pattern 127 for each hole, the operating characteristics of the semiconductor device may deteriorate.

In an embodiment of the present invention, even if the upper height of each of the channel structures 129 protruding from the gate stack GST is not excessively increased, the etch stop patterns 111P1 are formed during the formation of the contact holes 161B. Can be used as an etch stop. Accordingly, the embodiment of the present invention can prevent the phenomenon that the gate stacked body GST is exposed by the contact holes 161B, and can prevent punch defects. Thus, the embodiment of the present invention can increase the stability of the manufacturing process of the semiconductor device, and improve the operating characteristics of the semiconductor device.

Subsequently, the contact holes 161A and 161B illustrated in FIGS. 12A and 12B may be filled with a conductive material to form contact plugs CT illustrated in FIGS. 5A and 5B.

13 is a block diagram showing the configuration of a memory system according to an embodiment of the present invention.

Referring to FIG. 13, a memory system 1100 according to an embodiment of the present invention includes a memory element 1120 and a memory controller 1110.

The memory device 1120 may be a multi-chip package composed of a plurality of flash memory chips. The memory element 1120 may include a semiconductor memory device including at least one of the structures shown in FIGS. 5A and 5B.

The memory controller 1110 is configured to control the memory element 1120, static random access memory (SRAM) 1111, CPU 1112, host interface 1113, error correction code (ECC) 1114, memory Interface 1115. The SRAM 1111 is used as the operation memory of the CPU 1112, the CPU 1112 performs various control operations for data exchange of the memory controller 1110, and the host interface 1113 connects with the memory system 1100 The host has a data exchange protocol. In addition, the ECC 1114 detects and corrects errors included in data read from the memory element 1120, and the memory interface 1115 interfaces with the memory element 1120. In addition, the memory controller 1110 may further include a read only memory (ROM) for storing code data for interfacing with the host.

The above-described memory system 1100 may be a memory card or a solid state disk (SSD) in which the memory element 1120 and the memory controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 is a Universal Serial Bus (USB), MultiMedia Card (MMC), Peripheral Component Interconnection-Express (PCI-E), Serial Advanced Technology Attachment (SATA) ), External (e.g., host) through one of various interface protocols such as Parallel Advanced Technology Attachment (PATA), Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), etc. Can communicate with.

14 is a block diagram showing the configuration of a computing system according to an embodiment of the present invention.

Referring to FIG. 14, the computing system 1200 according to an embodiment of the present invention includes a CPU 1220 electrically connected to the system bus 1260, a random access memory (RAM) 1230, a user interface 1240, a modem ( 1250), a memory system 1210. In addition, when the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may be further included, and an application chipset, a camera image processor (CIS), and a mobile DRAM may be further included. .

The above-described embodiments are merely intended to easily describe the technical spirit of the present invention and provide specific examples, and are not intended to limit the scope of the present invention. It is obvious to those skilled in the art to which the present invention pertains that other modified examples based on the technical idea of the present invention can be implemented in addition to the embodiments disclosed herein.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have meanings generally understood in the technical field to which the present invention pertains. It is not to be construed in an ideal or excessively formal sense, unless explicitly defined in the present invention.

ES, 111P1: etch stop pattern ILD: interlayer insulating film
CP1 to CPn: Conductive pattern GST: Gate laminate
CH, 129: Channel structure DP: Concave
UD, 133: upper insulating film CT: contact plug
P1, 133P1: vertical part P2, 133P2: horizontal part
BI1, BI2, 145: blocking insulating film VS, 155: vertical structure
101: first material layer 103: second material layer
111: etch stop film ST: preliminary laminate
SI, 141: Slit 151P: Line pattern
131: trench 143: opening area
151: conductive film UC: undercut area

Claims (20)

Etch stop pattern;
A gate stack including interlayer insulating films and conductive patterns alternately stacked under the etch stop pattern;
Channel structures penetrating the etch stop pattern and the gate stack;
An insulating film extending to cover an upper surface of the etch stop pattern and a side wall of the etch stop pattern, and having a side wall formed with depressions; And
A semiconductor device including contact plugs penetrating the insulating film to be connected to the channel structures, respectively. According to claim 1,
The concave portion of the insulating layer is a semiconductor device superimposed on each of the channel structures passing through the etch stop pattern. According to claim 1,
The insulating film,
A vertical portion disposed on the sidewall of the etch stop pattern; And
And a horizontal portion extending from the vertical portion to cover the upper surface of the etch stop pattern. The method of claim 3,
The horizontal portion protrudes from the vertical portion toward a lateral direction intersecting the stacking direction of the interlayer insulating films and the conductive patterns,
The gate stack is a semiconductor device protruding from the vertical portion toward the lateral direction. The method of claim 4,
The recessed portion of the insulating film is a semiconductor device formed on the side of the vertical portion. The method of claim 4,
And a blocking insulating layer extending to cover a surface of the horizontal portion protruding from the vertical portion and a side surface of the vertical portion. The method of claim 6,
The blocking insulating film
Extending along each of the interfaces between the conductive patterns and the interlayer insulating films,
A semiconductor device extending to cover each sidewall of the conductive patterns facing the channel structures. According to claim 1,
The etch stop pattern includes a semiconductor device having a different etch rate from the insulating film. According to claim 1,
The etch stop pattern includes a nitride, and the insulating film includes an oxide. According to claim 1,
The semiconductor device further includes a vertical structure extending to cover the sidewall of the gate stack and the sidewall of the insulating layer, and including a protrusion protruding toward the recess. Forming a stack including alternately stacked first material films and second material films;
Forming an etch stop film on the laminate;
Forming an insulating film including vertical portions penetrating the etch stop film;
Forming a slit extending through the etch stop layer between the adjacent vertical portions and extending through the stack; And
And replacing the second material layers with line patterns through the slits. The method of claim 11,
The etch stop film is a method of manufacturing a semiconductor device including a material having a different etch rate from the insulating film. The method of claim 11,
The etch stop film includes a nitride, and the insulating film includes a semiconductor device. The method of claim 11,
A method of manufacturing a semiconductor device, wherein the etch stop layer and the second material layers include the same material. The method of claim 11,
Forming the insulating film,
Forming trenches penetrating the etch stop layer; And
And forming the insulating layer on the etch stop layer so that the vertical portions fill the trenches. The method of claim 11,
The step of replacing the second material layers with the line patterns may include:
Removing the second material layers through the slit such that opening regions are defined between the first material layers adjacent to each other in a stacking direction of the first material layers and the second material layers;
Forming a blocking insulating film on each surface of the opening regions;
Filling the opening regions and forming a conductive layer disposed on the blocking insulating layer; And
And forming the line patterns separated from each other by etching the conductive layer. The method of claim 16,
During the removal of the second material layers, a part of the etch stop layer disposed between the slit and the vertical portions is removed, so that an undercut region exposing the vertical portions is defined. The method of claim 17,
The blocking insulating film is a method of manufacturing a semiconductor device that extends to cover a sidewall facing the slit of each of the first material films and a surface of the undercut region. The method of claim 11,
And forming channel structures penetrating the etch stop layer and the laminate,
The insulating film further comprises a horizontal portion disposed on the etch stop layer to cover the channel structures. The method of claim 19,
And forming contact plugs penetrating the insulating film to be connected to the channel structures, respectively.

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