KR20200053887A - Display Apparatus - Google Patents

Abstract

The present invention relates to a display device which can improve uniformity of brightness of a display panel. The display device comprises: an active region including a first region having a release portion and a second region having no release portion; and a bezel region including a third region adjacent to the first region and having the release portion and a fourth region adjacent to the second region and having no release portion. The display device comprises: a power supply electrode disposed in the third region of the bezel region; a second dummy gate line disposed in the third region of the bezel region, and overlapping the power supply electrode to form a first compensation capacitance; and a first dummy gate line disposed in the third region of the bezel region, and overlapping the second dummy gate line to form a second compensation capacitance.

Description

Display Apparatus

This specification relates to a display device.

As the information society develops, the demand for a display device for displaying images is increasing in various forms. For example, it has rapidly developed into a thin, light and large-area display device that replaces a bulky cathode ray tube (CRT). As such a display device, an electroluminescent display device such as a liquid crystal display (LCD), an organic light emitting display (OLED), and a quantum dot light emitting display (QLED) ( Various display devices such as electroluminescent display (EL), field emission display (FED), and electrophoretic display (ED) have been developed and utilized.

Such display devices include a display panel including display elements for displaying information, a driving unit for driving the display panel, and a power supply unit for generating power to be supplied to the display panel and the driving unit.

These display devices may be designed to have various designs according to the use environment or use, and correspondingly, a display panel displaying an image may also be formed from a conventional single square shape, such as a partial curved surface or a notch such as a notch. ), As well as various shapes ranging from round to oval.

In this way, a display device having a release portion or a display panel formed of a circular or elliptical shape has an advantage in that it can appeal to consumers who value design aspects in that it can increase the degree of freedom in product design.

However, the number of pixels arranged for each line (for example, a horizontal line) in the release portion of the display panel where the curved surface or the notch is formed and the non-release portion of the display panel may differ (eg, the line of the release portion and the non-release portion) Deviation of the RC load (resistor-capacitor load) occurs due to a difference in the number of pixels arranged for each signal, which causes a delay in signal between lines, and this causes a problem in luminance unevenness of the display panel and display quality. There may be a problem that this decreases.

The present specification provides a display device capable of improving luminance unevenness of the display panel by compensating for the RC load of the release portion to correspond to the RC load according to the difference in the number of pixels in the region including the release portion of the display panel and the region not including the release portion. It is to provide.

The display device according to the exemplary embodiment of the present specification includes an active region including a first region having a release portion and a second region having no release portion, and a third region and a second region adjacent to the first region and having a release portion. And a bezel region including a fourth region having no release portion. The display device includes a power supply electrode disposed in a third area of the bezel area, a second dummy gate line disposed in a third area of the bezel area, and overlapping the power supply electrode to form a first compensation capacitance, and a bezel area The first dummy gate line may be disposed in the third region and overlap the second dummy gate line to form a second compensation capacitance.

According to the display device of the present specification, the RC load per gate line can be increased by arranging at least one compensation unit in the bezel area of the display panel having the release unit, and thus it can be compensated to be close to the RC load for each gate line of the non-release unit. It is possible to obtain an effect of improving luminance unevenness of the display panel.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present specification.
FIG. 2 is a plan view schematically showing the shape of the display panel shown in FIG. 1.
3 is a plan view showing R1 shown in FIG. 2.
4 is a cross-sectional view showing a structure in the pixel P shown in FIG. 1.
FIG. 5 is an enlarged plan view of a portion of the first compensation unit of FIG. 3.
6A is a cross-sectional view taken along line A-A 'in FIG. 5;
6B is a cross-sectional view taken along line B-B 'in FIG. 5.
7 is an enlarged plan view of a portion of the third compensation unit of FIG. 3.
8A is a cross-sectional view taken along line A-A 'in FIG. 7;
8B is a cross-sectional view taken along line B-B 'in FIG. 7.
9 is a graph showing a comparison between luminance before compensation and luminance of a display device after compensation according to an exemplary embodiment of the present specification.
FIG. 10 is an enlarged plan view of a portion of the first compensation unit of FIG. 3.
11 is a cross-sectional view of the line CC ′ of FIG. 10.
12 is an enlarged plan view of a portion of the third compensation unit of FIG. 3.
13 is a cross-sectional view taken along line CC ′ in FIG. 12.
14 is an enlarged plan view of a portion of the third compensation unit of FIG. 3.
15A is a cross-sectional view taken along line D-D 'in FIG. 14;
15B is a cross-sectional view taken along line E-E 'in FIG. 14;

Advantages and features of the present specification, and a method of achieving them will be apparent with reference to embodiments described below in detail together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present specification to be complete, and common knowledge in the art to which this specification belongs It is provided to completely inform the person who has the scope of the specification, and this specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present specification are exemplary and are not limited to the details shown in the present specification. The same reference numerals refer to the same components throughout the specification. In addition, in the description of the present specification, when it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present specification, the detailed description will be omitted. When 'include', 'have', 'consist of', etc. mentioned in this specification are used, other parts may be added unless '~ only' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, if the positional relationship of the two parts is described as '~ on', '~ on the top', '~ on the bottom', '~ next to', etc. Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

The first, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be the second component within the technical spirit of the present specification.

Each of the features of the various embodiments of the present specification may be partially or totally combined with or combined with each other, technically various interlocking and driving may be possible, and each of the embodiments may be independently implemented with respect to each other or may be implemented together in an associative relationship. It might be.

Hereinafter, a display device according to embodiments of the present disclosure will be described with reference to the accompanying drawings. Throughout the specification, the same reference numerals refer to substantially the same components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present specification may unnecessarily obscure the subject matter of the present specification, the detailed description will be omitted or briefly described.

Hereinafter, a display device according to an exemplary embodiment of the present specification will be described with reference to FIGS. 1 to 3.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present specification, and FIG. 2 is a plan view schematically showing the shape of the display panel illustrated in FIG. 1. FIG. 3 is a plan view illustrating a partial region R1 of the display panel illustrated in FIG. 2.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present specification includes a display panel 10, a data driver, a gate driver of a gate in panel (GIP) type, a power supply unit (PS), and a timing controller (TC). can do.

The display panel 10 may include an active area AA displaying information and a bezel area BA displaying no information.

The active area AA is an area in which an input image is displayed, and may be an area in which a plurality of pixels P are arranged in a matrix type.

The bezel area BA includes shift registers SRa and SRb of the gate driving circuit, gate link signal wirings GL1 to GLn, data link signal wirings DL1 to DLn, and first link power supply lines VDL1, VDL2), second link power supply lines (VSL1, VSL2), and power supply electrodes (VDLa, VDLb) and the like may be disposed. The active area AA includes a plurality of data lines D1 to Dn and a plurality of gate lines G1 to Gn arranged to cross each other, and pixels P arranged in a matrix form for each of the crossing areas. Can be.

Each pixel P is a light-emitting diode (LED), a driving thin film transistor (Thin Film Transistor, hereinafter referred to as TFT) that controls the amount of current flowing through the light-emitting diode (LED), and the gate-source voltage of the driving TFT (DT). It may include a programming unit (SC) for setting. The pixels P of the display panel 10 may receive the first power supply Vdd, which is a high potential voltage, through the first power supply lines VD1 to VDm from the power supply unit PS, and supply the second link power supply. The second power source Vss, which is a low potential voltage, may be supplied through the lines VSL1 and VSL2.

The first power lines VD1 to VDm include the lower first power supply electrode VDLa disposed in the bezel region BA on the side where the chip-on film 30 is attached, and the upper first disposed in the opposite bezel region. The first power source Vdd may be supplied from the power supply unit PS on both sides through the power supply electrode VDLb. Both ends of the lower first power supply electrode VDLa and the upper first power supply electrode VDLb may be connected to each other by first link power supply lines VDL1 and VDL2. However, the present invention is not limited thereto, and the lower first power supply electrode VDLa is formed by the first power lines VD1 to VDm without forming the first link power supply lines VDL1 and VDL2 connecting the both ends to each other. The upper first power supply electrodes VDLb may be connected to each other. Accordingly, it is possible to obtain an effect of minimizing a decrease in display quality due to an increase in RC according to the position of the pixels arranged in the active area AA.

The programming unit SC may include at least one switch TFT and at least one storage capacitor. The switch TFT is turned on in response to the scan signal from the gate lines G1 to Gn, thereby applying the data voltage from the data lines D1 to Dn to one electrode of the storage capacitor. The driving TFT DT may control the amount of current supplied to the light emitting diode LED according to the magnitude of the voltage charged in the storage capacitor to control the amount of light emission of the light emitting diode LED. The amount of light emitted by the light emitting diode (LED) may be proportional to the amount of current supplied from the driving TFT (DT).

The TFTs constituting the pixel P may be implemented in p-type or n-type. In addition, the semiconductor layer of the TFTs constituting the pixel P may include at least one of amorphous silicon, polysilicon, or oxide semiconductor material. The light emitting diode (LED) includes an anode electrode, a cathode electrode, and a light emitting structure interposed between the anode electrode and the cathode electrode. The anode electrode can be connected to the driving TFT (DT). The light emitting structure includes an emission layer (EML), a hole injection layer (HIL) and a hole transport layer (HTL) on one side with an emission layer interposed therebetween, and an electron transport layer (HTL) on the other side. Electron transport layer (ETL) and electron injection layer (EIL) may be disposed, respectively.

The data driver SD data SD may be mounted. In addition, one side may be connected to one end of the source printed circuit board 20, and the other side may include a chip-on film 30 attached to the bezel area BA of the display panel 10.

The data IC SD may convert digital video data input from the timing controller TC into an analog gamma compensation voltage to generate a data voltage. The data voltage output from the data IC SD may be supplied to the data lines D1 to Dn.

The GIP type gate driver is formed on the level shifters LSa and LSb mounted on the source printed circuit board 20, and the bezel areas BA of the display panel 10, and is provided from the level shifters LSa and LSb. It may include a shift register (SRa, SRb) for receiving the supplied signal.

The level shifters LSa and LSb may receive signals such as a start pulse ST, gate shift clocks GLCK, and a flicker signal FLK from the timing controller TC. Further, driving voltages such as a gate high voltage VGH and a gate low voltage VGL may be supplied. The start pulse ST, the gate shift clocks GCLK, and the flicker signal FLK may be signals swinging between approximately 0V and 3.3V. The gate shift clocks GLCK1 to n may be n-phase clock signals having a predetermined phase difference. The gate high voltage VGH is a voltage equal to or greater than a threshold voltage of the thin film transistor TFT formed on the thin film transistor array of the display panel 10, and may be a voltage of about 28V, and the gate low voltage VGL is the display panel 10. As a voltage lower than a threshold voltage of the thin film transistor TFT formed on the thin film transistor array, the voltage may be approximately -5 V, but is not limited thereto.

The level shifter LS is a shift clock signal in which the start pulse ST input from the timing controller TC and each of the gate shift clocks GLCK are level shifted to the gate high voltage VGH and the gate low voltage VGL. The CLK can be output. Therefore, each of the start pulse VST and the shift clock signals CLK output from the level shifter LS can swing between the gate high voltage VGH and the gate low voltage VGL. The level shifter LS may reduce the flicker by lowering the gate high voltage according to the flicker signal FLK to lower the kickback voltage ΔVp of the liquid crystal cell.

The output signals of the level shifter LS are shift registers through wirings formed on the chip-on film 30 on which the source drive IC SD is disposed and LOG (Line On Glass) wirings formed on the substrate of the display panel 10. SR). The shift register SR may be directly formed on the bezel area BA of the display panel 10 by a GIP process.

The shift register SR is a gate pulse that swings between the gate high voltage and the gate low voltage VGL by shifting the start pulse VST input from the level shifter LS according to the gate shift clock signals CLK1 to CLKn. Can be shifted sequentially. Gate pulses output from the shift register SR are sequentially supplied to the gate lines G1 to Gn.

The timing controller TC receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a main clock input from a host system (not shown), and receives data IC SD and gate drivers LSa and LSb. , SRa, SRb) are synchronized. The data timing control signal for controlling the data IC SD may include a source sampling clock (SSC), a source output enable signal (SOE), and the like. The gate timing control signals for controlling the gate drivers LSa, LSb, SRa, and SRb are gate start pulse (GSP), gate shift clock (GSC), and gate output enable signal (Gate Output). Enable, GOE).

In Fig. 1, the shift registers SRa and SRb are arranged on both sides outside the active area AA to supply gate pulses to the gate lines G1 to Gn at both ends of the active area AA. The specification is not limited thereto, and the shift register may be disposed only on one side of the active area AA to supply gate pulses to the gate lines G1 to Gn at one side of the active area AA. When the shift registers SRa and SRb are disposed on both sides outside the active area AA, gate pulses of the same phase and the same amplitude may be supplied to the pixels P disposed on the same horizontal line through the gate line.

Referring to FIG. 2, the display panel 10 of the present specification may include an active area AA and a bezel area BA outside the active area AA.

The active area AA is an area in which the pixels P are arranged, and includes a first area (a line b to a line d and a line e to a line f) having a free form portion. ) And a second region (regions from line d to line e) having no release portion. In addition, the first region having a release portion may include a first region 1a, which is an area from line b to a line d, and a first region b, which is an area from line e to line f. For example, as illustrated in FIG. 2, the first region 1a may be a region including a curved portion RO and a notch portion in a first region having a release portion in the display panel 10, and the first region 1b The region may be a region including only the curved portion RO.

The bezel area BA is an area surrounding the active area AA outside the active area AA, and has a third area (a line a to a line d and a line e having a release portion similar to the active area AA). To a line g) and a fourth region (a region from line d to line e) having no release portion. In addition, the third area having the release portion may include a third area (a) from line a to line d, and a third area (b) from line e to line g. For example, as illustrated in FIG. 2, the first region 1a includes a curved portion RO and a notch portion NO in a third region of the bezel region BA having a release portion in the display panel 10. The third area may be an area including only the curved portion RO.

The release portion may have at least one of a curved portion RO having a round shape at an edge portion of the display panel 10 and a notch portion NO having a predetermined area removed along one side of the display panel 10.

In the example of FIG. 2, although the curved portion RO and the notch portion NO are simultaneously shown, the notched portion NO shows a release portion formed at the center of one side of the display panel 10, but the present specification is limited to this. no. For example, the mold release portion may include only a curved portion, or only a notch portion, or a notch portion may be formed at an edge portion. Therefore, the example of FIG. 2 should not be interpreted as reducing the scope of the present specification.

As illustrated in FIG. 2, the active area AA may include a first area including a release part and a second area not including a release part. In addition, the first area (the area from line b to line d and the area from line e to line f) includes the first area (a area from line b to line d) and the first area (from line e to line f) Of the region). The number of pixels P arranged in each horizontal line in the second area (the area from line d to line e) in which the number of pixels P arranged in each horizontal line in the first area of the active area AA does not have a release part. There is no choice but to be less. For example, as illustrated in FIG. 3, the number of pixels P corresponding to the gate lines G4a and G4b disposed in the first region of the first region corresponds to the gate line G6 disposed in the second region. It may be less than the number of pixels (P). Accordingly, a difference in R-C load (resistor-capacitor load) may occur according to a difference in the number of pixels, which may cause a problem that the luminance is uneven. Accordingly, display quality may deteriorate.

In order to solve the problem of luminance non-uniformity in this specification, as illustrated in FIG. 3, at least one of the third region of the bezel region BA in which pixels are not formed to compensate for luminance non-uniformity of the first region and the second region The first to third load compensators DCA1, DCA2, and DCA3 are arranged.

In FIG. 3, the first area of the active area AA in the display panel 10 by the notch part NO is shown to include first and second sub-active areas divided horizontally, but the present specification is limited thereto. It does not work. For example, a plurality of notches NO may be disposed on either the left or right side of the active area AA, or a central portion. Therefore, the example of FIG. 3 should not be interpreted as reducing the protection scope of the present specification.

Referring to FIG. 3, the display panel 10 according to an exemplary embodiment of the present specification may include an active area AA and a bezel area BA. The active area AA may include a first area having a release part and a second area not having a release part. In addition, the first region may include a 1a region including the notch NO and the curved portion RO and a 1b region including the curved portion RO. The bezel area BA is positioned adjacent to the active area AA and may be disposed to surround the active area AA. In addition, the bezel region BA may include a third region having a release portion and a fourth region having no release portion. The third region may include a 3a region including the notch NO and the curved portion RO and a 3b region including the curved portion RO. In addition, the 3a region of the bezel region BA may be disposed adjacent to the 1a region of the active region AA, and the 3b region of the bezel region BA may be disposed adjacent to the 1b region of the active region AA. Can be. In addition, the 3a region of the bezel region BA may have the same release portion as the 1a region of the active region AA, and the 3b region of the bezel region BA may have the same release portion as the active region AA 1b region. Can have

In FIG. 3, first and second regions of the active region AA and third and fourth regions of the bezel region BA will be described. In addition, in order to simplify the description in FIG. 3, four gate lines extending in a horizontal direction to intersect with the first power lines VD1 to VDm in the first area of the first area in the active area AA of FIG. 2. The case where these are arranged side by side will be described as an example.

In addition, it will be described as an example that each of the pixels P in the active area AA corresponding to the first area and the second area has the same size.

When four gate lines are disposed in the first region of the first region, the two first and second gate lines disposed in the upper region of the first region are first and second gate pulses from the left shift register SRa. 1a and 2a gate lines G1a and G2a which are sequentially supplied with and 1b and 2b gate lines G1b and G2b which are sequentially supplied with the first and second gate pulses from the right shift register SRb. ).

Referring to FIG. 3, the first area 1a of the active area AA may include first and second sub-active areas divided left and right by the notch NO. The first and second gate lines G1a and G2a disposed in the first sub-active region located on the left side of the first-a region may extend from the first sub-active region to the third region of the bezel region BA. For example, the 1a and 2a gate lines G1a and G2a disposed in the first sub-active region of the 1a region may extend from the first sub-active region to the first compensation region located to the left of the 3a region. Can be. The 1a and 2a gate lines G1a and G2a are formed in a different layer from the 1a and 2a gate lines G1a and G2a in the first compensation area of the bezel area BA, and the 1a dummy gate line GD1a ) And the 2a dummy gate line GD2a. The 1a gate line G1a and the 1a dummy gate line GD1a may be connected to have an “inverted c” shape. In addition, the 2a gate line G2a and the 2a dummy gate line GD2a may be connected to have an “inverted c” shape.

The 1b and 2b gate lines G1b and G2b disposed in the second sub-active region located on the right side of the 1a region may extend from the second sub-active region to the 3a region of the bezel region BA. For example, the 1b and 2b gate lines G1b and G2b disposed in the second sub-active region of the 1a region may extend from the second sub-active region to the second compensation region located to the right of the 3a region. Can be. The 1b and 2b gate lines G1b and G2b are formed on a different layer from the first and second gate lines G1b and G2b in the second compensation region in the bezel region BA, and the first dummy gate line GD1b ) And the 2b dummy gate line GD2b. The 1b gate line G1b and the 1b dummy gate line GD1b may be connected to have a “c” shape. In addition, the 2b gate line G2b and the 2b dummy gate line GD2b may be connected to have a “c” shape.

The display panel 10 includes first and second dummy gate lines GD1a and GD2a disposed in a first compensation area positioned to the left of the 3a area in the bezel area BA and the first power supply electrode VDLb. The first compensation unit DCA1 formed by overlapping, and the first and second dummy gate lines GD1b and GD2b disposed in the second compensation area located on the right side of the 3a area are the first power supply electrodes VDLb. It may include a second compensation unit (DCA2) formed by overlapping.

In addition, when four gate lines are disposed in the first region of the first region, two third and fourth gate lines disposed in the lower region of the first region are third and fourth from the left shift register SRa. 3a and 4a gate lines G3a and G4a that are sequentially supplied with gate pulses, and 3b and 4b gate lines G3b that are sequentially supplied with the third and fourth gate pulses from the right shift register SRb. , G4b).

For example, when four gate lines are disposed in the first region of the first region, two third and fourth gate lines G3a and G4a disposed in the lower region of the first sub-active region of the first region. Arrangement of the 3a region of the bezel region BA in the notch part of the two 3b and 4b gate lines G3b and G4b disposed in the lower region of the second sub active region of the 1a region and the 1a region The third and fourth dummy gate lines GD3 and GD4 may be connected to each other.

Referring to FIG. 3, the 3a and 4a gate lines G3a and G4a of the first sub active region and the 3b and 4b gate lines G3b and G4b of the second sub active region and the first sub active region The third and fourth dummy gate lines GD3 and GD4 may be connected to each other by the third and fourth dummy gate lines GD3 and GD4 disposed in the third compensation area of the third area of the bezel area BA positioned between the second sub-active areas.

The display panel 10 is formed by overlapping the first and second dummy gate lines GD3 and GD4 with the first power supply electrode VDLb disposed in the third compensation area located in the center of the 3a area. 3 may include a compensation unit (DCA3).

The first compensator DCA1 and the second compensator DCA2 of the display panel 10 will be described in more detail with reference to FIGS. 5 and 6A and 6B, and the third compensator DCA3 will be illustrated in FIG. 7. And it will be described in more detail with reference to Figures 8a and 8b.

Since the positions in which the first compensator DCA1 and the second compensator DCA2 are formed are different and have substantially the same structure, in the following description with reference to FIGS. 5, 6A, and 6B, the first compensator DCA1 ) As an example, the description of the second compensation unit DCA2 is also provided.

Before describing the first to third compensation units DCA1, DCA2, and DCA3, the cross-sectional structure of the pixel P in the active area AA will be described with reference to FIG. 4.

4 is a cross-sectional view illustrating structures of a thin film transistor (TFT), a storage capacitor (Cst), and a light emitting diode (LED) in the pixel P shown in FIG. 1.

Referring to FIG. 4, a buffer layer BUF having a single layer or a multi-layer structure may be disposed on the substrate SUB. The substrate SUB may be formed of a flexible translucent material. In the buffer layer BUF, when the substrate SUB is formed of a material such as polyimide, inorganic and organic materials are used to prevent damage to the light emitting device from impurities such as alkali ions flowing out of the substrate SUB in a subsequent process. It may be formed of a single layer composed of any one of. In addition, the buffer layer BUF may be formed of multiple layers formed of different inorganic materials. Also, the buffer layer BUF may be formed of multiple layers formed of an organic material layer and an inorganic material layer. The inorganic material layer may include any one of a silicon oxide film (SiOx) and a silicon nitride film (SiNx), but is not limited thereto. The organic material may include photo acrylic, but is not limited thereto.

The semiconductor layer A may be disposed on the buffer layer BUF. The semiconductor layer A may include a source region SA and a drain region DA spaced apart with the channel region CA interposed therebetween. The source region SA and the drain region DA may be conductor regions. The semiconductor layer A may be formed using amorphous silicon or polycrystalline silicon crystallized from amorphous silicon. Alternatively, the semiconductor layer A may be formed of any one of zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), or zinc tin oxide (ZnSnO), but is not limited thereto. In addition, the semiconductor layer (A) may be made of a low-molecular-based or high-molecular-based organic material such as methocyanine, phthalocyanine, pentacene, and thiophene polymer, but is not limited thereto.

The gate insulating layer GI may be disposed to cover or cover the semiconductor layer A on the buffer layer BUF on which the semiconductor layer A is disposed. The gate insulating layer GI may be formed of a single layer made of an inorganic material or multiple layers made of different inorganic materials. For example, the gate insulating layer GI may be formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or multiple layers thereof, but is not limited thereto.

The gate electrode GE of the thin film transistor TFT and a gate line connected to the gate electrode GE are disposed on the gate insulating layer GI such that the channel layer CA of the semiconductor layer A overlaps at least a portion of the region. Can be. The first electrode C1 of the storage capacitor Cst may be disposed on the gate insulating layer GI. The gate electrode GE and the gate line and the first electrode C1 are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) ), Or an alloy thereof, and may be formed of a single layer or multiple layers, but is not limited thereto.

The first interlayer insulating layer INT1 may be disposed on the gate insulating layer GI on which the gate electrode GE and the first electrode C1 of the gate line and the storage capacitor Cst are disposed. The first interlayer insulating layer INT1 may be formed of a single layer made of an inorganic material or multiple layers made of different inorganic materials. For example, the gate insulating layer GI may be formed of a silicon oxide film (SiOx) or a silicon nitride film (SiNx), but is not limited thereto.

The second electrode C2 of the storage capacitor Cst may be disposed on the first interlayer insulating layer INT1 so as to overlap the first electrode C1. The second electrode C2 may be one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or alloys thereof. And may be composed of a single layer or multiple layers, but is not limited thereto.

In addition, the second interlayer insulating layer INT2 may be disposed to cover the second electrode C2 of the storage capacitor Cst. The second interlayer insulating layer INT2 may be formed of a single layer made of an inorganic material or multiple layers made of different inorganic materials. For example, the second interlayer insulating film INT2 may be formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof, but is not limited thereto.

The source electrode SE and the drain electrode DE of the thin film transistor TFT may be disposed on the second interlayer insulating layer INT2. The third electrode C3 may also be disposed on the second interlayer insulating layer INT2 so as to overlap the second electrode C2 of the storage capacitor Cst. The source electrode SE and the drain electrode DE are the source region SA and the drain of the semiconductor layer exposed through the contact holes passing through the gate insulating layer GI, the first and second interlayer insulating layers INT1 and INT2, Each may be connected to the areas DA. The third electrode C3 of the storage capacitor Cst may be connected to the second electrode C2 exposed through the contact hole of the second interlayer insulating layer INT2. The source electrode SE, the drain electrode DE, and the third electrode C3 of the storage capacitor Cst are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), and titanium (Ti). , One of nickel (Ni) and copper (Cu), or an alloy thereof, may be composed of a single layer or multiple layers, but is not limited thereto.

A passivation layer PAS covering the source electrode SE, the drain electrode DE, and the third electrode C3 of the storage capacitor Cst may be disposed. The passivation film (PAS) may be formed of a single layer made of an inorganic material or multiple layers made of different inorganic materials. For example, the passivation film (PAS) may be formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof, but is not limited thereto.

In addition, the first planarization layer PLN1 may be disposed on the passivation layer PAS. The first planarization layer PLN1 is to protect the lower structure while alleviating the step difference of the lower structure, and may be formed of an organic material layer. For example, the first planarization layer PLN1 may be formed of a photo acrylic layer. A connection electrode CON for connecting the anode electrode ANO of the light emitting diode (LED), which will be described later, to the drain electrode DE may be disposed on the first planarization layer PLN1. Also, a fourth electrode C4 connected to the third electrode C3 of the storage capacitor Cst may be disposed on the first planarization layer PL1. The connection electrode CON is connected to the drain electrode DE of the thin film transistor TFT exposed through the contact hole of the first planarization film PLN1 and the passivation film PAS, and the fourth of the storage capacitor Cst. The electrode C4 may be connected to the third electrode C3 of the storage capacitor Cst exposed through the contact hole of the first planarization layer PLN1 and the passivation layer PAS. The connecting electrode CON and the fourth electrode C4 of the storage capacitor Cst are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper It may be one of (Cu), or an alloy thereof, and may be formed of a single layer or multiple layers, but is not limited thereto.

The second planarization layer PLN2 may be disposed on the first planarization layer PLN1 to cover the connection electrode CON and the fourth electrode C4 of the storage capacitor Cst. The second planarization layer PLN2 may be a planarization layer that further protects the substructure while alleviating the step difference between the connection electrode CON on the first planarization layer PL and the fourth electrode C4 of the storage capacitor. have. The second planarization layer PLN2 may be formed of an organic material layer. For example, the second planarization layer PLN2 may be formed of a siloxane-based organic material, but is not limited thereto.

The anode electrode ANO may be disposed on the second planarization layer PLN2. The anode electrode ANO is connected to the connection electrode CN exposed through the contact hole passing through the second planarization layer PLN2. The anode electrode (ANO) may be formed of a transparent conductive material such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or Zinc Oxide (ZnO), but is not limited thereto.

A bank layer BN having an opening exposing the anode electrode ANO may be formed on the second planarization layer PLN2.

The opening of the bank layer BN may be an area defining an emission area. A light emitting laminate LES and a cathode electrode CAT may be stacked on the anode electrode ANO exposed through the emission region of the bank layer BL. The light emitting laminate (LES) may include a hole transport layer, a light emitting layer, and an electron transport layer. The cathode electrode CAT may be formed of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having a low work function, but is not limited thereto. In the present specification, it has been described that the light emitting stack (LES) is disposed on the anode electrode (ANO) and the cathode electrode (CAT) is disposed on the light emitting stack (LES), but the light emitting stack is on the cathode electrode (CAT). Water (LES) may be disposed, and an anode electrode (ANO) may be disposed on the light emitting laminate (LES).

An encapsulation layer ENC may be disposed on the second planarization layer PLN2 to cover the cathode electrode CA and the bank layer BL. The encapsulation layer ENC is for preventing moisture or oxygen from outside from penetrating into the luminescent laminate LES located inside the encapsulation layer ENC, and may be formed in a multi-layer structure in which the inorganic layer and the organic layer are alternately arranged. .

Next, the first compensation unit DCA1 and the second compensation unit DCA2 of the display panel 10 will be described in more detail with reference to FIGS. 3, 5 and 6A, and 6B. FIG. 5 is an enlarged plan view of a portion of the first compensation unit DCA of FIG. 3, and FIG. 6A is a cross-sectional view taken along the line A-A 'in FIG. 5. In addition, FIG. 6B is a cross-sectional view taken along line B-B 'in FIG. 5.

5 and 6A and 6B, the first compensation unit DCA1 of the display panel 10 includes a buffer layer BUF disposed on the substrate SUB and a semiconductor pattern disposed on the buffer layer BUF. ACT). The semiconductor pattern ACT of the first compensation unit DCA1 may be formed by the same process as the semiconductor layer A of the thin film transistor TFT. It can be formed on the same layer. In addition, the semiconductor pattern ACT of the first compensation unit DCA1 may be formed of the same material as the semiconductor layer A of the thin film transistor TFT. The semiconductor pattern ACT of the first compensation unit DCA1 may be a layer of a semiconductor material. The conductor formation of the semiconductor pattern ACT of the first compensation unit DCA1 is formed by conductor formation when the source region SA and the drain region DA of the semiconductor layer A of the thin film transistor TFT are conductive. Can be. The semiconductor pattern ACT of the first compensation unit DCA1 may include a plurality of semiconductor patterns (eg, ACT1 to ACT3). The gate insulating layer GI may be disposed on the buffer layer BUF to cover the semiconductor pattern ACT.

5 and 6A and 6B, a second gate line G2a and a first gate line G1a may be arranged side by side on the gate insulating layer GI.

In addition, the first interlayer insulating layer INT1 may be disposed on the gate insulating layer GI to cover or cover the 1a gate line G2a and the 1b gate line G1a. On the first interlayer insulating layer INT1, the 2a dummy gate line GD2a and the 1a dummy gate line GD1a are aligned with each other so that at least a portion overlaps the 2a gate line G2a and the 1a gate line G1a. Can be deployed. The 2a dummy gate line GD2a is connected to the 2a gate line G2a through the second contact hole CH2 passing through the first interlayer insulating layer INT1, and the 1a dummy gate line GD1a is the first. The first contact gate CH1 through the interlayer insulating layer INT1 may be connected to the first gate line G1a. 6A and 6B, the 1a gate line G2a and the 1b gate line G1a may be formed by the same process as the gate electrode GE of the thin film transistor TFT, and are formed on the same layer. Can be. In addition, the 1a gate line G2a and the 1b gate line G1a may be formed of the same material as the gate electrode GE of the thin film transistor TFT. In addition, the 1a dummy gate line GD1a and the 2a dummy gate line GD1b may be formed by the same process as the second electrode C2 of the storage capacitor Cst. It can be formed on the same layer. In addition, the 1a dummy gate line GD1a and the 2a dummy gate line GD2a may be formed of the same material as the second electrode C2 of the storage capacitor Cst.

5 and 6A and 6B, the 1a dummy gate line GD1a and the 2a dummy gate line GD1b are arranged to overlap a plurality of semiconductor patterns (eg, ACT1, ACT2, and ACT3). Can be. A plurality of semiconductor patterns to compensate for a capacitance value generated according to a difference between the number of pixels in the first region of the first region having the release portion in the active region AA and the number of pixels in the second region without the release portion. The areas where the (ACT1, ACT2, ACT3) and the 1a dummy gate line GD1a and the 2a dummy gate line GD1b overlap may be differently formed. For example, by using the number or size of the semiconductor patterns ACT, areas overlapping the semiconductor patterns ACT and the 1a dummy gate line GD1a and the 2a dummy gate line GD1b may be formed differently. . Alternatively, by adjusting the width or length of at least one of the first dummy gate line GD1a and the second dummy gate line GD1b, the semiconductor pattern ACT, the first dummy gate line GD1a, and the second dummy gate line An area where (GD1b) overlaps may be formed differently. Specifically, in FIG. 5, the 1a dummy gate line GD1a and the 2a dummy gate line GD1b are shown in a straight line, but may also be formed in a concave-convex shape or a stepped shape having a bend. As described above, when the 1a dummy gate line GD1a and the 2a dummy gate line GD1b are formed in an uneven or stepped shape, the lengths of the 1a dummy gate line GD1a are formed in a straight line as shown in FIG. 5. ) And the second dummy gate line GD1b. Accordingly, an area where the semiconductor pattern ACT overlaps the first dummy gate line GD1a and the second dummy gate line GD1b may increase. In addition, the capacitance value for compensation may be increased.

The second interlayer insulating layer INT2 may be disposed on the first interlayer insulating layer ILD1 to cover the 1a dummy gate line GD1a and the 2a dummy gate line GD2a.

A second power supply electrode VDLb overlapping the second dummy gate line GD2a and the first dummy gate line GD1a may be disposed on the second interlayer insulating layer INT2. The first power supply electrode VDLb is a semiconductor pattern through third and fourth contact holes CH3 and CH4 penetrating through the second interlayer insulating layer INT2, the first interlayer insulating layer INT1, and the gate insulating layer GI. (ACT). The first power supply electrode VDLb may overlap the plurality of semiconductor patterns ACT1, ACT2, and ACT3. In addition, the first power supply electrode VDLb may be disposed adjacent to the first area of the active area AA. In addition, the first power supply electrode VDLb may be disposed in the 3a region of the bezel region BA.

A passivation film (PAS) for protecting the first power supply electrode VDLb may be disposed on the first power supply electrode VDLb.

At least one layer of the first planarization layer PLN1, the second planarization layer PLN2, and the encapsulation layer ENC may be formed on the passivation layer PAS.

The second compensator DCA2 is formed similarly to the first compensator DCA1 and may be formed in the same manner as the first compensator DCA1, so the same description will be omitted.

Next, the third compensation unit DCA3 of the display panel 10 will be described in more detail with reference to FIGS. 3, 7, and 8A and 8B.

FIG. 7 is an enlarged plan view of a portion of the third compensation unit DCA3 of FIG. 3, and FIG. 8A is a cross-sectional view of FIG. 7 taken along line A-A '. 8B is a cross-sectional view taken along the line B-B '.

7 and 8A and 8B, the third compensation unit DCA3 of the display panel 10 includes a buffer layer BUF disposed on the substrate SUB and a plurality of semiconductors disposed on the buffer layer BUF. Patterns (eg, ACT5, ACT6, ACT7). The semiconductor pattern ACT of the third compensation unit DCA3 may be formed by the same process as the semiconductor layer A of the thin film transistor TFT. It can be formed on the same layer. In addition, the semiconductor pattern ACT of the third compensation unit DCA3 may be formed of the same material as the semiconductor layer A of the thin film transistor TFT. The semiconductor pattern ACT of the third compensation unit DCA3 may be a layer of a semiconductor material. The conductor formation of the semiconductor pattern ACT of the third compensation unit DCA3 is formed by conductor formation when the source region SA and the drain region DA of the semiconductor layer A of the thin film transistor TFT are conductors. Can be. A gate insulating layer GI may be disposed on the buffer layer BUF to cover or cover the semiconductor patterns ACT5, ACT6, and ACT7.

3, 7 and 8A and 8B, a third gate line G3a and a third gate line G3b may be disposed separately on the same line on the gate insulating layer GI. In addition, the 4a gate line G4a and the 4b gate line G4b may be disposed separately from each other. The 3a gate line G3a and the 4a gate line G3a may be arranged side by side. In addition, the 3b gate line G3b and the 4b gate line G4b may be arranged side by side.

The first interlayer insulating layer INT1 is disposed on the gate insulating layer GI to cover the 3a gate line G3a and the 3b gate line G3b and the 4a gate line G4a and the 4b gate line G4b. Can be. A third dummy gate line GD3 may be disposed on the first interlayer insulating layer INT1 so as to overlap one end of the 3a gate line G3a and one end of the 3b gate line G3b, and the 4a gate line The fourth dummy gate line GD4 may be disposed to overlap one end of the G4a and one end of the fourth gate line G4b.

The third dummy gate line GD3 may be connected to the 3a and 3b gate lines G3a and G3b, respectively, through the fifth contact holes CH5 passing through the first interlayer insulating layer INT1. The fourth dummy gate line GD4 may be connected to the 4a and 4b gate lines G4a and G4b, respectively, through the sixth contact holes CH6 passing through the first interlayer insulating layer INT1.

The 3a gate line G3a, the 3b gate line G3b, the 4a gate line G4a, and the 4b gate line G4b are formed by the same process as the gate electrode GE of the thin film transistor TFT. Can be, and can be formed on the same layer. In addition, the 3a gate line G3a, the 3b gate line G3b, the 4a gate line G4a, and the 4b gate line G4b are made of the same material as the gate electrode GE of the thin film transistor TFT. Can be formed. In addition, the third dummy gate line GD3 and the fourth dummy gate line GD4 may be formed by the same process as the second electrode C2 of the storage capacitor Cst. It can be formed on the same layer. In addition, the third dummy gate line GD3 and the fourth dummy gate line GD4 may be formed of the same material as the second electrode C2 of the storage capacitor Cst.

Referring to FIGS. 7, 8A, and 8B, on the first interlayer insulating layer INT1, the second interlayer insulating layer INT2 is formed to cover or cover the third dummy gate line GD3 and the fourth dummy gate line GD4. ) May be disposed.

A first power supply electrode VDLb overlapping the third dummy gate line GD3 and the fourth dummy gate line GD4 may be disposed on the second interlayer insulating layer INT2. The seventh and eighth contacts through which the first power supply electrode VDLb passes through the second interlayer insulating layer INT2, the first interlayer insulating layer INT1, and the gate insulating layer GI to expose the semiconductor patterns ACT5 and ACT6. The semiconductor patterns ACT5 and ACT6 may be respectively connected to the holes CH7 and CH8. Further, the first power supply electrode VDLb may overlap the plurality of semiconductor patterns ACT5, ACT6, and ACT7. In addition, the first power supply electrode VDLb may be disposed adjacent to the first area of the active area AA. In addition, the first power supply electrode VDLb may be disposed in the 3a region of the bezel region BA.

A passivation film (PAS) for protecting the first power supply electrode VDLb may be disposed on the first power supply electrode VDLb.

The first compensation unit DCA1 according to the above-described configuration is formed by each dummy gate line GD1a or GD2a and the first power supply electrode VDLb, as shown in FIGS. 5 and 6A and 6B. The first compensation component of the first compensation capacitances DC1 and the second compensation capacitances DC2 formed by each dummy gate line GD1a or GD2a and the plurality of semiconductor patterns ACT1, ACT2, and ACT2. It may include a second compensation component.

In addition, the second compensation unit DCA2, like the first compensation unit DCA1, has first compensation capacitances DC1 formed by each dummy gate line GD1b or GD2b and the first power supply electrode VDLb. And a second compensation component of each of the dummy gate lines GD1b or GD2b and the second compensation capacitances DC2 formed by the plurality of semiconductor patterns.

The third compensation unit DCA3 includes first compensation capacitances formed by each dummy gate line GD3 or GD4 and the first power supply electrode VDLb, as shown in FIGS. 7 and 8A and 8B. The first compensation component of (DC1), the second compensation component of the second compensation capacitances (DC2) formed by each dummy gate line (GD3 or GD4) and a plurality of semiconductor patterns (ACT5, ACT6, ACT7) It can contain.

Accordingly, in the display device according to the exemplary embodiment of the present specification, the display panel 10 includes a first compensation unit DCA1 and a second compensation unit having a double compensation capacitor structure of the first capacitance C1 and the second capacitance C2. The compensation capacitance DCA2 can maximize the compensation capacitance in a limited space of the 3a region of the bezel region BA positioned adjacent to the first and second sub-active regions. In addition, since the third compensation unit DCA3 has a double compensation capacitor structure similar to that of the first compensation unit DCA1, the third compensation region Da3 is limited to the notch portion NO of the active region AA. The compensation capacitance in space can be maximized. For example, since the third compensation unit DCA also has a double compensation capacitor structure similar to the first compensation unit DCA1, the bezel area BA corresponding to the area between the first and second sub-active areas The compensation capacitance can be maximized in the 3a region. Accordingly, since the RC load per pixel line can be increased through the first compensation unit DCA1, the second compensation unit DCA2, and the third compensation unit DAC3 located in the 3a area of the bezel area, the active area It is possible to compensate to approximate the RC load per pixel line disposed in the second region, which is the non-deformed portion of (AA), thereby obtaining an effect of improving luminance unevenness of the display panel.

Next, a luminance improvement effect obtained by the display device according to the exemplary embodiment of the present specification will be described with reference to FIG. 9.

9 is a graph showing a change in luminance of a display device in which a compensation unit is not formed and a change in luminance of a display device in which a compensation unit is formed according to an exemplary embodiment of the present specification. In FIG. 9, a solid line represents a change in luminance of a display device in which a compensation unit is not formed, and a dotted line represents a change in luminance of a display device in which a compensation unit is formed according to an embodiment of the present specification. In FIG. 9, the reference luminance of the display device is set to 150 nits.

In FIG. 9, the horizontal axis represents a gate line (1-30 th line) corresponding to the bc section of the 1a region of the display device illustrated in FIG. 2, and a gate line (30-90 th) corresponding to the cd section of the 1a region. Line), and a gate line (90-120th line) corresponding to the de section of the second region. In addition, the vertical axis represents the change in luminance of the display device. 0% on the vertical axis indicates that there is no change in luminance of the display device compared to the reference luminance of 150 nit.

Referring to FIG. 9, when looking at a solid line indicating a change in luminance of a display device in which the compensation unit is not formed, there is no change in luminance in the de section of the second region, which is the active region having the non-deformation portion, but the active region 1a, which has the release portion It can be seen that a change in luminance occurs in the bc and cd sections of the region. Therefore, it can be seen that the amount of change in luminance compared to the reference luminance is about 6% to 18%.

Referring to FIG. 9, when looking at a dotted line indicating a change in luminance of a display device having a compensation unit according to an exemplary embodiment of the present specification, as well as a de-section of a second region as an active region having a non-deformation portion, a first region as an active region having a release portion It can be seen that there is no change in luminance even in the bc and cd sections of. From the graph above, through the first compensation unit DCA1, the second compensation unit DCA2, and the third compensation unit DCA3 located in the 3a area of the bezel area BA, the active area AA including the release unit AA It can be seen that by increasing the RC load of the gate line located in the 1a region of), it can be compensated to approximate the RC load of each gate line located in the second region of the active region AA having a non-releasing portion.

The first compensation unit DCA1, the second compensation unit DCA2, and the third compensation unit DAC3 disposed in the third area of the bezel area BA adjacent to the first area A of the active area AA are Since it is possible to increase the RC load for each gate line of the 1a region, it is possible to compensate for the proximity of the RC load for each gate line of the second region in the active region AA, thereby improving luminance unevenness of the display panel. You can get the effect.

FIG. 10 is an enlarged plan view of a portion of the first compensation unit DCA1 of FIG. 3, and FIG. 11 is a cross-sectional view of the line C-C 'of FIG. 10. In the description of FIGS. 10 and 11, descriptions will be made with reference to FIGS. 3, 5, and 6A and 6B, and descriptions of overlapping parts will be omitted or briefly described.

Referring to FIGS. 10 and 11, the first compensation unit DCA1 of the display panel 10 includes a buffer layer BUF disposed on the substrate SUB and a semiconductor pattern ACT disposed on the buffer layer BUF. It can contain. The semiconductor pattern ACT of the first compensation unit DCA1 may be formed by the same process as the semiconductor layer A of the thin film transistor TFT. It can be formed on the same layer. In addition, the semiconductor pattern ACT of the first compensation unit DCA1 may be formed of the same material as the semiconductor layer A of the thin film transistor TFT. The semiconductor pattern ACT of the first compensation unit DCA1 may be a layer of a semiconductor material. The conductor formation of the semiconductor pattern ACT of the first compensation unit DCA1 is formed by conductor formation when the source region SA and the drain region DA of the semiconductor layer A of the thin film transistor TFT are conductive. Can be. The semiconductor pattern ACT of the first compensation unit DCA1 may include a plurality of semiconductor patterns (eg, ACT1 to ACT3).

Referring to FIG. 10, the 1a dummy gate line GD1a and the 2a dummy gate line GD1b may be arranged to overlap a plurality of semiconductor patterns (eg, ACT1, ACT2, and ACT3). A plurality of semiconductor patterns to compensate for a capacitance value generated according to a difference between the number of pixels in the first region of the first region having the release portion in the active region AA and the number of pixels in the second region without the release portion. The areas where the (ACT1, ACT2, ACT3) and the 1a dummy gate line GD1a and the 2a dummy gate line GD1b overlap may be differently formed.

For example, by using the number or size of the semiconductor patterns ACT, areas overlapping the semiconductor patterns ACT and the 1a dummy gate line GD1a and the 2a dummy gate line GD1b may be formed differently. . Then, the width or length of at least one of the 1a dummy gate line GD1a and the 2a dummy gate line GD1b is adjusted to adjust the semiconductor pattern ACT, the 1a dummy gate line GD1a, and the 2a dummy gate line. An area where (GD1b) overlaps may be formed differently.

In addition, the first opening portion OP1 may be formed on the semiconductor pattern ACT to form a different area overlapping the semiconductor pattern ACT, the first dummy gate line GD1a, and the second dummy gate line GD1b. have. For example, as illustrated in FIGS. 10 and 11, the first opening part may be removed by removing some regions of the semiconductor pattern ACT overlapping the first dummy gate line GD1a and the second dummy gate line GD1b. (OP1) can be formed. The width of the first opening OP1 may be formed to be larger than the widths of the first dummy gate line GD1a and the second dummy gate line GD1b.

Depending on the capacitance value for compensation, the width of the first opening portion OP1 may be smaller than the widths of the first dummy gate line GD1a and the second dummy gate line GD1b.

Referring to FIG. 10, the first opening portion OP1 is positioned in the semiconductor pattern ACT, and a plurality of first opening portions OP1 may be formed.

The gate insulating layer GI and the first interlayer insulating layer INT1 may be disposed to cover or cover the semiconductor pattern ACT and the first opening portion OP1 on the buffer layer BUF. In addition, the 1a dummy gate line GD1a and the 2a dummy gate line GD1b may be disposed on the first interlayer insulating layer INT to overlap the semiconductor pattern ACT and the first opening OP1.

In addition, the 1a dummy gate line GD1a and the 2a dummy gate line GD1b may be formed by the same process as the second electrode C2 of the storage capacitor Cst. It can be formed on the same layer. In addition, the 1a dummy gate line GD1a and the 2a dummy gate line GD2a may be formed of the same material as the second electrode C2 of the storage capacitor Cst.

Referring to FIG. 11, a second interlayer insulating layer INT2 may be disposed on the first interlayer insulating layer ILD1 so as to cover or cover the 1a dummy gate line GD1a and the 2a dummy gate line GD2a.

A second power supply electrode VDLb overlapping the second dummy gate line GD2a and the first dummy gate line GD1a may be disposed on the second interlayer insulating layer INT2. The first power supply electrode VDLb is connected to the semiconductor pattern ACT through a third contact hole CH3 penetrating through the second interlayer insulating film INT2, the first interlayer insulating film INT1, and the gate insulating film GI. Can be. Further, the first power supply electrode VDLb may overlap the plurality of semiconductor patterns ACT1, ACT2, and ACT3. Also, a partial opening of the first power supply electrode VDLb overlapping the 1a dummy gate line GD1a and the 2a dummy gate line GD1b may be removed to form the second opening OP2. The width of the second opening portion OP2 may be formed to be larger than the widths of the first dummy gate line GD1a and the second dummy gate line GD1b. Depending on the capacitance value for compensation, the width of the second opening OP2 may be smaller than the widths of the first dummy gate line GD1a and the second dummy gate line GD1b. In addition, the second opening portion OP2 may be disposed to overlap the semiconductor pattern ACT.

Referring to FIG. 11, the third contact hole CH3 penetrating the second interlayer insulating layer INT2, the first interlayer insulating layer INT1, and the gate insulating layer GI to expose the semiconductor pattern ACT is a first dummy gate. It may be disposed on both sides of the line GD1a and the 2a dummy gate line GD1b, and may not be overlapped with the first opening OP1 of the semiconductor pattern ACT. For example, the 3a contact hole CH3a and the 3b contact hole CH3b may be disposed on both sides of the 1a dummy gate line GD1a, and the 3b contact hole CH3b and the 3c contact hole CH3c ) May be disposed on both sides of the first dummy gate line GD1a. In addition, the 3a contact hole CH3a, the 3b contact hole CH3b, and the 3c contact hole CH3c may be disposed so as not to overlap the first opening OP1 of the semiconductor pattern ACT.

In addition, the second opening OP2 of the first power supply electrode VDLb may be disposed to overlap the first dummy gate line GD1a and the second dummy gate line GD1b. Also, the second opening portion OP2 of the first power supply electrode VDLb may be disposed so as not to overlap the first opening portion OP1 of the semiconductor pattern ACT. Also, the second opening OP2 of the first power supply electrode VDLb may be disposed so as not to overlap the third contact hole CH3.

The first power supply electrode VDLb may overlap the first opening OP1 of the semiconductor pattern ACT.

In addition, the first power supply electrode VDLb may be disposed adjacent to the 1a region of the active region AA, as shown in FIG. 3. In addition, the first power supply electrode VDLb may be disposed in the 3a region of the bezel region BA.

The first power supply electrode VDLb may be formed by the same process as the source electrode SE and drain electrode DE of the thin film transistor TFT. It can be formed on the same layer. In addition, the first power supply electrode VDLb may be formed of the same material as the source electrode SE and the drain electrode DE of the thin film transistor TFT.

The first opening OP1 of the semiconductor pattern ACT overlaps the first dummy gate line GD1a and the second dummy gate line GD1b, and overlaps the first power supply electrode VDLb, thereby opening the first opening. A region in which the portion OP1 is disposed may have a single compensation capacitor structure including only the first compensation component of the first compensation capacitance DC1. The first compensation capacitance DC1 has a structure in which the 1a dummy gate line GD1a and the 2a dummy gate line GD1b overlap the first power supply electrode VDLb with the second interlayer insulating layer INT2 interposed therebetween. Can be

The second opening OP2 of the first power supply electrode VDLb overlaps the semiconductor pattern ACT, and overlaps the first dummy gate line GD1a and the second dummy gate line GD1b. A region in which the opening part OP2 is disposed may have a single compensation capacitor structure including only the second compensation component of the second compensation capacitance DC2. The first compensation dummy gate line GD1a and the second dummy gate line GD1b are interposed between the gate insulating layer GI and the first interlayer insulating layer INT1 as the second compensation capacitance DC2. It may be a superimposed structure.

A passivation film (PAS) for protecting the first power supply electrode VDLb may be disposed on the first power supply electrode VDLb.

At least one layer of the first planarization layer PLN1, the second planarization layer PLN2, and the encapsulation layer ENC may be formed on the passivation layer PAS.

The second compensator DCA2 is formed similarly to the first compensator DCA1 and is formed in the same manner as the first compensator DCA1, so a description thereof will be omitted.

FIG. 12 is an enlarged plan view of a portion of the third compensation unit DCA3 of FIG. 3, and FIG. 13 is a cross-sectional view of line C-C 'of FIG. 12. 12 and 13 will be described with reference to FIGS. 3, 7, and 8A and 8B, and descriptions of overlapping parts will be omitted or briefly described.

Referring to FIG. 12, the third compensation unit DCA3 of the display panel 10 includes a buffer layer BUF disposed on the substrate SUB and a plurality of semiconductor patterns disposed on the buffer layer BUF (for example, ACT5, ACT6, ACT7). The semiconductor pattern ACT of the third compensation unit DCA3 may be formed by the same process as the semiconductor layer A of the thin film transistor TFT. It can be formed on the same layer. In addition, the semiconductor pattern ACT of the third compensation unit DCA3 may be formed of the same material as the semiconductor layer A of the thin film transistor TFT. The semiconductor pattern ACT of the third compensation unit DCA3 may be a layer of a semiconductor material. The conductor formation of the semiconductor pattern ACT of the third compensation unit DCA3 is formed by conductor formation when the source region SA and the drain region DA of the semiconductor layer A of the thin film transistor TFT are conductive. Can be. A gate insulating layer GI may be disposed on the buffer layer BUF to cover the semiconductor patterns ACT5, ACT6, and ACT7.

Referring to FIG. 12, the third dummy gate line GD3 and the fourth dummy gate line GD4 may be disposed to overlap a plurality of semiconductor patterns (eg, ACT5, ACT6, and ACT7). A plurality of semiconductor patterns to compensate for a capacitance value generated according to a difference between the number of pixels in the first region of the first region having the release portion in the active region AA and the number of pixels in the second region without the release portion. The areas where (ACT5, ACT6, and ACT7) overlap with the third dummy gate line GD3 and the fourth dummy gate line GD4 may be formed differently.

For example, the area overlapping the semiconductor pattern ACT, the third dummy gate line GD3, and the fourth dummy gate line GD4 may be differently formed using the number or size of the semiconductor patterns ACT. . Then, at least one width or length of the third dummy gate line GD3 and the fourth dummy gate line GD4 is adjusted to adjust the semiconductor pattern ACT, the third dummy gate line GD3, and the fourth dummy gate line. An area where (GD4) overlaps may be formed differently.

In addition, the third opening portion OP3 may be formed on the semiconductor pattern ACT to form a different area where the semiconductor pattern ACT overlaps the third dummy gate line GD3 and the fourth dummy gate line GD4. have. For example, as illustrated in FIGS. 12 and 13, a third opening portion may be removed by removing a portion of the semiconductor pattern ACT overlapping the third dummy gate line GD3 and the fourth dummy gate line GD4. (OP3) can be formed. The width of the third opening OP3 may be larger than that of the third dummy gate line GD3 and the fourth dummy gate line GD4.

Depending on the capacitance value for compensation, the width of the third opening OP3 may be smaller than that of the third dummy gate line GD3 and the fourth dummy gate line GD4.

Referring to FIG. 12, the third opening OP3 is positioned in the semiconductor pattern ACT, and a plurality of third openings OP3 may be formed.

Referring to FIG. 13, a gate insulating layer GI and a first interlayer insulating layer INT1 may be disposed on the buffer layer BUF to cover the semiconductor pattern ACT and the third opening portion OP3. In addition, the third dummy gate line GD3 and the fourth dummy gate line GD4 may be disposed on the first interlayer insulating layer INT to overlap the semiconductor pattern ACT and the third opening OP3.

In addition, the third dummy gate line GD3 and the fourth dummy gate line GD4 may be formed by the same process as the second electrode C2 of the storage capacitor Cst. It can be formed on the same layer. In addition, the third dummy gate line GD3 and the fourth dummy gate line GD4 may be formed of the same material as the second electrode C2 of the storage capacitor Cst.

In addition, the second interlayer insulating layer INT2 may be disposed on the first interlayer insulating layer INT1 to cover or cover the third dummy gate line GD3 and the fourth dummy gate line GD4.

A first power supply electrode VDLb overlapping the third dummy gate line GD3 and the fourth dummy gate line GD4 may be disposed on the second interlayer insulating layer INT2. The seventh and eighth contacts through which the first power supply electrode VDLb passes through the second interlayer insulating layer INT2, the first interlayer insulating layer INT1, and the gate insulating layer GI to expose the semiconductor patterns ACT5 and ACT6. The semiconductor patterns ACT5 and ACT6 may be respectively connected to the holes CH7 and CH8. Further, the first power supply electrode VDLb may overlap the plurality of semiconductor patterns ACT5, ACT6, and ACT7. In addition, the first power supply electrode VDLb may be disposed adjacent to the first area of the active area AA. In addition, the first power supply electrode VDLb may be disposed in the 3a region of the bezel region BA.

The fourth opening part OP4 may be formed by removing a portion of the first power supply electrode VDLb overlapping the third dummy gate line GD3 and the fourth dummy gate line GD4. The width of the fourth opening portion OP4 may be larger than that of the third dummy gate line GD3 and the fourth dummy gate line GD4. Depending on the capacitance value for compensation, the width of the fourth opening OP4 may be smaller than the width of the third dummy gate line GD3 and the fourth dummy gate line GD4. In addition, the fourth opening OP4 may be disposed to overlap the semiconductor pattern ACT.

Referring to FIG. 13, a seventh contact hole CH7 exposing the semiconductor pattern ACT through the second interlayer insulating layer INT2, the first interlayer insulating layer INT1, and the gate insulating layer GI is a third dummy gate It may be disposed on both sides of the line GD3 and the fourth dummy gate line GD4, and may not be overlapped with the third opening OP3 of the semiconductor pattern ACT. For example, the 7a contact hole CH7a and the 7b contact hole CH7b may be disposed on both sides of the third dummy gate line GD3, and the 7b contact hole CH7b and the 7c contact hole CH7c ) May be disposed on both sides of the fourth dummy gate line GD4. In addition, the 7a contact hole CH7a, the 7b contact hole CH7b, and the 7c contact hole CH7c may be disposed so as not to overlap the third opening OP3 of the semiconductor pattern ACT.

The fourth opening OP4 of the first power supply electrode VDLb may be disposed to overlap the third dummy gate line GD3 and the fourth dummy gate line GD4. In addition, the fourth opening portion OP4 of the first power supply electrode VDLb may be disposed so as not to overlap the third opening portion OP3 of the semiconductor pattern ACT. Also, the fourth opening OP4 of the first power supply electrode VDLb may be disposed so as not to overlap the seventh contact hole CH7.

The first power supply electrode VDLb may overlap the third opening OP3 of the semiconductor pattern ACT.

The third opening OP3 of the semiconductor pattern ACT overlaps the third dummy gate line GD3 and the fourth dummy gate line GD4 and overlaps the first power supply electrode VDLb, thereby opening the third opening A region in which the portion OP3 is disposed may have a single compensation capacitor structure including only the first compensation component of the first compensation capacitance DC1. The first compensation capacitance DC1 has a structure in which the third dummy gate line GD3 and the fourth dummy gate line GD4 overlap the first power supply electrode VDLb with the second interlayer insulating layer INT2 interposed therebetween. Can be

The fourth opening OP4 of the first power supply electrode VDLb overlaps the semiconductor pattern ACT, and overlaps the third dummy gate line GD3 and the fourth dummy gate line GD4. A region in which the opening part OP2 is disposed may have a single compensation capacitor structure including only the second compensation component of the second compensation capacitance DC2. In the second compensation capacitance DC2, the third dummy gate line GD3 and the fourth dummy gate line GD4 are interposed between the gate insulating layer GI and the first interlayer insulating layer INT1 and the semiconductor pattern ACT. It can be a superimposed structure.

A passivation film (PAS) for protecting the first power supply electrode VDLb may be disposed on the first power supply electrode VDLb. In addition, at least one layer of the first planarization film PLN1, the second planarization film PLN2, and the encapsulation layer ENC may be formed on the passivation film PAS.

14 is an enlarged plan view of a portion of the third compensation unit DCA3 of FIG. 3, and FIG. 15A is a cross-sectional view of the line D-D 'of FIG. 14. And, Figure 15b is a cross-sectional view of the line E-E 'of Figure 14. 14, 15A, and 15B will be described with reference to FIGS. 3, 7, and 8A, and 8B, and descriptions of overlapping parts will be omitted or briefly described.

14 and 15A, the third compensation unit DCA3 of the display panel 10 includes a buffer layer BUF disposed on the substrate SUB and a gate insulating layer GI disposed on the buffer layer BUF. And a third dummy gate line GD3 disposed on the gate insulating layer GI. The third dummy gate line GD3 of the third compensation unit DCA3 may be formed to extend from the 3a gate line G3a and the 3b gate line G3b. In addition, the third dummy gate line GD3 may be integrally formed with the 3a gate line G3a and the 3b gate line G3b. The third dummy gate line GD3 may be integrally formed by extending from one end of the 3a gate line G3a and one end of the 3b gate line G3b. The third dummy gate line GD3, the 3a gate line G3a, and the 3b gate line G3b may be formed integrally with each other. In addition, the third dummy gate line GD3 has at least one protrusion, and the protrusion of the third dummy gate line GD3 overlaps the fourth dummy gate line GD4 with the first interlayer insulating layer INT1 interposed therebetween. can do. The third dummy gate line GD3 may have an uneven structure, and the protrusion of the third dummy gate line GD3 having an uneven structure may have a fourth dummy gate line GD4 with the first interlayer insulating layer INT1 interposed therebetween. And can overlap.

The first interlayer insulating layer INT1 may be disposed on the gate insulating layer GI to cover or cover the third dummy gate line GD3. In addition, the fourth dummy gate line GD4 may be disposed on the first interlayer insulating layer INT1. Referring to FIG. 14, the fourth dummy gate line GD4 may be arranged to overlap the protrusion of the third dummy gate line GD3.

14 and 15B, the fourth dummy gate line GD4 may be disposed to overlap one end of the fourth gate line G4a and one end of the fourth gate line G4b. The fourth dummy gate line GD4 may be connected to the 4a and 4b gate lines G4a and G4b, respectively, through the sixth contact holes CH6 passing through the first interlayer insulating layer INT1.

In addition, the fourth dummy gate line GD4 has at least one protrusion, and the protrusion of the fourth dummy gate line GD4 overlaps the third dummy gate line GD3 and the first interlayer insulating layer INT1. can do. The fourth dummy gate line GD4 may have an uneven structure, and the protrusion of the fourth dummy gate line GD4 having an uneven structure may have a third dummy gate line GD3 with the first interlayer insulating layer INT1 interposed therebetween. And can overlap.

A concavo-convex structure so as to compensate for a capacitance value generated according to a difference between the number of pixels in the first region of the first region having the release portion in the active region AA and the number of pixels in the second region without the release portion An area where the third dummy gate line GD3 and the fourth dummy gate line GD4 having an uneven structure overlap may be formed differently. For example, by adjusting the width, number, or length of the protrusions of the third dummy gate line GD3 overlapping the fourth dummy gate line GD4, the third dummy gate line GD3 and the fourth dummy gate The area where the line GD4 overlaps may be formed differently, or the width, number, or length of the protrusions of the fourth dummy gate line GD4 overlapping the third dummy gate line GD3 may be adjusted to adjust the third area. An area where the dummy gate line GD3 and the fourth dummy gate line GD4 overlap may be formed differently.

The third dummy gate line GD3, the 3a gate line G3a, the 3b gate line G3b, the 4a gate line G4a, and the 4b gate line G4b are gate electrodes of the thin film transistor TFT. It may be formed by the same process as (GE), it may be formed on the same layer. In addition, the third dummy gate line GD3, the third gate line G3a, the third gate line G3b, the fourth gate line G4a, and the fourth gate line G4b are the thin film transistor TFT. It may be formed of the same material as the gate electrode GE.

In addition, the fourth dummy gate line GD4 may be formed by the same process as the second electrode C2 of the storage capacitor Cst. It can be formed on the same layer. In addition, the fourth dummy gate line GD4 may be formed of the same material as the second electrode C2 of the storage capacitor Cst.

In addition, referring to FIG. 15A, the second interlayer insulating layer INT2 may be disposed to cover or cover the fourth dummy gate line GD4 on the first interlayer insulating layer INT1 and the fourth dummy gate line GD4. have.

A first power supply electrode VDLb overlapping the third dummy gate line GD3 and the fourth dummy gate line GD4 may be disposed on the second interlayer insulating layer INT2. A passivation layer PAS for protecting the first power supply electrode VDLb may be disposed on the first power supply electrode VDLb.

The first power supply electrode VDLb may be disposed adjacent to the first area 1a of the active area AA. In addition, the first power supply electrode VDLb may be disposed in the 3a region of the bezel region BA.

The third compensation unit DCA3 is the first compensation of the third compensation capacitances DC3 formed by the fourth dummy gate line GD4 and the first power supply electrode VDLb, as illustrated in FIG. 15A. A component and a second compensation component of the fourth compensation capacitances DC4 formed by the third dummy gate line GD3 and the fourth dummy gate line GD4 may be included.

As described above, since the structure of the compensation capacitances can be simplified, wiring can be effectively formed in the cutout area BA of the narrow display panel 10. By utilizing the second electrode C2 of the gate line or the storage capacitor Cst formed in the active area AA, the compensation capacitance structure can be effectively performed within the limited space of the bezel area BA. Accordingly, a compensation capacitance structure formed in the first compensation part DCA1 and the second compensation part DCA2 may be formed in the third compensation part DCA3 which is the third compensation area.

For example, referring to FIG. 3, the first area 1a of the active area AA may include first and second sub-active areas divided left and right by the notch NO. One end of the first a gate line G1a disposed in the first sub active area located on the left side of the first a region, and the first b gate line G1b disposed in the second sub active region located on the right side of the first a region. One end of may be extended to the third compensation area (DCA3) which is the third compensation area. In addition, the first dummy gate line GD1 is connected to each other as one end of the 1a gate line G1a and one end of the 1b gate line G1b extend to the third compensation area DCA3, which is the third compensation area. Can be formed. Accordingly, the first dummy gate line GD1 may be integrally formed with the first gate line G1a and the first gate line G1b. The first dummy gate line GD1 is formed by connecting one end of the 1a gate line G1a and one end of the 1b gate line G1b to each other while being extended to the third compensation area, so that the third compensation part DCA3 Can be placed on. In addition, the first dummy gate line GD1 may have at least one protrusion.

The protrusions of the first dummy gate line GD1 may overlap the second dummy gate line GD2 and the first interlayer insulating layer INT1. The first dummy gate line GD1 may have an uneven structure, and a protrusion of the first dummy gate line GD1 having an uneven structure may be provided between the second dummy gate line GD2 and the first interlayer insulating layer INT1. Can be placed and nested.

The first dummy gate line GD1, the first a gate line G1a, and the first b gate line G1b are formed of the same material and may be disposed on the same layer.

In addition, the 2a gate line G2a disposed in the first sub active region located on the left side of the 1a region and the 2b gate line G2b disposed in the second sub active region located on the right side of the 1a region include The third compensation area DCA3 may be extended. In addition, the second dummy gate line GD2 is disposed in the third compensation area DCA3 which is the third compensation area so as to overlap one end of the second gate line G2a and one end of the second gate line G2b. Can be. The second dummy gate line GD2 may be respectively connected to the second and second gate lines G2a and G2b through the contact hole of the first interlayer insulating layer INT2.

In addition, the second dummy gate line GD2 may have at least one protrusion, and the protrusion of the second dummy gate line GD2 may include the first dummy gate line GD1 with the first interlayer insulating layer INT1 interposed therebetween. ). The second dummy gate line GD2 may have an uneven structure, and the protrusion of the second dummy gate line GD2 having an uneven structure may have the first dummy gate line GD1 with the first interlayer insulating layer INT1 interposed therebetween. And can overlap.

The first dummy gate line GD1, the first a gate line G1a, the first b gate line G1b, the second a gate line G2a, and the second b gate line G2b are gate electrodes of the thin film transistor TFT. It may be formed by the same process as (GE), or may be formed on the same layer. In addition, the first dummy gate line GD1, the first a gate line G1a, the first b gate line G1b, the second a gate line G2a, and the second b gate line G2b are the thin film transistor TFT. It may be formed of the same material as the gate electrode GE.

In addition, the second dummy gate line GD2 may be formed by the same process as the second electrode C2 of the storage capacitor Cst. It can be formed on the same layer. In addition, the second dummy gate line GD2 may be formed of the same material as the second electrode C2 of the storage capacitor Cst.

In addition, the first power supply electrode VDLb may overlap the second dummy gate line GD4 with the second interlayer insulating layer INT2 therebetween.

The third compensation unit DCA3 includes a first compensation component of the first compensation capacitances DC1 formed by the fourth dummy gate line GD4 and the first power supply electrode VDLb, and a third dummy gate line ( GD3) and a second compensation component of the second compensation capacitances DC2 formed by the fourth dummy gate line GD4. In addition, the first compensation component of the first compensation capacitances DC1 formed by the second dummy gate line GD2 and the first power supply electrode VDLb, and the first dummy gate line GD1 and The second compensation component of the second compensation capacitances DC2 formed by the two dummy gate lines GD2 may be further included.

As in the exemplary embodiment of the present specification, the active area AA is divided left and right by the notch NO, and may be formed of a first sub-active area disposed on the left side and a second sub-active region disposed on the right side. Further, the plurality of gate lines formed in the first sub-active region and the second sub-active region may include a plurality of dummy gate lines disposed in the bezel region BA positioned between the first sub-active region and the second sub-active region. Each can be connected. In addition, the plurality of dummy gate lines may be formed of an uneven structure having a protrusion, and the protrusions formed on the plurality of dummy gate lines may overlap the adjacent dummy gate lines to form the first compensation capacitance DC1. In addition, the second compensation capacitance DC2 may be formed by overlapping the power supply electrodes disposed on the plurality of dummy gate lines.

The display device according to the present specification may be described as follows.

The display device according to the exemplary embodiment of the present specification includes an active region including a first region having a release portion and a second region having no release portion, and a third region and a second region adjacent to the first region and having a release portion. And a bezel region including a fourth region having no release portion. The display device includes a power supply electrode disposed in a third area of the bezel area, a second dummy gate line disposed in a third area of the bezel area, and overlapping the power supply electrode to form a first compensation capacitance, and a bezel area The first dummy gate line may be disposed in the third region and overlap the second dummy gate line to form a second compensation capacitance.

According to the exemplary embodiment of the present specification, the first region of the active region includes a 1a region including a curved portion and a notch having one side of the active region removed, and a 1b region including only a curved portion, and a bezel region. The third region may include a 3a region adjacent to the 1a region and a 3b region adjacent to the 1b region. According to the exemplary embodiment of the present specification, the 1a region including the notch portion may include first and second sub-active regions divided left and right by the notch portion. According to the exemplary embodiment of the present specification, a first a gate line and a second gate line disposed in the first sub active region and a first b gate line and a second b gate line disposed in the second sub active region may be included. According to the exemplary embodiment of the present specification, the first dummy gate line and the second dummy gate line may be disposed in the third region of the bezel region positioned between the first sub-active region and the second sub-active region. According to the exemplary embodiment of the present specification, the first dummy gate line is connected to the first a gate line disposed in the first sub-active region and the first b gate line disposed in the second sub-active region, and the second dummy gate line is the first dummy gate line. It may be connected to the 2a gate line disposed in the 1 sub active region and the 2b gate line disposed in the second sub active region.

According to the exemplary embodiment of the present specification, the first dummy gate line, the first a gate line, the first b gate line, the second a gate line, and the second gate line are disposed on the gate insulating layer, and the second dummy gate line is the first The first interlayer insulating layer covering the dummy gate line, the 1a gate line, the 1b gate line, the 2a gate line, and the 2b gate line, and the power supply electrode is a second interlayer insulation covering the second dummy gate line The first dummy gate line may have at least one protrusion, and the protrusion of the first dummy gate line may be disposed between the second dummy gate line with the first interlayer insulating film interposed therebetween. The second compensation capacitance may be formed by overlapping. According to the exemplary embodiment of the present specification, the second dummy gate line has at least one protrusion, and the protrusion of the second dummy gate line overlaps the first dummy gate line with the first interlayer insulating film interposed therebetween to obtain a second compensation capacitance. Can form. According to the exemplary embodiment of the present specification, the second dummy gate line may be connected to the second a gate line and the second b gate line through the contact hole of the second interlayer insulating layer. According to the exemplary embodiment of the present specification, the power supply electrode may form a first compensation capacitance by overlapping the second dummy gate line with a second interlayer insulating film therebetween. According to the exemplary embodiment of the present specification, the first dummy gate line may be integrally formed by being connected to the 1a gate line and the 1b gate line. According to the exemplary embodiment of the present specification, a 3a gate line and a 4a gate line disposed in the first sub active region and a 3b gate line and a 4b gate line disposed in the second sub active region may be further included. According to the exemplary embodiment of the present specification, the third dummy gate line and the fourth dummy gate line disposed in the third region of the bezel region positioned between the first sub-active region and the second sub-active region are further included. The dummy gate line may overlap the fourth dummy gate line to form a fourth compensation capacitance, and the fourth dummy gate line may overlap the power supply electrode to form a third compensation capacitance.

According to the exemplary embodiment of the present specification, the third dummy gate line is connected to the 3a gate line disposed in the first sub active region and the third b gate line disposed in the second sub active region, and the fourth dummy gate line is It may be connected to the 4a gate line disposed in the 1 sub active region and the 4b gate line disposed in the second sub active region.

According to the exemplary embodiment of the present specification, the third dummy gate line, the 3a gate line, the 3b gate line, the 4a gate line, and the 4b gate line are disposed on the gate insulating layer, and the fourth dummy gate line is the third The first interlayer insulating layer covering the dummy gate line, the 3a gate line, the 3b gate line, the 4a gate line, and the 4b gate line, and the power supply electrode is a second interlayer insulation covering the fourth dummy gate line It can be placed on the membrane.

According to the exemplary embodiment of the present specification, the third dummy gate line has at least one protrusion, and the protrusion of the third dummy gate line and the fourth dummy gate line overlap each other with the first interlayer insulating film therebetween to overlap the fourth compensation capacitance. To form, and the power supply electrode and the second dummy gate line overlap each other with a second interlayer insulating film therebetween to form a third compensation capacitance.

According to the exemplary embodiment of the present specification, the third dummy gate line is integrally formed and connected to the 3a gate line and the 3b gate line, and the fourth dummy gate line is connected to the fourth a through a contact hole of the second interlayer insulating layer. It may be connected to the gate line and the 4b gate line.

Through the above description, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical idea of the present specification. In the example shown in the present specification, an electroluminescent display device is described as an example, but the present specification is not limited thereto, and a liquid crystal display device (LCD) and a field emission display device (FED) , And an electrophoretic display device (ED). Therefore, the technical scope of the present specification is not limited to the contents described in the detailed description of the specification, but should be determined by the scope of the claims.

10: Display panel
AA: active area
BA: Bezel area
D1 ~ Dn: Data line
GD1a, GD1b, GD2a, GD2b, GD3, GD4: dummy gate line
G1a, G1b, G2a, G2b, G3a, G3b, G4a, G4b, G5 ... Gn: Gate line
DCA1: 1st compensation unit
DCA2: 2nd compensation unit
DCA3: 3rd compensation unit
PS: Power supply
VD1 ~ VDm: 1st power line
VDLa, VDLb: first power supply electrode

Claims (19)

An active region including a first region having a release portion and a second region not having a release portion, a third region adjacent to the first region and having a release portion, and a fourth region adjacent to the second region and having no release portion In the display device including a bezel region including,
A power supply electrode disposed in the third region of the bezel region;
A second dummy gate line disposed in the third region of the bezel region and overlapping the power supply electrode to form a first compensation capacitance; And
And a first dummy gate line disposed in the third region of the bezel region and overlapping the second dummy gate line to form a second compensation capacitance. According to claim 1,
The first region of the active region includes a 1a region including a curved portion having a corner and a notch portion from which one side of the active region is removed, and a 1b region including only the curved portion,
The third area of the bezel area includes a third area adjacent to the first area and a third area adjacent to the first area. According to claim 2,
The first area including the notch portion includes first and second sub-active regions divided left and right by the notch portion. The method of claim 3,
A 1a gate line and a 2a gate line disposed in the first sub-active region; And
And a 1b gate line and a 2b gate line disposed in the second sub-active area. According to claim 3,
The first dummy gate line and the second dummy gate line are disposed in the third region of the bezel region positioned between the first sub active region and the second sub active region. The method of claim 5,
The first dummy gate line is connected to the first a gate line disposed in the first sub active region and the first b gate line disposed in the second sub active region,
The second dummy gate line is connected to the 2a gate line disposed in the first sub-active region and the second b gate line disposed in the second sub-active region. The method of claim 6,
The first dummy gate line, the first a gate line, the first b gate line, the second a gate line, and the second b gate line are disposed on the gate insulating layer,
The second dummy gate line is disposed on a first interlayer insulating layer covering the first dummy gate line, the first a gate line, the first b gate line, the second a gate line, and the second b gate line,
The power supply electrode is disposed on a second interlayer insulating layer covering the second dummy gate line. The method of claim 7,
The first dummy gate line has at least one protrusion, and the protrusion of the first dummy gate line overlaps the second dummy gate line with the first interlayer insulating layer therebetween to form the second compensation capacitance. , Display device. The method of claim 7,
The second dummy gate line has at least one protrusion, and the protrusion of the second dummy gate line overlaps the first dummy gate line with the first interlayer insulating layer therebetween to form the second compensation capacitance. , Display device. The method of claim 7,
The second dummy gate line is connected to the second a gate line and the second b gate line through a contact hole of a second interlayer insulating layer. The method of claim 7,
The power supply electrode overlaps the second dummy gate line with the second interlayer insulating film therebetween to form the first compensation capacitance. The method of claim 7,
The first dummy gate line is connected to the first gate line and the first gate line and is formed integrally with each other. The method of claim 4,
A 3a gate line and a 4a gate line disposed in the first sub-active region; And
And a 3b gate line and a 4b gate line disposed in the second sub-active region. The method of claim 13,
Further comprising a third dummy gate line and a fourth dummy gate line disposed in the third region of the bezel region positioned between the first sub active region and the second sub active region,
The third dummy gate line overlaps the fourth dummy gate line to form a fourth compensation capacitance,
The fourth dummy gate line overlaps the power supply electrode to form a third compensation capacitance. The method of claim 14,
The third dummy gate line is connected to the 3a gate line disposed in the first sub active region and the 3b gate line disposed in the second sub active region,
The fourth dummy gate line is connected to the 4a gate line disposed in the first sub-active region and the 4b gate line disposed in the second sub-active region. The method of claim 15,
The third dummy gate line is connected to the 3a gate line disposed in the first sub active region and the 3b gate line disposed in the second sub active region,
The fourth dummy gate line is connected to the 4a gate line disposed in the first sub-active region and the 4b gate line disposed in the second sub-active region. The method of claim 16,
The third dummy gate line, the 3a gate line, the 3b gate line, the 4a gate line, and the 4b gate line are disposed on the gate insulating layer,
The fourth dummy gate line is disposed on the first interlayer insulating layer covering the third dummy gate line, the 3a gate line, the 3b gate line, the 4a gate line, and the 4b gate line,
The power supply electrode is disposed on a second interlayer insulating layer covering the fourth dummy gate line. The method of claim 17,
The third dummy gate line has at least one protrusion, and the protrusion of the third dummy gate line and the fourth dummy gate line overlap each other with the first interlayer insulating film therebetween to form the fourth compensation capacitance. and
The display device forming the third compensation capacitance by overlapping each other with the second interlayer insulating layer interposed between the power supply electrode and the second dummy gate line. The method of claim 17,
The third dummy gate line is integrally formed and connected to the 3a gate line and the 3b gate line,
The fourth dummy gate line is connected to the fourth a gate line and the fourth b gate line through the contact hole of the second interlayer insulating layer.

Images