KR20200053129A - Circuit element improving snap-back and phase change random access memory element comprising the same - Google Patents

Abstract

Disclosed are a circuit element that alleviates the snap back phenomenon of an ovonic threshold switch (OTS) and a phase change memory element including the same. According to an embodiment, the phase change memory element comprises: a bit line PMOS serving as a switch for the bit line; an OTS disposed under the bit line PMOS; a phase change layer disposed under the OTS; a source line NMOS disposed at the bottom of the phase change layer and serving as a switch for the source line; and a PMOS Diode disposed between the bit line PMOS and the OTS to serve as a variable resistor.

Description

Circuit element that improves the snapback phenomenon of OTS and a phase change memory element including the same {CIRCUIT ELEMENT IMPROVING SNAP-BACK AND PHASE CHANGE RANDOM ACCESS MEMORY ELEMENT COMPRISING THE SAME}

The following embodiments are for improving the snap-back phenomenon of an OTS (Ovonic Threshold Switch) used as a switching element for the selective operation of a memory cell in a phase-change memory element, a technique using a circuit compensation method to be.

The OTS of the phase change memory device is used as a switching device that supports selecting and operating a specific memory cell among memory cells. The OTS maintains an amorphous state and maintains an off state with a high resistance at a voltage below a threshold, and an on state while changing to a low resistance when a voltage above a threshold is applied ( On state).

That is, when a bias (Bias) above a threshold value is applied, the OTS is changed from an off state to an on state. At this time, a very large current is instantaneously generated by a snap-back phenomenon in the memory cell corresponding to the OTS. Is done. The snap-back phenomenon can cause an error in the read operation of the phase change memory device, and a very large current flows instantaneously to change the phase change layer existing as crystalline in the set state to amorphous. have.

Therefore, there is a need for a technique for alleviating and improving the snapback phenomenon.

One embodiment proposes a circuit element that mitigates the snapback phenomenon of the OTS and prevents the crystalline phase change layer from being changed to amorphous in a set state, and a phase change memory device including the same.

In particular, one embodiment proposes a circuit element applicable to a phase change memory of a three-dimensional architecture while alleviating the snapback phenomenon of the OTS and preventing the crystalline phase change layer from being changed to an amorphous state in the set state.

According to an embodiment, a phase-change memory device that improves a snap-back phenomenon of an OTS (Ovonic Threshold Switch) includes: a bit line PMOS serving as a switch for a bit line; An OTS (Ovonic Threshold Switch) disposed under the bit line PMOS; A phase change layer disposed under the OTS; A source line NMOS disposed at the bottom of the phase change layer and serving as a switch for the source line; And a PMOS Diode (Diode Connected PMOS) disposed between the bit line PMOS and the OTS to serve as a variable resistor.

According to one aspect, the PMOS Diode, the amount of current flowing through the resistance value increases as the current flowing through the phase change memory element increases and the gate voltage increases in response to the OTS being turned on. Can be reduced.

According to another aspect, the PMOS diode, by reducing the amount of the current flowing, alleviates the snap-back phenomenon and prevents the crystalline phase change layer from being changed to amorphous in a set state. Can be.

According to an embodiment, a bit line PMOS serving as a switch for a bit line, an OTS (Ovonic Threshold Switch), a phase change layer and a source line NMOS serving as a switch for the source line are used in the phase change memory device. The circuit element is formed of a PMOS Diode (Diode Connected PMOS) disposed between the bit line PMOS and the OTS and serving as a variable resistor.

According to one aspect, the circuit element, as the current flowing through the phase change memory element in response to the OTS is turned on (Turn-on) increases and the gate voltage of the PMOS Diode increases, the resistance of the PMOS Diode The value is increased to reduce the amount of current flowing through the PMOS diode.

According to another aspect, the circuit element, by reducing the amount of current flowing through the PMOS Diode, alleviates the snap-back phenomenon of the OTS and the crystalline phase change layer in the set state is amorphous To prevent it from being changed.

According to an embodiment, a bit line PMOS serving as a switch for a bit line, an OTS (Ovonic Threshold Switch) disposed under the bit line PMOS, a phase change layer disposed under the OTS, and a phase change layer Snap in a phase-change memory device including a source line NMOS that is disposed at the bottom and serves as a switch to the source line, and a PMOS diode (Diode Connected PMOS) that is disposed between the bit line PMOS and the OTS to serve as a variable resistor. An operation method for improving the back phenomenon may include increasing a gate voltage of the PMOS diode as the current flowing through the phase change memory element increases in response to the OTS being turned on; And increasing the gate voltage of the PMOS diode to decrease the amount of current flowing through the PMOS diode as the resistance value of the PMOS diode increases.

According to one aspect, the step of reducing the amount of current flowing through the PMOS diode mitigates the snap-back phenomenon of the OTS and changes the crystalline phase change layer to amorphous in a set state. It may be a step to prevent.

According to an embodiment, a phase-change memory device that improves a snap-back phenomenon of an OTS (Ovonic Threshold Switch) includes: a bit line PMOS serving as a switch for a bit line; An OTS (Ovonic Threshold Switch) disposed under the bit line PMOS; A phase change layer disposed under the OTS; A source line NMOS disposed at the bottom of the phase change layer and serving as a switch for the source line; And in order to mitigate the snap-back phenomenon of the OTS and prevent the crystalline phase change layer from being changed to amorphous in a set state, disposed between the bit line PMOS and the OTS to form the phase. It includes a PMOS Diode (Diode Connected PMOS) that serves as a variable resistor whose resistance value changes according to the current flowing through the change memory element.

According to an embodiment, a bit line PMOS serving as a switch for a bit line, an OTS (Ovonic Threshold Switch), a phase change layer and a source line NMOS serving as a switch for the source line are used in the phase change memory device. The circuit element is disposed between the bit line PMOS and the OTS to mitigate the snap-back phenomenon of the OTS and prevent the crystalline phase change layer from being changed to amorphous in a set state. It is formed of a PMOS Diode (Diode Connected PMOS) that serves as a variable resistor whose resistance value changes according to the current flowing through the phase change memory element.

One embodiment may propose a circuit element that mitigates the snapback phenomenon of the OTS and prevents the crystalline phase change layer from being changed to amorphous in a set state, and a phase change memory device including the same.

Particularly, one embodiment may propose a circuit element applicable to a phase change memory of a 3D architecture while alleviating the snapback phenomenon of the OTS and preventing the crystalline phase change layer from being changed to amorphous in the set state. .

1 is a diagram illustrating a phase change memory device according to an embodiment.
2 is a view for explaining that the phase change memory device according to an embodiment alleviates the snapback phenomenon of the conventional OTS.
3 is a flowchart illustrating an operation method for improving a snap back phenomenon in a phase change memory device according to an embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the embodiments. In addition, the same reference numerals shown in each drawing denote the same members.

In addition, terms used in the present specification (terminology) are terms used to properly represent a preferred embodiment of the present invention, which may vary according to a user, an operator's intention, or customs in the field to which the present invention pertains. Therefore, definitions of these terms should be made based on the contents throughout the specification.

1 is a view showing a phase change memory device according to an embodiment, and FIG. 2 is a view for explaining that the phase change memory device according to an embodiment mitigates the snapback phenomenon of a conventional OTS.

1 to 2, the phase change memory device 100 according to an embodiment includes a bit line PMOS 110 serving as a switch for a bit line, and an OTS (located at the bottom of the bit line PMOS 110). Ovonic Threshold Switch (120), a phase change layer (PCM) 130 disposed at the bottom of the OTS 120, and disposed at the bottom of the phase change layer 130 to serve as a switch for the source line It includes a PMOS Diode (Diode Connected PMOS) 150 which is a circuit element disposed between the source line NMOS 140 and the bit line PMOS 110 and OTS 120.

Here, the OTS 120 is a component that performs a role of selectively switching the voltage applied between the bit line and the source line connected to the phase change memory element 100 to the phase change layer 130, a conventional selection Since the device is configured in the same way as the OTS, detailed description will be omitted.

The phase change layer 130 is a data storage component of the memory cell, and the crystalline state is crystalline (set state with low resistance) and amorphous (reset state with high resistance) by the voltage applied between the bit line and the source line. It can vary between and represent the memory states of binary values [1] and [0] depending on the set state and reset state. Since the phase change layer 130 is configured in the same way as the conventional phase change layer, a detailed description will be omitted.

The circuit element PMOS Diode 150 is formed in a structure in which a diode is connected to the PMOS, and serves as a variable resistor whose resistance value changes according to a current flowing through the phase change memory element.

For example, when a bias greater than or equal to a threshold value is applied and the OTS 120 is turned on, the current flowing through the phase change memory element 100 increases. At this time, as the current flowing through the phase-change memory element 100 increases, the voltage at the top of the OTS 120 increases, and the gate voltage of the PMOS Diode 150 increases so that the resistance value of the PMOS Diode 150 increases. do. Accordingly, since the amount of current flowing through the PMOS Diode 150 is reduced, the PMOS Diode 150 reduces the amount of current flowing as a result, alleviating the snap-back phenomenon and in the Set state. It is possible to prevent the crystalline phase change layer 130 from being changed to amorphous.

For a more specific example, as shown in the graph on the left side of FIG. 2, when a bias over a threshold is applied to a bit line in a conventional phase change memory element, a conventional phase change memory element (more precisely, a memory cell corresponding to OTS) It can be seen that a very large current is generated and flows instantaneously. On the other hand, as shown in the graph on the right in FIG. 2, when a bias of a bit line or higher is applied to the bit line in the phase change memory device 100 according to an embodiment, the resistance value of the PMOS diode 150 changes and the amount of current flowing By reducing, the phase change memory element 100 (more precisely, the memory cell corresponding to the OTS 120) may flow a smaller amount of current than in the prior art. Therefore, the snap back phenomenon can be alleviated, and the phase change layer 130 existing as crystalline in the Set state can be prevented from being changed to amorphous.

As described above, the phase-change memory device 100 according to an embodiment includes a PMOS diode 150 that is a circuit element that serves as a variable resistor whose resistance value changes according to a current flowing through, so that the OTS 120 is turned on. In this case, the amount of current flowing through the PMOS diode 150 is reduced to mitigate the snapback phenomenon of the OTS, and it is possible to prevent the crystalline phase change layer 130 from being changed to amorphous.

In addition, since the above-described PMOS Diode 150 is implemented in a concise structure in which a diode is connected to the PMOS, the phase change memory device 100 according to an embodiment including the PMOS Diode 150 is a highly integrated three-dimensional architecture. It is applicable to the phase change memory.

3 is a flowchart illustrating an operation method for improving a snap back phenomenon in a phase change memory device according to an embodiment.

Referring to FIG. 3, it is assumed that an operation method according to an embodiment is performed in the phase change memory device 100 described above with reference to FIGS. 1 to 2.

The phase change memory device 100 is gated of the PMOS Diode 150 as the current flowing through the phase change memory device 100 increases in response to the OTS 120 being turned on in step S310. Increase the voltage.

Thereafter, in step S320, the phase change memory element 100 increases the gate voltage of the PMOS Diode 150, and as the resistance value of the PMOS Diode 150 increases, the amount of current flowing through the PMOS Diode 150 increases. Reduces it.

Thus, through step S320, the phase change memory element 100 mitigates the snap-back phenomenon of the OTS 120 and the crystalline phase change layer 130 becomes amorphous in the set state. It can be prevented from being changed.

As described above, although the embodiments have been described by a limited embodiment and drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques are performed in a different order than the described method, and / or the components of the described system, structure, device, circuit, etc. are combined or combined in a different form from the described method, or other components Alternatively, even if substituted or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (10)

In the phase change memory device to improve the snap-back phenomenon of the OTS (Ovonic Threshold Switch),
A bit line PMOS serving as a switch for the bit line;
An OTS (Ovonic Threshold Switch) disposed under the bit line PMOS;
A phase change layer disposed under the OTS;
A source line NMOS disposed at the bottom of the phase change layer and serving as a switch for the source line; And
And a PMOS Diode (Diode Connected PMOS) disposed between the bit line PMOS and the OTS to serve as a variable resistor. According to claim 1,
The PMOS Diode,
In response to the OTS being turned on (Turn-on), as the current flowing through the phase change memory element increases and the gate voltage increases, a resistance value increases to decrease the amount of current flowing through the phase change memory element. According to claim 2,
The PMOS Diode,
By reducing the amount of the current flowing, the phase change memory device to alleviate the snap-back phenomenon and prevent the crystalline phase change layer from being changed to amorphous in a set state. A circuit device used in a phase change memory device including a bit line PMOS serving as a switch for a bit line, an OTS (Ovonic Threshold Switch), a phase change layer and a source line NMOS serving as a switch for the source line,
A circuit element formed between a PMOS Diode (Diode Connected PMOS) serving as a variable resistor disposed between the bit line PMOS and the OTS. The method of claim 4,
The circuit element,
As the current flowing through the phase change memory element increases and the gate voltage of the PMOS diode increases in response to the OTS being turned on, the resistance value of the PMOS diode increases and the current flowing through the PMOS diode increases. Reducing the amount of, circuit elements. The method of claim 5,
The circuit element,
By reducing the amount of current flowing through the PMOS Diode, alleviating the snap-back phenomenon of the OTS and preventing the crystalline phase change layer from being changed to amorphous in a set state. A bit line PMOS serving as a switch for a bit line, an OTS (Ovonic Threshold Switch) disposed under the bit line PMOS, a phase change layer disposed under the OTS, and a source line disposed under the phase change layer To improve the snapback phenomenon in a phase change memory device including a source line NMOS and a bit line PMOS and a PMOS diode (Diode Connected PMOS) that acts as a variable resistor between the bit line PMOS and the OTS. In the operation method,
Increasing the gate voltage of the PMOS diode as the current flowing through the phase change memory element increases in response to the OTS being turned on; And
Decreasing the amount of current flowing through the PMOS diode as the resistance value of the PMOS diode increases by increasing the gate voltage of the PMOS diode.
Method for improving the snapback phenomenon in the phase-change memory device comprising a. The method of claim 7,
The step of reducing the amount of current flowing through the PMOS diode,
An operation for alleviating the snap-back phenomenon of the OTS and preventing the crystalline phase change layer from being changed to amorphous in a set state, to improve the snap back phenomenon in a phase change memory device Way. In the phase change memory device to improve the snap-back phenomenon of the OTS (Ovonic Threshold Switch),
A bit line PMOS serving as a switch for the bit line;
An OTS (Ovonic Threshold Switch) disposed under the bit line PMOS;
A phase change layer disposed under the OTS;
A source line NMOS disposed at the bottom of the phase change layer and serving as a switch for the source line; And
In order to mitigate the snap-back phenomenon of the OTS and prevent the crystalline phase change layer from being changed to amorphous in a set state, it is disposed between the bit line PMOS and the OTS to change the phase. A phase change memory device comprising a PMOS Diode (Diode Connected PMOS) serving as a variable resistor whose resistance value changes according to a current flowing through the memory device. A circuit device used in a phase change memory device including a bit line PMOS serving as a switch for a bit line, an OTS (Ovonic Threshold Switch), a phase change layer and a source line NMOS serving as a switch for the source line,
In order to mitigate the snap-back phenomenon of the OTS and prevent the crystalline phase change layer from being changed to amorphous in a set state, it is disposed between the bit line PMOS and the OTS to change the phase. A circuit element formed of a PMOS Diode (Diode Connected PMOS) that serves as a variable resistor whose resistance value changes according to a current flowing through the memory element.

Images