KR20200050843A - Memory circuit and semiconductor device - Google Patents

Abstract

The present invention is to provide a memory circuit having a function of recovering data when the power supply is momentarily stopped. According to the present invention, the memory circuit (100) comprises: a bistable circuit capable of holding data in a complementary relationship to a node (N1) and a node (N2); a first nonvolatile memory circuit (NV1) connected to the node (N1); and a second nonvolatile memory circuit (NV2) connected to the node (N2). The first nonvolatile memory circuit (NV1) stores boot data. The second nonvolatile memory circuit (NV2) inverts a logic level of the data held in the second node when the data held in the second node is stored.

Description

Memory circuit and semiconductor device {MEMORY CIRCUIT AND SEMICONDUCTOR DEVICE}

The present invention relates to a memory circuit and a semiconductor device including a bistable circuit such as SRAM.

Since bistable circuits such as SRAM are volatile, when the power of the bistable circuit is cut off, data is lost. Therefore, in order to enable the power supply of the bistable circuit, before storing the power of the bistable circuit, the data stored in the bistable circuit is stored in a nonvolatile magnetic tunnel junction (MTJ). , It is known to restore data read from the MTJ to the bistable circuit when the bistable circuit is powered on.

[Patent Document 1] US Patent No. 9,601,198

In the system-on-chip, in order to allow the sensor or system to operate on the fly, boot, trimming, cache code, etc. are required for the system. And, the retained data can be updated during operation. If the power supply is suddenly cut off, it returns to the original data requiring programming update.

The present invention provides a memory circuit having a function of recovering original data.

In addition, an object of the present invention is to provide a memory circuit capable of shortening the start-up time when the power is turned on.

In some embodiments, the nonvolatile memory circuit includes a variable resistance element, and when the data held in the node is at a first logic level, sets the variable resistance element and holds the node. When the generated data is at the second logic level, a reset of the variable resistor element is performed. In one embodiment, the non-volatile memory circuit includes an access transistor and a variable resistor element connected in series between the node and the source line, and conducts the access transistor when performing a set of variable resistor elements. In the state of (導 通), when the bias from the node to the source line is applied to the variable resistance element, and reset write of the variable resistance element is performed, the access transistor is brought into a conduction state, and the A bias from the source line to the node is applied to the variable resistance element. In one embodiment, when setting the stored data of the nonvolatile memory circuit to the node, reset writing is performed on the variable resistance element that has undergone set write, and set is set on the variable resistance element that has undergone reset write. Fill in. In some embodiments, the node is connected to a bit line through a transistor and verifies by reading data stored in the variable resistance element through the bit line. In some embodiments, the memory circuit further includes other non-volatile memory circuits connected to other nodes, and the other non-volatile memory circuits store boot data required at power-on. In some embodiments, upon power-on, boot data stored in the other nonvolatile memory circuit is read to the first node. In some embodiments, the other nonvolatile memory circuit includes an access transistor and a variable resistor element connected in series between the other node and the source line.

1 is a diagram showing the configuration of a memory circuit according to an embodiment of the present invention.
[Fig. 2] Fig. 2 is a table showing an example of a bias voltage applied to each part at the time of forming, setting and resetting the memory circuit according to the present embodiment.
[Fig. 3] Fig. 3 is a diagram showing an operation flow when data held in the memory circuit according to the embodiment of the present invention is written to the nonvolatile memory circuit.
4 is a diagram showing an operation flow when data stored in a nonvolatile memory circuit is recovered in a bistable circuit in a memory circuit according to an embodiment of the present invention.
5 is a diagram showing an example of a system including a memory circuit according to an embodiment of the present invention.

[Example]

1 is a diagram showing a configuration of a memory circuit according to an embodiment of the present invention. As shown in the figure, the memory circuit 100 of this embodiment includes a bistable circuit in which a pair of inverters are cross-coupled, and a pair of nonvolatile memory circuits NV1 and NV2 connected to the bistable circuit. It is comprised. Although the memory circuit 100 for storing 1-bit complementary data is illustrated here, the memory circuit 100 is, for example, an SRAM or latch circuit including a plurality of matrix-shaped bistable circuits, Such SRAM can be mounted on a controller that controls a NAND type flash memory.

The memory circuit 100 shown in the figure illustrates a memory cell of an SRAM composed of six MOS transistors, a first CMOS inverter composed of a PMOS transistor TP1 and an NMOS transistor TN1, and a PMOS transistor A second CMOS inverter composed of (TP2) and NMOS transistor TN2, an NMOS transistor TN3 for access connected to node N1, and an NMOS transistor TN4 for access connected to node N2. It includes. The output of the first CMOS inverter is connected to the input of the second CMOS inverter, the output of the second CMOS inverter is connected to the input of the first CMOS inverter, the node N1 is connected to the output of the first CMOS inverter, and the node (N2) is connected to the output of the second CMOS inverter, and complementary data is held in the nodes N1 and N2.

The first voltage supply unit V1 is connected to one terminal of the PMOS transistor TP1, and GND is connected to one terminal of the NMOS transistor TN1. Similarly, the second voltage supply unit V2 is connected to one terminal of the PMOS transistor TP2, and GND is connected to one terminal of the NMOS transistor TN2. The memory circuit 100 is supplied with a voltage of approximately 2.5 V or greater, for example, as the power supply voltage Vcc, and the first and second voltage supply units V1 and V2 level the power supply voltage Vcc. The shifted voltage VDD can be supplied to the bistable circuit. The bistable circuit retains data to the nodes N1 and N2 while power is being supplied from the voltage supply units V1 and V2, and when the power supply from the voltage supply units V1 and V2 is cut off, the node N1 , N2) is a so-called volatile holding circuit in which data retained is erased.

The reading or writing of data held in the bistable circuit or writing of data is performed through the access transistors TN3 and TN4. One terminal of the access transistor TN3 is connected to the bit line BLm, the other terminal is connected to the node N1, and the gate is connected to the word line WLn. Further, one terminal of the access transistor TN4 is connected to the bit line / BLm, the other terminal is connected to the node N2, and the gate is connected to the word line WLn.

In the read operation, the access transistors TN3 and TN4 are turned on by applying a positive voltage to the word line WLn and held at the nodes N1 and N2 on the bit lines BLm and / BLm. Data is read.

In the write operation, the access transistors TN3 and TN4 are turned on by applying a positive voltage to the word line WLn, and data to be written is applied to the bit lines BLm and / BLm. For example, when the H level data held in the node N1 is rewritten, the L level data is applied to the bit line BLm.

Further, the memory circuit 100 of this embodiment includes a set of nonvolatile memory circuits NV1 and NV2 connected to the nodes N1 and N2, respectively. The nonvolatile memory circuit NV1 has an NMOS transistor Q1 for booting and a variable resistance element VR1 connected in series with it. One terminal of the transistor Q1 is connected to the node N1, the other terminal is connected to the variable resistance element VR1, and a gate is connected to a boot control line BOOTn. Further, one terminal of the variable resistor element VR1 is connected to the transistor Q1, and the other terminal is connected to the source line SL.

The nonvolatile memory circuit NV2 has a NMOS transistor Q2 for recovery and a variable resistor element VR2 connected in series therewith. One terminal of the transistor Q2 is connected to the node N2, the other terminal is connected to the variable resistance element VR2, and the gate is connected to the recovery control line RECOVn. Further, one terminal of the variable resistor element VR2 is connected to the transistor Q2, and the other terminal is connected to the source line SL.

2 shows an example of a bias voltage applied to each part during forming, set, and reset. For example, when forming the variable resistor element VR1, the power supply voltage Vcc is applied to the bit line BLm, GND is applied to the source line SL, and the boot transistor Q1 is applied. 1.4 V is applied to the gate BOOTn, and Vcc is applied to the gate WLn of the access transistor TN3. VDD of the voltage supply unit V1 is set to 2.9 V lower than Vcc. A bias is applied to the variable resistance element VR1 from the node N1 toward the source line SL, and current flows in that direction, so that the variable resistance element VR1 is formed into a low resistance state. Forming of the variable resistor element VR2 is similarly performed.

When writing a set, VDD of the voltage supply unit V1 is set to 2.2 V, and 1.7 V is applied to the gate BOOTn of the boot transistor Q1, resulting in a slightly smaller bias voltage and bias current than during forming. It is applied to the variable resistance element VR1.

When the node N1 is at the H level, the Vcc of the bit line BLm is supplied to the node N1 through the transistor TN3, so the node N1 remains at the H level. A bias is applied to the variable resistance element VR1 from the node N1 toward the source line SL, and current flows in the bias direction, and as a result, the variable resistance element VR1 has a low resistance state. do. On the other hand, when the node N1 is at the L level, the node N1 is pulled up by the Vcc of the bit line BLm, so that the node N1 is inverted from the L level to the H level. A bias is applied to the variable resistance element VR1 from the node N1 toward the source line SL, and current flows in the bias direction, and as a result, the variable resistance element VR1 is brought into a low resistance state.

In the case of reset writing, a bias in which the bias direction of the set writing is reversed is applied to the variable resistor element VR1. That is, GND is applied to the bit line BLm, 2.7 V is applied to the source line SL, 2.9 V is applied to the gate BOOTn of the boot transistor Q1, and the access transistor TN3 is applied. Vcc is applied to the gate WLn, and 2.7 V is set to VDD of the voltage supply unit V1.

When the node N1 is at the H level, the node N1 is pulled down to the GND of the bit line BLm through the transistor TN3, and the node N1 is inverted from the H level to the L level. A bias is applied to the variable resistance element VR1 from the source line SL toward the node N1, and current flows in the bias direction, and as a result, the variable resistance element VR1 has a high resistance state. do. On the other hand, when the node N1 is at the L level, the node N1 is at the L level. A bias is applied to the variable resistance element VR1 from the source line SL toward the node N1, and current flows in the bias direction, and as a result, the variable resistance element VR1 is brought into a high resistance state.

The boot data is data required to initially set them when the system or device is started.

In the conventional general technique, upon power-on, the ROM storing boot data is accessed, and the boot data read from the ROM is written into the memory circuit 100. In this embodiment, since the memory circuit 100 incorporates a nonvolatile memory circuit NV1, the boot data read from the nonvolatile memory circuit NV1 upon power-on is instantaneously the node N1 of the bistable circuit. ), It is possible to shorten the time required for setting the boot data than in the prior art. At the same time, it is possible to allocate a ROM for storing boot data or reduce the storage capacity of the ROM.

Next, the nonvolatile memory circuit NV2 will be described. The storage circuit 100 equipped with the SRAM is used as a cache memory because the access time is faster than other volatile memories. The memory circuit 100 of the present embodiment incorporates a nonvolatile memory circuit NV2, and the data held in the bistable circuit is evacuated to the nonvolatile memory circuit NV2, thereby recovering the retained data. It is possible.

Next, the set and reset write operation of the nonvolatile memory circuit NV2 will be described. This operation is controlled by a controller not shown here.

First, when the node N2 holds H level data, set writing is performed on the nonvolatile memory circuit NV2. At this time, the access transistor TN4 may be in a non-conducting state, or may be in a conducting state. When the access transistor TN4 is turned on, the bit line / BLm is a floating state in which the power supply voltage Vcc is precharged. A bias is applied to the variable resistance element VR2 from the node N2 toward the source line SL, and a current flows in that direction, and the variable resistance element VR2 is in a low resistance state. In this case, node N2 is inverted from H level to L level. When the bit line / BLm is connected to the node N2, current flows until the potential of the bit line / BLm is discharged to GND.

When the node N2 is holding the L level, the nonvolatile memory circuit NV2 is reset and written. At this time, the access transistor TN4 may be in a non-conducting state, or may be in a conducting state. A bias is applied to the variable resistance element VR2 from the source line SL toward the node N2, and current flows in that direction, so that the variable resistance element VR2 is in a high resistance state. At the time of reset writing, the source line SL is 2.7 V, the gate voltage of the transistor Q2 is 2.9 V, and a large drain current flows from the transistor Q2 to the node N2. For this reason, the node N2 inverts from the L level to the H level.

The controller reads H-level or L-level data of the node N2 of the bistable circuit through a bit line (/ BLm), and stores non-volatile data stored in the node N2 based on the read result. Set write or reset write is performed to the circuit NV2.

In addition, when data is written to the nonvolatile memory circuit NV2, the controller can perform write verify. The write verification is performed by reading data written to the nonvolatile memory circuit NV2. That is, the transistor TN4 is conducted through the word line WLn, and the transistor Q2 is conducted through the RECOVn, so that a positive read voltage is applied to the bit line / BLm.

In addition, when the data stored in the nonvolatile memory circuit NV2 is recovered to the bistable circuit, reset write is performed to the nonvolatile memory circuit NV2 that has been set to write. 2.7 V is applied to the source line SL, the transistor Q2 is conducted, and the node N2 is pulled up to the H level. On the other hand, set writing is performed for the nonvolatile memory circuit NV2 that has undergone reset writing. Vcc is applied to the bit line / BLm, the transistor Q2 is conducted, and the node N2 is pulled down to GND of the source line SL.

In addition, with respect to the operation of the nonvolatile memory circuit NV2, when collecting data from the variable resistor element VR2 itself, the static electricity is reversed / reversed according to the amount of charge remaining in the node N2.轉), but it is ideal to operate from the state where the word line WLn is in the GND state and the node N1 is in the GND state. The discharge time of the charge at the node N2 is managed by a positive pulse signal applied to the gate RECOVn of the recovery transistor Q2.

Fig. 3 shows an example of an operation flow when writing data held in the bistable circuit to the nonvolatile memory circuit NV2. The controller that controls the memory circuit 100 determines whether or not to store the data held in the node N2 in the nonvolatile memory circuit NV2 (S100). Which timing to evacuate is arbitrary, for example, when the power supply is likely to stop momentarily, when the power supply voltage is fluctuating, when a predetermined schedule time is reached, or when a certain time interval is reached. It is judged to evacuate the back. When it is determined that data is to be saved, the controller accesses a specific memory cell of the SRAM according to the matrix address, and reads the data of the node N2 (S102).

Next, the controller checks whether the data of the node N2 is the H level or the L level (S104). If it is the H level, set writing is performed for the nonvolatile memory circuit NV2 (S106), and if it is the L level, reset writing is performed for the nonvolatile memory circuit NV2 (S108). Next, the controller verifies the nonvolatile memory circuit NV2 (S110), and if not, sets write or reset write again, and if successful, ends the sequence (S112). In addition, the verification of the write data may be arbitrary.

Next, Fig. 4 shows an example of an operation flow when the memory circuit is recovered by the data stored in the nonvolatile memory circuit NV2. The controller determines whether to recover the data of the nonvolatile memory circuit NV2 (S200). It is arbitrary at which timing to recover, but, for example, when the power is re-supplied after the power is temporarily stopped.

If it is determined to recover, the controller accesses a specific memory cell according to the matrix address, and reads data stored in the nonvolatile memory circuit NV2 (S202). Next, the controller determines whether the nonvolatile memory circuit NV2 is in a low resistance state (that is, data "0", "1") based on the read data (S204), and if it is in a low resistance state, Reset write is performed (S206), and set writing is performed if it is in a high resistance state (S208), whereby data stored in the nonvolatile memory circuit NV2 is recovered to the node N2 (S210).

Next, an example of application of the memory circuit of this embodiment will be described. As described above, the memory circuit of the present embodiment is incorporated into a logic or a controller in an embodiment that can be used as an SRAM or a latch circuit. For example, in a memory device stacking a plurality of NAND flash memory chips, the memory circuit of this embodiment is incorporated into a controller that controls each NAND flash memory chip. The memory circuit holds boot data of each flash memory, and also backs up update data of each flash memory.

Next, an example of a system including the memory circuit 100 of this embodiment is shown in FIG. 5. The system 200 of this embodiment is equipped with a circuit 210, a RAM 220, a ROM 230, and a controller 240. The controller 240 controls the circuit 210, RAM 220, and ROM 230.

The circuit 210 is any circuit mounted in the system, and includes, for example, a memory (eg, flash memory), logic, driver, A / D or D / A converter, voltage generation circuit, level shifter, and the like. .

The RAM 220 is, for example, an SRAM, and one memory cell is a bistable circuit and a nonvolatile memory circuit NV1 connected to the nodes N1 and N2 of the bistable circuit, as shown in FIG. NV2). The RAM 220 can function as a cache memory of the controller 240, and cache codes and the like are stored in the nonvolatile memory circuit NV2 during system operation. In addition, boot data required at the time of system startup is stored in the nonvolatile memory circuit NV1 of the RAM 220.

The ROM 230 stores programs, software, and the like executed by the controller 240. For example, in the ROM 230, a power-up sequence program executed when power is turned on is stored. When the power is turned on, the controller 240 executes a power-up sequence program, sets boot data stored in the nonvolatile memory circuit NV1 to a node N1 of the bistable circuit, and circuits based on the boot data Initial setting of 210 is performed. Further, the ROM 230 stores a data stored in the RAM 220 in a nonvolatile memory circuit NV2 or a recovery program for recovering the RAM 220 using the data. The controller 240 executes a recovery program, for example, when the power supply voltage becomes unstable, saves the volatile data in the nonvolatile memory circuit NV2, and when the power supply voltage stabilizes, the saved data Recover to a bistable circuit.

In the above embodiment, variable resistance elements are used for the nonvolatile memory circuits NV1 and NV2, but the present invention is not limited to this, and other nonvolatile memory elements (eg, magnetic material memory, flash memory, etc.) may be used. It is okay.

Although the preferred embodiment of the present invention has been described above, the present invention is not limited to a specific embodiment, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

100: memory circuit
V1, V2: voltage supply
TP1, TP2: P-type transistor (PMOS transistor)
TN1 to TN4, Q1, Q2: N-type transistor (NMOS transistor)
NV1, NV2: Non-volatile memory circuit
VR1, VR2: Variable resistance element

Claims (10)

A bistable circuit capable of maintaining data complementary to each node,
Non-volatile memory circuit connected to one node
Have,
The nonvolatile memory circuit,
A storage circuit that, when storing data held in the node, inverts a logical level of data held in the node. According to claim 1,
The nonvolatile memory circuit includes a variable resistance element,
When the data held in the node is the first logic level, set writing of the variable resistor element is performed,
When the data held in the node is at a second logic level, the memory circuit performs reset writing of the variable resistance element. The method according to claim 1 or 2,
The nonvolatile memory circuit,
An access transistor connected in series between the node and the source line, and a variable resistor element,
When writing the set of the variable resistance element, the access transistor is turned on, and a bias from the node to the source line is applied to the variable resistance element,
The memory circuit which sets the access transistor in a conducting state and applies a bias from the source line to the node to the variable resistance element when resetting the variable resistance element. According to claim 2,
When setting the stored data of the nonvolatile memory circuit to the node,
Reset writing is performed on the variable resistor element that has undergone set writing,
A memory circuit in which set writing is performed for a variable resistor element that has been reset writing. According to claim 2,
The node,
Connected to the bit line through a transistor,
A memory circuit that verifies by storing data stored in the variable resistance element through the bit line. According to claim 1,
The memory circuit,
Other non-volatile memory circuits connected to other nodes
Further comprising,
The other nonvolatile memory circuit,
A storage circuit that stores boot data required at power-on. The method of claim 6,
A memory circuit in which boot data stored in the other nonvolatile memory circuit is read to a first node when the power is turned on. The method of claim 6 or 7,
The other nonvolatile memory circuit,
An access transistor connected in series between the other node and the source line, and a variable resistor element
Memory circuit comprising a. The memory circuit according to claim 1,
A controller that controls the memory circuit
A semiconductor device comprising a. The method of claim 9,
The semiconductor device,
At least one flash memory
Further comprising,
The controller,
To control the flash memory
Semiconductor devices.

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