KR20200037170A - Thin film transistor array panel - Google Patents

Abstract

According to an embodiment of the present invention, a thin film transistor display panel, which maintains an overlapping area between a gate electrode and a dummy gate electrode, and the drain electrode and the dummy drain electrode constant even if the shape of the drain electrode changes depending on the position by forming a dummy gate electrode and a dummy drain electrode so that the drain electrode and the dummy drain electrode are formed to have the same area change along the extending direction of the gate line based on a constant width. Accordingly, the parasitic capacity can be maintained uniformly, thereby preventing degradation of image quality due to parasitic capacity differences.

Description

Thin film transistor panel {THIN FILM TRANSISTOR ARRAY PANEL}

The present invention relates to a thin film transistor array panel.

A liquid crystal display (Liquid Crystal Display) is one of the most widely used flat panel display (Flat Panel Display), a display that controls the amount of light transmitted by rearranging the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode Device.

In general, a liquid crystal display device includes two substrates including an electric field generating electrode and a liquid crystal layer interposed therebetween. The pixel electrodes of the electric field generating electrodes are arranged in a matrix form, and are connected to a switching element such as a thin film transistor (TFT) to receive data voltages one by one in turn.

When manufacturing a display panel including a switching element such as a thin film transistor, a photolithography process is used. At this time, in the process of forming the gate wiring and the data wiring, due to an error in the exposure process, the position of the gate wiring and the data wiring may change for each region, and the difference between the positions of the two wirings may cause the gate wiring and the data wiring. The overlapping area becomes different. As described above, when the overlapping areas of the gate electrode and the source drain electrode of the thin film transistor are different, a difference in parasitic capacitance occurs, which leads to deterioration in image quality, such as defects in stitching or flicker.

The problem to be solved by the present invention is to maintain a uniform parasitic capacitance between the gate electrode and the drain electrode, thereby preventing degradation of image quality due to parasitic capacitance difference.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes a substrate, a gate line including a gate electrode and a dummy gate electrode positioned on the substrate, a gate insulating layer positioned on the gate electrode and the dummy gate electrode, and positioned on the gate insulating layer. A semiconductor, and a source electrode, a drain electrode, and a dummy drain electrode positioned on the semiconductor, the drain electrode and the dummy drain electrode are connected to each other, and the drain electrode faces the source electrode on the gate electrode. , The dummy drain electrode overlaps the dummy gate electrode or is located adjacent to the dummy gate electrode, and the drain electrode includes a plurality of first regions having a constant width in a direction in which the gate line extends, and the dummy drain The electrode is the gate line It includes a plurality of second regions having a constant width in an extended direction, and at least one of the plurality of second regions includes an edge forming an angle of 0 degrees or more and 90 degrees or less with the gate line, and the plurality of second regions At least one area of the area is different from each area of the remaining areas of the plurality of second areas.

At least one of the plurality of first regions of the drain electrode includes an edge that forms an angle of 0 degrees or more and 90 degrees or less with the gate line, and an area of at least one of the plurality of first regions is the plurality of first regions. It may be different from each area of the remaining areas of the area.

The area of the plurality of first regions and the area of the plurality of second regions may be wider or narrower as they are further away from the source electrode.

The plurality of first regions include a first subregion, a second subregion, and a third subregion disposed in an order close to the source electrode, and the plurality of second regions are disposed in a distant order from the source electrode And a fourth subregion, a fifth subregion, and a sixth subregion, wherein an area of the first subregion is equal to an area of the sixth subregion, and an area of the second subregion is the fifth subregion. The area of the area may be the same as that of the third sub-region, and the area of the fourth sub-region may be the same.

The source electrode, the drain electrode, and a passivation layer positioned on the dummy drain electrode, and a pixel electrode positioned on the passivation layer and connected to the drain electrode through a contact hole formed in the passivation layer may be further included.

A common electrode overlapping the pixel electrode and the insulating layer may be further included.

One of the pixel electrode and the common electrode may include a plurality of branch electrodes, and the merge may have a plate-like planar shape.

A thin film transistor array panel according to another exemplary embodiment of the present invention includes a substrate, a gate line including a gate electrode and a dummy gate electrode positioned on the substrate, a gate insulating layer positioned on the gate electrode and the dummy gate electrode, and a gate insulating layer positioned on the gate insulating layer. And a source electrode, a drain electrode, and a dummy drain electrode positioned on the semiconductor, the drain electrode and the dummy drain electrode are connected to each other, and the drain electrode faces the source electrode on the gate electrode. Reportedly, the dummy drain electrode overlaps the dummy gate electrode or is located adjacent to the dummy gate electrode, and the drain electrode includes a plurality of first regions having a constant width in a direction in which the gate line extends, and the dummy Gate electrode is said gay The third line includes a plurality of third regions having a constant width in the extended direction, and an area of at least one of the plurality of third regions is different from each area of the remaining regions of the plurality of third regions.

The area of the plurality of first regions and the area of the plurality of third regions may be wider or narrower as they are further away from the source electrode.

A thin film transistor array panel according to an embodiment of the present invention forms a dummy gate electrode and a dummy drain electrode, and the drain electrode and the dummy drain electrode are formed to have the same area change based on a constant width along a direction in which the gate line extends, The drain electrode and the dummy gate electrode are formed to have the same area change based on a constant width along the direction in which the gate line extends, so that even if the shape of the drain electrode changes depending on the position, the gate electrode and the dummy gate electrode, the drain electrode, and the dummy The overlapping area between the drain electrodes can be kept constant. Accordingly, the parasitic capacity can be maintained uniformly, thereby preventing degradation of image quality due to parasitic capacity differences.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II.
3 is a diagram illustrating a part of the thin film transistor array panel of FIG. 1.
4 and 5 are diagrams for explaining misalignment of the thin film transistor array panel of FIG. 3.
6 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.
7 is a cross-sectional view of the thin film transistor array panel shown in FIG. 6 taken along line VII-VII.
8 is a diagram illustrating a part of the thin film transistor array panel of FIG. 6.
9 and 10 are views for explaining misalignment of the thin film transistor array panel of FIG. 8.
11 to 17 are views illustrating a portion of a thin film transistor array panel according to other embodiments of the present invention.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily practice. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein.

In the drawings, thicknesses are enlarged to clearly represent various layers and regions. The same reference numerals are used for similar parts throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be “above” another portion, this includes not only the case “directly above” the other portion but also another portion in the middle. Conversely, when one part is "just above" another, it means that there is no other part in the middle.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference to the drawings.

First, the thin film transistor array panel 100 according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 3. 1 is a layout view of a thin film transistor array panel according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II, and FIG. 3 is a thin film transistor array panel of FIG. 1. It is a diagram showing a part.

A plurality of gate lines 121 are formed on an insulating substrate 110 made of transparent glass or plastic.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 and a plurality of dummy gate electrodes 125. Although not illustrated, the gate line 121 further includes a gate pad portion having a large area for connection with other layers or external driving circuits. The gate driving circuit (not shown) for generating the gate signal is mounted on a flexible printed circuit film (not shown) attached on the substrate 110, or directly mounted on the substrate 110, It may be integrated on the substrate 110. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may be extended and directly connected to it.

Although not illustrated, a storage electrode line made of the same layer as the gate line 121 may be further included.

The gate line 121 is aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, molybdenum (Mo) or molybdenum alloy, etc. It can be made of molybdenum-based metals, such as chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multi-film structure including two conductive films (not shown) having different physical properties, and may be made of various metals or conductors.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate line 121.

A plurality of semiconductors 154 are formed on the gate insulating layer 140. The semiconductor 154 may be made of hydrogenated amorphous silicon (amorphous silicon is abbreviated as a-Si), polysilicon, or an oxide semiconductor.

A plurality of ohmic contacts 163 and 165 are formed on the semiconductor 154. The resistive contact members 163 and 165 may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are doped at a high concentration, or may be made of silicide. The resistive contact members 163 and 165 are paired and disposed on the semiconductor 154.

A plurality of data lines 171, a plurality of drain electrodes 175a, and a plurality of dummy drain electrodes 175b are formed on the resistive contact members 163 and 165.

The data line 171 transmits a data signal and mainly extends in a vertical direction to intersect the gate line 121. Each data line 171 has a data pad portion (not shown) having a large area for connection to a plurality of source electrodes 173 extending toward the gate electrode 124 and other layers or external driving circuits. Includes. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached on the substrate 110, mounted directly on the substrate 110, or integrated on the substrate 110 Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended and directly connected to it.

The drain electrode 175a is separated from the data line 171 and faces the source electrode 173 around the gate electrode 124.

The drain electrode 175a and the dummy drain electrode 175b are connected to each other, and the dummy drain electrode 175b is positioned adjacent to the dummy gate electrode 125.

One gate electrode 124, one source electrode 173, and one drain electrode 175 form one thin film transistor (TFT) together with the semiconductor 154, and a channel of the thin film transistor (channel) ) Is formed on the semiconductor 154 between the source electrode 173 and the drain electrode 175.

The data line 171, the drain electrode 175a, and the dummy drain electrode 175b are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium or an alloy thereof, and a refractory metal film (not shown) ) And a low-resistance conductive film (not shown). However, the data line 171 and the drain electrode 175 may be made of various metals or conductors.

The resistive contact members 163 and 165 exist only between the semiconductor 154 thereunder and the data line 171 thereon, the drain electrode 175a and the dummy drain electrode 175b, and lower the contact resistance between them. give. However, when the semiconductor 154 is an oxide semiconductor, the ohmic contact members 163 and 165 may be omitted.

A passivation layer 180 is formed on the exposed portion of the data line 171, the drain electrode 175a, the dummy drain electrode 175b, and the semiconductor 154.

The protective layer 180 is made of an inorganic insulating material or an organic insulating material and may have a flat surface. Examples of the inorganic insulating material include silicon nitride and silicon oxide. The organic insulating material may have photosensitivity, and its dielectric constant is preferably about 4.0 or less. However, the protective layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to harm the exposed portion of the semiconductor 154 while utilizing excellent insulating properties of the organic layer.

A plurality of contact holes 185 exposing the extended portion of the drain electrode 175a is formed in the passivation layer 185.

A plurality of pixel electrodes 191 is formed on the passivation layer 180. The pixel electrode 191 may be made of a transparent conductive material such as ITO or IZO, or a reflective metal such as aluminum, silver, chromium, or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives a data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied is generated between the two electrodes 191 and 270 by generating an electric field together with the common electrode 270 of the counter panel 200 to which a common voltage is applied. The direction of the liquid crystal molecules (not shown) of the liquid crystal layer 3 is determined. The polarization of light passing through the liquid crystal layer 3 is changed according to the direction of the liquid crystal molecules determined as described above.

The counter display panel 200 will be briefly described. The opposing display panel 200 includes a plurality of light blocking members 220 formed on the insulating substrate 210 and a plurality of color filters 230 and a plurality of light blocking members located within an area defined by the plurality of light blocking members 220 ( 220) and a plurality of color filters 230, the overcoat 250, and the overcoat 250, and the common electrode 270. The overcoat 250 may be omitted.

Next, with reference to FIG. 3, the gate electrode 124 and the dummy gate electrode 125 and the drain electrode 175a and the dummy drain electrode 175b of the thin film transistor array panel according to the present embodiment will be described in more detail.

Referring to FIG. 3, the drain electrode 175a and the dummy drain electrode 175b are connected to each other. The drain electrode 175a faces the source electrode 173 on the gate electrode 124. The dummy drain electrode 175b is positioned on the opposite side to the drain electrode 175a and is adjacent to the dummy gate electrode 125.

The drain electrode 175a includes a plurality of subregions R1, R2, and R3 having a constant width based on a direction in which the gate line 121 extends. The dummy drain electrode 175b also includes a plurality of subregions R4, R5, and R6 having a constant width based on the direction in which the gate line 121 extends. The plurality of sub-regions R1, R2, and R3 of the drain electrode 175a include a first sub-region R1, a second sub-region R2, and a third sub-region R3 in a sequence close to the source electrode. do. The plurality of sub-regions R4, R5, and R6 of the dummy drain electrode 175b are arranged in a fourth sub-region R4, a fifth sub-region R5, and a sixth sub-region R6 in a distant order from the source electrode. Includes.

As illustrated, at least one of the plurality of subregions R1, R2, and R3 of the drain electrode 175a includes an edge forming a first angle θ1 with the gate line 121, and the dummy drain electrode 175b At least one of the plurality of sub-regions R4, R5, and R6 includes an edge forming the second angle θ2 with the gate line 121. The first angle θ1 and the second angle θ2 may be 0 degrees or more and 90 degrees or less.

The areas of the plurality of sub-regions R1, R2, and R3 of the drain electrode 175a may be wider or narrower as they are further away from the source electrode. In the illustrated embodiment, the area of the subregions R1, R2, and R3 of the drain electrode 175a increases as the area away from the source electrode increases, but in the case of a thin film transistor array panel according to other embodiments of the present invention, drain The area of the subregions R1, R2, and R3 of the electrode 175a may be narrower as it moves away from the source electrode, and only one of the plurality of subregions R1, R2, and R3 may be different from the remaining area have. In addition, the areas of the plurality of sub-regions R4, R5, and R6 of the dummy drain electrode 175b may be narrower or wider as they are closer to the source electrode. In the illustrated embodiment, the area of the plurality of sub-regions R4, R5, and R6 of the dummy drain electrode 175b is getting smaller as it approaches the source electrode, but the area of the thin film transistor array panel according to other embodiments of the present invention In this case, the area closer to the source electrode may be wider, and only one area among the plurality of sub-regions R4, R5, and R6 may be different from the remaining area.

At this time, the area of the first subregion R1 of the drain electrode 175a may be the same as the area of the sixth subregion R6 of the dummy drain electrode 175b. Also, the area of the second subregion R2 of the drain electrode 175a may be equal to the area of the fifth subregion R5 of the dummy drain electrode 175b, and the third subregion of the drain electrode 175a ( The area of R3) may be the same as the area of the fourth subregion R4 of the dummy drain electrode 175b.

Next, with reference to FIGS. 4 and 5 together with FIG. 3, the parasitic capacitance due to misalignment of the thin film transistor array panel according to an embodiment of the present invention will be described. 4 and 5 are diagrams for explaining misalignment of the thin film transistor array panel of FIG. 3. 4 illustrates a case in which the gate wiring of the gate electrode 124 and the dummy gate electrode 125 is moved to the right, and FIG. 5 shows the gate wiring of the gate electrode 124 and the dummy gate electrode 125 is moved to the left. One case is shown.

In FIG. 3, overlapping portions of the gate electrode 124 and the dummy gate electrode 125 and the drain electrode 175a and the dummy drain electrode 175b are indicated by diagonal lines. More specifically, the first overlapping region A of the gate electrode 124 and the drain electrode 175a and the second overlapping region B of the dummy gate electrode 125 and the dummy drain electrode 175b are included.

Referring to FIG. 4, the gate electrode 124 and the dummy gate electrode 125 move to the right, and the area of the third overlapping region A1 of the gate electrode 124 and the dummy gate electrode 125 is illustrated in FIG. 3. The area of the first overlapping region A of the illustrated gate electrode 124 and the dummy gate electrode 125 is wider. More specifically, the area of the third subregion R3 of the drain electrode 175a is widened. In addition, the area of the fourth overlapping region B1 of the dummy gate electrode 125 and the dummy drain electrode 175b is the second overlapping region of the dummy gate electrode 125 and the dummy drain electrode 175b shown in FIG. 3 ( It becomes narrower than the area of B). More specifically, the area of the fourth sub-region R4 of the dummy drain electrode 175b is narrowed.

However, as described above, the area of the third subregion R3 of the drain electrode 175a is the same as that of the fourth subregion R4 of the dummy drain electrode 175b. Thus, in the example shown in FIG. 3, the first overlapping region A of the gate electrode 124 and the drain electrode 175a and the second overlapping region B of the dummy gate electrode 125 and the dummy drain electrode 175b The sum of the areas of) is the third overlapping region A1 of the gate electrode 124 and the drain electrode 175a, the fourth of the dummy gate electrode 125 and the dummy drain electrode 175b in the example shown in FIG. 4. It becomes equal to the sum of the areas of the overlapping region B1.

Referring to FIG. 5, the gate electrode 124 and the dummy gate electrode 125 move to the left, and the area of the fifth overlapping region A2 of the gate electrode 124 and the dummy gate electrode 125 is illustrated in FIG. 3. The area of the first overlapped region A of the illustrated gate electrode 124 and the dummy gate electrode 125 is narrower. More specifically, the area of the second subregion R2 of the drain electrode 175a is narrowed. In addition, the area of the sixth overlapping region B2 of the dummy gate electrode 125 and the dummy drain electrode 175b is the second overlapping region of the dummy gate electrode 125 and the dummy drain electrode 175b shown in FIG. 3 ( It becomes wider than the area of B). More specifically, it is widened by the area of the fifth sub-region R5 of the dummy drain electrode 175b.

However, as described above, the area of the second subregion R2 of the drain electrode 175a is equal to the area of the fifth subregion R5 of the dummy drain electrode 175b. Thus, in the example shown in FIG. 3, the first overlapping region A of the gate electrode 124 and the drain electrode 175a and the second overlapping region B of the dummy gate electrode 125 and the dummy drain electrode 175b The sum of the areas of) is the fifth overlapping region A2 of the gate electrode 124 and the drain electrode 175a and the sixth of the dummy gate electrode 125 and the dummy drain electrode 175b in the example shown in FIG. 5. It becomes equal to the sum of the areas of the overlapping region B2.

As described above, according to the thin film transistor array panel according to an embodiment of the present invention, the gate electrode 124 and the dummy gate electrode 125 and the drain electrode 175a and the dummy drain electrode 175b are included, and the drain electrode 175a And the edge of the dummy drain electrode 175b includes a portion at an angle with the gate line 121, and the drain electrode 175a and the dummy drain electrode 175b have a constant width in the direction in which the gate line 121 extends. It includes a plurality of sub-regions, the area of each sub-region may be wider or narrower as far as the source electrode, the corresponding area of the sub-region of the drain electrode 175a and the sub-region of the dummy drain electrode 175b This is the same.

Therefore, even if the area of the drain electrode 175a is changed from the source electrode 173 to the area, the gate electrode 124 and the dummy gate electrode are generated even when an alignment error between the gate wiring and the data wiring occurs. The area of the region where the drain electrode 175a and the dummy drain electrode 175b overlap may be kept constant. Therefore, since the total overlapping area between the gate wiring of the gate electrode 124 and the dummy gate electrode 125 and the drain wiring of the drain electrode 175a and the dummy drain electrode 175b does not change, the gate wiring and the drain wiring The size of the parasitic capacity according to the overlap becomes constant.

Next, the thin film transistor array panel 100 according to another exemplary embodiment of the present invention will be described with reference to FIGS. 6 to 8. 6 is a layout view of a thin film transistor array panel according to another embodiment of the present invention, FIG. 7 is a cross-sectional view of the thin film transistor array panel shown in FIG. 6 taken along line VII-VII, and FIG. 8 is a thin film of FIG. 6 It is a diagram showing a part of the transistor display panel.

A plurality of gate lines 121 are formed on the insulating substrate 110. Each gate line 121 includes a plurality of gate electrodes 124 and a plurality of dummy gate electrodes 125. Although not illustrated, a storage electrode line made of the same layer as the gate line 121 may be further included.

A gate insulating layer 140 is formed on the gate line 121.

A plurality of semiconductors 154 are formed on the gate insulating layer 140. The semiconductor 154 may be made of hydrogenated amorphous silicon (amorphous silicon is abbreviated as a-Si), polysilicon, or an oxide semiconductor.

A plurality of ohmic contacts 163 and 165 are formed on the semiconductor 154. The resistive contact members 163 and 165 may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are doped at a high concentration, or may be made of silicide. The resistive contact members 163 and 165 are paired and disposed on the semiconductor 154.

A plurality of data lines 171, a plurality of drain electrodes 175a, and a plurality of dummy drain electrodes 175b are formed on the ohmic contacts 163 and 165.

The data line 171 may have a first curved portion having a curved shape in order to obtain the maximum transmittance of the liquid crystal display, and the curved portions may meet each other in the middle region of the pixel region to form a V-shape. The middle region of the pixel region may further include a second bent portion curved to form a predetermined angle with the first bent portion. The first bent portion of the data line 171 may be bent to form about 7 ° with a vertical reference line (reference line extending in the y and y directions) that forms 90 degrees with a direction in which the gate line 121 extends (x direction). . The second bent portion disposed in the middle region of the pixel area may be further bent to form about 7 ° to about 15 ° with the first bent part.

The source electrode 173 is a part of the data line 171 and is disposed on the same line as the data line 171. The drain electrode 175a is formed to extend in parallel with the source electrode 173. Therefore, the drain electrode 175a is parallel to a part of the data line 171.

The thin film transistor array panel according to the present embodiment includes an area occupied by a data conductor by including a source electrode 173 positioned on the same line as the data line 171 and a drain electrode 175a extending parallel to the data line 171. It is possible to widen the width of the thin film transistor without widening, and accordingly, the aperture ratio of the liquid crystal display may be increased.

The drain electrode 175a is separated from the data line 171 and faces the source electrode 173 around the gate electrode 124.

The drain electrode 175a and the dummy drain electrode 175b are connected to each other, and the dummy drain electrode 175b is positioned adjacent to the dummy gate electrode 125.

The resistive contact members 163 and 165 exist only between the semiconductor 154 thereunder and the data line 171 thereon, the drain electrode 175a and the dummy drain electrode 175b, and lower the contact resistance between them. give. However, when the semiconductor 154 is an oxide semiconductor, the ohmic contact members 163 and 165 may be omitted.

A first passivation layer 180x is formed on the data line 171, the drain electrode 175a, the dummy drain electrode 175b, and the exposed portions of the semiconductor 154. The first passivation layer 180x may be made of an organic insulating material or an inorganic insulating material.

The second passivation layer 180y is disposed on the first passivation layer 180x. The second passivation layer 180y may be omitted. The second passivation layer 180y may be a color filter. When the second passivation layer 180y is a color filter, the second passivation layer 180y may uniquely display one of the primary colors, and examples of the primary color include three primary colors such as red, green, blue, or yellow ( yellow), cyan, magenta, and the like. Although not illustrated, the color filter may further include a color filter displaying a mixed color of the primary colors or white in addition to the primary colors.

The common electrode 270 is formed on the second passivation layer 180y. The common electrode 270 may be formed as a plate on the entire surface of the substrate 110 as a planar shape, and may have an opening (not shown) disposed in a region corresponding to the vicinity of the drain electrode 175a. That is, the common electrode 270 may have a flat shape in the form of a plate.

The common electrodes 270 positioned in adjacent pixels may be connected to each other to receive a common voltage having a constant magnitude supplied from outside the display area.

The third passivation layer 180z is disposed on the common electrode 270. The third passivation layer 180z may be made of an organic insulating material or an inorganic insulating material.

The pixel electrode 191 is formed on the third passivation layer 180z. The pixel electrode 191 includes a curved edge almost parallel to the first curved portion and the second curved portion of the data line 171. The pixel electrode 191 has a plurality of first cutouts 92 and includes a plurality of first branch electrodes 192.

A contact hole 185 exposing the drain electrode 175 is formed in the first passivation layer 180x, the second passivation layer 180y, and the third passivation layer 180z. The pixel electrode 191 is physically and electrically connected to an extension of the drain electrode 175a through the contact hole 185 to receive a voltage from the drain electrode 175a.

When the counter display panel 200 is described, the light blocking member 220 is formed on the insulating substrate 210 and a plurality of color filters 230 are formed. When the second passivation layer 180y of the thin film transistor array panel 100 is a color filter, the color filter 230 of the opposing panel 200 may be omitted. In addition, the light blocking member 220 of the opposing display panel 200 may also be formed on the thin film transistor array panel 100.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220. An overcoat 250 is formed on the color filter 230 and the light blocking member 220. The overcoat 250 may be omitted.

8, the gate electrode 124 and the dummy gate electrode 125 and the drain electrode 175a and the dummy drain electrode 175b of the thin film transistor array panel according to the present embodiment will be described in more detail.

Referring to FIG. 8, the drain electrode 175a and the dummy drain electrode 175b are connected to each other. The drain electrode 175a faces the source electrode 173 on the gate electrode 124. The dummy drain electrode 175b is positioned on the opposite side to the drain electrode 175a and is adjacent to the dummy gate electrode 125.

The drain electrode 175a includes a plurality of subregions R1, R2, and R3 having a constant width based on a direction in which the gate line 121 extends. The dummy drain electrode 175b also includes a plurality of subregions R4, R5, and R6 having a constant width based on the direction in which the gate line 121 extends. The plurality of sub-regions R1, R2, and R3 of the drain electrode 175a include a first sub-region R1, a second sub-region R2, and a third sub-region R3 in a sequence close to the source electrode. do. The plurality of sub-regions R4, R5, and R6 of the dummy drain electrode 175b are arranged in a fourth sub-region R4, a fifth sub-region R5, and a sixth sub-region R6 in a distant order from the source electrode. Includes.

As illustrated, at least one of the plurality of subregions R1, R2, and R3 of the drain electrode 175a includes an edge forming a first angle θ1 with the gate line 121, and the dummy drain electrode 175b At least one of the plurality of sub-regions R4, R5, and R6 includes an edge forming the second angle θ2 with the gate line 121. The first angle θ1 and the second angle θ2 may be 0 degrees or more and 90 degrees or less.

The areas of the plurality of sub-regions R1, R2, and R3 of the drain electrode 175a may be wider or narrower as they are further away from the source electrode. In the illustrated embodiment, the area of the subregions R1, R2, and R3 of the drain electrode 175a is wider as it is farther from the source electrode, but in another embodiment of the present invention, it is narrower as it is farther from the source electrode. In addition, only one area among the plurality of sub-regions R1, R2, and R3 may be different from the remaining area. In addition, the areas of the plurality of sub-regions R4, R5, and R6 of the dummy drain electrode 175b may be narrower or wider as they are closer to the source electrode. In the illustrated embodiment, the area of the subregions R1, R2, and R3 of the drain electrode 175a is getting smaller as it is farther from the source electrode, but in another embodiment of the present invention, it is getting wider as it is farther from the source electrode. In addition, only one area among the plurality of sub-regions R4, R5, and R6 may be different from the remaining area.

At this time, the area of the first subregion R1 of the drain electrode 175a may be the same as the area of the sixth subregion R6 of the dummy drain electrode 175b. Also, the area of the second subregion R2 of the drain electrode 175a may be equal to the area of the fifth subregion R5 of the dummy drain electrode 175b, and the third subregion of the drain electrode 175a ( The area of R3) may be the same as the area of the fourth subregion R4 of the dummy drain electrode 175b.

Then, with reference to FIGS. 9 and 10 along with FIG. 8, parasitic capacitances due to misalignment of the thin film transistor array panel according to an embodiment of the present invention will be described. 9 and 10 are views for explaining misalignment of the thin film transistor array panel of FIG. 8. 9 shows a case in which the gate wiring of the gate electrode 124 and the dummy gate electrode 125 is moved to the right, and FIG. 10 shows the gate wiring of the gate electrode 124 and the dummy gate electrode 125 is moved to the left. One case is shown.

In FIG. 8, overlapping portions of the gate electrode 124 and the dummy gate electrode 125 and the drain electrode 175a and the dummy drain electrode 175b are indicated by diagonal lines. More specifically, the seventh overlapping area AA of the gate electrode 124 and the drain electrode 175a and the eighth overlapping area BB of the dummy gate electrode 125 and the dummy drain electrode 175b are included.

Referring to FIG. 9, the gate electrode 124 and the dummy gate electrode 125 move to the right, so that the area of the ninth overlapping region AA1 of the gate electrode 124 and the dummy gate electrode 125 is illustrated in FIG. 8. The area of the seventh overlapping area AA of the illustrated gate electrode 124 and the dummy gate electrode 125 becomes wider. More specifically, the area of the second subregion R2 of the drain electrode 175a is widened. In addition, the area of the tenth overlapping region BB1 of the dummy gate electrode 125 and the dummy drain electrode 175b is the eighth overlapping region of the dummy gate electrode 125 and the dummy drain electrode 175b shown in FIG. 8 ( It becomes smaller than the area of BB). More specifically, the area of the fifth sub-region R5 of the dummy drain electrode 175b is narrowed.

However, as described above, the area of the second subregion R2 of the drain electrode 175a is the same as that of the fifth subregion R5 of the dummy drain electrode 175b. Accordingly, in the example shown in FIG. 8, the seventh overlapping area AA of the gate electrode 124 and the drain electrode 175a and the eighth overlapping area BB of the dummy gate electrode 125 and the dummy drain electrode 175b In the example shown in FIG. 9, the sum of the areas of) is the ninth overlapping area AA1 of the gate electrode 124 and the drain electrode 175a, the tenth of the dummy gate electrode 125 and the dummy drain electrode 175b. It becomes equal to the sum of the areas of the overlapping area BB1.

Referring to FIG. 10, the gate electrode 124 and the dummy gate electrode 125 move to the left, and the area of the eleventh overlapping area AA2 of the gate electrode 124 and the dummy gate electrode 125 is illustrated in FIG. 8. The area of the seventh overlapping area AA of the illustrated gate electrode 124 and the dummy gate electrode 125 is narrower. More specifically, the area of the first subregion R1 of the drain electrode 175a is narrowed. Also, the area of the twelfth overlapping region BB2 of the dummy gate electrode 125 and the dummy drain electrode 175b is the eighth overlapping region of the dummy gate electrode 125 and the dummy drain electrode 175b shown in FIG. 8 ( BB). More specifically, the area of the sixth subregion R6 of the dummy drain electrode 175b is widened.

However, as described above, the area of the first subregion R1 of the drain electrode 175a is equal to the area of the sixth subregion R6 of the dummy drain electrode 175b. Accordingly, in the example shown in FIG. 8, the seventh overlapping area AA of the gate electrode 124 and the drain electrode 175a and the eighth overlapping area BB of the dummy gate electrode 125 and the dummy drain electrode 175b In the example shown in FIG. 10, the sum of the areas of) is the eleventh overlapping area AA2 of the gate electrode 124 and the drain electrode 175a, the twelfth of the dummy gate electrode 125 and the dummy drain electrode 175b. It becomes equal to the sum of the areas of the overlapping area BB2.

As described above, according to the thin film transistor array panel according to an embodiment of the present invention, the gate electrode 124 and the dummy gate electrode 125 and the drain electrode 175a and the dummy drain electrode 175b are included, and the drain electrode 175a And the edge of the dummy drain electrode 175b includes a portion at an angle with the gate line 121, and the drain electrode 175a and the dummy drain electrode 175b have a constant width in the direction in which the gate line 121 extends. It includes a plurality of sub-regions, the area of each sub-region may be wider or narrower as far as the source electrode, the corresponding area of the sub-region of the drain electrode 175a and the sub-region of the dummy drain electrode 175b This is the same.

Therefore, even if the area of the drain electrode 175a is changed from the source electrode 173 to the area, the gate electrode 124 and the dummy gate electrode are generated even when an alignment error between the gate wiring and the data wiring occurs. The area of the region where the drain electrode 175a and the dummy drain electrode 175b overlap may be kept constant. Therefore, since the total overlapping area between the gate wiring of the gate electrode 124 and the dummy gate electrode 125 and the drain wiring of the drain electrode 175a and the dummy drain electrode 175b does not change, the gate wiring and the drain wiring The size of the parasitic capacity according to the overlap becomes constant.

Then, examples of the gate electrode wiring and the drain electrode wiring of the thin film transistor array panel according to other embodiments of the present invention will be described with reference to FIGS. 11 to 17. 11 to 17 are views illustrating a portion of a thin film transistor array panel according to other embodiments of the present invention. Specifically, FIGS. 11 to 17 illustrate the gate electrode 124 and the dummy gate electrode 125 and the drain electrode 175a and the dummy drain electrode 175b of the thin film transistor array panel according to other embodiments of the present invention, respectively. City.

11 and 12, the gate electrode 124 and the dummy gate electrode 125 of the thin film transistor array panel according to the present exemplary embodiments, and the drain electrode 175a and the dummy drain electrode 175b are previously described with reference to FIGS. 1 and 12. It is similar to the thin film transistor array panel according to the embodiment described with reference to FIG.

The drain electrode 175a faces the source electrode 173 on the gate electrode 124 and overlaps the gate electrode 124. The dummy drain electrode 175b is positioned on the opposite side to the drain electrode 175a and is adjacent to the dummy gate electrode 125.

The drain electrode 175a includes a plurality of subregions R1, R2, and R3 having a constant width based on a direction in which the gate line 121 extends. The dummy drain electrode 175b also includes a plurality of subregions R4, R5, and R6 having a constant width based on the direction in which the gate line 121 extends.

At least one of the plurality of subregions R1, R2, and R3 of the drain electrode 175a includes an edge forming a first angle θ1 with the gate line 121.

The areas of the plurality of sub-regions R1, R2, and R3 of the drain electrode 175a may be wider or narrower as they are further away from the source electrode. In the illustrated embodiment, the area of the subregions R1, R2, and R3 of the drain electrode 175a is wider as it is farther from the source electrode, but in another embodiment of the present invention, it is narrower as it is farther from the source electrode. In addition, only one area among the plurality of sub-regions R1, R2, and R3 may be different from the remaining area. In addition, the areas of the plurality of sub-regions R4, R5, and R6 of the dummy drain electrode 175b may be narrower or wider as they are closer to the source electrode. In the illustrated embodiment, the area of the subregions R1, R2, and R3 of the drain electrode 175a is getting smaller as it is farther from the source electrode, but in another embodiment of the present invention, it is getting wider as it is farther from the source electrode. In addition, only one area among the plurality of sub-regions R4, R5, and R6 may be different from the remaining area.

At this time, the area of the first subregion R1 of the drain electrode 175a may be the same as the area of the sixth subregion R6 of the dummy drain electrode 175b. Also, the area of the second subregion R2 of the drain electrode 175a may be equal to the area of the fifth subregion R5 of the dummy drain electrode 175b, and the third subregion of the drain electrode 175a ( The area of R3) may be the same as the area of the fourth subregion R4 of the dummy drain electrode 175b.

However, in the illustrated embodiments, the planar shape of the plurality of sub-regions R4, R5, R6 of the dummy drain electrode 175b is different from the plurality of sub-regions R1, R2, R3 of the drain electrode 175a. . Specifically, the edges of the plurality of sub-regions R1, R2, R3 of the drain electrode 175a have a rounded shape, but the plurality of sub-regions R4, R5, R6 of the dummy drain electrode 175b Each has a rectangular shape. That is, the plurality of sub-regions R4, R5, and R6 include an edge parallel to the gate line 121.

Next, referring to FIGS. 13 to 15, the gate electrode 124 and the dummy gate electrode 125 and the drain electrode 175a and the dummy drain electrode 175b of the thin film transistor display panel according to the present exemplary embodiments are described above. Similar to the thin film transistor array panel according to the embodiment described with reference to FIGS. 1 to 3.

The drain electrode 175a faces the source electrode 173 on the gate electrode 124 and overlaps the gate electrode 124. The dummy drain electrode 175b is positioned on the opposite side to the drain electrode 175a and is adjacent to the dummy gate electrode 125.

The drain electrode 175a includes a plurality of subregions R1, R2, and R3 having a constant width based on a direction in which the gate line 121 extends. The dummy drain electrode 175b also includes a plurality of subregions R4, R5, and R6 having a constant width based on the direction in which the gate line 121 extends.

At least one of the plurality of subregions R1, R2, and R3 of the drain electrode 175a includes an edge forming a first angle θ1 with the gate line 121, and a plurality of portions of the dummy drain electrode 175b. At least one of the regions R4, R5, and R6 includes an edge forming the second angle θ2 with the gate line 121.

In the illustrated embodiments, the area of the subregions R1, R2, and R3 of the drain electrode 175a increases as the area away from the source electrode increases, but in the case of a thin film transistor array panel according to other embodiments of the present invention, The area of the sub-regions R1, R2, and R3 of the drain electrode 175a may be narrower as it moves away from the source electrode, and only one of the plurality of sub-regions R1, R2, and R3 is different from the remaining area It might be. In addition, in the illustrated embodiments, the areas of the plurality of sub-regions R4, R5, and R6 of the dummy drain electrode 175b become narrower as they approach the source electrode, but the thin film according to other embodiments of the present invention In the case of a transistor display panel, it may be wider as it approaches the source electrode, and only one area among the plurality of sub-regions R4, R5, and R6 may be different from the remaining area.

At this time, the area of the first subregion R1 of the drain electrode 175a may be the same as the area of the sixth subregion R6 of the dummy drain electrode 175b. Also, the area of the second subregion R2 of the drain electrode 175a may be equal to the area of the fifth subregion R5 of the dummy drain electrode 175b, and the third subregion of the drain electrode 175a ( The area of R3) may be the same as the area of the fourth subregion R4 of the dummy drain electrode 175b.

However, in the illustrated embodiments, the planar shape of the plurality of sub-regions R4, R5, R6 of the dummy drain electrode 175b is different from the plurality of sub-regions R1, R2, R3 of the drain electrode 175a. . Specifically, specifically, the edges of the plurality of sub-regions R1, R2, R3 of the drain electrode 175a have a rounded shape, but the plurality of sub-regions R4, R5 of the dummy drain electrode 175b, R6) each has a trapezoidal or rectangular shape. That is, the plurality of sub-regions R4, R5, and R6 include angled edges, and a portion includes an edge parallel to the gate line 121.

Next, referring to FIG. 16, the gate electrode 124 and the dummy gate electrode 125 of the thin film transistor array panel according to the present embodiment, and the drain electrode 175a and the dummy drain electrode 175b are described above. It is different from the thin film transistor array panel according to.

Specifically, the plurality of sub-regions of the dummy drain electrode 175b have the same area, and the dummy gate electrode 125 includes a plurality of sub-regions Ra, Rb, and Rc. The area of the plurality of sub-regions Ra, Rb, and Rc may be wider or narrower as the drain electrode 175a is closer. However, in the case of the thin film transistor array panel according to another embodiment of the present invention, the dummy drain electrode 175b and the dummy gate electrode 125 may also include a plurality of sub-regions having different areas.

In the case of the thin film transistor array panel according to the present embodiment, the dummy drain electrode 175b has a certain shape, but the dummy gate electrode 125 overlapping the dummy drain electrode 175b has a plurality of sub-regions ( By including Ra, Rb, and Rc, even when the gate wiring of the gate electrode 124 and the dummy gate electrode 125 moves to the right or left, the overlapping area between the drain electrode 175a and the gate electrode 124 The sum of the overlapping areas of the dummy drain electrode 175b and the dummy gate electrode 125 may be kept constant. Therefore, since the total overlapping area between the gate wiring of the gate electrode 124 and the dummy gate electrode 125 and the drain wiring of the drain electrode 175a and the dummy drain electrode 175b does not change, the gate wiring and the drain wiring The size of the parasitic capacity according to the overlap becomes constant.

Next, referring to FIG. 17, the gate electrode 124 and the dummy gate electrode 125 and the drain electrode 175a and the dummy drain electrode 175b of the thin film transistor array panel according to the present embodiment are illustrated in FIGS. 6 to 8. It is similar to the thin film transistor array panel according to the embodiment described for reference.

However, the plurality of subregions of the dummy drain electrode 175b of the thin film transistor array panel according to the present embodiment have the same area, and the dummy gate electrode 125 has a plurality of subregions (Rx, Ry) having different areas. It includes a protrusion (125a) including. The area of the plurality of sub-regions Rx and Ry of the protrusion 125a may be wider or narrower as the drain electrode 175a is closer. However, in the case of the thin film transistor array panel according to another exemplary embodiment of the present invention, both the dummy drain electrode 175b and the protrusion 125a of the dummy gate electrode 125 may include a plurality of subregions having different areas.

In the case of the thin film transistor array panel according to the present embodiment, the dummy drain electrode 175b has a certain shape, but the dummy gate electrode 125 overlapping the dummy drain electrode 175b has a plurality of sub-regions ( By including the protrusions 125a including Rx and Ry, even when the gate wiring of the gate electrode 124 and the dummy gate electrode 125 moves to the right or left, the drain electrode 175a and the gate electrode 124 ), The sum of the overlapping area of the dummy drain electrode 175b and the protrusion 125a of the dummy gate electrode 125 may be kept constant. Therefore, since the total overlapping area between the gate wiring of the gate electrode 124 and the dummy gate electrode 125 and the drain wiring of the drain electrode 175a and the dummy drain electrode 175b does not change, the gate wiring and the drain wiring The size of the parasitic capacity according to the overlap becomes constant.

The area change of the dummy gate electrode 125 is not limited to the embodiment illustrated in FIG. 16 or 17, and may be changed in various ways.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (10)

Board,
A gate line positioned on the substrate and including a gate electrode and a dummy gate electrode spaced apart from each other,
A gate insulating layer on the gate electrode and the dummy gate electrode,
A semiconductor positioned on the gate insulating film, and
A source electrode, a drain electrode, and a dummy drain electrode extended from the drain electrode,
The drain electrode faces the source electrode on the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode or is positioned adjacent to the dummy gate electrode,
The drain electrode includes a plurality of first regions having a constant width in the direction in which the gate line extends, and the dummy drain electrode includes a plurality of second regions having a constant width in the direction in which the gate line extends,
The thin film transistor array panel of each of the plurality of first regions of the drain electrode increases as the distance from the source electrode increases, and that of each of the plurality of second regions of the dummy drain electrode increases as the area of the drain electrode increases.
In claim 1,
At least one of the plurality of first regions of the drain electrode includes a first edge that forms a first angle of 0 degrees or more and 90 degrees or less with the gate line,
At least one of the plurality of second regions of the dummy drain electrode includes a second edge that forms a second angle of 0 degrees or more and 90 degrees or less with the gate line,
The first angle and the second angle are the same thin film transistor array panel.
In claim 1,
At least one of the plurality of first regions of the drain electrode includes an edge that forms an angle of 0 degrees or more and 90 degrees or less with the gate line,
An area of at least one of the plurality of first areas is different from each area of the remaining areas of the plurality of first areas.
In claim 3,
The plurality of first regions include a first sub-region, a second sub-region, and a third sub-region arranged in an order close to the source electrode,
The plurality of second regions includes a fourth subregion, a fifth subregion, and a sixth subregion, which are disposed in a distant order from the source electrode,
The area of the first sub-region is equal to the area of the sixth sub-region,
The area of the second sub-region is equal to the area of the fifth sub-region,
The area of the third sub-region is the same as that of the fourth sub-region.
In claim 4,
A protective film positioned on the source electrode, the drain electrode, and the dummy drain electrode, and
A thin film transistor array panel further comprising a pixel electrode positioned on the passivation layer and connected to the drain electrode through a contact hole formed in the passivation layer.
In claim 5,
Further comprising a common electrode overlapping the pixel electrode and the insulating film therebetween,
One of the pixel electrode and the common electrode includes a plurality of branch electrodes, and the other is a thin film transistor array panel having a plate-like planar shape.
In claim 1,
The plurality of first regions include a first sub-region, a second sub-region, and a third sub-region arranged in an order close to the source electrode,
The plurality of second regions includes a fourth subregion, a fifth subregion, and a sixth subregion, which are disposed in a distant order from the source electrode,
The area of the first sub-region is equal to the area of the sixth sub-region,
The area of the second sub-region is equal to the area of the fifth sub-region,
The area of the third sub-region is the same as that of the fourth sub-region.
In claim 7,
A protective film positioned on the source electrode, the drain electrode, and the dummy drain electrode, and
A thin film transistor array panel further comprising a pixel electrode positioned on the passivation layer and connected to the drain electrode through a contact hole formed in the passivation layer.
In claim 8,
Further comprising a common electrode overlapping the pixel electrode and the insulating film therebetween,
One of the pixel electrode and the common electrode includes a plurality of branch electrodes, and the other is a thin film transistor array panel having a plate-like planar shape.
In claim 1,
The gate electrode includes a plurality of third regions having a predetermined width in a direction in which the gate line extends,
The dummy gate electrode includes a plurality of fourth regions having a constant width in a direction in which the gate line extends,
The thin film transistor array panel of claim 1, wherein each area of the plurality of third regions of the gate electrode is constant, and each area of the plurality of fourth regions of the dummy gate electrode decreases as the distance from the drain electrode increases.

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