KR20200037079A - Bump layout for coplanarity improvement - Google Patents

Abstract

A method includes the following steps of: storing a first design for conductive bumps on a first surface of an interposer, wherein the conductive bumps in the first design have the same cross section area; grouping the conductive bumps of the first design into a first group of conductive bumps located in a first area of the first surface and a second group of conductive bumps located in a second area of the first surface, wherein the bump pattern density of the second area is lower than the bump pattern density of the first area; forming a second design by modifying the first design, wherein the modification of the first design includes the modification of the cross section area of the conductive bumps of the second group in the second area; and forming conductive bumps on the first surface of the interposer in accordance with the second design. After the step of forming the conductive bumps on the first surface of the interposer in accordance with the second design, the conductive bumps of the first group and the conductive bumps of the second group have different cross section areas.

Description

Bump Layout for Improving Coplanarity {BUMP LAYOUT FOR COPLANARITY IMPROVEMENT}

Priority claims and cross-references

This application claims priority to U.S. Provisional Patent Application No. 62 / 738,929 filed on September 28, 2018 in the name of the invention entitled "Bump Layout for Coplanarity Improvement".

The semiconductor industry has experienced rapid growth due to the continuous improvement of the integration density of various electronic components (eg transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density is due to iterative reduction in minimum feature size, which allows more components to be integrated in a given area.

As the demand for miniaturization of electronic devices has increased, the need for packaging technology for smaller and more creative semiconductor dies has emerged. An example of the packaging system described above is a package-on-package (PoP) technology. In PoP devices, the top semiconductor package is stacked on top of the bottom semiconductor package, providing a high level of integration and component density. Another example is a chip-on-wafer-on-substrate (CoWoS) structure. In some embodiments, a plurality of semiconductor chips are attached to the wafer to form a CoWoS structure, followed by a dicing process to separate the wafer into a plurality of interposers, each interposer having one or more A semiconductor chip is attached. The interposer to which the semiconductor chip (s) is attached is referred to as a chip-on-wafer (CoW) structure in some embodiments. The CoW structure is then attached to a substrate (eg, printed circuit board) to form a CoWoS structure. These and other advanced packaging technologies enable the production of semiconductor devices with improved functionality and small footprint.

In an embodiment, the method comprises receiving a first design for a conductive bump on the first surface of the interposer, wherein the conductive bumps in the first design have the same cross-sectional area; Grouping the conductive bumps of the first design into a first group of conductive bumps in the first area of the first surface and a second group of conductive bumps in the second area of the first surface, the bumps of the second area Grouping the conductive bumps, wherein the pattern density is lower than the bump pattern density of the first region; Modifying the first design, wherein modifying the first design includes modifying the cross-sectional area of the second group of conductive bumps in the second area; forming a second design; And forming a conductive bump on the first surface of the interposer according to the second design, and after forming the conductive bump on the first surface of the interposer according to the second design, the first group of conductivity The bump and the second group of conductive bumps have different cross-sectional areas. In an embodiment, the size of the first group of conductive bumps remains unchanged in the first and second designs. In an embodiment, forming a conductive bump comprises: forming a patterned mask layer having bump openings on a first surface of the interposer; And performing a plating process to form a conductive material in the bump openings of the patterned mask layer. In an embodiment, the size of the bump opening in the first area is smaller than the size of the bump opening in the second area. In an embodiment, the bump pattern density of the first region is greater than about 25%. In an embodiment, in the second design, the first group of conductive bumps has a first cross-section with a first dimension, the second group of conductive bumps has a second cross-section with a separate second dimension, and When the bump pattern density is from about 15% to about 25%, the second dimension is from about 1.1 to about 1.25 times the first dimension, and when the bump pattern density in the second region is less than about 15%, the second dimension is from the first dimension About 1.35 times to about 1.55 times the dimension. In an embodiment, the step of grouping the conductive bumps of the first design further comprises grouping the third group of conductive bumps in the third region of the first surface, the bump pattern density of the third region being the second region Is lower than the bump pattern density. In an embodiment, forming the second design further comprises modifying the cross-sectional area of the third group of conductive bumps in the third area. In an embodiment, the bump pattern density of the first region is greater than about 25%, the bump pattern density of the second region is about 15% to about 25%, and the bump pattern density of the third region is less than about 15%. In an embodiment, in the second design, the first group of conductive bumps has a first cross-section with a first dimension, the second group of conductive bumps has a second cross-section with a separate second dimension, and the third group of The conductive bump has a third cross section with distinct third dimensions, the second dimension is from about 1.1 times to about 1.25 times the first dimension, and the third dimension is from about 1.35 times to about 1.55 times the first dimension. In an embodiment, the first cross section, the second cross section and the third cross section have geometrically similar shapes. In an embodiment, the method further comprises attaching the substrate to the conductive bump of the interposer.

In an embodiment, the method is a step of analyzing a first design for a conductive bump on a first surface of the workpiece, the analysis comprising: a first area having a first conductive bump and a second conductive surface of the first surface of the workpiece Dividing into a second region having bumps, the first bump pattern density of the first conductive bumps in the first region is greater than the second bump pattern density of the second conductive bumps in the second region, and the first region Analyzing a first design wherein the first bump pitch of the first conductive bump is less than the second bump pitch of the second conductive bump in the second region; Modifying the first design to form a second design, wherein modifying the first design includes adding dummy bumps to the second area to reduce the second bump pitch; Forming a conductive bump and a dummy bump on the first surface of the workpiece according to the second design; And bonding the workpiece to the substrate through a conductive bump. In an embodiment, the first bump pattern density is greater than about 25%. In an embodiment, the dummy bump is formed of the same material as the conductive bump, and the dummy bump is electrically isolated.

In an embodiment, a semiconductor device includes a die attached to the top surface of the interposer; A first conductive bump in the first region of the lower surface of the interposer, the first region having a first bump pattern density; A second conductive bump in the second region of the lower surface of the interposer, the second region having a second bump pattern density less than the first bump pattern density; And a dummy bump in the circumferential region of the lower surface of the interposer, the circumferential region surrounding the first and second regions. In an embodiment, the first conductive bump in the first region has a first bump pitch, the second conductive bump in the second region has a second bump pitch greater than the first bump pitch, and the dummy bump in the peripheral region is the first. It has a third bump pitch that matches the bump pitch. In an embodiment, the semiconductor device is in a third region of the lower surface of the interposer, the third region has a third bump pattern density less than the second bump pattern density and a fourth bump pitch greater than the second bump pitch. 3 further comprising a conductive bump, wherein the circumferential region surrounds the first region, the second region and the third region. In an embodiment, the first bump pattern density is greater than about 25%. In an embodiment, the first conductive bump and the second conductive bump have the same cross-sectional area.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, according to industry standard practice, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of explanation.
1 illustrates a cross-sectional view of a semiconductor device, in accordance with some embodiments.
2 illustrates the layout of a conductive bump on the surface of an interposer, in some embodiments.
3 illustrates a conductive bump in the surface area of an interposer, in some embodiments.
4A and 4B illustrate top views of conductive bumps with different shapes in some embodiments.
5 illustrates an embodiment of a method of improving the coplanarity of a conductive bump.
6 illustrates an embodiment of a method of improving the coplanarity of a conductive bump.
7A and 7B illustrate embodiments of conductive bumps in the surface area of the interposer before and after applying the method illustrated in FIG. 6.
8A illustrates the layout of a conductive bump on the surface of an interposer in some embodiments.
8B illustrates an enlarged view of a portion of the layout illustrated in FIG. 8A.
9 illustrates a flow chart for a method of forming a semiconductor device in some embodiments.
10 illustrates a flow chart for a method of forming a semiconductor device in some embodiments.
11 illustrates a flow chart for a method of forming a semiconductor device in some embodiments.

The disclosure below presents several different embodiments or examples for implementing different features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples, and are not intended to be limiting. For example, in the following description, the formation of the first feature on the second feature or on the second feature may include embodiments in which the first and second features are formed in direct contact with the first feature. It may also include embodiments in which other features can be formed between the first feature and the second feature such that the second feature cannot be in direct contact. In addition, the present disclosure may repeat reference signs and / or characters in various examples. Throughout the description, unless indicated otherwise, similar reference numerals refer to the same or similar components formed by the same or similar methods using the same or similar material (s).

Moreover, spatial relative terms such as “beneath”, “below”, “lower”, “above”, “upper”, etc., are as illustrated herein in the drawings. It can be used for convenience of description describing the relationship of one element or feature to another element (s) or feature (s). Spatial relative terms are intended to encompass different orientations of the device in use or in process as well as orientation shown in the figures. The device can be oriented differently (rotated 90 degrees or oriented in a different orientation), and the spatially relative descriptors used herein can be interpreted accordingly.

Embodiments of the present disclosure are described with respect to forming conductive bumps, particularly with respect to forming conductive bumps with improved flatness at the surface (eg, bottom surface) of the interposer. In some embodiments, the size of the conductive bumps in areas with low bump pattern density (eg, cross-sectional area) is increased compared to the size of the conductive bumps in the area with high bump pattern density. In some embodiments, dummy bumps are formed between the conductive bumps in the region where the bump pattern density is low, reducing the bump pitch in the region where the bump pattern density is low, and dummy bumps are not formed in the region where the bump pattern density is high. Does not. In some embodiments, dummy bumps are formed in the circumferential region of the surface of the interposer to reduce the bump pitch in the circumferential region, and the bump pitch in other regions of the surface enclosed by the circumferential region remains unchanged ( For example, dummy bumps are not formed in other areas).

1 illustrates a cross-sectional view of a portion of a semiconductor device 100, in accordance with some embodiments. The semiconductor device 100 has a chip on wafer on substrate (CoWoS) structure. For brevity, FIG. 1 shows only the left portion of the semiconductor device 100, and the right portion of the semiconductor device 100 is the same as the left portion shown in FIG. 1 (e.g., symmetrical) as readily understood by those skilled in the art. Or similar.

To form the semiconductor device 100, one or more dies 101 (also referred to as semiconductor dies, chips, or integrated circuits (ICs)) are attached to the interposer 200 to form a chip-on-wafer (CoW) structure. And then a CoW structure is attached to the substrate 300 (eg, a printed circuit board) to form a chip on wafer on board (CoWoS) structure. Die 101 is a die of the same type (eg, memory die or logic die) in some embodiments. In other embodiments, dies 101 are of different types, for example some dies 101 are logic dies and other dies 101 are memory dies.

Each die 101 is interconnected over a substrate, an electrical element formed in / on the substrate (eg, transistors, resistors, capacitors, diodes, etc.) and electrical elements connecting the electrical elements to form a functional circuit of the die 101 Includes structure. Die 101 also includes a conductive pillar 103 (also called a die connector) that provides electrical connection to the circuitry of die 101. For the sake of brevity, not all features of die 101 are illustrated.

The substrate of the die 101 may be a semiconductor substrate, a doped or undoped type, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of semiconductor material, such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that can be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

The electrical components of die 101 include a wide range of active devices (eg transistors) and passive devices (eg capacitors, resistors, inductors) and the like. The electrical element of die 101 may be formed in or on the substrate of die 101 using any suitable method. The interconnect structure of the die 101 includes one or more metallization layers (eg, copper layers) formed in one or more dielectric layers, and is used to connect various electrical elements to form a functional circuit. In an embodiment, the interconnect structure is formed of alternating dielectric layers and conductive (eg, copper) layers, and can be formed through any suitable process (deposition, damascene, dual damascene, etc.).

In order to provide a certain degree of protection for the underlying structure of the die 101, one or more passivation layers may be formed over the interconnect structure of the die 101. The passivation layer may be made of low-k dielectrics such as silicon oxide, silicon nitride, and carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, and combinations thereof. The passivation layer can be formed through a process such as Chemical Vapor Deposition (CVD), but any suitable process can be utilized.

The conductive pad can be formed over the passivation layer and can extend through the passivation layer to make electrical contact with the interconnect structure of the die 101. The conductive pad may include aluminum, but other materials such as copper may be used as an alternative.

The conductive filler 103 of the die 101 is formed on a conductive pad to provide a conductive region electrically connected to the circuit of the die 101. The conductive filler 103 may be a copper filler, a contact bump such as a micro bump, or the like, and may include a material such as copper, tin, silver, or other suitable material.

Looking at the interposer 200 (also referred to as a workpiece) substrate 211, through vias 215 (also called substrate through vias (TSV)), conductive pads 213 on the top surface of the substrate 211, UBM (Under-Bump-Metallurgy) structure 230 on the bottom surface of the substrate 211, and conductive bumps 231 on the UBM structure 230 (also referred to as bumps, connectors, or conductive fillers). 1 also illustrates the surface dielectric layer 219 of the substrate 211 (eg, the lowest dielectric layer). The UBM structure 230 extends through the surface dielectric layer 219 and is electrically coupled with conductive features of the interposer 200 (eg, through vias 215).

The substrate 211 may be, for example, a silicon substrate, a doped or undoped type, or an active layer of a silicon on insulator (SOI) substrate. However, the substrate 211 may alternatively be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate capable of providing adequate protection and / or interconnect functionality.

In some embodiments, substrate 211 may include electrical elements such as resistors, capacitors, signal distribution circuits, combinations thereof, and the like. These electrical elements can be active, passive or combinations thereof. In another embodiment, the substrate 211 is free of both active and passive electrical elements therein. All such combinations are intended to be included entirely within the scope of this disclosure.

The through via 215 extends from the upper surface of the substrate 211 to the lower surface of the substrate 211 and provides electrical connection between the conductive pad 213 and the conductive pump 231. The through via 215 may be formed of a suitable conductive material, such as copper, tungsten, aluminum, alloy, doped polysilicon, combinations thereof, and the like. A barrier layer may be formed between the through via 215 and the substrate 211. The barrier layer may include a suitable material such as titanium nitride, but other materials such as tantalum nitride, titanium, etc. may be used as an alternative.

In an embodiment, UBM structure 230 includes three conductive material layers, such as a titanium layer, a copper layer, and a nickel layer. However, the placement of several suitable materials and layers suitable for the formation of the UBM structure 230, such as the placement of chromium / chromium-copper alloy / copper / gold, the placement of titanium / titanium tungsten / copper, or the placement of copper / nickel / gold. There is. Any suitable material or layer of material usable for the UBM structure 230 is intended to be included entirely within the scope of this disclosure.

The UBM structure 230 forms an opening in the surface dielectric layer 219 to expose conductive features in the substrate 211 (eg, conductive pads electrically coupled to the through vias 215); Forming a seed layer over the surface dielectric layer 219 and along the interior of the opening in the surface dielectric layer 219; Forming a patterned mask layer (eg, photoresist) on the seed layer; Forming conductive material (s) in the opening of the patterned mask layer and over the seed layer (eg, by plating); Removing the mask layer; And removing the portion of the seed layer on which the conductive material (s) is not formed. Other methods for forming the UBM structure 230 are possible, and are intended to be entirely included within the scope of the present disclosure.

The conductive bump 231 is a micro bump, a copper filler, a controlled collapse chip connection (C4) bump, a copper layer, a nickel layer, a lead free (LF) layer, an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) layer, a Cu / LF Any suitable type of external contact, such as a layer, Sn / Ag layer, Sn / Pb layer, combinations thereof, and the like.

In some embodiments, the conductive bump 231 may be a metal filler such as a copper filler formed by a plating process such as electroplating or electroless plating, or may include the metal filler. The conductive bump 231 includes forming a patterned mask layer (eg, photoresist) having an opening exposing the UBM structure 230; Forming conductive material (s) in the opening of the patterned mask layer (eg, by plating) and over the UBM structure 230; And removing the mask layer. Other methods for forming the conductive bump 231 are possible, and are intended to be entirely included within the scope of the present disclosure. In the example of FIG. 1, the UBM structure 230 and each conductive bump 231 have the same width.

In some embodiments, the size of the opening in the mask layer (eg, photoresist) used to form the conductive bump 231 (eg, through a plating process) corresponds to the cross-sectional area of the conductive bump 231 (eg , The same), thereby determining the cross-sectional area of this conductive bump. The cross-sectional area of the conductive bump 231 refers to the cross-sectional area of the conductive bump 231 along cross-section A-A of FIG. 1 in some embodiments. The cross section of the conductive bump 231 may have, for example, a circular shape or an elliptical shape. For ease of explanation, the opening in the patterned mask layer (eg, photoresist) used to form the conductive bump 231 (eg, through a plating process) may hereinafter be referred to as a bump opening.

As illustrated in FIG. 1, the conductive filler 103 of the die 101 is bonded to the conductive pad 213 of the interposer 200 by, for example, solder regions 105. A reflow process may be performed to bond die 101 to interposer 200.

After die 101 is bonded to interposer 200, an underfill material 107 is formed between die 101 and interposer 200. The underfill material 107 may include a liquid epoxy that is then dispensed into a gap between the die 101 and the interposer 200 using a dispensing needle or other suitable dispensing tool. As illustrated in FIG. 1, underfill material 107 may fill the gap between die 101 and interposer 200 and may also fill the gap between the sidewalls of dies 101.

Next, a molding material 109 is formed over the interposer 200 and around the die 101. The molding material 109 also surrounds the underfill material 107. The molding material 109 may include, for example, an epoxy, an organic polymer, a silica-based filler or a polymer with or without a glass filler, or other materials. In some embodiments, the molding material 109 includes a Liquid Molding Compound (LMC), which is a gel-type liquid when applied. The molding material 109 may also include liquids or solids when applied. Alternatively, the molding material 109 can include other sequestering and / or encapsulating materials. The molding material 109 is applied using a wafer level molding process in some embodiments. The molding material 109 can be molded using, for example, compression molding, transfer molding, Molded UnderFill (MUF) or other methods.

Next, the molding material 109 is cured using a curing process in some embodiments. The curing process may include heating the molding material 109 to a defined temperature for a defined period of time using an annealing process or other heating process. The curing process may also include an ultraviolet (UV) light exposure process, an infrared (IR) energy exposure process, a combination thereof, or a combination of these and a heating process. Alternatively, the molding material 109 can be cured using other methods. In some embodiments, a curing process is not included.

After the molding material 109 is formed, a planarization process, such as chemical and mechanical planarization (CMP), can be performed to remove excess portions of the molding material 109 over the die 101, thereby forming the molding material 109 ) And die 101 have a top surface of the same height. As illustrated in FIG. 1, molding material 109 is adjacent to substrate 211.

In the example of FIG. 1, the CoW structure includes interposer 200, die 101, underfill material 107 and molding material 109. Next, the CoW structure may be bonded to the substrate 300-which may be a printed circuit board (PCB)-to form a CoWoS structure.

Looking at the substrate 300, in some embodiments, the substrate 300 is a multilayer circuit board. For example, the substrate 300 is one formed of BT (Bismaleimide Triazine) resin, FR-4 (composite made of glass fiber fabric having a flame-retardant epoxy resin binder), ceramic, glass, plastic, tape, film, or other supporting material. The above dielectric layers 321/323/325 may be included. Substrate 300 may include electrically conductive features (eg, conductive lines 327 and vias 329) formed in / on substrate 300. As illustrated in FIG. 1, the substrate 300 has a conductive pad 326 formed on the upper surface of the substrate 300 and a conductive pad 328 formed on the lower surface of the substrate 300, and the conductive pad (326/238) is electrically coupled to the conductive feature of the substrate 300. An external connector 331, such as a solder ball, copper filler or copper filler with solder on top, is formed on the conductive pad 328 as illustrated in FIG. 1.

The interposer 200 is bonded to the substrate 300. A reflow process can be performed to electrically and mechanically couple the interposer 200 to the substrate 300 through, for example, solder regions 217. Next, an underfill material 112 is formed between the interposer 200 and the substrate 300. The underfill material 112 may be the same or similar to the underfill material 107, and may be formed in the same or similar formation method as the underfill material 107, so the details are not repeated. After the interposer 200 is bonded to the substrate 300, the CoWoS structure of FIG. 1 is formed.

As the integration density of the semiconductor device 100 increases, more die 101 is attached to the interposer 200, so that more functions can be achieved within the semiconductor package. As a result, the interposer 200 May increase in size. Since the size of the interposer 200 increases, the coplanarity (eg, flatness and level) of the conductive bumps of the interposer 200, such as the conductive bumps 231 on the lower surface of the interposer 200, is increased. It becomes increasingly difficult to maintain. The coplanarity of the conductive bumps 231 can be measured by the maximum offset between the end faces of the conductive bumps distal to the substrate 211. For example, the coplanarity of the conductive bumps 231 can be measured by calculating the maximum difference (eg, maximum offset) between the lowest surface of the conductive bumps 231 located in the center region and the circumferential region of the interposer 200. have. As another example, the coplanarity of the conductive bumps 231 may be measured using commercial equipment using a suitable measurement method, such as a peak to least mean square (LMS) method. Thus, a large difference between the bottom surfaces of the conductive bumps indicates poor coplanarity, which can cause problems such as cold-joint or bridging (eg, leakage between conductive bumps). Thereby, the yield of the manufacturing process can be reduced accordingly. Various embodiment methods and structures in the present disclosure improve the coplanarity of the conductive bump 231, thereby improving the reliability of the semiconductor device 100 formed and improving the production yield.

FIG. 2 illustrates a layout (also referred to as a layout design or design) for the conductive pump 231 on the bottom surface of the interposer 200 of FIG. 1 in some embodiments. Accordingly, FIG. 2 is a plan view of the lower surface of the interposer 200. In particular, FIG. 2 illustrates regions (eg, 401, 402, 403) of the lower surface of the interposer 200, on which the conductive bumps 231 are formed, and each region may have a different bump pattern density, and Details regarding the layout of 2 (eg, how to determine the boundaries of different areas) are described later. For brevity, the conductive bumps 231 in the regions (eg, 401, 402, 403) are not illustrated in FIG. 2 but illustrated in FIG. 3.

3 shows an area of the lower surface of the interposer 200 on which the conductive bumps 231 are formed. The region illustrated in FIG. 3 may be any of the regions illustrated in FIG. 2 or a portion of the regions illustrated in FIG. 2 (eg, 401, 402, 403). An example of the shape of the bump 231 of FIG. 3 is illustrated in FIGS. 4A and 4B. In particular, FIG. 4A illustrates a bump 231 having a circular cross section with a diameter R, and FIG. 4B illustrates a bump 231 having an elliptical cross section having a first dimension R1 and a second dimension R2. Illustratively, the second dimension R2 is measured along the longitudinal direction of the elliptical shape (eg, the direction along the long axis of the elliptical shape), and the first dimension R1 is measured along the direction perpendicular to the longitudinal direction. In the illustrated embodiment, the shape and size of the bump 231 in the top view of FIG. 3 is the same as the shape and size of the cross section of the bump 231 (along section A-A of FIG. 1). Thus, the shape and size of the bump 231 corresponds to the shape and size of the bump opening in the mask layer used to form the bump 231, as described above in some embodiments (eg, the same).

Referring again to FIG. 2, region 401 represents a region having a first pattern density for bump 231, region 402 represents a region having a second pattern density for bump 231, Region 403 represents a region having a third pattern density for bump 231, and the term “pattern density” refers to bump 231 within a predetermined region (eg, the region of the lower surface of interposer 200). Refers to the density of

The pattern density of the bumps 231 in a given region may be calculated by dividing the total area of the bumps 231 in the region by the area of the region. In the example of FIG. 3, the illustrated region is a rectangular region having a width b and a length a, thus having an area of a × b. The total area of the bumps 231 in the area is the sum of the areas of the bumps 231 inside the area (eg, the area of the circular shape or elliptical shape of the bump 231 in the plan view of FIG. 3). In the following description, the pattern density of the bump 231 in a given area may be referred to as a pattern density of the corresponding area or a bump pattern density of the corresponding area. In the illustrated embodiment, region 401 has a pattern density greater than about 25%, region 402 has a pattern density from about 15% to about 25%, and region 403 is less than about 15%. It has a pattern density. In the description below, region 401 may be referred to as a high pattern density region, region 402 may be referred to as an intermediate pattern density region, and region 403 may be referred to as a low pattern density region.

In the example of FIG. 2, region 401 includes contiguous regions (eg, rectangular shaped regions), region 402 includes four distinct regions (eg, four rectangular shaped regions), and regions ( 403 includes areas on the lower surface of the interposer 200, other than the areas 401 and 402. The number of regions (e.g., 401, 402, 403) in FIG. 2, the location of the regions and the shape of the regions are merely illustrative, not limiting, and other numbers of regions, different locations of the regions and other shapes of the regions It is also possible and is intended to be included entirely within the scope of this disclosure.

In previous processing not using the present disclosure, the bump openings for forming bumps 231 in different regions (eg, 401, 402, 403) have the same size, and thus conductive bumps 231 formed in different regions. Has the same cross-sectional area. However, it is observed that by using the same bump opening size, the bumps 231 formed in the region with a high pattern density can have a lower height than the bumps 231 formed in the region with a low pattern density. The difference in height of the conductive bumps 231 in regions having different pattern densities may be referred to as a loading effect of the conductive bumps 231 (height) due to the pattern density change. The loading effect contributes to the deterioration of coplanarity of the conductive bump 231. Without being limited to a particular theory, during the plating process to form the bumps 231, the chemical fluid has a substantially uniform metal ion concentration, so that regions with high pattern density have less metal per bump 231. It may have ions, and accordingly, the bump 231 formed in the high pattern density region may have a lower height than the bump 231 formed in the low pattern density region.

Various methods of the present disclosure reduce the height difference of the bumps 231 in regions having different pattern densities, thereby improving the coplanarity of the bumps 231. 5 shows that the bumps 231 reduce the height difference by adjusting the size (eg, cross-section) of the bumps 231 so that the sizes of the bumps 231 in different areas (eg, 401, 402, 403) are different. Illustrates the method. In particular, the size of the bump 231 in the low pattern density area 403 and the size of the bump 231 in the medium density area 402 are increased compared to the size of the bump 231 in the high pattern density area ( See below for details). Adjusting the size of the bumps 231 can be achieved by adjusting the size of the bump openings in the mask layer used to form the bumps 231 as described above.

In some embodiments, the method illustrated in FIG. 5 consists in accommodating a first layout design for conductive bumps 231 (eg, an existing design used as a starting point to improve coplanarity using the methods disclosed herein). Is started by. The first layout design (also referred to as the first design) may include the size (eg, cross-sectional area) of the bump 231 and the location of the bump 231. In the description below, the layout design of FIG. 2 is used as an example of the first design, assuming that bumps 231 in all areas (eg, 401, 402, 403) have the same size (eg, cross-sectional area). Can be. The design of FIG. 2 is eventually modified to form a second design that achieves improved coplanarity for bump 231, the details of which are described below.

Next, the method of FIG. 5 evaluates (e.g., computes) bump pattern density in different areas on the bottom surface of the interposer 200. Based on the pattern density of the bumps 231 in the different regions, the method of FIG. 5 provides the bumps 231 with a high pattern density region 401 (e.g., a pattern density of 25% or more), an intermediate pattern density region ( 402) (e.g., about 15% to about 25% pattern density) or low pattern density area 403 (e.g., 15% or less pattern density). That is, the method includes three regions (401, 402 in FIG. 2) of the lower surface of the interposer 200, such as a high pattern density region 401, an intermediate pattern density region 402, and a low pattern density region 403. 403).

In some embodiments, determining the boundaries of the different areas (eg, 401, 402, 403) may include the lower surface of the interposer 200 in a plurality of non-overlapping grid-like small areas (eg, about 1 mm in size × about Dividing into 0.5 mm rectangular areas, calculating the bump pattern density in each small area, and assigning each small area to one of the areas (eg, 401, 402, 403) based on the calculated pattern density It may include. In some embodiments, the first design may have bumps 231 formed as clusters, each bump cluster having a different bump pattern density, in which case the boundary of each bump 231 cluster is assigned by the bump cluster It can be used as a boundary for the area to be. These and other ways of determining the boundaries of different areas are intended to be entirely within the scope of this disclosure.

Next, the method of FIG. 5 modifies the first layout design to form a second layout design (also referred to as a second design). In particular, in the second layout design, the size (eg, cross-sectional area) of the bump 231 in the low pattern density area 403 and the size (eg, cross-sectional area) of the bump 231 in the middle pattern density area 402 Is adjusted to be greater than the size (eg, cross-sectional area) of the bump 231 in the high density area 401 (eg, increased). The size of the bumps 231 in the high pattern density region 401 remains unchanged between the first layout design and the second layout design in the illustrated embodiment.

In some embodiments, increasing the size (e.g., cross-sectional area) of the bumps 231 in the low and medium pattern density areas, for example, of the mask layer used in the plating process to form the bumps 231 This is achieved by increasing the size of the bump opening. In particular, assuming that the bumps 231 in the first layout design have a circular shape with a diameter R in all regions (eg, 401, 402, 403), applying the method of FIG. 5, the intermediate pattern density region The diameter R 'of the bump opening (e.g., circular shape) in 402 is adjusted to be from about 1.1R to about 1.25R, and the diameter R "of the bump opening in the low pattern density region 403 is It is adjusted to be about 1.35R to about 1.55R. The diameter of the bump opening in the high pattern density region 401 remains R.

If the opening in the first layout design has an elliptical shape with the first dimension R1 and the second dimension R2 in all regions (eg, 401, 402, 403), the intermediate pattern density region 402 in the second design ), The bump opening (e.g., elliptical shape) is adjusted to have a first dimension (R1 ') and a second dimension (R2'), where R1 'is about 1.1R1 to 1.25R1, and the second dimension (R2' ) Is from about 1.1R2 to about 1.25R2. Additionally, the bump opening (eg, elliptical shape) in the low density region 403 is adjusted to have a first dimension (R1 ") and a second dimension (R2"), where R1 "is from about 1.35R1 to about 1.55. R1 and the second dimension (R2 ") is from about 1.35R2 to about 1.55R2. The opening in the high pattern density region 401 still has the first dimension R1 and the second dimension R2.

As described above, the size of the bump openings in the middle pattern density region 402 and the low pattern density region 403 is adjusted to be larger than the size of the bump openings in the high pattern density region 401 by a predetermined percentage. Since the size of the bump openings corresponds to the cross-sectional area of the subsequently formed bumps 231 (e.g., the same), the conductive bumps 231 formed in the regions having different pattern densities using the second layout design have different cross-sectional areas Have Additionally, the relationship between the dimensions of the bump openings in the different areas described above is also the dimensions of the conductive bumps 231 formed in the different areas using the second layout design (e.g., the diameter of the circular shape in FIG. 4A or FIG. 4B). Also applies to the elliptical shape of the first dimension and the second dimension).

The method of FIG. 5 may include additional processing steps, such as forming a conductive bump 231 according to the second layout design. In the example of FIG. 2, region 401 is a high pattern density region, region 402 is a middle pattern density region, and region 403 is a low pattern density region. Therefore, after forming the conductive bump 231 according to the second layout design, the conductive bump 231 in the region 403 has a larger cross-sectional area than the conductive bump 231 in the region 402, and the region 402 The conductive bump 231 in) has a larger cross-sectional area than the conductive bump 231 in the region 401.

As an example, consider a first design in which the bump 231 in the high pattern density region 401 has a first dimension R1 of 70 μm and a second dimension R2 of 90 μm. After the bump sizes in the low pattern density region 403 and the middle pattern density region 402 have been adjusted, the bump 231 in the middle pattern density region 402 has a first dimension of 82 μm and 105 in the second design. The second dimension of μm, and the bump 231 in the low pattern density region 403 has a first dimension of 98 μm and a second dimension of 125 μm.

6 illustrates a method of improving the coplanarity of the conductive bump 231 in another embodiment. In the embodiment of FIG. 6, processing begins by accepting the first design for the conductive bump 231 and evaluating the bump pattern density for different areas on the bottom surface of the interposer 200. Based on the bump pattern density in the different regions, the conductive bumps 231 have a high pattern density region 401 (eg, pattern density of about 25% or more), an intermediate pattern density region 402 (eg, pattern density) Is grouped into different regions, such as about 15% to about 25%) or a low pattern density area 403 (eg, pattern density is 15% or less). The processing is similar to that described above with reference to Fig. 5, so details are not repeated. In the illustrated embodiment, in the first design, the bump pitch P1 in the high pattern density region 401 is smaller than the bump pitch P2 in the intermediate pattern density region 402, and in the intermediate pattern density region 402 The bump pitch P2 of is smaller than the bump pitch P3 in the low pattern density region 403.

Next, the first design is modified to form a second design. Specifically, the pitch of the bumps 231 in the low pattern density region 403 and the pitch of the bumps 231 in the middle density region 402 match the pitch of the bumps 231 in the high pattern density region 401 It is adjusted as much as possible. In some embodiments, to adjust the bump pitch between adjacent bumps 231 / 231D (e.g., to reduce), for example, existing bumps in low pattern density regions 403 and middle pattern density regions 402 ( Dummy bumps 231D (see FIG. 7B) are added between the 231s, so that the adjusted bump pitch in the low pattern density region 403 and the middle pattern density region 402 is high in the pattern density region 401. Matching the bump pitch, the dummy bump 231D is a conductive bump that is electrically isolated (eg, not electrically coupled with other electrically conductive features). In contrast, each conductive bump 231 is electrically coupled to at least one electrically conductive feature of the interposer 200 (eg, contact pads, through vias 215, etc.). The dummy bump 231D may be formed using the same material (s) as the bump 231 and with the same processing steps as the bump 231. The term “matching” herein can be a match between pitches within manufacturing limits or a match between pitches within a given percentage. For example, the bump pitch in the low pattern density region 403 and the middle pattern density region 402 is within a predetermined percentage of the bump pitch in the high pattern density region 401 (eg, ± 15%, ± 10%, or ± 5). %).

As an example, the bump pitch P1 in the high pattern density region 401 is 150 μm, the bump pitch P2 in the middle pattern density region 402 is 180 μm, and in the low pattern density region 403 Consider a first design with a bump pitch (P3) of 250 μm. After correcting the bump pitch, the bump pitch for the bumps 231 in all areas (eg, 401, 402, 403) has the same bump pitch of 150 μm.

In the illustrated embodiment, the cross-sectional areas of the bumps 231 in different areas (eg, 401, 402, 403) do not change between the first design and the second design. In some embodiments, the cross-sectional areas of bumps 231 in different regions (eg, 401, 402, 403) are the same. The method of FIG. 6 may include additional processing steps, such as forming bumps 231 and dummy bumps 231D according to the second design.

7A and 7B respectively illustrate an embodiment of the design for the conductive bump 231 in the region of the lower surface of the interposer 200 before and after applying the method illustrated in FIG. 6. The regions illustrated in FIGS. 7A and 7B may be, for example, portions of the low pattern density region 403 and portions of the middle pattern density region 402. As illustrated in FIG. 7A, the pitch between the bumps 231 of the first design is, for example, 250 μm. 7B shows a dummy bump 231D formed between the bumps 231. For example, the dummy bump 231D may be formed between adjacent bumps 231 in the same row. Additionally, FIG. 7B also illustrates a dummy bump 231D row formed between two adjacent bump 231 rows. In the formed dummy bump 231D, the pitch of the bumps (eg, 231, 231D) is reduced to, for example, 125 μm, to match the pitch density of the high pattern density region 401.

8A illustrates the layout design for the conductive bump 231 on the bottom surface of the interposer 200 using the method of the embodiment. In the example of FIG. 8A, the first design (eg, see FIG. 2) is accepted and evaluated. The pattern density for different areas of the first design is calculated. Based on the calculated pattern density, the bumps 231 have a high pattern density area 401 (e.g., pattern density of 25% or more), an intermediate pattern density area 402 (e.g., pattern density of about 15% to about 25%). %) And low pattern density regions 403 (eg, pattern density of 15% or less). In the embodiment of FIG. 8A, the cross-sectional areas of bumps 231 in different regions (eg, 401, 402, 403) are the same. In FIG. 8A, the high pattern density region 401 has a bump pitch P1, the middle pattern density region has a bump pitch P2, and the low pattern density region has a bump pitch P3. In the illustrated embodiment, the bump pitch P1 is smaller than the bump pitch P2, and the bump pitch P2 is smaller than the bump pitch P3.

In order to reduce the height difference of the conductive bumps 231 in the regions having different pattern densities, the embodiment method of FIG. 8A uses the perimeter 200P (eg sidewall) of the interposer 200 to form a second design. The first design is modified by adding a dummy bump 231D (see FIG. 8B) to the area 404 (also illustrated as a shaded pattern in FIG. 8A). Here, the term “matching” is within a certain percentage of bump pitch in the high pattern density region 401 or matching between pitches within manufacturing limits (eg, within ± 15%, ± 10% or ± 5%). It may be a match between the pitches at.

As illustrated in FIG. 8A, region 404 has a hollow rectangular shape, although other suitable shapes are also contemplated within the scope of the present disclosure. Region 404 may be selected to include N outermost bump columns and / or N outermost bump rows 231 on the bottom surface of interposer 200 in the first design, where N is 5 , May be 5 to 15, such as 10 or 15, that is, there is no bump 231 or 231D between the region 404 and the circumference 200P of the interposer 200. Accordingly, in the second design, the region 404 is formed with both the dummy bump 231D and the conductive bump 231 therein, and the other regions of FIG. 8A (eg, 401, 402, 403) are internally [eg, dummy bump (Not 231D)] Only the conductive bump 231 is formed.

In the embodiment illustrated in FIG. 8A, region 404 surrounds high pattern density region 401, middle pattern density region 402 and low pattern density region 403. Note that in FIG. 8A, region 404 includes sites that previously belonged to low pattern density region 403. Accordingly, in the second design illustrated in FIG. 8A, the region 403 includes a portion of the lower surface of the interposer 200 located inside the region 404 in addition to the region 401/402.

As an example, the bump pitch P1 in the high pattern density region 401 is 150 μm, the bump pitch P2 in the middle pattern density region 402 is 180 μm, and in the low pattern density region 403 Consider a first design with a bump pitch (P3) of 250 μm. In the second design, a dummy bump 231D is formed in the region 404 so that the bump pitch P4 between the bumps (eg, between 231 and 231D) is 150 μm. The method of FIG. 8A may include additional processing steps, such as forming bumps 231 and dummy bumps 231D according to the second design.

In the embodiment of FIG. 8A, the cross-sectional areas of bumps 231 in all regions 401, 402, 403 are the same, and do not change between the first and second designs. Moreover, in the illustrated embodiment, the cross-sectional area of the dummy bump 231D in the region 404 is the same as the cross-sectional area of the conductive bump 231.

8B illustrates an enlarged view of a portion 210 of the region 404 illustrated in FIG. 8A. As illustrated in FIG. 8B, a dummy bump 231D is formed between the bumps 231. 8B also illustrates a row of dummy bumps 231D formed between two rows of conductive bumps 231. The bump pitch (eg, between 231 and 231D) of the region 404 is P4, and P4 matches the bump pitch P1 of the high pattern density region 401.

Modifications to the disclosed embodiments are possible, and are intended to be included entirely within the scope of this disclosure. For example, although various embodiment methods adjust the bump size (eg, cross-sectional area) or bump pitch, it is also possible to improve the coplanarity of the bump 231 by adjusting both the bump size and the bump pitch. For example, the bump opening size in various regions (eg, 401, 402, 403) can be adjusted while the bump pitch in various regions is adjusted. Additionally, while the present disclosure is described in connection with forming conductive bumps 231 on the bottom surface of interposer 200, the disclosed method is directed to other components and / or other surfaces (eg, top surface instead of bottom surface). It can be used to improve the coplanarity of the conductive bump formed on the image.

Embodiments can achieve several advantages. By adjusting the bump size (eg, cross-sectional area) or bump pitch in the design of the conductive bump 231, the height difference of the bumps in areas with different pattern densities is reduced, and the coplanarity of the conductive bumps is improved. The improved coplanarity prevents or reduces problems such as cold joints of the bumps (eg poorly formed solder areas that fail to properly bond the conductive bumps of the two devices) and bridging, thereby improving the reliability of the formed device, Improve production yield. In order to meet the requirements for the coplanarity of conductive bumps without using the currently disclosed method, the reference method may have to reduce the electroplating rate and / or metal ions in the chemical fluid used for electroplating. It may be necessary to increase the concentration (eg, the concentration of Ag), which reduces production throughput and increases manufacturing costs. The present disclosure avoids these problems, thereby achieving increased throughput (eg, higher electroplating rates) and reduced manufacturing costs.

9, 10, and 11 illustrate flow charts respectively for a method of manufacturing a semiconductor device (1000, 2000, 300), according to some embodiments. It should be understood that the embodiment method illustrated in FIGS. 9, 10 and 11 is merely an example of several possible embodiment methods. Those skilled in the art will understand various variations, alternatives and modifications. For example, the various steps illustrated in FIGS. 9, 10 and 11 can be added, removed, replaced, reconfigured and repeated.

Referring to FIG. 9, at block 1010 of method 1000, a first design for a conductive bump on the first surface of the interposer is accommodated, and the conductive bump of the first design has the same cross-sectional area. In block 1020, the conductive bumps of the first design are grouped into a first group of conductive bumps in a first area of the first surface and a second group of conductive bumps in a second area of the first surface, wherein the second The bump pattern density of the region is lower than the bump pattern density of the first region. In block 1030, a second design is formed by modifying the first design, and modifying the first design includes modifying the cross-sectional area of the second group of conductive bumps in the second region. At block 1040, a conductive bump is formed according to the second design on the first surface of the interposer, wherein the first group of conductive bumps and the second group of conductive bumps have different cross-sectional areas after formation.

Referring to FIG. 10, at block 2010 of method 2000, a first design for a conductive bump on a first surface of the workpiece is analyzed, and the analysis is performed on the first surface of the workpiece and the first conductive bump. Dividing into a first region having and a second region having a second conductive bump, the first bump pattern density of the first conductive bump in the first region is the second bump pattern of the second conductive bump in the second region Greater than the density, the first bump pitch of the first conductive bump in the first region is less than the second bump pitch of the second conductive bump in the second region. At block 2020, the first design is modified to form a second design, and modifying the first design includes adding dummy bumps to the second area to reduce the second bump pitch. At block 2030, a conductive bump and a dummy bump are formed on the first surface of the workpiece according to the second design. At block 2040, the workpiece is bonded to the substrate through conductive bumps.

Referring to FIG. 11, at block 3010 of method 3000, a first design for a conductive bump on a first surface of a workpiece-conductive bumps having the same cross-sectional area-is accommodated, wherein the conductive bump is the first surface A first conductive bump in the first region of the first and a second conductive bump in the second region of the first surface, the second region surrounding the first region, and the second bump the first bump of the first bump It has a second bump pitch greater than the pitch. At block 3020, the first design is changed to the second design by adding dummy bumps to the second region to reduce the second bump pitch such that the second bump pitch substantially matches the first bump pitch. At block 3030, a conductive bump is formed according to the second design on the first surface of the workpiece.

In an embodiment, the method comprises receiving a first design for a conductive bump on the first surface of the interposer, wherein the conductive bumps in the first design have the same cross-sectional area; Grouping the conductive bumps of the first design into a first group of conductive bumps in the first area of the first surface and a second group of conductive bumps in the second area of the first surface, the bumps of the second area Grouping the conductive bumps, wherein the pattern density is lower than the bump pattern density of the first region; Modifying the first design, wherein modifying the first design includes modifying the cross-sectional area of the second group of conductive bumps in the second area; forming a second design; And forming a conductive bump on the first surface of the interposer according to the second design, and after forming the conductive bump on the first surface of the interposer according to the second design, the first group of conductivity The bump and the second group of conductive bumps have different cross-sectional areas. In an embodiment, the size of the first group of conductive bumps remains unchanged in the first and second designs. In an embodiment, forming a conductive bump comprises: forming a patterned mask layer having bump openings on a first surface of the interposer; And performing a plating process to form a conductive material in the bump openings of the patterned mask layer. In an embodiment, the size of the bump opening in the first area is smaller than the size of the bump opening in the second area. In an embodiment, the bump pattern density of the first region is greater than about 25%. In an embodiment, in the second design, the first group of conductive bumps has a first cross-section with a first dimension, the second group of conductive bumps has a second cross-section with a separate second dimension, and When the bump pattern density is from about 15% to about 25%, the second dimension is from about 1.1 to about 1.25 times the first dimension, and when the bump pattern density in the second region is less than about 15%, the second dimension is from the first dimension About 1.35 times to about 1.55 times the dimension. In an embodiment, the step of grouping the conductive bumps of the first design further comprises grouping the third group of conductive bumps in the third region of the first surface, the bump pattern density of the third region being the second region Is lower than the bump pattern density. In an embodiment, forming the second design further comprises modifying the cross-sectional area of the third group of conductive bumps in the third area. In an embodiment, the bump pattern density of the first region is greater than about 25%, the bump pattern density of the second region is about 15% to about 25%, and the bump pattern density of the third region is less than about 15%. In an embodiment, in the second design, the first group of conductive bumps has a first cross-section with a first dimension, the second group of conductive bumps has a second cross-section with a separate second dimension, and the third group of The conductive bump has a third cross section with distinct third dimensions, the second dimension is from about 1.1 times to about 1.25 times the first dimension, and the third dimension is from about 1.35 times to about 1.55 times the first dimension. In an embodiment, the first cross section, the second cross section and the third cross section have geometrically similar shapes. In an embodiment, the method further comprises attaching the substrate to the conductive bump of the interposer.

In an embodiment, the method is a step of analyzing a first design for a conductive bump on a first surface of the workpiece, the analysis comprising: a first area having a first conductive bump and a second conductive surface of the first surface of the workpiece Dividing into a second region having bumps, the first bump pattern density of the first conductive bumps in the first region is greater than the second bump pattern density of the second conductive bumps in the second region, and the first region Analyzing a first design wherein the first bump pitch of the first conductive bump is less than the second bump pitch of the second conductive bump in the second region; Modifying the first design to form a second design, wherein modifying the first design includes adding dummy bumps to the second area to reduce the second bump pitch; Forming a conductive bump and a dummy bump on the first surface of the workpiece according to the second design; And bonding the workpiece to the substrate through a conductive bump. In an embodiment, the first bump pattern density is greater than about 25%. In an embodiment, the dummy bump is formed of the same material as the conductive bump, and the dummy bump is electrically isolated.

In an embodiment, a semiconductor device includes a die attached to the top surface of the interposer; A first conductive bump in the first region of the lower surface of the interposer, the first region having a first bump pattern density; A second conductive bump in the second region of the lower surface of the interposer, the second region having a second bump pattern density less than the first bump pattern density; And a dummy bump in the circumferential region of the lower surface of the interposer, the circumferential region surrounding the first and second regions. In an embodiment, the first conductive bump in the first region has a first bump pitch, the second conductive bump in the second region has a second bump pitch greater than the first bump pitch, and the dummy bump in the peripheral region is the first. It has a third bump pitch that matches the bump pitch. In an embodiment, the semiconductor device is in a third region of the lower surface of the interposer, the third region has a third bump pattern density less than the second bump pattern density and a fourth bump pitch greater than the second bump pitch. 3 further comprising a conductive bump, wherein the circumferential region surrounds the first region, the second region and the third region. In an embodiment, the first bump pattern density is greater than about 25%. In an embodiment, the first conductive bump and the second conductive bump have the same cross-sectional area.

The preceding description outlines features of multiple embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be readily used as a basis for constructing or modifying other processes and structures that fulfill the same objectives of the embodiments introduced herein and / or achieve the same advantages of the above embodiments. Only. Those skilled in the art should also understand that such equivalent configurations are not departed from the spirit and scope of the present disclosure, and various changes, replacements, and modifications can be made by those skilled in the art without departing from the spirit and scope of the present disclosure.

Claims (10)

As a method,
Receiving a first design for a conductive bump on the first surface of the interposer, wherein the conductive bumps in the first design have the same cross-sectional area;
Grouping the conductive bumps of the first design into a first group of conductive bumps in the first area of the first surface and a second group of conductive bumps in the second area of the first surface, the bumps of the second area Grouping the conductive bumps, wherein the pattern density is lower than the bump pattern density of the first region;
Modifying the first design, wherein modifying the first design includes modifying the cross-sectional area of the second group of conductive bumps in the second area; forming a second design; And
Forming a conductive bump on the first surface of the interposer according to the second design
And after forming a conductive bump on the first surface of the interposer according to the second design, the first group of conductive bumps and the second group of conductive bumps have different cross-sectional areas. The method of claim 1, wherein the size of the first group of conductive bumps remains unchanged in the first and second designs. The method of claim 1, wherein forming the conductive bump
Forming a patterned mask layer having bump openings on the first surface of the interposer; And
Performing a plating process to form a conductive material in the bump openings of the patterned mask layer
How to include. The method of claim 1, wherein grouping the conductive bumps of the first design further comprises grouping the third group of conductive bumps in the third area of the first surface, wherein the bump pattern density of the third area is The method is less than the bump pattern density of the second region. As a method,
Analyzing a first design for a conductive bump on a first surface of a workpiece, the analysis comprising: a first area of the workpiece having a first region having a first conductive bump and a second conductive bump Dividing into a second region, the first bump pattern density of the first conductive bump in the first region is greater than the second bump pattern density of the second conductive bump in the second region, and the first in the first region Analyzing a first design wherein the first bump pitch of the conductive bump is less than the second bump pitch of the second conductive bump in the second region;
Modifying the first design to form a second design-modifying the first design includes steps to add dummy bumps to the second area to reduce the second bump pitch;
Forming a conductive bump and a dummy bump on the first surface of the workpiece according to the second design; And
Bonding the workpiece to the substrate via conductive bumps
How to include. As a semiconductor device,
A die attached to the top surface of the interposer;
A first conductive bump in the first region of the lower surface of the interposer, the first region having a first bump pattern density;
A second conductive bump in the second region of the lower surface of the interposer, the second region having a second bump pattern density less than the first bump pattern density; And
Dummy bumps in the circumferential area of the lower surface of the interposer-the circumferential area surrounds the first and second areas
A semiconductor device comprising a. 7. The method of claim 6, wherein the first conductive bump in the first region has a first bump pitch, the second conductive bump in the second region has a second bump pitch greater than the first bump pitch, and is in the peripheral region The dummy bump has a third bump pitch that matches the first bump pitch. 8. The third of claim 7, wherein the third area of the lower surface of the interposer-the third area has a third bump pattern density less than the second bump pattern density and a fourth bump pitch greater than the second bump pitch. A semiconductor device further comprising a conductive bump, wherein the circumferential region surrounds the first region, the second region, and the third region. 7. The semiconductor device of claim 6, wherein the first bump pattern density is greater than 25%. The semiconductor device according to claim 6, wherein the first conductive bump and the second conductive bump have the same cross-sectional area.

Images