KR20200032360A - Semiconductor package and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor package using an interposer substrate provided with an air vent and to a manufacturing method thereof. In the present invention, by packaging using an interposer substrate provided with a plurality of air vents at a predetermined position, interlayer peeling and cracks due to a popcorn phenomenon of a package generated during a high-temperature reflow can be prevented, and also an under-fill process is omitted to promote the improvement of the simplicity and productivity of the process.

Description

Semiconductor package and its manufacturing method {SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME}

The present invention relates to a semiconductor package using an interposer substrate equipped with an air vent and a method for manufacturing the same, and more specifically, it occurs during a reflow process by packaging using an interposer substrate provided with a plurality of air vents at a predetermined position. The present invention relates to a semiconductor package having high reliability and excellent physical properties by preventing interlayer peeling and cracks inside the package due to defective popcorn.

Semiconductor packaging protects the integrated circuit or chip from physical damage and external stress. In addition, a thermally conductive path can be provided to efficiently remove heat from the chip, and electrical connections can be provided to other components, such as, for example, printed circuit boards.

Meanwhile, packaging in the form of a package in package (PiP) is required for the purpose of changing the ball layout of the assembled package. When an example of the packaging is described with reference to FIGS. 1 and 6, a pre-packaged package is mounted on an interposer PCB, and a molding process is performed to seal the package. At this time, in order to prevent a defect in popcorn caused when mounting the motherboard due to unfilled molding material and the molding material voids (EMC Void) generated in the lower portion of the package, in the empty space between the interposer substrate and the lower package The underfill process of filling the underfill member is first performed to remove voids under the pre-completed package, and then the molding process is performed (see S30 to S40 in FIG. 6).

However, in the case of the above-described packaging, an investment in equipment is generated as the underfill process is essential, and an increase in TAT and an increase in material cost are caused by adding the process. In addition, when a high-temperature reflow process is performed on the packaging manufactured as described above, moisture inside the package exposed to the high temperature evaporates, causing stress, or the underfill expands, resulting in a problem that popcorn cracks in the package still occur. .

The present invention has been devised to solve the problems of the prior art as described above, and by packaging using an interposer substrate provided with a plurality of air vents at a predetermined position, popcorn defects when the motherboard is mounted even if the conventional underfill process is omitted It is to be prevented, and to provide a semiconductor package and a manufacturing method capable of improving the simplicity and productivity of the process as a technical problem.

In order to achieve the above technical problem, the present invention is an interposer substrate having an air vent formed vertically through; A package unit mounted on an air vent positioned on one surface of the interposer substrate and having at least one semiconductor chip embedded therein; A solder ball formed on the other surface of the interposer substrate; And an encapsulation portion sealing one surface of the interposer substrate and the package unit, a cavity region is formed between the interposer substrate and the package unit, and a portion of the cavity region is provided for air discharge in the cavity. Provides a semiconductor package in communication with the air vent.

According to an embodiment of the present invention, an underfill member filling the cavity region between the interposer substrate and the package unit may be included.

According to an embodiment of the present invention, the package unit may include a plurality of solder balls formed on a bottom surface facing the interposer substrate.

According to an embodiment of the present invention, a part of the solder ball formed on the bottom surface of the package unit is sealed by the sealing part, and the other part can be exposed.

According to an embodiment of the present invention, the package units may be arranged to be symmetrical with respect to the air vent.

According to an embodiment of the present invention, the interposer substrate may include a trench portion recessed at a predetermined depth in both peripheral regions of the air vent.

According to one embodiment of the present invention, the interposer substrate may include a dam portion protruding to a predetermined height in both peripheral regions thereof around the air vent.

According to an embodiment of the present invention, the trench portion and the dam portion may each be a member for preventing leakage of a sealing material constituting the sealing portion.

According to one embodiment of the present invention, the sealing material may include a molding compound (Epoxy Molding Compound).

In addition, the present invention provides a method of manufacturing the above-described semiconductor package.

According to one embodiment of the present invention, the manufacturing method comprises the steps of: (i) preparing an interposer substrate having a plurality of air vents formed vertically through; (ii) mounting a package unit in which at least one semiconductor chip is embedded, on a plurality of air vents positioned on one surface of the interposer substrate; (iii) sealing one surface of the interposer substrate and the package unit; (iv) forming a solder ball on the other surface of the sealed interposer substrate; And (v) dividing the interposer substrate on which the solder balls are formed into semiconductor package units.

According to an embodiment of the present invention, the manufacturing method includes: (i-1) forming a trench portion recessed at a predetermined depth in both peripheral areas of the center of a plurality of air vents provided on the interposer substrate; It may further include.

According to an embodiment of the present invention, the manufacturing method includes: (i-2) forming a dam portion protruding at a predetermined height in both peripheral regions of the air vents provided on the interposer substrate; It may further include.

According to an embodiment of the present invention, even if a conventional underfill process for filling a substrate and a package unit is omitted, it is possible to implement a semiconductor package having excellent physical properties and reliability by preventing popcorn defects when mounting the motherboard. In addition, it is possible to provide a new packaging method with improved process simplicity, productivity and economic efficiency.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a cross-sectional view of a conventional semiconductor package.
2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.
3 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.
4 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.
5 is a process sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.
6 is a process cross-sectional view for explaining a method of manufacturing a conventional semiconductor package.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art, and the following embodiments can be modified in various other forms, and the scope of the present invention It is not limited to the example. At this time, the same reference numerals refer to the same structure throughout the present specification.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used as meanings commonly understood by those skilled in the art to which the present invention pertains. In addition, terms defined in the commonly used dictionary are not ideally or excessively interpreted unless specifically defined.

In addition, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, the present invention is not necessarily limited to what is illustrated. In the drawings, thicknesses are enlarged to clearly represent various layers and regions. In the drawings, thicknesses of some layers and regions are exaggerated for convenience of description.

Also, in the specification, when a part “includes” a certain component, it means that other components may be further included instead of excluding other components, unless otherwise stated. In addition, throughout the specification, "above" or "on" means that not only is located above or below the target part, but also when there is another part in the middle, and the direction of gravity must be determined. It does not mean that it is located above the standard. In addition, in the present specification, terms such as “first” and “second” are not used to indicate any order or importance, but are used to distinguish elements from each other.

In addition, throughout the specification, when referred to as "planar", this means when the object part is viewed from above, and when it is referred to as "cross-sectional", it means when the cross section of the object part vertically cut is viewed from the side.

<Semiconductor package>

The present invention provides a semiconductor package capable of continuously maintaining reliability and excellent electrical characteristics by preventing popcorn cracks caused by voids when mounting a motherboard while securing high design freedom by changing the ball layout of the assembled package. do.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 2 to 4.

2 is a cross-sectional view schematically showing the structure of a semiconductor package 100 according to an embodiment of the present invention.

Referring to FIG. 2, a semiconductor package 100 according to an embodiment of the present invention includes an interposer substrate 10, a package unit 20 in which at least one semiconductor chip is embedded, and an encapsulation portion 30 sealing them. And a solder ball 40 for connecting an external terminal. Specifically, the semiconductor package 100 includes an interposer substrate 10 having an air vent 15; An airtight package unit 20 mounted on the air vent 15 located on one surface of the interposer substrate 10; A plurality of solder balls 40 fused to the other surface of the interposer substrate 10 on which the package unit 20 is not mounted; And an encapsulation portion 30 sealing one surface of the interposer substrate 10 and the package unit 20.

The interposer substrate 10 may be a package substrate, and may include various materials known in the art. In one example, the interposer substrate 100 may be made of a semiconductor material or an insulating material, and may include, for example, silicon, germanium, silicon-germanium, gallium-arsenide (GaAs), glass, ceramic, and the like. In addition, the interposer substrate 10 can be used without limitation a conventional printed circuit board known in the art.

In the present invention, the printed circuit board (PCB) refers to a circuit wiring board laminated in a single layer or a multilayer structure of at least two or more layers by a plating through-hole method or a build-up method. These printed circuit boards are single-sided or double-sided, or include both coreless printed circuit boards. In addition, a conventional substrate in the art made of a copper foil layer or having a form in which an insulating adhesive layer and a copper foil layer are laminated, a copper foil with a resin, a copper foil laminate (CCL), a flexible copper foil laminate (FCCL), and a printed circuit board (PCB). Alternatively, a flexible printed circuit board (FPCB) may be used. Specifically, the interposer substrate 10 may be a printed circuit board (PCB) including a circuit pattern of at least one layer, and in particular, a PCB substrate for a semiconductor package using a BT (Bismaleimide-Triazine) core desirable.

According to an embodiment of the present invention, the interposer substrate 10 includes a first insulating layer 11; A copper foil layer 12 disposed on both sides of the first insulating layer 11; And a second insulating layer 13 disposed on the copper foil layer 12, respectively. At this time, the first insulating layer 11 and the second insulating layer 13 are the same as or different from each other, and may each include a common configuration known in the art. The first insulating layer 11 and the second insulating layer 13 may be used without limitation, a conventional polymer resin known in the art, for example, a thermosetting resin, a thermoplastic resin and a combination thereof. Specifically, the first insulating layer 11 may be a prepreg, BT or FR4 in a composite form in which glass fibers and resin are mixed, and the second insulating layer 13 may be a photoresist layer (PSR). have. However, it is not limited thereto.

The interposer substrate 10 is provided with a plurality of air vents 15 formed to penetrate from the upper surface to the lower surface of the substrate 10. The air vent 15 provides a path for discharging the air inside the package to the outside. The size of the air vent 15 is not particularly limited, and may have a hole size of a level used when forming a general PCB via. In one example, the cross-sectional diameter of the air vent 15 may be 50 to 200 μm, and preferably 80 to 120 μm. In addition, the number of air vents 15 formed on the interposer substrate 10 can be freely adjusted according to the size of the substrate. For example, it may be 1 to 5, specifically 1 to 3, but is not particularly limited thereto. The shape of the air vent 15 is not particularly limited, and may be in various forms. For example, the cross-sectional shape may be square, circular, oval, or oval.

The package unit 20 is mounted on one surface of the interposer substrate 10, and preferably mounted on an air vent 15 located on one surface of the interposer substrate 10. The package unit 10 may be disposed to be symmetrical with respect to the air vent 15, specifically, a first direction line (eg, a longitudinal direction of the interposer substrate) passing through the center of the air vent 15. It can be arranged to have a symmetrical or centrosymmetrically symmetrical structure. In addition, the package unit 20 includes a conventional connecting member in the art to form an electrical connection structure with the interposer substrate 10. The connecting member may be formed on the bottom surface of the package unit 20 facing the interposer substrate 10, and a plurality of solder balls 21 may be used. Some of the solder balls 21 are sealed by the sealing portion 30 to be described later, while others are not sealed and may be disposed in an exposed form in the cavity region 50.

The package unit 20 may be a pre-completed package in which at least one semiconductor chip (not shown) is embedded, or may be a single number of semiconductor chips or a plurality of semiconductor chips known in the art. For example, when the package unit 20 is a pre-completed package, at least one semiconductor chip is mounted on one surface of the substrate, a plurality of solder balls for connection fused to the other surface are disposed, and one surface of the substrate and the semiconductor chip It may be a structure in which an encapsulation portion for sealing is formed.

The semiconductor chip is not particularly limited, and may be, for example, a logic semiconductor chip or a memory semiconductor chip. For example, semiconductor chips include system large scale integration (LSI), logic circuits, image sensors such as CMOS imaging sensors (CIS), flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, ReRAM, high bandwidth memory (HBM), HMC Memory devices such as (hybrid memory cubic), or one or more selected from a microelectromechanical system (MEMS) device. When a plurality of semiconductor chips are mounted on the package unit 20, they may be horizontally spaced apart at predetermined intervals, or vertically stacked.

The solder ball 40 serves to connect to an external terminal, and is formed on the other surface (eg, a lower surface) of the interposer substrate 10 on which the package unit 20 is not mounted. Although not shown in the drawing, a solder ball pad may be disposed between the interposer substrate 10 and the solder ball 40. The solder ball 40 may electrically connect the semiconductor package to a module board or a main circuit board. In the present invention, a solder ball is exemplified and described as a connection terminal, but it is also within the scope of the present invention to use other connection terminals such as conductive bumps.

The encapsulation unit 30 is formed to cover the entire surface (top surface) of the interposer substrate 10 including the package unit 20. The encapsulation unit 30 is formed to fill the space between the package unit 20 and the interposer substrate 10 to protect the package unit 20, and the adhesive force between the package unit 20 and the interposer substrate 10 It can serve to increase. In addition, the external shape of the semiconductor package may be maintained, and the package unit 20 in which the semiconductor chip is embedded may be protected from external physical shock or moisture. The encapsulation portion 30 may be used without limitation, a conventional sealing material known in the art, for example, may include a molding compound (EMC: Epoxy Molding Compound).

On the other hand, in order to prevent voids inside the package, the conventional semiconductor package has a packaged structure by filling the underfill member 60 between the interposer substrate 10 and the package unit 20. In contrast, the semiconductor package 100 of the present invention is a void space that is not sealed with an encapsulation 30 between the interposer substrate 10 and the package unit 20, that is, a cavity area 50 ) Is formed, and a part of the cavity region 50 has a structure in communication with the air vent 15. In particular, a portion of the bottom surface of the package unit 20 is exposed in the cavity region 50. Accordingly, since the air inside the cavity 50 generated from the package unit 20 during reflow can serve as an air channel for discharging the air through the air vent 15 to the outside, it is high without generating popcorn defects. Reliability can be achieved.

3 is a cross-sectional view schematically showing a cross-section of a semiconductor package 200 according to another embodiment of the present invention. 3, the same reference numerals as those in FIG. 2 denote the same members.

Hereinafter, in the description of FIG. 3, overlapping content with FIG. 2 will not be described again, and only the differences will be described. Referring to FIG. 3, the semiconductor package 200 according to the present embodiment has a predetermined depth in the peripheral areas on both sides of the air vent 15 positioned on one surface of the interposer substrate 10 as compared to FIG. 2. The recessed trench portion 16 is further included.

In the case of the semiconductor package 100 of FIG. 2, the sealing material flows into the cavity 50 and overflows with the air vent 15 in the process of injecting or curing the sealing material (eg, EMC) constituting the sealing part 30 The encapsulation material may be lost or overflowed.

On the other hand, the trench portion 16 of FIG. 3 is a sealing material overflow prevention member for preventing leakage of the sealing material constituting the encapsulation portion 30 or flowing out of the air vent 15. The trench portion 16 may be formed to be symmetrical or centered symmetrically around the air vent 15. The method of forming the trench portion 16 is not particularly limited, and an etching method known in the art can be used without limitation. In one example, the trench portion 16 may be formed by physically or chemically etching a portion of the second insulating layer 13 provided on the outermost surface of the interposer substrate 10, for example, a PSR.

The trench portion 16 is formed around the air vent 15 and serves to minimize the flow of the sealing material, EMC, into the air vent 15. Accordingly, if the external leakage of the above-described sealing material can be prevented, the shape, size, and number of trench portions 16 are not particularly limited. In one example, the depth of the trench portion 16 may be the thickness level of the PSR applied to the interposer substrate, and may be specifically 20 to 100 μm. In addition, the width of the trench portion 16 is 50 to 300 μm, and preferably 100 to 200 μm. In addition, the number of trench portions 16 is not particularly limited, and may be composed of a plurality of at least two or more. As illustrated in FIG. 3, the trench portions 16 may be formed one at a time (eg, 1 pair), respectively, around the air vent 15, or composed of a plurality of two (eg, 2 pairs) or more. Can be. As described above, when a plurality of trench portions 16 are formed, they may be continuously formed or spaced apart at a predetermined distance. In addition, the plurality of trench portions 16 may each have the same depth and width, or may have different depths. When a plurality of trench portions 16 having different depths are provided, the depth of the trench portions 16 may increase as the air vents 16 are adjacent to each other.

In addition, the trench portion 16 may be formed in a circular shape on both sides of the air vent 15, but is not particularly limited thereto.

In addition, in the embodiment of FIG. 3, since the description of the semiconductor package of FIG. 2 may be applied to the description of the material, structure, and the like of each component, a detailed description thereof will be omitted.

4 is a cross-sectional view schematically illustrating a cross-section of a semiconductor package 300 according to another embodiment of the present invention. 4, the same reference numerals as those in FIG. 2 denote the same members.

Hereinafter, in the description of FIG. 4, overlapping content with FIG. 2 will be omitted, and only the differences will be described. Unlike the embodiment of FIG. 2, the semiconductor package 300 of FIG. 4 has a dam portion 17 protruding to a predetermined height in both peripheral regions of the air vent 15 positioned on one surface of the interposer substrate 10 It further includes.

The dam portion 17 is a sealing material overflow prevention member for preventing the leakage of the sealing material constituting the encapsulation portion 30 from flowing out of the air vent 15 or overflowing. The dam portion 17 may be formed to be symmetrical to the left or right centered around the air vent 15. The method for forming the dam portion 17 is not particularly limited, and a coating method known in the art can be used without limitation. In one example, the dam portion 17 may be formed by applying a conventional resin in the art on the surface of the interposer substrate 10, preferably the same components as the second insulating layer 13, for example, PSR coating Can be formed.

Dam portion 17 is also formed around the air vent 15 serves to minimize the flow of the sealing material EMC flows into the air vent (15). Accordingly, if the external leakage of the sealing material can be prevented, the shape, size, and number of the dam portions 17 are not particularly limited. As an example, the height of the dam portion 17 may be 20 to 100 μm. In addition, the width of the dam portion 17 is 50 to 300 μm, and preferably may be 100 to 200 μm. In addition, the number of dam portions 17 is not particularly limited, and may be composed of a plurality of at least two or more. As illustrated in FIG. 4, each of the dam parts 17 may be formed one (eg, one pair) in the periphery of the air vent 15, or may be composed of a plurality of two (eg, two pairs) or more. You can. In this way, when the dam parts 17 are composed of a plurality, they may be continuously formed or spaced apart at a predetermined distance. In addition, the plurality of dam parts 17 may each have the same height and width, or may have different heights. When a plurality of dam parts 17 having different heights are provided, the height of the dam parts 17 may increase as the air vents 15 are adjacent to each other.

In addition, the dam portion 17 may be formed in a circular shape on both sides of the air vent 15, but is not particularly limited thereto.

In addition, in the embodiment of FIG. 4, description of the material and structure of each component may be applied to the semiconductor package of FIG. 2 as it is, and detailed description thereof will be omitted.

Meanwhile, FIGS. 3 and 4 specifically illustrate an embodiment (two in total) in which the trench portion 16 and the dam portion 17 are formed on both sides of the air vent 15, respectively. However, the present invention is not limited thereto, and the number, shape, and size of the trench portion 16 and the dam portion 17 are not particularly limited. That is, the configuration of the trench portion 16 and the dam portion 17 is not particularly limited, and can be freely deformed to have various shapes and sizes.

<Method of manufacturing a semiconductor package>

Hereinafter, a method for manufacturing the above-described semiconductor package according to an embodiment of the present invention will be described. However, it is not limited only by the following manufacturing method or order, and the steps of each process may be modified or selectively mixed as necessary.

For a preferred embodiment of the method for manufacturing a semiconductor package according to the present invention, (i) preparing an interposer substrate 10 having a plurality of air vents 15 formed through the top and bottom (step S10) ); (ii) mounting each of the package units 20 on which at least one semiconductor chip is embedded on a plurality of air vents 15 located on one surface of the interposer substrate 10 ('step S20'); (iii) sealing one surface of the interposer substrate 10 and the package unit 20 ('S30 step'); (iv) forming a solder ball 40 on the other surface of the sealed interposer substrate 10 ('step S40'); And (v) dividing the interposer substrate 10 on which the solder ball 40 is formed into semiconductor package units ('S50 step'). The semiconductor packaging method of the present invention configured as described above can omit the underfill process performed before the conventional molding process, thereby increasing the simplicity and productivity of the process and securing economical efficiency due to the use of the underfill material. have.

5 is a cross-sectional view schematically showing a method of manufacturing the semiconductor package 100 of FIG. 2. Hereinafter, referring to the accompanying drawings, the manufacturing method is divided into steps for each process and described as follows.

1) Preparing the interposer substrate with air vent (hereinafter referred to as 'S10 step')

In step S10, an interposer substrate 10 in which a plurality of air vents 15 are formed at a predetermined position is prepared (see S10 in FIG. 5).

Referring to S10 of FIG. 5, the interposer substrate 10 has a plurality of package unit areas (not shown) for mounting the package unit 20 on one surface, and an air vent is provided at the center of each package unit area. 15 is formed.

The interposer substrate 10 may be a printed circuit board (PCB) on which a predetermined circuit pattern (not shown) is formed. In detail, the interposer substrate 10 has a strip structure in which a plurality of semiconductor package unit regions (not shown) in which a package unit 20 is mounted to complete one package is divided along a horizontal and vertical direction. Therein, a sawing line may be formed at a boundary portion dividing each package unit region.

As a method of forming a plurality of air vents 15 on the interposer substrate 10, methods known in the art may be used without limitation. For example, laser cutting or mechanical punching may be used.

After passing through the step S10, in the present invention, a trench portion 16 concave at a predetermined depth is formed in both peripheral regions of the air vent 15 provided in the interposer substrate 10, as required. Step (S11) to do; And (i-2) forming a dam portion 17 protruding to a predetermined height in both peripheral areas of the center of the air vent 15 provided in the interposer substrate 10 (S12). It may contain one more.

2) Package unit mounting stage (hereinafter referred to as 'S20 stage')

In the step S20, the package units 20 are mounted on a plurality of air vents 15 located on one surface of the interposer substrate 10, respectively (see S20 in FIG. 5).

The package unit 20 may be a pre-completed package in which at least one semiconductor chip (not shown) is embedded, or an electronic device such as a semiconductor chip known in the art may be used. For example, it may be related to a light source, a backlight driving circuit, a camera driving circuit, a power driving circuit, and the like.

The package unit 20 may be mounted on the interposer substrate 10 according to conventional methods known in the art. In one example, a connecting member may be formed on the bottom surface of the package unit 20 facing the interposer substrate 10. Examples of such connection members include solder balls 21 or conductive bumps. Alternatively, it may be mounted on the interposer substrate 10 using a conductive adhesive tape, adhesive, anisotropic conductive film (ACF), or the like.

3) Sealing step (hereinafter referred to as 'S30 step')

In the step S30, a process of sealing the entire surface of the interposer substrate 10 and the package unit 20 with a sealing material such as an epoxy mold compound (EMC) is performed (see S30 in FIG. 5).

As the sealing material, a conventional encapsulant material known in the art may be used without limitation, and for example, EMC (Epoxy Molding Compound) or other thermosetting resin may be used. In addition, the sealing material may further include a conventional filler in the encapsulant material resin. The components of the filler are not particularly limited, and for example, materials having excellent thermal conductivity such as silica (SiO ₂ ), alumina (Al ₂ O ₃ ), boron nitride (BN), and the above-mentioned electromagnetic wave shielding fillers (eg, metal, carbon Materials, ferrite, etc.) or a mixture of these.

In addition, the method of forming the sealing portion 30 using the above-described sealing material, it is possible to use without limitation a molding process known in the art. As an example, a transfer molding method in which a molding resin (eg, EMC) is injected and molded at a high pressure; A compression molding method for molding a semiconductor package by dipping it into a molding resin; Or a film assist molding method.

When the step S30 is performed, one surface of the interposer substrate 10 on which the package unit 20 is mounted is sealed in bulk, and some of the plurality of solder balls 21 formed on the bottom surface of the package unit 20 are sealed by EMC. And the other part is unsealed and exposed. Particularly, in the present invention, due to the omission of an underfill process, a part of the space between the package unit 20 and the interposer substrate 10 exists as a void area (cavity). ) A part of the bottom surface of the package unit 20 is exposed in a part of the area. Compared to the conventional semiconductor package, it was difficult to prevent the molding material voids (EMC Void) generated under the packaged package even when the underfill member was charged, and the popcorn defect caused when mounting the motherboard due to the unfilled molding material. By forming an air channel through a structure in which the cavity 50 existing in the semiconductor package and the air vent 15 connected to the outside communicate with each other, air discharge in the cavity 50 during high temperature reflow process It can be easily done. Therefore, the above-described popcorn generation and reliability reduction can be eliminated.

4) Solder ball forming step (hereinafter referred to as 'S40 step')

Subsequently, in the step S40, a plurality of solder balls 40 are fused to the other surface of the interposer substrate 10 according to a conventional method known in the art (see S40 in FIG. 5 below).

The shape and size of the formed solder ball 40 is not particularly limited, and can be appropriately adjusted within a conventional range known in the art. In one example, it may be an array (array) shape.

5) Singulation stage (hereinafter referred to as 'S50 stage')

Subsequently, in the step S50, the solder ball 280 is fused to the other surface, and the interposer substrate 10 on which one surface is resin-sealed is sawed in individual units, thereby completing the semiconductor package of the present invention.

At this time, the process of completely cutting the interposer substrate 10 in the form of a printed circuit board in a package unit may be performed using a conventional process known in the art, such as saw blade or laser cutting. have.

The semiconductor package of the present invention manufactured as described above may be manufactured through batch encapsulation and singulation, and for example, the encapsulation method is a semiconductor package, such as a MAP (Moldied Array Packaging) method, or a WL (Wafer Lebel packaging) method. Can be lifted. In addition, examples of the shape of the semiconductor package include a ball grid array (BGA), a quad flat non-leaded package (QFN), and a small outline non-leaded package (SON).

In the above, embodiments of the semiconductor package and the manufacturing method of the present invention have been described with reference to the accompanying drawings. The present invention is not limited to the above-described embodiments, and various substitutions, modifications and changes are possible within the scope of the technical spirit of the present invention to those skilled in the art to which the present invention pertains. Therefore, the scope of the present invention should be construed as being limited to the described embodiments, and should be interpreted as including the claims and equivalents as well as the claims described later.

100, 200, 300: semiconductor package
10: interposer substrate
11: 1st insulating layer
12: copper foil layer
13: second insulating layer
15: air vent
16: Trench
17: dam section
20: package unit
21, 40: solder ball
30: sealing bag
50: cavity
60: no underfill

Claims (12)

An interposer substrate having an air vent formed vertically through;
A package unit mounted on an air vent positioned on one surface of the interposer substrate and having at least one semiconductor chip embedded therein;
A solder ball formed on the other surface of the interposer substrate; And
And an encapsulation portion sealing the package unit and one surface of the interposer substrate,
A semiconductor package in which a cavity region is formed between the interposer substrate and the package unit, and a portion of the cavity region communicates with the air vent to discharge air in the cavity. According to claim 1,
A semiconductor package comprising an underfill member filling a cavity region between the interposer substrate and the package unit. According to claim 1,
The package unit, a semiconductor package including a plurality of solder balls formed on the bottom surface facing the interposer substrate. According to claim 3,
A portion of the solder ball formed on the bottom surface of the package unit is sealed by the encapsulation portion, and the other portion is exposed to the semiconductor package. According to claim 1,
The package unit, the semiconductor package is disposed to be symmetrical with respect to the air vent. According to claim 1,
The interposer substrate is a semiconductor package including a trench portion recessed at a predetermined depth in both peripheral areas thereof around the air vent. According to claim 1,
The interposer substrate, the semiconductor package including a dam portion protruding to a predetermined height on both sides of the peripheral area around the air vent. The method of claim 6 or 7,
Each of the trench portion and the dam portion is a semiconductor package that is a member for preventing overflow of a sealing material constituting the sealing portion. The method of claim 8,
The sealing material is a semiconductor package containing a molding compound (Epoxy Molding Compound). (i) preparing an interposer substrate provided with a plurality of air vents that are formed to penetrate vertically;
(ii) mounting a package unit in which at least one semiconductor chip is embedded, on a plurality of air vents positioned on one surface of the interposer substrate;
(iii) sealing one surface of the interposer substrate and the package unit;
(iv) forming a solder ball on the other surface of the sealed interposer substrate; And
(v) dividing the interposer substrate on which the solder balls are formed into semiconductor package units
The manufacturing method of the semiconductor package of Claim 1 containing. The method of claim 10,
The manufacturing method,
(i-1) forming a trench portion recessed to a predetermined depth in both peripheral regions of the center of the plurality of air vents provided on the interposer substrate; further comprising a semiconductor package manufacturing method. The method of claim 10,
The manufacturing method,
(i-2) forming a dam portion protruding to a predetermined height in both peripheral regions of the center of the plurality of air vents provided on the interposer substrate; further comprising a semiconductor package manufacturing method.

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