KR20200024027A - Display device - Google Patents

Abstract

According to the present invention, a display device comprises: vertical lines arranged on a substrate and configured to receive predetermined signals, respectively; a buffer layer arranged on the vertical lines; and transistors arranged on the buffer layer. The transistors each include: a semiconductor layer; a gate insulation layer; a gate electrode; a source electrode; and a drain electrode. The semiconductor layer is arranged on the buffer layer and includes a channel region, a source region, and a drain region. The gate insulation layer covers the semiconductor layer and includes a source contact hole which at least partially exposes the source region of the semiconductor layer and a drain contact hole which at least partially exposes the drain region of the semiconductor layer. The gate electrode overlaps the channel region while having the gate insulation layer therebetween. The source electrode is arranged on the gate insulation layer and is in contact with the source region of the semiconductor layer through the source contact hole. The drain electrode is arranged on the gate insulation layer, is in contact with the drain region of the semiconductor layer through the drain contact hole, and is separated by a predetermined distance from the source electrode. According to the present invention, it is possible to prevent a short defect between lines.

Description

Display {DISPLAY DEVICE}

The present invention relates to a display device.

Various display devices are being developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and organic light emitting display devices (OLEDs); ) May be implemented.

Among these flat panel displays, an organic light emitting display device is a self-luminous display device that excites an organic compound to emit light, and does not require a backlight used in an LCD. In addition, organic light emitting display devices are widely used in that they can be manufactured at low temperature, have a response speed of 1 ms or less, high speed response speed, and low power consumption, wide viewing angle, and high contrast. .

The organic light emitting display includes an organic light emitting diode that converts electrical energy into light energy. The organic light emitting diode includes an anode, a cathode, and an organic light emitting layer disposed therebetween. In the organic light emitting diode display, holes and electrons injected from the anode and the cathode, respectively, are combined within the light emitting layer to form an exciton, which is an exciton, and the formed exciton is a ground state in an excited state. It will fall to the light emitting to display an image.

Recently, efforts have been made to provide a thin organic light emitting display device. In this case, since the spacing between the lines is reduced, a short failure may occur in an overlap region even though lines to which different signals are applied are arranged with at least one insulating layer interposed therebetween. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of securing a sufficient distance between lines to which different signals are applied without increasing the overall thickness of the display device.

The display device according to the present invention includes vertical lines disposed on a substrate and configured to receive a predetermined signal, buffer layers disposed on the vertical lines, and transistors disposed on the buffer layer. Each of the transistors includes a semiconductor layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode. The semiconductor layer is disposed on the buffer layer and includes a channel region, a source region, and a drain region. The gate insulating layer covers the semiconductor layer and has a source contact hole exposing at least a portion of the source region of the semiconductor layer and a drain contact hole exposing at least a portion of the drain region of the semiconductor layer. The gate electrode is disposed to overlap the channel region with the gate insulating layer interposed therebetween. The source electrode is disposed on the gate insulating layer and contacts the source region of the semiconductor layer through the source contact hole. The drain electrode is disposed on the gate insulating layer, and contacts the drain region of the semiconductor layer through the drain contact hole, and is spaced apart from the source electrode by a predetermined distance.

The present invention can secure sufficient spacing between lines to which different signals are applied without increasing the overall thickness of the display device. Accordingly, the present invention can prevent short defects between lines, which has the advantage of ensuring reliability.

The present invention does not require a separate compensation structure for repairing pixel defects. Accordingly, the present invention has an advantage that it can be easily applied to a high resolution display device because it is not necessary to allocate a separate repair area in the display area.

1 is a schematic block diagram of an organic light emitting display device.
2 is a schematic circuit diagram of a subpixel.
3 is an exemplary circuit configuration of a subpixel.
4 illustrates a cross-sectional view of a display panel.
5 is a diagram schematically illustrating a planar layout of subpixels according to a comparative example.
6A is an enlarged plan view of the first region of FIG. 5.
FIG. 6B is an enlarged plan view of the second region of FIG. 5.
6C is an enlarged plan view of the third region of FIG. 5.
FIG. 7 is a cross-sectional view taken along line II ′ of FIG. 5.
8 is a cross-sectional view taken along the line II-II ', III-III', and IV-IV 'of FIGS. 6A to 6C, respectively.
9 is a diagram schematically illustrating a planar layout of subpixels according to an exemplary embodiment of the present invention.
FIG. 10A is an enlarged plan view of the first region of FIG. 9.
FIG. 10B is an enlarged plan view of the second region of FIG. 9.
FIG. 10C is an enlarged plan view of the third region of FIG. 9.
FIG. 11 is a cross-sectional view taken along line VV ′ of FIG. 9.
FIG. 12 is a cross-sectional view of FIGS. 10A to 10C taken along line VI-VI ', VIII-VIII and VIII-VIII, respectively.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals refer to substantially identical components throughout the specification. In the following description, when it is determined that the detailed description of the known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In the description of the comparative example and the embodiment, the same components are representatively described at the beginning and may be omitted in other parts below.

Terms including ordinal numbers such as first and second may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The display device according to the present invention is a display device in which a display element is formed on a substrate. The display device may be implemented as an organic light emitting display device, a liquid crystal display device, an electrophoretic display device, or the like. Hereinafter, the organic light emitting display device is described as an example for convenience of description.

1 is a schematic block diagram of an organic light emitting display device. 2 is a schematic circuit diagram of a subpixel. 3 is an exemplary circuit configuration of a subpixel. 4 illustrates a cross-sectional view of a display panel.

As shown in FIG. 1, the OLED display includes an image processor 110, a timing controller 120, a data driver 130, a scan driver 140, and a display panel 150.

The image processor 110 outputs a data enable signal DE and the like together with the data signal DATA supplied from the outside. The image processor 110 may output one or more of a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of description.

The timing controller 120 receives a data signal DATA from the image processor 110 along with a drive signal including a data enable signal DE or a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and the like. The timing controller 120 may include a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130 based on the driving signal. Outputs

The data driver 130 samples, latches, and converts the data signal DATA supplied from the timing controller 120 to a gamma reference voltage in response to the data timing control signal DDC supplied from the timing controller 120. . The data driver 130 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an integrated circuit (IC).

The scan driver 140 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 140 outputs a scan signal through the gate lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or a gate in panel (Gate In Panel) method in the display panel 150.

The display panel 150 displays an image corresponding to the data signal DATA and the scan signal supplied from the data driver 130 and the scan driver 140. The display panel 150 includes subpixels SP that operate to display an image.

The subpixels SP include red subpixels, green subpixels, and blue subpixels or include white subpixels, red subpixels, green subpixels, and blue subpixels. The subpixels SP may have one or more different emission areas according to emission characteristics.

As illustrated in FIG. 2, one subpixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED.

The switching transistor SW performs a switching operation such that a data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst in response to a scan signal supplied through the first gate line GL1. The driving transistor DR operates so that a driving current flows between the power supply line EVDD (high potential voltage) and the cathode power supply line EVSS (low potential voltage) according to the data voltage stored in the capacitor Cst. The organic light emitting diode OLED operates to emit light according to the driving current formed by the driving transistor DR.

The compensation circuit CC is a circuit added in the subpixel to compensate for the threshold voltage of the driving transistor DR. The compensation circuit CC is composed of one or more transistors. The configuration of the compensation circuit CC is very diverse according to an external compensation method.

As illustrated in FIG. 3, the compensation circuit CC includes a sensing transistor ST and a sensing line VREF (or a reference line). The sensing transistor ST is connected between a source electrode of the driving transistor DR and an anode electrode of the organic light emitting diode OLED (hereinafter referred to as sensing node). The sensing transistor ST supplies an initialization voltage (or a sensing voltage) transferred through the sensing line VREF to the sensing node of the driving transistor DR or the voltage of the sensing node or the sensing line VREF of the driving transistor DR. Or it operates to sense current.

In the switching transistor SW, a first electrode is connected to the first data line DL1 and a second electrode is connected to the gate electrode of the driving transistor DR. In the driving transistor DR, a first electrode is connected to the power line EVDD, and a second electrode is connected to the anode electrode of the organic light emitting diode OLED. The capacitor Cst has a first electrode connected to the gate electrode of the driving transistor DR and a second electrode connected to the anode electrode of the organic light emitting diode OLED. In the organic light emitting diode OLED, an anode electrode is connected to the second electrode of the driving transistor DR, and a cathode electrode is connected to the second power line EVSS. In the sensing transistor ST, a first electrode is connected to the sensing line VREF, and a second electrode is connected to an anode electrode of the organic light emitting diode OLED, which is a sensing node, and a second electrode of the driving transistor DR.

The operating time of the sensing transistor ST may be similar / same or different from the switching transistor SW according to an external compensation algorithm (or a configuration of a compensation circuit). For example, the switching transistor SW may have a gate electrode connected to the first gate line GL1, and the sensing transistor ST may have a gate electrode connected to the second gate line GL2. In this case, the scan signal Scan is transmitted to the first gate line GL1 and the sensing signal Sense is transmitted to the second gate line GL2. As another example, the first gate line GL1 connected to the gate electrode of the switching transistor SW and the second gate line GL2 connected to the gate electrode of the sensing transistor ST may be connected in common.

The sensing line VREF may be connected to the data driver. In this case, the data driver may sense the sensing node of the subpixel during the real time, the non-display period of the image, or the N frame (N is an integer of 1 or more) and generate the sensing result. The switching transistor SW and the sensing transistor ST may be turned on at the same time. In this case, the sensing operation through the sensing line VREF and the data output operation for outputting the data signal are separated (divided) based on the time division method of the data driver.

In addition, the compensation target according to the sensing result may be a digital data signal, an analog data signal, or a gamma. The compensation circuit for generating a compensation signal (or compensation voltage) based on the sensing result may be implemented in the data driver, the timing controller, or a separate circuit.

The light blocking layer LS may be disposed only under the channel region of the driving transistor DR or under the channel region of the switching transistor SW and the sensing transistor ST as well as under the channel region of the driving transistor DR. The light blocking layer LS may be simply used to block external light, or the light blocking layer LS may be connected to another electrode or line and used as an electrode constituting a capacitor. Therefore, the light blocking layer LS is selected as a metal layer of a multilayer layer (multilayer of dissimilar metals) so as to have light shielding characteristics.

In addition, in FIG. 3, a subpixel having a 3T (Capacitor) structure including a switching transistor SW, a driving transistor DR, a capacitor Cst, an organic light emitting diode OLED, and a sensing transistor ST is illustrated. Although described as an example, when the compensation circuit (CC) is added, it may be composed of 3T2C, 4T2C, 5T1C, 6T2C and the like. Hereinafter, for convenience of description, it will be described based on the example shown in FIG. 3.

As illustrated in FIG. 4, subpixels are formed on the display area AA of the substrate (or thin film transistor substrate) SUB1 based on the circuit described in FIG. 3. The subpixels formed on the display area AA are sealed by the protective film (or protective substrate) SUB2. Other non-described NA means non-display area. The substrate SUB1 may be selected from glass or a material having ductility.

The subpixels are arranged horizontally or vertically in the order of red (R), white (W), blue (B), and green (G) on the display area AA. In the subpixels, red (R), white (W), blue (B), and green (G) become one pixel (P). However, the arrangement order of the subpixels may be variously changed according to the light emitting material, the light emitting area, and the configuration (or structure) of the compensation circuit. In addition, the subpixels may be one pixel P such as red (R), blue (B), and green (G).

5 is a diagram schematically illustrating a planar layout of subpixels according to a comparative example. 6A is an enlarged plan view of the first region of FIG. 5. FIG. 6B is an enlarged plan view of the second region of FIG. 5. 6C is an enlarged plan view of the third region of FIG. 5. FIG. 7 is a cross-sectional view taken along line II ′ of FIG. 5. FIG. 8 is a cross-sectional view of FIGS. 6A to 6C taken along II-II ', III-III' and IV-IV ', respectively.

3 and 5, the first subpixel SPn1 to the fourth subpixel SPn4 having the emission area EMA and the circuit area DRA are disposed on the display area AA of the substrate SUB1. Is formed. An organic light emitting diode (light emitting device) is formed in the light emitting region EMA, and a circuit including switching, sensing and driving transistors for driving the organic light emitting diode is formed in the circuit region DRA. The first subpixel SPn1 to the fourth subpixel SPn4 allow the organic light emitting diode positioned in the light emitting region EMA to emit light in response to an operation of a switching and driving transistor in the circuit region DRA. do. “WA” positioned between the first subpixel SPn1 and the fourth subpixel SPn4 is a line region, and includes a power line EVDD, a sensing line VREF, and first to fourth data lines DL1 ˜. Vertical lines such as DL4) are arranged. The vertical lines may refer to lines extending across neighboring subpixels in a first direction (eg, X-axis direction). Horizontal lines such as the first and second gate lines GL1 and GL2 are intersected with the first subpixel SPn1 to the fourth subpixel SPn4. The horizontal line may refer to lines extending in a second direction (eg, Y-axis direction) that intersects with the first direction.

Lines such as the power supply line EVDD, the sensing line VREF, and the first to fourth data lines DL1 to DL4 as well as the electrodes constituting the thin film transistors may be disposed on different layers, as necessary. It may be electrically connected through a contact hole (via hole) passing through the insulating layer disposed therebetween. The sensing line VREF may be connected to each sensing transistor of the first to fourth subpixels SPn1 to SPn4 through a sensing connection line (or a sensing jumping line) VREFC. The power line EVDD may be connected to each driving transistor of the first to fourth subpixels SPn1 to SPn4 through a power connection line (or a power jumping line) EVDDC. The first and second gate lines GL1 and GL2 are connected to respective sensing and switching transistors of the first to fourth subpixels SPn1 to SPn4. The first to fourth data lines DL1 to DL4 may be connected to the switching transistors of the corresponding subpixels SPn1, SPn2, SPn3, and SPn4.

6 to 8, the display device according to the present invention includes transistors and a substrate SUB1 on which an organic light emitting diode driven by the transistors is formed. The transistors may include a switching transistor SW, a driving transistor DR, and a sensing transistor ST.

The light blocking layer LS may be disposed on the substrate SUB1. The light blocking layer LS may be disposed under the transistor to overlap at least the channel region. In the drawing, the case where the light blocking layer LS is disposed only under the driving transistor DR is illustrated as an example, but is not limited thereto. The power connection line EVDDC and the sensing connection line VREFC are formed on the same layer as the light blocking layer LS and made of the same material LM.

The buffer layer BUF is formed on the light blocking layer LS. The buffer layer BUF may block ions or impurities diffused from the first substrate SUB1 and may block external moisture penetration.

The switching transistor SW, the driving transistor DR, and the sensing transistor ST are formed on the buffer layer BUF. The region in which the sensing transistor ST is formed may be defined as the first region AR1. The region in which the driving transistor DR is formed may be defined as the second region AR2. The region in which the switching transistor SW is formed may be defined as a third region AR3.

The switching transistor SW includes a switching semiconductor layer SWSE, a switching gate electrode SWG, a switching source electrode SWS, and a switching drain electrode SWD.

The switching semiconductor layer SWSE is disposed on the buffer layer BUF. The switching semiconductor layer SWSE may be divided into a channel region, a source region provided at one side of the channel region, and a drain region provided at the other side of the channel region.

The switching gate electrode SWG is disposed on the channel region of the switching semiconductor layer SWSE with the gate insulating layer GI interposed therebetween. The switching gate electrode SWG may be part of the first gate line GL1 and the first gate line GL1, or may be a branch branched from the first gate line GL1. That is, the switching gate electrode SWG and the first gate line GL1 are formed of the same material GM in the same layer.

The intermediate insulating layer ILD is disposed on the switching gate electrode SWG. The gate insulating layer GI and the intermediate insulating layer ILD may be formed of a silicon oxide film SiOx or a silicon nitride film SiNx, but are not limited thereto.

The switching source electrode SWS and the switching drain electrode SWD are disposed on the intermediate insulating layer ILD and spaced apart from each other. The switching source electrode SWS is connected to the source region of the switching semiconductor layer SWSE through the switching source contact hole SWSH passing through the intermediate insulating layer ILD. The switching drain electrode SWD is connected to the drain region of the switching semiconductor layer SWSE through the switching drain contact hole SWDH passing through the intermediate insulating layer ILD.

The data line DL may be formed of the same material SM on the same layer as the source electrode and the drain electrode of the transistors. The switching drain electrode SWD may be part of the data line DL or may be a part branched from the data line DL.

The driving transistor DR includes a driving semiconductor layer DRSE, a driving gate electrode DRG, a driving source electrode DRS, and a driving drain electrode DRD.

The driving semiconductor layer DRSE is disposed on the buffer layer BUF. The driving semiconductor layer DRSE may be divided into a channel region, a source region provided at one side of the channel region, and a drain region provided at the other side of the channel region.

The driving gate electrode DRG is disposed on the channel region of the driving semiconductor layer DRSE with the gate insulating layer GI interposed therebetween. The driving gate electrode DRG is electrically connected to the switching source electrode SWS of the switching transistor SW to receive a signal. The intermediate insulating layer ILD is disposed on the driving gate electrode DRG.

The driving source electrode DRS and the driving drain electrode DRD are spaced apart from each other on the intermediate insulating layer ILD. The driving source electrode DRS is connected to the source region of the driving semiconductor layer DRSE through the driving source contact hole DRSH passing through the intermediate insulating layer ILD. The driving drain electrode DRD is connected to the drain region of the driving semiconductor layer DRSE through the driving drain contact hole DRDH that penetrates the intermediate insulating layer ILD. The driving source electrode DRS may be connected to the light blocking layer LS through a contact hole LH passing through the intermediate insulating layer ILD and the buffer layer BUF.

The power line EVDD may be formed of the same material SM on the same layer as the source electrode and the drain electrode of the transistors. The driving drain electrode DRD is electrically connected to the power line EVDD. The driving drain electrode DRD may be connected to the power line EVDD through the power connection line EVDDC. One end and the other end of the power connection line EVDDC are connected to the driving drain electrode DRD and the power line through contact holes (C1 and C2 of FIG. 5) passing through the buffer layer BUF and the intermediate insulating layer ILD. EVDD), respectively.

The sensing transistor ST includes a sensing semiconductor layer STSE, a sensing gate electrode STG, a sensing source electrode STS, and a sensing drain electrode STD.

The sensing semiconductor layer STSE is disposed on the buffer layer BUF. The sensing semiconductor layer STSE may be divided into a channel region, a source region provided at one side of the channel region, and a drain region provided at the other side of the channel region.

The sensing gate electrode STG is disposed on the channel region of the sensing semiconductor layer STSE with the gate insulating layer GI interposed therebetween. The sensing gate electrode STG may be a portion of the second gate line GL2 or a portion branched from the second gate line GL2. That is, the sensing gate electrode STG and the second gate line GL2 are formed of the same material GM in the same layer. The intermediate insulating layer ILD is disposed on the sensing gate electrode STG.

The sensing source electrode STS and the sensing drain electrode STD are spaced apart from each other on the intermediate insulating layer ILD. The sensing source electrode STS is connected to the source region of the sensing semiconductor layer STSE through the sensing source contact hole STSH passing through the intermediate insulating layer ILD. The sensing drain electrode STD is connected to the drain region of the sensing semiconductor layer STSE through the sensing drain contact hole STDH that penetrates the intermediate insulating layer ILD.

The sensing line VREF may be formed of the same material SM on the same layer as the source and drain electrodes of the transistors. The sensing drain electrode STD is electrically connected to the sensing line VREF. The sensing drain electrode STD may be connected to the sensing line VREF through the sensing connection line VREFC. One end and the other end of the sensing connection line VREFC are connected to the sensing drain electrode STD and the sensing line through contact holes (C3 and C4 of FIG. 5) passing through the buffer layer BUF and the intermediate insulating layer ILD. VREF), respectively.

The protective layer PAS is disposed on the substrate on which the switching transistor SW, the driving transistor DR, and the sensing transistor ST are formed. The protective layer PAS is an insulating layer protecting the lower device, and may be a silicon oxide film SiOx, a silicon nitride film SiNx, or a multilayer thereof. The overcoat layer OC is disposed on the protective layer PAS. The overcoat layer OC may be a planarization film for alleviating the step of the lower structure, and may be made of organic material such as polyimide, benzocyclobutene series resin, and acrylate. If necessary, one of the passivation film PAS and the planarization film OC may be omitted.

An organic light emitting diode is disposed on the overcoat layer OC. The organic light emitting diode includes a first electrode E1, an organic compound layer OL, and a second electrode E2 facing each other.

The first electrode E1 may be an anode. The first electrode E1 is connected to the driving source electrode DRS of the driving transistor DR through the pixel contact hole PH passing through the overcoat layer and the protective layer PAS. The first electrode E1 may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO) in response to the adopted light emission method, and may function as a transmission electrode. It may include a reflective layer to function as a reflective electrode. The reflective layer may be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), or an alloy thereof, preferably made of APC (silver / palladium / copper alloy).

The bank layer BN is disposed on the substrate SUB1 on which the first electrode E1 is formed. The bank layer BN may be formed of an organic material, such as polyimide, benzocyclobutene series resin, and acrylate.

The bank layer BN includes an opening that exposes most of the first electrode E1. The bank layer BN may be disposed to expose the central portion of the first electrode E1 and to cover the side end of the first electrode E1. A central portion of the first electrode E1 exposed by the opening of the bank layer BN may be defined as a light emitting area.

The organic compound layer OL is disposed on the substrate SUB1 on which the bank layer BN is formed. The organic compound layer (OL) is a layer in which electrons and holes combine to emit light. The organic compound layer (OL) includes an emission layer (EML), a hole injection layer (HIL), a hole transport layer (HTL), and an electron. It may further include any one or more of a transport layer (ETL) and an electron injection layer (EIL).

The second electrode E2 is disposed on the organic compound layer OL. The second electrode E2 may be formed on the entire surface of the substrate SUB1. The second electrode E2 can function as a transmissive electrode or a reflective electrode, corresponding to the adopted light emission method. When the second electrode E2 is a transmissive electrode, the second electrode E2 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the light may be transmitted therethrough. It may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag) or an alloy thereof having a thin thickness.

In order for such an organic light emitting display device to be easily applied to various electronic devices, the organic light emitting display device needs to be thinned. In the case of a thin organic light emitting display device, since spacing between lines is reduced, short defects may occur even though lines to which different signals are applied are arranged with at least one insulating layer interposed therebetween. .

For example, vertical lines such as the power line EVDD, sensing line VREF, and data lines DL, and horizontal lines such as the first and second gate lines GL1 and GL2 may be formed in a predetermined region. Cross each other. The intersection area may be referred to as the overlap area OA. Although the vertical line and the horizontal line are spaced apart from each other with an intermediate insulating layer ILD interposed therebetween, it is difficult to secure a sufficient thickness (or spaced interval) for thinning. That is, the intermediate insulating layer ILD may be set to a thickness of approximately 5000 to 5500 mV in order to maintain the overall thickness of the preset display device. However, the intermediate insulating layer ILD has a limit in preventing short defects. Therefore, when a short occurs between the vertical line and the horizontal line, a compensation structure capable of repairing the short is required.

The compensation structure may have a form in which at least one of the horizontal lines is divided into a plurality of branches in the overlap area OA. For example, as shown in FIG. 5, the first and second gate lines GL1 and GL2 respectively form the first branch line AL1 and the second branch line AL2 in the overlap region OA. Can have. In this case, even if the first branch line AL1 has a short line defect with the vertical line, a preset signal may be transmitted to neighboring pixels through the second branch line AL2. In this case, the first branch line AL1 may be cut through a cutting process, thereby preventing unwanted signal transmission.

However, in such a structure, since the repair area for forming the compensation structure needs to be separately allocated in the display area of the display device, the opening ratio is inevitable. Therefore, there is a problem in that a single pixel size is difficult to be applied to a relatively high resolution display device.

<Example>

9 is a diagram schematically illustrating a planar layout of subpixels according to an exemplary embodiment of the present invention. FIG. 10A is an enlarged plan view of the first region of FIG. 9. FIG. 10B is an enlarged plan view of the second region of FIG. 9. FIG. 10C is an enlarged plan view of the third region of FIG. 9. FIG. 11 is a cross-sectional view taken along line VV ′ of FIG. 9. FIG. 12 is a cross-sectional view of FIGS. 10A to 10C taken as VI-VI ', VIII-VIII, and VIX-VIII, respectively.

Referring to FIG. 3 along with FIG. 3, on the display area AA of the substrate SUB1, the first subpixel SPn1 to the fourth subpixel SPn4 having the emission area EMA and the circuit area DRA may be formed. Is formed. An organic light emitting diode (light emitting device) is formed in the light emitting region EMA, and a circuit including switching, sensing and driving transistors for driving the organic light emitting diode is formed in the circuit region DRA. The first subpixel SPn1 to the fourth subpixel SPn4 allow the organic light emitting diode positioned in the light emitting region EMA to emit light in response to an operation of a switching and driving transistor in the circuit region DRA. do. “WA” positioned between the first subpixel SPn1 and the fourth subpixel SPn4 is a line region, and includes a power line EVDD, a sensing line VREF, and first to fourth data lines DL1 ˜. Vertical lines such as DL4) are arranged. The vertical lines may refer to lines extending across neighboring subpixels in the first direction. Horizontal lines such as the first and second gate lines GL1 and GL2 are intersected with the first subpixel SPn1 to the fourth subpixel SPn4. The horizontal line may refer to lines extending in a second direction crossing the first direction.

Lines such as the power supply line EVDD, the sensing line VREF, and the first to fourth data lines DL1 to DL4 as well as the electrodes constituting the thin film transistors may be disposed on different layers, as necessary. It may be electrically connected through a contact hole (via hole) passing through the insulating layer disposed therebetween. The sensing line VREF may be connected to each sensing transistor of the first to fourth subpixels SPn1 to SPn4 through a sensing connection line (or a sensing jumping line) VREFC. The power line EVDD may be connected to each driving transistor of the first to fourth subpixels SPn1 to SPn4 through a power connection line (or a power jumping line) EVDDC. The first and second gate lines GL1 and GL2 are connected to respective sensing and switching transistors of the first to fourth subpixels SPn1 to SPn4. The first to fourth data lines DL1 to DL4 may be connected to the switching transistors of the corresponding subpixels SPn1, SPn2, SPn3, and SPn4.

10 to 12, a display device according to the present invention includes transistors and a substrate on which an organic light emitting diode driven by the transistors is formed. The transistors may include a switching transistor SW, a driving transistor DR, and a sensing transistor ST.

The light blocking layer LS may be disposed on the substrate SUB1. The light blocking layer LS may be disposed under the transistor to overlap at least the channel region. In the drawing, the case where the light blocking layer LS is disposed below the driving transistor DR is illustrated as an example, but is not limited thereto.

Unlike the comparative example, the vertical lines such as the power line EVDD, the sensing line VREF, and the first to fourth data lines DL1 to DL4 of the present invention are formed on the same layer as the light blocking layer LS. The vertical lines such as the power line EVDD, the sensing line VREF, and the data line DL of the present invention may be formed of the same material LM as the light blocking layer LS.

The buffer layer BUF is formed on the light blocking layer LS. The buffer layer BUF may block ions or impurities diffused from the first substrate SUB1 and may block external moisture penetration.

The switching transistor SW, the driving transistor DR, and the sensing transistor ST are formed on the buffer layer BUF. The region in which the sensing transistor ST is formed may be defined as the first region AR1. The region in which the driving transistor DR is formed may be defined as the second region AR2. The region in which the switching transistor SW is formed may be defined as a third region AR3.

The switching transistor SW includes a switching semiconductor layer SWSE, a switching gate electrode SWG, a switching source electrode SWS, and a switching drain electrode SWD.

The switching semiconductor layer SWSE is disposed on the buffer layer BUF. The switching semiconductor layer SWSE may be divided into a channel region, a source region provided at one side of the channel region, and a drain region provided at the other side of the channel region.

The gate insulating layer GI is disposed on the switching semiconductor layer SWSE. The gate insulating layer GI includes a switching source contact hole SWSH exposing a source region of the switching semiconductor layer SWSE, and a switching drain contact hole SWDH exposing a drain region of the switching semiconductor layer SWSE. do.

The switching gate electrode SWG, the switching source electrode SWS, and the switching drain electrode SWD are disposed to be spaced apart from each other on the gate insulating layer GI. The switching gate electrode SWG, the switching source electrode SWS, and the switching drain electrode SWD are formed on the same layer. The switching gate electrode SWG, the switching source electrode SWS, and the switching drain electrode SWD may be formed of the same material GM.

The switching gate electrode SWG is disposed on the channel region of the switching semiconductor layer SWSE with the gate insulating layer GI interposed therebetween. The switching gate electrode SWG may be part of the first gate line GL1 and the first gate line GL1, or may be a branch branched from the first gate line GL1.

One end of the switching source electrode SWS is connected to the source region of the switching semiconductor layer SWSE through the switching source contact hole SWSH passing through the gate insulating layer GI. One end of the switching drain electrode SWD is connected to the drain region of the switching semiconductor layer SWSE through the switching drain contact hole SWDH passing through the gate insulating layer GI.

The switching drain electrode SWD is electrically connected to the data line DL. The switching drain electrode SWD is connected to the data line DL through the jumping line JL. The jumping line JL may be a portion extending from the switching drain electrode SWD. One end of the jumping line JL may be connected to the data line DL through the data contact hole DH passing through the gate insulating layer GI and the buffer layer BUF.

The driving transistor DR includes a driving semiconductor layer DRSE, a driving gate electrode DRG, a driving source electrode DRS, and a driving drain electrode DRD.

The driving semiconductor layer DRSE is disposed on the buffer layer BUF. The driving semiconductor layer DRSE may be divided into a channel region, a source region provided at one side of the channel region, and a drain region provided at the other side of the channel region.

The gate insulating layer GI is disposed on the driving semiconductor layer DRSE. The gate insulating layer GI includes a driving source contact hole DRSH exposing a source region of the driving semiconductor layer DRSE, and a driving drain contact hole DRDH exposing a drain region of the driving semiconductor layer DRSE. do.

The driving gate electrode DRG, the driving source electrode DRS, and the driving drain electrode DRD are spaced apart from each other on the gate insulating layer GI. The driving gate electrode DRG, the driving source electrode DRS, and the driving drain electrode DRD are formed on the same layer. The driving gate electrode DRG, the driving source electrode DRS, the driving drain electrode DRD, the switching gate electrode SWG, the switching source electrode SWS, and the switching drain electrode SWD are formed of the same material GM. Can be.

The driving gate electrode DRG is disposed on the channel region of the driving semiconductor layer DRSE with the gate insulating layer GI interposed therebetween. The driving gate electrode DRG is electrically connected to the switching source electrode SWS of the switching transistor SW to receive a signal.

One end of the driving source electrode DRS is connected to the source region of the driving semiconductor layer DRSE through the driving source contact hole DRSH passing through the gate insulating layer GI. One end of the driving drain electrode DRD is connected to the drain region of the driving semiconductor layer DRSE through the driving drain contact hole DRDH penetrating through the gate insulating layer GI. The driving source electrode DRS may be connected to the light blocking layer LS through a contact hole LH passing through the gate insulating layer GI and the buffer layer BUF.

The driving drain electrode DRD is electrically connected to the power line EVDD. The driving drain electrode DRD is connected to the power line EVDD through the power connection line EVDDC. The power connection line EVDDC may be a portion extending from the driving drain electrode DRD. One end of the power connection line EVDDC may be connected to the power line EVDD through a power contact hole EH passing through the gate insulating layer GI and the buffer layer BUF.

The sensing transistor ST includes a sensing semiconductor layer STSE, a sensing gate electrode STG, a sensing source electrode STS, and a sensing drain electrode STD.

The sensing semiconductor layer STSE is disposed on the buffer layer BUF. The sensing semiconductor layer STSE may be divided into a channel region, a source region provided at one side of the channel region, and a drain region provided at the other side of the channel region.

The gate insulating layer GI is disposed on the sensing semiconductor layer STSE. The gate insulating layer GI includes a sensing source contact hole STSH exposing a source region of the sensing semiconductor layer STSE, and a sensing drain contact hole STDH exposing a drain region of the sensing semiconductor layer STSE. do.

The sensing gate electrode STG, the sensing source electrode STS, and the sensing drain electrode STD are disposed to be spaced apart from each other on the gate insulating layer GI. The sensing gate electrode STG, the sensing source electrode STS, and the sensing drain electrode STD are formed in the same layer. Sensing gate electrode STG, sensing source electrode STS, sensing drain electrode STD, driving gate electrode DRG, driving source electrode DRS, driving drain electrode DRD, switching gate electrode SWG, switching The source electrode SWS and the switching drain electrode SWD may be formed of the same material GM.

The sensing gate electrode STG is disposed on the channel region of the sensing semiconductor layer STSE with the gate insulating layer GI interposed therebetween. The sensing gate electrode STG may be a portion of the second gate line GL2 or a portion branched from the second gate line GL2.

One end of the sensing source electrode STS is connected to the source region of the sensing semiconductor layer STSE through the sensing source contact hole STSH passing through the gate insulating layer GI. One end of the sensing drain electrode STD is connected to the drain region of the sensing semiconductor layer STSE through the sensing drain contact hole STDH penetrating through the gate insulating layer GI.

The sensing drain electrode STD is electrically connected to the sensing line VREF. The sensing drain electrode STD is connected to the sensing line VREF through the sensing connection line VREFC. The sensing connection line VREFC may be a portion extending from the sensing drain electrode STD. One end of the sensing connection line VREFC may be connected to the sensing line VREF through a sensing contact hole (SH of FIG. 9) passing through the gate insulating layer GI and the buffer layer BUF.

The protective layer PAS is disposed on the substrate on which the switching transistor SW, the driving transistor DR, and the sensing transistor ST are formed. The protective layer PAS is an insulating layer protecting the lower device, and may be a silicon oxide film SiOx, a silicon nitride film SiNx, or a multilayer thereof. The overcoat layer OC is disposed on the protective layer PAS. The overcoat layer OC may be a planarization film for alleviating the step of the lower structure, and may be made of organic material such as polyimide, benzocyclobutene series resin, and acrylate. If necessary, one of the passivation film PAS and the planarization film OC may be omitted.

An organic light emitting diode is disposed on the overcoat layer OC. The organic light emitting diode includes a first electrode E1, an organic compound layer OL, and a second electrode E2 facing each other.

The first electrode E1 may be an anode. The first electrode E1 is connected to the driving source electrode DRS of the driving transistor DR through the pixel contact hole PH passing through the overcoat layer OC and the protective layer PAS. The first electrode E1 may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO) in response to the adopted light emission method, and may function as a transmission electrode. It may include a reflective layer to function as a reflective electrode. The reflective layer may be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), or an alloy thereof, preferably made of APC (silver / palladium / copper alloy).

The bank layer BN is disposed on the substrate SUB1 on which the first electrode E1 is formed. The bank layer BN may be formed of an organic material, such as polyimide, benzocyclobutene series resin, and acrylate.

The bank layer BN includes an opening that exposes most of the first electrode E1. The bank layer BN may be disposed to expose the central portion of the first electrode E1 and to cover the side end of the first electrode E1. A central portion of the first electrode E1 exposed by the opening of the bank layer BN may be defined as a light emitting area.

The organic compound layer OL is disposed on the substrate SUB1 on which the bank layer BN is formed. The organic compound layer (OL) is a layer in which electrons and holes combine to emit light. The organic compound layer (OL) includes an emission layer (EML), a hole injection layer (HIL), a hole transport layer (HTL), and an electron. It may further include any one or more of a transport layer (ETL) and an electron injection layer (EIL).

The second electrode E2 is disposed on the organic compound layer OL. The second electrode E2 may be formed on the entire surface of the substrate SUB1. The second electrode E2 can function as a transmissive electrode or a reflective electrode, corresponding to the adopted light emission method. When the second electrode E2 is a transmissive electrode, the second electrode E2 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the light may be transmitted therethrough. It may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag) or an alloy thereof having a thin thickness.

In the preferred embodiment of the present invention, in the overlap region OA, vertical lines such as the power line EVDD, the sensing line VREF, and the data lines DL, and the first and second gate lines GL1, The gate insulating layer GI and the buffer layer BUF are interposed between the GL2s. In the exemplary embodiment of the present invention, unlike the comparative example, since the intermediate insulating layer ILD (FIG. 6) has a structure in which the intermediate insulating layer ILD is removed, the buffer layer BUF can be sufficiently secured without increasing the overall thickness of the display device. have. That is, in the comparative example, the buffer layer BUF and the intermediate insulation layer ILD need to be set to have a thickness of about 3000-4500 μs in order to reduce the thickness while performing the original functions. In FIG. 6, as the intermediate insulating layer ILD is removed, the buffer layer BUF may have a thickness of 8000 to 10,000 μm without increasing the overall thickness of the display device. Therefore, since the preferred embodiment of the present invention can sufficiently secure the distance between the horizontal line and the vertical line, there is an advantage that a short defect between the horizontal line and the vertical line in the overlap area OA can be prevented.

Furthermore, since the display device according to the preferred embodiment of the present invention can significantly improve short defects, it is not necessary to provide a separate compensation structure for repairing as in the comparative example. Therefore, since the aperture ratio can be remarkably improved compared with the comparative example, there is an advantage that a single pixel size can be easily applied to a relatively high resolution display device.

Although not shown, the buffer layer BUF may be formed of two or more layers. For example, the buffer layer BUF may be provided as a plurality of layers in which a silicon oxide film SiOx and a silicon nitride film SiNx are alternately arranged. In a preferred embodiment of the present invention, unlike the prior art, it is necessary to form a buffer layer (BUF) to a thick thickness, there may be a process difficulty in forming a buffer layer (BUF) of a single film through one process. Therefore, the preferred embodiment of the present invention has the advantage of reducing process defects by forming the buffer layer BUF into a plurality of films through a plurality of processes so as to satisfy the thickness of the target buffer layer BUF.

In addition, as in the preferred embodiment of the present invention, when the buffer layer BUF is implemented as a plurality of films, the cleaning process may be performed for each film forming process, and thus foreign substances between the films may be prevented from remaining. Accordingly, short defects due to foreign matter in the overlap region OA can be improved.

It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

SUB1: Substrate BUF: Buffer Layer
SW: switching transistor DR: driving transistor
ST: sensing transistor GL1: first gate line
GL2: second gate line DL: data line
EVDD: Power Line EVDDC: Power Connection Line
VREF: Sensing Line VREFC: Sensing Connection Line

Claims (13)

Vertical lines disposed on the substrate and configured to receive predetermined signals, respectively;
A buffer layer disposed on the vertical lines; And
Transistors disposed on the buffer layer,
Each of the transistors,
A semiconductor layer disposed on the buffer layer and defining a channel region, a source region, and a drain region;
A gate insulating layer covering the semiconductor layer, the gate insulating layer having a source contact hole exposing at least a portion of the source region of the semiconductor layer and a drain contact hole exposing at least a portion of the drain region of the semiconductor layer;
A gate electrode disposed to overlap the channel region with the gate insulating layer interposed therebetween;
A source electrode disposed on the gate insulating layer and in contact with the source region of the semiconductor layer through the source contact hole; And
And a drain electrode disposed on the gate insulating layer and in contact with the drain region of the semiconductor layer through the drain contact hole and spaced apart from the source electrode by a predetermined distance.
The method of claim 1,
The gate electrode, the source electrode, and the drain electrode,
A display device disposed on the same layer and spaced apart from each other by a predetermined interval.
The method of claim 1,
And a jumping line connecting the vertical line and the transistor.
The jumping line is,
A display device on the gate insulating layer, the same layer as the gate electrode.
The method of claim 1,
Receiving a preset signal and including a horizontal line crossing the vertical line,
The horizontal line is,
And a gap between the buffer layer and the gate insulating layer.
The method of claim 1,
On the substrate, further comprising a light blocking layer disposed on the same layer as the vertical line,
The light blocking layer,
And at least a portion of the transistor.
The method of claim 5, wherein
The transistors,
And a driving transistor connected to the light blocking layer.
The method of claim 1,
An insulating layer covering the transistors; And
Further comprising an organic light emitting diode disposed on the insulating layer,
The transistors,
And a driving transistor connected to the organic light emitting diode.
The method of claim 1,
The vertical line is,
A power line, and a data line,
The transistors,
A switching transistor coupled to the data line; And
And a driving transistor connected to the power line.
The method of claim 8,
An insulating layer covering the transistors; And
Further comprising an organic light emitting diode disposed on the insulating layer,
A drain electrode of the switching transistor is connected to the data line,
A source electrode of the switching transistor is connected to a gate electrode of the driving transistor,
The drain electrode of the driving transistor is connected to the power line,
And a source electrode of the driving transistor is connected to the first electrode of the organic light emitting diode.
The method of claim 9,
The vertical line is,
Including sensing line,
The transistors,
And a sensing transistor connected to the sensing line.
The method of claim 10,
The sensing transistor,
And a display device connected between the source electrode of the driving transistor and the first electrode of the organic light emitting diode.
The method of claim 1,
The thickness of the buffer layer,
Display set in the range of 8000 to 10000 Hz.
The method of claim 12,
The buffer layer,
A display device comprising a plurality of layers in which a silicon oxide film (SiOx) is alternately arranged with a silicon nitride film (SiNx).

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