KR20200008393A - Method for manufacturing of P type and N type coexisting wafers, P type and N type coexisting wafers manufactured by the method, method for manufacturing solar cell using P type and N type coexisting wafers and solar cell manufactured by the method - Google Patents

Abstract

One embodiment of the present invention provides a method for manufacturing a P-type and N-type coexistence wafer, a P-type and N-type coexistence wafer manufactured thereby, a method for manufacturing a photovoltaic cell using the P-type and N-type coexistence wafer, and a photovoltaic cell manufactured by the method for manufacturing photovoltaic cell. An impurity doping concentration gradient is formed in a horizontal direction of a substrate on a P-type doping area and N-type doping area in the P-type and N-type coexistence wafer manufactured according to one embodiment of the present invention. By adjusting a doping material in a wafer, a saturation current value may be reduced.

Description

Method for manufacturing P-type and N-type coexisting wafer, solar cell manufacturing method using P-type and N-type coexisting wafer, P-type and N-type coexisting wafer manufactured thereby, and solar cell manufactured thereby N type coexisting wafers, P type and N type coexisting wafers manufactured by the method, method for manufacturing solar cell using P type and N type coexisting wafers and solar cell manufactured by the method}

The present invention relates to a P-type and N-type coexistence wafer manufacturing method, and more particularly, to a P-type and N-type coexistence wafer manufacturing method, P and N-type coexisting wafer, P-type and N-type coexisting wafer produced thereby It relates to a solar cell manufacturing method and a solar cell produced thereby.

Solar cells are a technology that converts the sun's light energy into electrical energy. A solar cell is a key element of photovoltaic power generation that directly converts sunlight into electricity, and is basically a diode composed of a p-n junction.

In the process of converting sunlight into electricity by solar cells, when solar light is incident on the semiconductor layer of the solar cell, electron-hole pairs are generated, and electrons move to n layers and holes move to p layers by the electric field. Photovoltaic power is generated between the pn junctions, and when a load or a system is connected to both ends of the solar cell, current flows to generate power.

Generally, a solar cell can be classified into a silicon solar cell and a thin film solar cell. A silicon solar cell is a solar cell manufactured by using a semiconductor material such as silicon as a substrate, and a thin film solar cell is formed on a substrate such as glass by CIGS. It is prepared by forming the compound in the form of a thin film.

On the other hand, Equation 1 is a formula for the current-voltage characteristics of the solar cell device.

[Equation 1]

I = I ₀ (e ^{qV / kT} -1) -I _L

Where I ₀ is the saturation current value, I _L is the load current value, q is the charge of the electron, V is the voltage across the diode, k is the Boltzmann constant, and T is the absolute temperature at the diode junction.

Referring to Equation 1, the value of I ₀ (e ^{qV / kT} −1) in the solar cell diode equation for the current value of the solar cell element is called a diode current, and reducing this value is important for obtaining a high current. It works. In particular, it is important to reduce the value of I ₀ (saturation current).

Therefore, there is a need for a technique for reducing the value of I ₀ (saturation current).

Republic of Korea Patent Publication No. 10-2017-0108107

The technical problem to be achieved by the present invention is to provide a P-type and N-type coexisting wafer manufacturing method that can reduce the saturation current value by adjusting the doping material in the wafer and to provide a P-type and N-type coexisting wafer manufactured by the manufacturing method will be.

In addition, the technical problem to be achieved by the present invention is to provide a solar cell manufacturing method using the above-described P-type and N-type coexisting wafer and a solar cell manufactured by the manufacturing method.

The technical problem to be achieved by the present invention is not limited to the technical problem mentioned above, and other technical problems not mentioned above may be clearly understood by those skilled in the art from the following description. There will be.

In order to achieve the above technical problem, an embodiment of the present invention provides a P-type and N-type coexistence wafer manufacturing method.

P-type and N-type coexistence wafer manufacturing method according to an embodiment of the present invention by applying a P-type doped silicon particles and N-type doped silicon particles in the horizontal direction of the substrate alternately on the P-type particle region and Forming a pattern in which N-type particle regions are alternately formed, and passing the substrate on which the pattern is formed to a heating unit to melt and cool the P-type doped silicon particles and N-type doped silicon particles, thereby cooling the P-type particle region. And forming an N-type particle region into a P-type doped region and an N-type doped region, wherein the P-type and N-type doped regions have an impurity doping concentration gradient formed in a horizontal direction of the substrate. .

In addition, the substrate is characterized in that the substrate having a temperature resistance.

In addition, the substrate is characterized in that the SiC, SiN _x or SiO _x coated glass.

Further, in the forming of the P-type particle region and the N-type particle region into a P-type doped region and an N-type doped region, the P-type doped silicon particles and the N-type doped silicon particles are melted and cooled, and a doping material is cooled. The degree of impurity doping of the P-type doped region and the N-type doped region varies in the horizontal direction of the substrate according to the segregation coefficient of.

In order to achieve the above technical problem, another embodiment of the present invention provides a P-type and N-type coexistence wafer.

P-type and N-type coexisting wafers according to an embodiment of the present invention includes a substrate, a P-type doping region and an N-type doping region alternately positioned in the horizontal direction of the substrate on the substrate, P-type doping region and N The type doped region is characterized in that an impurity doping concentration gradient having a different impurity doping degree is formed in the horizontal direction of the substrate.

In addition, the substrate is characterized in that the substrate having a temperature resistance.

In addition, the substrate is characterized in that the SiC, SiN _x or SiO _x coated glass.

The P-type doped region may be a P-type doped silicon region, and the N-type doped region may be an N-type doped silicon region.

In order to achieve the above technical problem, another embodiment of the present invention provides a solar cell manufacturing method.

A solar cell manufacturing method according to an embodiment of the present invention comprises the steps of preparing a P-type and N-type coexistence wafers prepared by the above-described P-type and N-type coexistence wafer manufacturing method, the substrate in the P-type and N-type coexistence wafer And removing the P-type doped region and the N-type doped region as an active layer, forming an emitter layer on the active layer, and forming a backside field layer under the active layer.

The method may further include forming a first electrode on the emitter layer between the forming of the emitter layer and the forming of the backside field layer.

The method may further include forming a second electrode under the back surface layer after forming the back surface layer under the active layer.

In addition, the back surface field layer is a P-type semiconductor layer, the emitter layer is characterized in that the N-type semiconductor layer.

In order to achieve the above technical problem, another embodiment of the present invention provides a solar cell.

According to an exemplary embodiment of the present invention, a solar cell includes an active layer including an P-type doped region and an N-type doped region that are alternately positioned in a horizontal direction, an emitter layer positioned on the active layer, a rear field layer disposed below the active layer, A first electrode on the emitter layer and a second electrode on the bottom of the backside field layer, wherein the P-type doping region and the N-type doping region have an impurity doping concentration gradient formed in the horizontal direction of the active layer. It features.

The p-type doped region is a p-type doped silicon region, and the n-type doped region is an n-type doped silicon region.

The back surface field layer is a P-type semiconductor layer, the emitter layer is characterized in that the N-type semiconductor layer.

According to an embodiment of the present invention, it is possible to provide a P-type and N-type coexistence wafer manufacturing method.

Therefore, in the P-type and N-type coexisting wafers manufactured according to the embodiment of the present invention, an impurity doping concentration gradient may be formed in the horizontal direction of the substrate. As a result, the diffusion current is changed into a drift current, thereby reducing the saturation current value I ₀ .

Therefore, a solar cell having a high current can be provided by manufacturing a solar cell using such P-type and N-type coexisting wafers.

The effects of the present invention are not limited to the above-described effects, but should be understood to include all the effects deduced from the configuration of the invention described in the detailed description or claims of the present invention.

1 is a flow chart showing a P-type and N-type coexistence wafer manufacturing method according to an embodiment of the present invention.
2 and 3 are cross-sectional views showing a P-type and N-type coexistence wafer manufacturing method according to an embodiment of the present invention.
4 is a conceptual diagram illustrating a P-type and N-type coexisting wafer manufacturing method according to an embodiment of the present invention.
5 is a cross-sectional view illustrating a solar cell using a P-type and an N-type coexisting wafer according to an embodiment of the present invention.
6 is a cross-sectional view illustrating a current flow of a solar cell using a P-type and an N-type coexisting wafer according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is said to be "connected (connected, contacted, coupled) with another part, it is not only" directly connected "but also" indirectly connected "with another member in between. "Includes the case. In addition, when a part is said to "include" a certain component, it means that it may further include other components, without excluding the other components unless otherwise stated.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

It describes a P-type and N-type coexistence wafer manufacturing method according to an embodiment of the present invention.

1 is a flow chart showing a P-type and N-type coexistence wafer manufacturing method according to an embodiment of the present invention.

Referring to FIG. 1, in the P-type and N-type coexistence wafer manufacturing method according to an embodiment of the present invention, forming a pattern in which P-type particle regions and N-type particle regions are alternately formed on a substrate (S110) and the The method may include forming the P-type particle region and the N-type particle region into the P-type doped region and the N-type doped region by passing the substrate on which the pattern is formed through the heating unit (S120).

2 and 3 are cross-sectional views showing a P-type and N-type coexistence wafer manufacturing method according to an embodiment of the present invention. 2 and 3 will be described a P-type and N-type coexistence wafer manufacturing method according to an embodiment of the present invention.

Referring to FIG. 2, first, a P-type particle region 210 and an N-type particle region 220 are alternately formed on a substrate 100 (S110).

For example, P-type doped silicon particles 10 and N-type doped silicon particles 20 are alternately coated on the substrate 100 in the horizontal direction of the substrate 100 to form a P-type particle region 210. ) And the N-type particle region 220 may be formed to alternately form a pattern.

At this time, the P-type doped silicon particles 10 and the N-type doped silicon particles 20 may be applied alternately at least once.

At this time, the substrate 100 is characterized in that the substrate 100 having a temperature resistance. This is because the substrate 100 should not melt in the process of heating and melting the silicon particles. For example, at this time, the substrate 100 is preferably a substrate 100 having a temperature resistance that can withstand without melting at a temperature of 800 ℃ to 1400 ℃.

For example, the substrate 100 having temperature resistance may be SiC, SiN _x or SiO _x coated glass.

In this case, the P-type doped silicon particles 10 are silicon particles doped with P-type impurities. Therefore, the P-type impurity at this time may be a pentavalent material. As a specific example, the P-type impurities at this time may include B, Al, Ga or In.

For example, the P-type doped silicon particles 10 are precipitated by EG-Si (Electronic Grade-Silicon) and then pulverized using a known method such as ball milling method to form silicon particles, and then P It can be prepared by doping with a type impurity.

In this case, the N-type doped silicon particles 20 are silicon particles doped with N-type impurities. Therefore, the N-type impurities at this time may be a trivalent material. As a specific example, the N-type impurities at this time may include P, As or Sb.

For example, the N-type doped silicon particles 20 are formed by depositing EG-Si (Electronic Grade-Silicon) and pulverizing the same using a known method such as ball milling to form silicon particles. It can be prepared by doping with a type impurity.

In addition, the screen printing method may be performed by alternately applying the P-type doped silicon particles 10 and the N-type doped silicon particles 20 on the substrate 100 in the horizontal direction of the substrate 100. It may be formed by printing, spraying or spin coating.

Next, referring to FIG. 3, the P-type particle region 210 and the N-type particle region 220 are passed through the P-type doped region 310 and N by passing the substrate 100 on which the pattern is formed through a heating unit. It is formed as a type doping region 320 (S120).

At this time, the heat source (heat source) preferably has a temperature capable of melting the P-type doped silicon particles 10 and the N-type doped silicon particles 20.

Typical silicon melting point is about 1400 ° C. As the silicon is in the form of particles, the smaller the particle size, the lower the melting point may be lower than 1400 ℃. In other words, when the silicon particles become nanoparticles, the melting point may be lowered.

Thus, for example, the temperature of the heating unit may be set to 800 ° C to 1400 ° C.

For example, the P-type doped silicon particles 10 and the N-type doped silicon particles 20 are melted and cooled by passing the substrate 100 on which the pattern is formed through a heating unit, and cooling the P-type particle region. The 210 and N-type particle regions 220 may be formed as the P-type doped region 310 and the N-type doped region 320.

Meanwhile, as another embodiment, the P-type doped region 310 and the N-type doped region 320 may be formed by moving the heating unit from one side of the substrate 100 to the other side on the substrate 100.

Accordingly, the P-type doped region 310 may be a P-type doped silicon region, and the N-type doped region 320 may be an N-type doped silicon region.

Therefore, at this time, the P-type doping region 310 and the N-type doping region 320 is characterized in that the impurity doping concentration gradient is formed in the horizontal direction of the substrate 100. Therefore, a gradient wafer having a P-type and an N-type doped region coexist and having an impurity doping concentration gradient can be manufactured.

This is because the P-type doped silicon particles 10 and the N-type doped silicon particles 20 are melted and cooled in the horizontal direction of the substrate 100 according to a segregation coefficient of the doping material. The degree of impurity doping of the P-type doped region 310 and the N-type doped region 320 may vary.

Segregation refers to a phenomenon in which component elements, impurities, etc. are locally concentrated or diluted in metals and alloys.

Therefore, in the process of melting the P-type doped silicon particles 10 and the N-type doped silicon particles 20 through the heating part and cooling again, the P-type doped material according to the segregation coefficient (segregation coefficient) In the doped region 310, the doping concentration of the region that passes through the heating unit first and is cooled first is low, and the doping concentration of the region that passes through the heating unit later and is cooled later becomes high.

Similarly, in the N-type doped region 320, the doping concentration of the region to be cooled first through the heating unit is low, and the doping concentration of the region to be cooled later through the heating unit is high.

For example, the P-type doped region 310 and the N-type doped region 320 may be formed in each of the concentration gradient to increase the impurity doping concentration in one direction.

Accordingly, the degree of impurity doping of each of the P-type doped region 310 and the N-type doped region 320 in the horizontal direction of the substrate 100 is changed, so that the diffusion current in the wafer is changed to the drift current. Can be changed to

That is, the diffusion current in the wafer is changed into a drift current by inducing the concentration carrier of the doping material in the wafer to flow in one direction.

The diffusion current corresponds to a diode current, and when the diffusion current is changed to a drift current, the value of the saturation current I ₀ is reduced. Therefore, through this, it is possible to provide a solar cell device having high current characteristics.

4 is a conceptual diagram illustrating a P-type and N-type coexisting wafer manufacturing method according to an embodiment of the present invention.

Referring to FIG. 4, the P-type doped region 210 and the N-type are formed by alternately applying P-type doped silicon spherical particles and N-type doped silicon spherical particles onto a substrate 100 having a specific temperature resistance. The doped regions 220 form alternate patterns.

When the patterned substrate 100 is passed through a heat source, the P-type doped silicon particles and the N-type doped silicon particles are melted and cooled, and the P-type particle region 210 and the N-type particle region are cooled. 220 may be formed as a P-type doped region 310 and an N-type doped region 320. In this case, the degree of impurity doping of the P-type doped region 310 and the N-type doped region 320 in the horizontal direction of the substrate 100 varies according to a segregation coefficient of the doping material. A gradient wafer in which a doping concentration gradient is formed may be manufactured.

P-type and N-type coexisting wafers according to an embodiment of the present invention will be described.

P-type and N-type coexistence wafer according to an embodiment of the present invention may be a wafer manufactured by the above-described P-type and N-type coexistence wafer manufacturing method of the present invention. Therefore, it demonstrates with reference to FIG.

P-type and N-type coexistence wafers according to an embodiment of the present invention is a substrate 100, the P-type doped region 310 and the N-type alternately positioned in the horizontal direction of the substrate 100 on the substrate 100 And a doping region 320, wherein the P-type doping region 310 and the N-type doping region 320 are formed with an impurity doping concentration gradient having a different degree of impurity doping in the horizontal direction of the substrate.

At this time, the substrate 100 is characterized in that the substrate having a temperature resistance. This is because the substrate should not melt during the melting and heating of the silicon particles. For example, at this time, the substrate 100 is preferably a substrate having a temperature resistance that can withstand without melting at a temperature of 800 ℃ to 1400 ℃.

For example, the substrate 100 having temperature resistance may be SiC, SiN _x or SiO _x coated glass.

In this case, the P-type doped region 310 may be a P-type doped silicon region, and the N-type doped region 320 may be an N-type doped silicon region.

Therefore, when the P-type doped region 310 is a P-type doped silicon region, the P-type impurity may include B, Al, Ga, or In.

In addition, when the N-type doped region 320 is an N-type doped silicon region, the N-type impurities at this time may include P, As, or Sb.

In this case, the P-type doped region 310 and the N-type doped region 320 may be alternately positioned at least once in the horizontal direction of the substrate.

In FIG. 3, an example in which the P-type doped region 310 and the N-type doped region 320 are alternately positioned two times is not limited thereto.

In this case, the P type doped region 310 is a P type doped silicon region, and the N type doped region 320 is an N type doped silicon region.

In order to achieve the above technical problem, another embodiment of the present invention provides a solar cell manufacturing method.

A solar cell manufacturing method according to an embodiment of the present invention comprises the steps of preparing a P-type and N-type coexistence wafers prepared by the above-described P-type and N-type coexistence wafer manufacturing method, the substrate in the P-type and N-type coexistence wafer And removing the P-type doped region and the N-type doped region as an active layer, forming an emitter layer on the active layer, and forming a backside field layer under the active layer.

First, P-type and N-type coexisting wafers prepared by the above-described P-type and N-type coexisting wafer manufacturing method are prepared.

Next, the P-type doped region and the N-type doped region are prepared as an active layer by removing the substrate from the P-type and N-type coexisting wafers.

For example, at this time, the method of removing the substrate may be removed by performing a known method such as a wet etching method or a dry etching method.

An emitter layer can then be formed over this active layer. For example, the emitter layer may be an N-type semiconductor layer.

Such an emitter layer may be formed on the active layer by using a lamination-diffusion process method or an ion implantation method. Meanwhile, the present invention is not limited thereto, and the emitter layer may be formed by performing various known methods.

For example, after a doping source layer including N-type impurities is deposited on the active layer by using atmosphere pressure chemical vapor deposition (APCVD), plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD), The diffusion process may be performed to form an emitter layer, which is an N-type semiconductor layer. For example, the N-type impurities at this time may include P, As or Sb.

Subsequently, a backside field layer may be formed under the active layer. In this case, the backside field layer may be a P-type semiconductor layer.

The backside field layer may be formed under the active layer by using a lamination-diffusion process method or an ion implantation method. Meanwhile, the present invention is not limited thereto, and a backside field layer may be formed by performing various known methods.

For example, after a doping source layer including p-type impurities is deposited on the bottom of the active layer by using atmosphere pressure chemical vapor deposition (APCVD), plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD), A diffusion process may be performed to form a backside field layer, which is a p-type semiconductor layer. For example, the P-type impurity at this time may include B, Al, Ga or In.

The method may further include forming a first electrode on the emitter layer between the forming of the emitter layer and the forming of the backside field layer.

In some cases, a first electrode may be formed on the emitter layer after the step of forming the back field layer.

For example, the first electrode 600 may include any one selected from Al, Au, Cu, Pt, Ag, W, Ni, Zn, Ti, Zr, Hf, Cd, Pd, and alloys thereof. .

For example, the first electrode may be formed using sputtering, evaporation, metal organic chemical vapor deposition (MOCVD), or molecular beam epitaxy (MBE). Can be formed.

The method may further include forming a second electrode under the back surface layer after forming the back surface layer under the active layer.

For example, the second electrode 700 may include any one selected from Mo, Al, Au, Cu, Pt, Ag, W, Ni, Zn, Ti, Zr, Hf, Cd, Pd, and alloys thereof. Can be.

For example, the second electrode may be formed by sputtering, evaporation, metal organic chemical vapor deposition (MOCVD), or molecular beam epitaxy (MBE). Can be formed.

In order to achieve the above technical problem, another embodiment of the present invention provides a solar cell.

5 is a cross-sectional view showing a solar cell using a P-type and N-type coexistence wafer according to an embodiment of the present invention.

Referring to FIG. 5, a solar cell according to an exemplary embodiment of the present invention includes an active layer 300 and an active layer 300 including a P-type doped region 310 and an N-type doped region 320 that are alternately positioned in a horizontal direction. ) An emitter layer 400 disposed above, a back field layer 500 positioned below the active layer 300, a first electrode 600 located on the emitter layer 400, and the back field layer 500. The second electrode 700 is positioned below, and each of the P-type doped region 310 and the N-type doped region 320 has an impurity doping concentration gradient formed in the horizontal direction of the active layer.

The active layer 300 may include a P-type doped region 310 and an N-type doped region 320 that are alternately positioned in the horizontal direction. For example, the P-type doped region 310 may be a P-type doped silicon region, and the N-type doped region 320 may be an N-type doped silicon region.

In particular, the P-type doping region 310 and the N-type doping region 320 constituting the active layer 300 is characterized in that the impurity doping concentration gradient is formed in the horizontal direction of the active layer 300. Therefore, by forming such an impurity doping concentration gradient, the diffusion current in the active layer 300 is changed into a drift current, thereby reducing the saturation current value I ₀ . Therefore, it is possible to provide a solar cell having a high current.

In addition, in the active layer 300, adjacent P-type doped regions 310 and N-type doped regions 320 form a P-N junction. Due to the built-inpotential difference generated by the PN junction, the electron-hole pairs, which are charges generated by light incident on the active layer 300, are separated into electrons and holes, and the electrons are n-type doped region 320. ) And the holes will move towards the P-type doped region 310.

In addition, the emitter layer 400 may be located above the active layer 300. For example, the emitter layer 400 may be an N-type semiconductor layer.

Therefore, when the emitter layer 400 is an N-type semiconductor layer, the P-type doped region 310 of the emitter layer 400 and the active layer 300 forms a P-N junction.

In addition, the back surface field layer 500 may be located under the active layer 300. For example, the backside field layer 500 may be a P-type semiconductor layer.

Therefore, when the backside field layer 500 is a P-type semiconductor layer, the N-type doped region 320 of the backside field layer 500 and the active layer 300 forms a P-N junction.

In addition, the first electrode 600 may be located on the emitter layer 400.

The first electrode 600 may serve as a cathode for collecting electrons generated at the above-described P-N junction. The first electrode 600 may be made of a conductive material. The first electrode 600 may be made of metal or an alloy thereof.

For example, the first electrode 600 may include any one selected from Al, Au, Cu, Pt, Ag, W, Ni, Zn, Ti, Zr, Hf, Cd, Pd, and alloys thereof. .

In addition, the second electrode 700 may be located under the back field layer 500.

The second electrode 700 may serve as an anode for collecting holes generated at the above-described P-N junction. Therefore, the second electrode 700 may be made of a conductive material having a low resistance. The second electrode 700 may be made of a metal or an alloy thereof.

For example, the second electrode 700 may include any one selected from Mo, Al, Au, Cu, Pt, Ag, W, Ni, Zn, Ti, Zr, Hf, Cd, Pd, and alloys thereof. Can be.

6 is a cross-sectional view illustrating a current flow of a solar cell using a P-type and an N-type coexisting wafer according to an embodiment of the present invention.

Referring to FIG. 6, the P-type doped region 310 and the N-type doped region 320 in the active layer 300 form a P-N junction. Due to the internal potential difference generated by the PN junction, electron-hole pairs, which are charges generated by light incident on the active layer 300, are separated into electrons (e) and holes (h), and electrons are n-type doped region 320. After moving to the) side and the first electrode 600, the hole will move to the P-type doped region 310 and then to the second electrode 700.

In addition, in FIG. 6, the interface between the p-type doped region 310 and the N-type doped region 320 is not smooth as shown in the drawing as an actual interface. This is because the temperature distribution in the wafer is not constant due to diffusion by heat, and the interface is formed by diffusion.

According to an embodiment of the present invention, it is possible to provide a P-type and an N-type coexisting wafer manufacturing method. Therefore, in the P-type and N-type coexisting wafers manufactured according to the embodiment of the present invention, the impurity doping concentration gradient may be formed in the P-type doped region and the N-type doped region in the horizontal direction of the substrate. As a result, the diffusion current is changed into a drift current, thereby reducing the saturation current value I ₀ .

Therefore, a solar cell having a high current can be provided by manufacturing a solar cell using such P-type and N-type coexisting wafers.

The above description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. For example, each component described as a single type may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined form.

The scope of the present invention is represented by the following claims, and it should be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalents are included in the scope of the present invention.

10: P-type doped silicon particle 20: N-type doped silicon particle
100: substrate 210: P-type particle region
220: N-type particle region 300: active layer
310: P-type doped region 320: N-type doped region
400: emitter layer 500: rear field layer
600: first electrode 700: second electrode

Claims (15)

Alternately applying P-type doped silicon particles and N-type doped silicon particles in a horizontal direction of the substrate to form a pattern in which P-type particle regions and N-type particle regions are alternately formed; And
The P-type doped silicon particles and the N-type doped silicon particles are melted and cooled by passing the substrate having the pattern formed thereon through a heating unit, and the P-type particle region and the N-type particle region are P-type and N-type doped. Forming a region;
The P-type and N-type coexisting wafer manufacturing method of the P-type and N-type doped region characterized in that the impurity doping concentration gradient is formed in the horizontal direction of the substrate. The method of claim 1,
The substrate is a P-type and N-type coexistence wafer manufacturing method, characterized in that the substrate having a temperature resistance. The method of claim 2,
The substrate is a P-type and N-type coexistence wafer manufacturing method, characterized in that the SiC, SiN _x or SiO _x coated glass. The method of claim 1,
In the forming of the P-type particle region and the N-type particle region into a P-type doped region and an N-type doped region, the P-type doped silicon particles and the N-type doped silicon particles are melted and cooled, and a portion of the doping material is cooled. The method of manufacturing a P-type and N-type coexistence wafer according to the stone coefficient, characterized in that the doping degree of the impurity of the P-type and N-type doped region in the horizontal direction of the substrate is different. Board; And
A p-type doped region and an n-type doped region, which are alternately positioned in the horizontal direction of the substrate, on the substrate;
A P-type and an N-type coexisting wafer, wherein the P-type doping region and the N-type doping region are formed with an impurity doping concentration gradient having a different degree of impurity doping in the horizontal direction of the substrate. The method of claim 5,
The substrate is a P-type and N-type coexistence wafer, characterized in that the substrate having a temperature resistance. The method of claim 6,
The substrate is a P-type and N-type coexistence wafer, characterized in that the glass coated with SiC, SiN _x or SiO _x . The method of claim 5,
Wherein the P-type doped region is a P-type doped silicon region, and the N-type doped region is an N-type doped silicon region. Preparing a P-type and N-type coexisting wafer prepared by the P-type and N-type coexisting wafer manufacturing method of claim 1;
Removing the substrate from the P-type and N-type coexisting wafers to prepare the P-type and N-type doped regions as an active layer;
Forming an emitter layer on the active layer; And
A solar cell manufacturing method comprising the step of forming a backside field layer under the active layer. The method of claim 9,
Between the step of forming the emitter layer and the step of forming the back field layer,
Forming a first electrode on the emitter layer further comprises a solar cell manufacturing method. The method of claim 9,
After the step of forming a back field layer below the active layer,
And forming a second electrode under the backside field layer. The method of claim 9,
The backside field layer is a P-type semiconductor layer, the emitter layer is a solar cell manufacturing method characterized in that the N-type semiconductor layer. An active layer including a P-type doped region and an N-type doped region that are alternately positioned in the horizontal direction;
An emitter layer on the active layer;
A rear field layer disposed below the active layer;
A first electrode on the emitter layer; And
A second electrode disposed under the rear field layer;
The P-type doped region and the N-type doped region is a solar cell, characterized in that the impurity doping concentration gradient is formed in the horizontal direction of the active layer. The method of claim 13,
Wherein the P-type doped region is a P-type doped silicon region, and the N-type doped region is an N-type doped silicon region. The method of claim 13,
The backside field layer is a P-type semiconductor layer, the emitter layer is a solar cell, characterized in that the N-type semiconductor layer.

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