KR20200006266A - Display device - Google Patents

Abstract

The present invention relates to a display device for reducing manufacturing costs. The display device comprises: a display panel having a plurality of pixels; a source drive IC providing a data voltage to the pixels; a timing controller providing a drive control signal to the source drive IC; and an antenna unit connecting the timing controller and source drive IC. The timing controller adjusts a voltage level or operating frequency of the drive control signal outputted from the timing controller based on a voltage or frequency received from the antenna unit.

Description

Display device

The present invention relates to a display device.

With the development of information technology, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of display devices such as organic light emitting display (OLED), liquid crystal display (LCD), plasma display panel (PDP), and the like is increasing.

Some of the display devices described above, for example, a liquid crystal display device or an organic light emitting display device, when a gate signal and a data signal are supplied to the subpixels included in the display panel, the selected subpixels emit light to display an image. .

The display device as described above includes a display panel including a plurality of subpixels and a driver for driving the display panel. The driver includes a gate driver for supplying a gate signal (or scan signal) to the display panel and a data driver for supplying a data signal to the display panel. In addition, the timing controller controls the operation of the gate driver and the data driver by using the driving control signal.

When the display apparatus is exposed to an external communication environment, an interference phenomenon due to a communication signal may occur in the driving control signal output from the timing controller. Such signal interference causes noise on the screen output from the display panel and lowers the communication reception rate of the display device.

An object of the present invention is to detect the external or internal communication signal, and to change the voltage level or operating frequency band of the drive control signal based on this, to eliminate the screen defects due to signal interference.

In addition, an object of the present invention is to reduce the size and manufacturing cost of the display device by using a conventional signal transmission line as an antenna, or by providing a pattern operable as an antenna on the non-display area of the display panel.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention which are not mentioned above can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. Also, it will be readily appreciated that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

According to an aspect of the present invention, there is provided a display panel including a plurality of pixels, a source drive IC providing a data voltage to the pixels, and a driving control signal to the source drive IC. A timing controller providing a timing controller; and an antenna unit connecting the timing controller and the source drive IC, wherein the timing controller is based on a voltage or frequency received from the antenna unit, and the driving control signal output from the timing controller. Adjust voltage level or operating frequency of

The antenna unit may include an antenna signal line to which any one of the plurality of driving control signals are applied, and one end of the antenna signal line may be connected to the timing controller and the other end of the antenna signal line may be connected to the source drive IC. .

The antenna signal line may include a closed loop pattern formed between the one end and the other end.

In addition, the antenna signal line may be formed between the one end and the other end, and may include a toggle pattern in which bending is repeated at a predetermined interval.

The timing controller may further include a comparison unit for comparing a voltage or frequency of a signal applied to the antenna unit with a predetermined reference value, an output value of the comparison unit, and an adjustment value for a voltage level or an operating frequency of the driving control signal. And a memory unit for storing a table indicating a relationship between the controller and a controller for adjusting a voltage level or an operating frequency of the driving control signal with reference to the table.

The timing controller may further include a signal terminal unit configured to receive a signal applied to the antenna unit, and the signal terminal unit and the comparison unit may be connected in parallel between the antenna unit and the control unit.

The comparator may include a voltage comparator for comparing the voltage of the signal applied to the antenna unit with a predetermined reference voltage.

The comparator compares a frequency of a signal applied to the antenna unit with a first reference frequency that is predetermined, and compares a frequency of the signal applied to the antenna unit with a second reference frequency. A second frequency comparator may be further included, wherein the first reference frequency may be set differently from the second reference frequency.

The comparator may include a voltage comparator, first and second frequency comparators, and the antenna part may include different first and second antenna parts, and the voltage comparator is connected to the first antenna part. The first and second frequency comparators may be connected to the second antenna unit.

In addition, the timing controller, the source drive IC and the antenna unit may be formed on the same printed circuit board (PCB).

According to another aspect of the present invention, there is provided a display area including a pixel array, a display panel divided into a non-display area different from the display area, and a printed circuit spaced apart from the display panel. A substrate (PCB), a flexible circuit film connecting the display panel and the printed circuit board, a source drive IC disposed on the printed circuit board or the flexible circuit film and providing a data voltage to the pixel array; A timing controller disposed on a circuit board and configured to provide a driving control signal to the source drive IC, and an antenna unit disposed on the non-display area and connected to one end of the timing controller, wherein the timing controller includes the antenna; The phrase output from the timing controller based on the voltage or frequency received from the negative It controls the voltage level or the operating frequency of the control signal.

The antenna unit may include a closed loop pattern formed along an outer circumferential surface of the non-display area.

In addition, the antenna unit may include a toggle pattern in which bending is repeated at a predetermined interval in the non-display area.

The apparatus may further include a communication module disposed in the non-display area, and the antenna unit may be disposed adjacent to the communication module in the non-display area to detect a radio signal generated from the communication module.

The timing controller may further include a comparison unit comparing a voltage or frequency of a signal applied to the antenna unit with a predetermined reference value, and a relationship between an output value of the comparison unit and an adjustment value for a voltage level or an operating frequency of a driving control signal. And a memory for storing a table, and a controller for adjusting a voltage level or an operating frequency of the driving control signal with reference to the table.

The timing controller may further include a signal terminal unit configured to receive a signal applied to the antenna unit, and the signal terminal unit and the comparison unit may be connected in parallel between the antenna unit and the controller.

The comparator may include a voltage comparator for comparing the voltage of the signal applied to the antenna unit with a predetermined reference voltage, a frequency of the signal applied to the antenna unit, and a first frequency for comparing the predetermined first reference frequency. The comparator may include a comparator and a second frequency comparator comparing the frequency of the signal applied to the antenna unit with a second predetermined reference frequency.

The antenna unit may include different first and second antenna units, and the voltage comparator may be connected to the first antenna unit, and the first and second frequency comparators may be connected to the second antenna unit. have.

The first antenna unit may be disposed on one side of the non-display area, and the second antenna unit may be disposed on the other side of the non-display area.

The display device of the present invention can solve the problem that a screen failure occurs due to interference with a communication signal. Through this, the sensitivity of the communication signal of the display device can be lowered. In addition, by changing the operating frequency band, a phenomenon in which the communication reception rate of the display device is lowered may be reduced. Therefore, the driving stability of the display device can be improved.

In addition, the display device of the present invention can reduce the cost required to provide an additional antenna by using the signal line on the printed circuit board as an antenna. In addition, the size of the display apparatus may be reduced by providing a pattern operating as an antenna on the non-display area of the display panel.

1 and 2 are block diagrams schematically showing the display device of the present invention.
3 is a block diagram illustrating a relationship between an antenna unit and a timing controller according to an exemplary embodiment of the present invention.
4 is a schematic diagram illustrating a printed circuit board (PCB) having an antenna unit and a timing controller according to an exemplary embodiment of the present invention.
FIG. 5 is a diagram illustrating some embodiments of an antenna signal line provided in the printed circuit board (PCB) of FIG. 4.
6 to 9 illustrate some embodiments of an antenna unit provided in a non-display area of a display panel.
10 is a block diagram illustrating a relationship between an antenna unit and a comparison unit according to an embodiment of the present invention.
FIG. 11 is a timing diagram illustrating an input signal and an output signal of the comparator of FIG. 10.
FIG. 12 is a diagram illustrating a table stored in a memory unit of FIG. 3.
13 and 14 illustrate an operation result of a display apparatus according to an exemplary embodiment of the present invention.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments of the present invention make the disclosure of the present invention complete, and the general knowledge in the technical field to which the present invention belongs. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims.

Shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are exemplary, and thus, the present invention is not limited thereto. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In the case where 'comprises', 'haves', 'consists of' and the like mentioned in the present specification are used, other parts may be added unless 'only' is used. In the case where the component is expressed in the singular, the plural includes the plural unless specifically stated otherwise.

In the case of the description of the positional relationship, for example, if the positional relationship of the two parts is described as 'on', 'upper', 'lower', 'next to', etc. Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be a second component within the technical spirit of the present invention.

Each of the features of the various embodiments of the present invention may be combined or combined with each other, in part or in whole, various technically interlocking and driving, each of the embodiments may be implemented independently of each other or may be implemented in association It may be.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like numbers refer to like elements throughout the specification.

The display device according to the present invention will be described with reference to the case of a liquid crystal display device. In addition, the liquid crystal display may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The liquid crystal mode applicable to the present invention is a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, or a horizontal electric field driving such as IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) mode. The method can be applied, and all other liquid crystal modes currently known can be applied.

In addition, the display device according to the present invention is implemented as a television, set-top box, navigation, video player, Blu-ray player, personal computer (PC), home theater and mobile phone. The display device may be a liquid crystal display, an organic light emitting display, a quantum dot display, an electrophoretic display, a plasma display, or the like, but is not limited thereto.

A general display device includes a timing controller, a data driver circuit, a gate driver circuit, and a display panel. The timing controller receives video data and timing signals from a source, processes them, and provides them as image signals and control signals to the data driving circuit and the gate driving circuit. The data driving circuit and the gate driving circuit are directly connected to the pixels included in the panel through the data lines and the gate lines to display an image through the pixels.

The source and timing controllers can be connected by wiring lines along a system interface such as Vx1. Timing controllers and data drive circuits can be connected by wire line pairs along an internal panel interface, such as an embedded clock P-P interface (EPI). The timing controller and the gate driving circuit may be connected by a predetermined number of lines. The data driving circuit and the gate driving circuit may be directly connected to the panel by the number of lines corresponding to the resolution of the display panel.

Hereinafter, a display apparatus according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 14.

1 and 2 are block diagrams schematically showing the display device of the present invention.

Referring to FIG. 1, the display apparatus includes a display panel PNL, a timing controller 200 (T-CON), a source drive IC 310 (SIC1 to SIC4), and a source 10. Here, the gate driving circuit (or scan driving circuit) is omitted. In this case, a plurality of source drive ICs 310 may be provided, and is not limited to four as shown in FIG. 1.

The source drive IC 310 receives a clock signal, a control signal CTR, and pixel data (or video data) of an input image from the timing controller 200 through an intra panel interface such as an EPI interface. Receive

The timing controller 200 and each source drive IC 310 are connected 1: 1 through an EPI wiring pair (EPI). That is, the timing controller 200 and each source drive IC 310 may be connected in a point-to-point form.

The source drive IC 310 may recover the clock from the signal provided by the timing controller 200 and fix the phase and frequency of the internal clock. Subsequently, the source drive IC 310 may output a lock signal to the timing controller 200. When the lock signal is received from the last source drive IC 310, the timing controller 200 may transmit a data packet including control data and video data to the source drive IC 310.

Referring to FIG. 2, the display device according to the present invention may include a display panel PNL, a timing controller 200, a data driving circuit 300, and a gate driving circuit 400.

In the display panel PNL, a plurality of data lines 14A, a sensing line 14B, and a plurality of gate lines (or scan lines) 15A and 15B intersect with each other, and pixels P are in a matrix form at each of the crossing regions. Are arranged to form a pixel array.

The display panel PNL is divided into an active area (hereinafter, AA) in which a pixel array is formed, and a non-active area (hereinafter, NA) in which various signal lines, ground lines, pads, etc. are formed. do. In this case, the non-display area NA may be disposed outside the display area AA. The display panel PNL is implemented to include a liquid crystal layer or an organic light emitting layer according to the configuration of the sub-pixel SP.

The gate lines 15A and 15B may include a plurality of first gate lines 15A supplied with the first scan signal SCAN and a plurality of second gate lines 15B supplied with the second scan signal SEN. Can be. In addition, touch sensors for implementing a touch user interface (UI) may be built in the pixel array.

Each pixel P may include one of the data lines 14A, one of the sensing lines 14B, one of the first gate lines 15A, and one of the second gate lines 15B. Can be connected to. Each of the pixels P may receive a high potential driving voltage and a low potential driving voltage from a power generator not shown.

The display device to which the present invention is applied may perform a signal compensation operation. The signal compensation operation refers to sensing the magnitude of the voltage of the communication signal or the operating frequency band and correcting the digital data DATA of the driving control signal or the input image according to the sensing value.

In this case, the timing controller 200 may sense the voltage or the operating frequency band of the communication signal and separate the display driving for displaying the input image reflecting the compensation value according to a predetermined control sequence in time.

For example, the signal compensation operation of the timing controller 200 is performed in the vertical blank period (or vertical blank time) during display driving, or the image is displayed after the power-on sequence period (drive power is applied) before the display driving is started. It may be performed in a non-display section until the image display section to be displayed, or in a power off sequence period (non-display section from immediately after the image display is finished until the driving power is cut off) after the display &

Here, the vertical blank period is a period in which the input video data DATA is not written, and is disposed between the vertical active periods in which the input video data DATA for one frame is written. The power on sequence period refers to a transient period from when the driving power is turned on until the input image is displayed. The power off sequence period refers to a transient period from when the input image is displayed until the driving power is turned off.

As the display device to which the present invention is applied, an OLED display device will be described, but the present invention is not limited thereto. For example, the display device of the present invention may be applied to a liquid crystal display (LCD) or an inorganic light emitting display device using an inorganic material as a light emitting layer.

The timing controller 200 is based on a data driving circuit based on timing signals, such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE, which are input from a host system. The data control signal DDC for controlling the operation timing of the operation 300 and the gate control signal GDC for controlling the operation timing of the gate driving circuit 400 may be generated.

Hereinafter, control signals (eg, DDC and GDC) generated by the timing controller 200 will be defined and described as driving control signals.

The gate control signal GDC may include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like.

Specifically, the gate start pulse GSP is applied to the gate stage generating the first scan signal to control the gate stage so that the first scan signal is generated. The gate shift clock GSC is a clock signal input to the gate stages in common and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE is a masking signal that controls the output of the gate stages.

The data control signal DDC includes a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, and the like.

Specifically, the source start pulse SSP controls the data sampling start timing of the data driving circuit 300. The source sampling clock SSC is a clock signal that controls sampling / timing of data in each of the source drive ICs 310 based on the rising or falling edge. The source output enable signal SOE controls the output timing of the data driving circuit 300.

The timing controller 200 may correct the magnitudes or frequency bands of the signals described above with reference to the compensation table stored in the memory unit 230 of FIG. 3. Detailed description thereof will be described later.

The data driving circuit 300 may include at least one source drive IC 310. The source drive IC 310 includes a plurality of digital-to-analog converters (hereinafter referred to as DACs) connected to the data lines 14A and sensing circuits connected to the sensing lines 14B, and the sensing circuits include the sensing lines 14B. ) May include a plurality of sensing units SU and an analog-to-digital converter (ADC). The source drive ICs 310 are connected to the data lines DL of the display panel PNL by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate driving circuit 400 sequentially generates a gate pulse for display based on the gate control signal GDC during display driving and sequentially supplies the gate pulses 15A and 15B connected to the pixel lines.

Here, the pixel lines mean a set of horizontally neighboring pixels P. The gate pulse swings between the gate high voltage VGH and the gate low voltage VGL. The gate high voltage VGH is set to a voltage higher than the threshold voltage of the TFT to turn on the TFT, and the gate low voltage VGL represents a voltage lower than the threshold voltage of the TFT.

Hereinafter, the configuration of the timing controller 200 according to some embodiments of the present invention will be described in detail.

3 is a block diagram illustrating a relationship between an antenna unit and a timing controller according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the above-described timing controller 200 is connected to the antenna unit 100. The timing controller 200 may include a comparator 210, a signal terminal unit 215, a controller 220, and a memory unit 230.

The antenna unit 100 may detect an external communication signal. In this case, the antenna unit 100 may be formed on a printed circuit board (PCB). Specifically, a signal line formed to transmit a signal on a printed circuit board (PCB) may be used as the antenna unit 100.

The signal line used by the timing controller 200 to transmit driving control signals (eg, DDC, GDC) to the source drive IC 310 may be used as the antenna unit 100. In addition, a signal line used by the source drive IC 310 to transmit a feedback signal (eg, a lock signal) to the timing controller 200 may also be used as the antenna unit 100. In this case, the antenna unit 100 may transmit a signal and sense a voltage and a frequency of an external communication signal.

In addition, the antenna unit 100 may be used to detect an internal communication signal output from a communication unit (eg, 600 of FIG. 6) included in the display device. In this case, the antenna unit 100 may be disposed to be adjacent to the communication unit 600. In this case, the antenna unit 100 may be formed in the non-display area NA of the display panel PNL. One end of the antenna unit 100 may be electrically connected to the timing controller 200.

Here, the size and frequency of the communication signal that can be received may vary depending on the size, width, thickness, and length of the antenna unit 100.

Detailed description of the antenna unit 100 will be described below with reference to FIGS. 4 to 9.

The comparison unit 210 may compare the voltage and frequency of the communication signal detected by the antenna unit 100 with a predetermined reference value. The comparator 210 may include a plurality of comparators.

The comparator 210 may include a voltage comparator (Vcomp of FIG. 10) and a frequency comparator (Fcomp).

In detail, the voltage comparator (Vcomp of FIG. 10) may compare the voltage of the communication signal detected from the antenna unit 100 with a predetermined reference voltage.

The frequency comparator (Fcomp of FIG. 10) may compare the frequency of the communication signal detected by the antenna unit 100 with a predetermined reference frequency. The comparator 210 may include a plurality of frequency comparators Fcomp. In this case, reference frequencies used by the respective frequency comparators Fcomp may be different from each other.

The comparator 210 may include only a voltage comparator Vcomp or a frequency comparator Fcomp. In addition, the comparator 210 may include both a voltage comparator Vcomp and a frequency comparator Fcomp.

However, hereinafter, for convenience of description, the comparator 210 will be described with an example including both the voltage comparator Vcomp and the frequency comparator Fcomp.

The signal terminal unit 215 may be connected to a signal line used as the antenna unit 100. The signal terminal unit 215 may receive a signal applied to the antenna unit 100. In addition, the signal terminal unit 215 may provide a driving control signal provided from the timing controller 200 to the antenna unit 100.

The signal terminal unit 215 may exchange data with the control unit 220. That is, the signal terminal unit 215 may transmit a signal applied to the antenna unit 100 to the control unit 220, or may transmit a driving control signal generated by the control unit 220 to the antenna unit 100.

In this case, the signal terminal unit 215 may be connected to the same signal line as the comparator 210 (that is, the same antenna unit 100). In addition, between the control unit 220 and the antenna unit 100, the signal terminal unit 215 may be connected in parallel with the control unit 220.

The controller 220 receives an output value of the comparator 210. With reference to the table stored in the memory unit 230, the controller 220 may adjust the voltage level (or the magnitude of the voltage amplitude) or the operating frequency band of the driving control signal based on the output of the comparator 210. In this case, the output value of the comparator 210 may be provided to the controller 220 in the form of address data.

For example, when the voltage of the signal detected by the antenna unit 100 is smaller than the reference voltage, the controller 220 may increase the voltage level (or the magnitude of the voltage amplitude) of the driving control signal. In addition, when the frequency of the signal detected by the antenna unit 100 is smaller than the reference frequency, the controller 220 may move the operating frequency band of the drive control signal.

The memory unit 230 stores information about driving conditions of the timing controller 200. In detail, the memory 230 may store a table indicating a relationship between an output value of the comparator 210 and a voltage level (or magnitude of voltage amplitude) of the driving control signal or an operating frequency band. Details of the table will be described later with reference to FIG. 12.

4 is a schematic diagram illustrating a printed circuit board (PCB) having an antenna unit and a timing controller according to an exemplary embodiment of the present invention. FIG. 5 is a diagram illustrating some embodiments of an antenna signal line provided in the printed circuit board (PCB) of FIG. 4.

Referring to FIG. 4, the above-described antenna unit 100, the data driving circuit 300, and the timing controller 200 may be provided on a printed circuit board (PCB).

Here, the data driving circuit 300 may include a plurality of source drive ICs 310. In this case, the plurality of source drive ICs 310 may be mounted on a printed circuit board (PCB). The plurality of source drive ICs 310 may be disposed to be spaced apart from each other.

The printed circuit board PCB may be connected to the display panel PNL through the flexible circuit film FPCB. In the printed circuit board PCB, bonding regions D1, D2, and D3 for bonding with the flexible circuit film FPCB may be formed.

The flexible circuit film FPCB may connect the display panel PNL and the printed circuit board PCB using various methods. For example, the flexible circuit film FPCB may connect the display panel PNL and the printed circuit board PCB by using a tape automated bonding (TAB) method.

At this time, in another embodiment, the source drive IC 310 may be disposed on the flexible circuit film (FPCB). Therefore, in order to be electrically connected to the source drive IC 310, a connection line may be formed on the bonding regions D1, D2, and D3 of the printed circuit board PCB for bonding with the flexible circuit film FPCB. .

In summary, the source drive IC 310 may be disposed on a printed circuit board (PCB) or a flexible circuit film (FPCB).

Hereinafter, for convenience of description, the source drive IC 310 is disposed at one end of the printed circuit board (PCB).

The signal line L1 for signal transmission is disposed between the timing controller 200 and the source drive IC 310. Although only one signal line L1 is illustrated in FIG. 4, a plurality of signal lines may be provided on the printed circuit board PCB according to the number of transmitted signals.

In this case, any one signal line L1 of the plurality of signal lines may be used as the antenna unit 100. The signal line L1 used as the antenna unit 100 may be connected to the plurality of input terminals P11 and P12 of the timing controller 200, respectively. That is, the signal line L1 may be branched at one end and connected to the plurality of input terminals P11 and P12, respectively.

In addition, the antenna unit 100 may be formed in various patterns to detect a communication signal.

For example, referring to FIG. 5A, the antenna unit 100 may include a first antenna signal line LP1 having a closed loop pattern. In this case, one end A1 of the first antenna signal line LP1 may be connected to the timing controller 200, and the other end A2 may be connected to the source drive IC 310. In this case, according to the specification required by the antenna unit 100, the size and shape of the closed loop pattern may be variously modified.

As another example, referring to FIG. 5B, the antenna unit 100 may include a second antenna signal line LP2 having a toggle pattern (ie, a zigzag pattern) in which bending is repeated at a predetermined interval. It may include. In this case, one end B1 of the second antenna signal line LP2 may be connected to the timing controller 200, and the other end B2 may be connected to the source drive IC 310.

In this case, the interval and shape of the zigzag pattern may be variously modified according to the specifications required by the antenna unit 100.

Depending on the overall length, thickness, width, shape of the cross section, etc. of the signal line L1, the frequency band and the reflection coefficient of the signal received by the antenna unit 100 may vary. In addition, the characteristics of the antenna unit 100 may vary according to the specification of the printed circuit board (PCB). For example, the characteristics of the signal received by the antenna unit 100 may vary according to the thickness of the copper foil of the PCB, the thickness of the dielectric layer, and the dielectric constant of the substrate.

Therefore, a person skilled in the art can change the structure of the antenna unit 100 and the printed circuit board (PCB) to have a necessary specification.

6 to 9 illustrate some embodiments of an antenna unit provided in a non-display area of a display panel.

Referring to FIG. 6, the display panel PNL includes a display area AA formed at the center and a non-display area NA disposed outside the display area AA. As described above, the pixel array is disposed in the display area AA. Various signal lines, ground lines, pads, etc. may be formed in the non-display area NA.

The display apparatus according to the embodiment of the present invention may further include a communication unit 600 for wireless communication with the external device.

The communication unit 600 may exchange data with other external devices or other internal components via wired or wireless. Wireless communication networks used by the communication unit 600 include WLAN, Wi-Fi, WiBro, WiMAX, World Interoperability for Microwave Access (WMAX), and HSDPA (High Speed Downlink Packet Access). ), Long Term Evolution (LTE), IEEE802.16, and Wireless Mobile Broadband Service (WMBS).

In addition, short-range wireless communication networks used by the communication unit 600 include beacons, Bluetooth, Radio Frequency Identification (RFID), Infrared Data Association (IrDA), UWB (Ultra Wideband), ZigBee (ZigBee). And Z-Wave. However, these are only examples and the present invention is not limited thereto.

The communication unit 600 may be disposed on the non-display area NA of the display panel PNL.

Like the communication unit 600, the antenna unit 100 may be formed on the non-display area NA of the display panel PNL. In this case, the antenna unit 100 may be disposed adjacent to the communication unit 600 to detect a communication signal (that is, an internal communication signal) output from the communication unit 600.

The antenna unit 100 may include an antenna pattern AP for receiving a communication signal (that is, an internal communication signal) output from the communication unit 600. The antenna pattern AP may be formed in various shapes according to the type of the signal output from the communication unit 600.

In addition, the antenna unit 100 may detect a communication signal (ie, an external communication signal) applied from the outside. In this case, the antenna unit 100 may be arranged to be spaced apart from the communication unit 600 to be less affected by the communication signal output from the communication unit 600. The antenna pattern AP may be formed in various shapes according to the type of external signal considered in the design.

The antenna pattern AP may be electrically connected to the timing controller 200. The connection line CL may be used to connect the antenna pattern AP and the timing controller 200.

In addition, although not clearly shown in the drawings, the antenna pattern AP may be formed on a layer on which a source / drain is formed in the panel. However, this is only one example and the present invention is not limited thereto.

For example, referring to FIG. 7, the antenna unit 100 may include a first antenna line AP1 having a closed loop pattern formed along an outer circumferential surface of the display panel PNL. The first antenna line AP1 may be formed on the non-display area NA.

In this case, the first antenna line AP1 may be electrically connected to the timing controller 200 through the connection line CL. The connection line CL may be disposed on the flexible circuit film FPCB connecting the display panel PNL and the printed circuit board PCB.

According to the specifications required by the antenna unit 100, the size and shape of the closed loop pattern may be variously modified.

As another example, referring to FIG. 8, the antenna unit 100 may include a second antenna line AP2 having a toggle pattern (or a zigzag pattern) in which bending is repeated. The second antenna line AP2 may be formed on the non-display area NA.

The second antenna line AP2 may be electrically connected to the timing controller 200 through the connection line CL. The connection line CL may be disposed on the flexible circuit film FPCB connecting the display panel PNL and the printed circuit board PCB.

According to the specification required by the antenna unit 100, the spacing and shape of the zigzag pattern may be variously modified.

As another example, referring to FIG. 9, the antenna unit 100 may include a third antenna line AP3 having a pattern used for a specific communication protocol. The third antenna line AP3 may be formed on the non-display area NA. In addition, the third antenna line AP3 may be formed in a pattern of a predetermined standard for receiving a signal of a communication protocol used by the communication unit 600.

The third antenna line AP3 may be electrically connected to the timing controller 200 through the connection line CL. The connection line CL may be disposed on the flexible circuit film FPCB connecting the display panel PNL and the printed circuit board PCB.

According to the specification required by the antenna unit 100, the shape and size of the pattern used in the communication protocol may be variously modified.

The frequency band and the reflection coefficient of the signal received by the antenna unit 100 may vary according to the overall length, thickness, width, shape of the cross section, and the like of each antenna line AP1, AP2, and AP3. In addition, the characteristics of the antenna unit 100 may vary according to the specification of the display panel PNL. For example, characteristics of a signal received by the antenna unit 100 may vary according to the thickness of the copper foil of the display panel PNL, the thickness of the dielectric layer, and the dielectric constant of the substrate.

10 is a block diagram illustrating a relationship between an antenna unit and a comparison unit according to an embodiment of the present invention.

Referring to FIG. 10, the comparator 210 may include a voltage comparator Vcomp and / or a frequency comparator Fcmop. That is, the comparator 210 may include only the voltage comparator Vcomp. In addition, the comparator 210 may include only a frequency comparator (Fcmop). In addition, the comparator 210 may include both a voltage comparator Vcomp and a frequency comparator Fcmop.

Meanwhile, the voltage comparator Vcomp and the frequency comparator Fcmop may receive signals from the same antenna. Alternatively, the voltage comparator Vcomp and the frequency comparator Fcmop may receive signals from different antennas.

The antenna unit 100 may include different first and second antenna units 110 and 120. In this case, the first antenna unit 110 and the second antenna unit 120 may be disposed to be spaced apart from each other.

For example, the first antenna unit 110 may be used to detect an internal communication signal used in the display device, and the second antenna unit 120 may be used to detect an external communication signal applied to the display device. That is, the first antenna unit 110 may be disposed to be adjacent to the communication unit 600, and the second antenna unit 120 may be disposed to be spaced apart from the communication unit 600.

As another example, the first antenna unit 110 may be disposed on the printed circuit board PCB, and the second antenna unit 120 may be disposed on the display panel PNL.

However, this is only a few examples, and the arrangement of the first antenna unit 110 and the second antenna unit 120 may be variously modified.

Hereinafter, for convenience of description, the case where the comparator 210 includes both the voltage comparator Vcomp and the frequency comparator Fcmop will be described as an example. In addition, for convenience of explanation, the voltage comparator Vcomp receives a signal from the first antenna unit 110 and the frequency comparator Fcmop receives a signal from the second antenna unit 120 as an example. .

The voltage comparator Vcomp may compare the voltage of the signal Ant1 applied from the first antenna unit 110 with a predetermined reference voltage Vref. If the voltage of the applied signal Ant1 is greater than the reference voltage Vref, the voltage comparator Vcomp may output a logic high signal (ie, '1') to the first output terminal Out1. On the other hand, when the voltage of the applied signal Ant1 is smaller than the reference voltage Vref, the voltage comparator Vcomp may output a logic low signal (ie, '0') to the first output terminal Out1.

The frequency comparator Fcmop may include a plurality of frequency comparators Fcmop1 and Fcmop2 using different reference frequencies. That is, the comparator 210 may include a plurality of frequency comparators Fcmop1 and Fcmop2. In the following description, the comparator 210 includes first and second frequency comparators Fcmop1 and Fcmop2.

The first frequency comparator Fcmop1 may compare the frequency of the signal Ant2 applied from the second antenna unit 120 with the predetermined first reference frequency Fref1. If the frequency of the applied signal Ant2 is greater than the first reference frequency Fref1, the first frequency comparator Fcmop1 may output a logic high signal (ie, '1') to the second output terminal Out2. Can be. On the other hand, when the frequency of the applied signal Ant2 is smaller than the first reference frequency Fref1, the first frequency comparator Fcmop1 may output a logic low signal (ie, '0') to the second output terminal Out2. Can be.

Similarly, the second frequency comparator Fcmop2 may compare the frequency of the signal Ant2 applied from the second antenna unit 120 with the predetermined second reference frequency Fref2. If the frequency of the applied signal Ant2 is greater than the second reference frequency Fref2, the second frequency comparator Fcmop2 may output a logic high signal (ie, '1') to the third output terminal Out3. Can be. On the other hand, when the frequency of the applied signal Ant2 is smaller than the second reference frequency Fref2, the second frequency comparator Fcmop2 may output a logic low signal (ie, '0') to the third output terminal Out3. Can be.

In this case, the first reference frequency Fref1 and the second reference frequency Fref2 may be different from each other. For example, the first reference frequency Fref1 may be set to 850 Mhz and the second reference frequency Fref2 may be set to 750 Mhz. If the frequency of the applied signal Ant2 is 800 Mhz, the first frequency comparator Fcmop1 outputs a logic low signal (ie, '0'), and the second frequency comparator Fcmop2 outputs a logic high signal (ie, , '1').

For reference, the comparator 210 may operate only when a specific signal is applied from the timing controller 200. For example, the comparator 210 may operate only when a reset signal Reset is applied from the timing controller 200. However, this is only one example, and the present invention is not limited thereto.

The signal output from the comparator 210 through the first to third output terminals Out1, Out2, and Out3 may be applied to the controller 220. Signals output through the first to third output terminals Out1, Out2, and Out3 form address data.

The controller 220 may adjust a voltage level (or voltage amplitude) and an operating frequency of the driving control signal output from the timing controller 200 based on the address data received from the comparator 210. In this case, the controller 220 refers to a table stored in the memory 230.

Hereinafter, the operation of the controller 220 will be described with reference to the examples shown in FIGS. 11 and 12.

FIG. 11 is a timing diagram illustrating an input signal and an output signal of the comparator of FIG. 10. FIG. 12 is a diagram illustrating a table stored in a memory unit of FIG. 3.

11 and 12, in the period <D1>, the voltage of the signal applied to the first antenna unit 110 is smaller than the reference voltage Vref of the voltage comparator Vcomp. In addition, the frequency of the signal applied to the second antenna unit 120 is smaller than the reference frequencies Fref2 and Fref2 of the first and second frequency comparators Fcmop1 and Fcmop2. Therefore, the address data input to the controller 220 becomes '000'.

In the table stored in the memory unit 230, the voltage level VID and the operating frequency EPI Freq. Corresponding to '000' may represent basic setting values. Therefore, the controller 220 outputs the driving control signal according to the basic setting value.

Subsequently, in the period <D2>, the voltage V1 of the signal applied to the first antenna unit 110 becomes greater than the reference voltage Vref of the voltage comparator Vcomp. However, the frequency F1 of the signal applied to the second antenna unit 120 is kept smaller than the reference frequencies Fref1 and Fref2 of the first and second frequency comparators Fcmop1 and Fcmop2. Therefore, the address data input to the controller 220 becomes '100'.

In this case, the controller 220 may adjust the voltage level (or voltage amplitude) of the driving control signal with reference to the table stored in the memory 230. For example, the controller 220 may increase the voltage level (or voltage amplitude) of the driving control signal from 250 mV to 450 mV.

Subsequently, in the period <D3>, the voltage V1 of the signal applied to the first antenna unit 110 is still larger than the reference voltage Vref of the voltage comparator Vcomp. Meanwhile, the frequency F1 of the signal applied to the second antenna unit 120 is smaller than the reference frequency Fref1 of the first frequency comparator Fcmop1 and greater than the reference frequency Fref2 of the second frequency comparator Fcmop2. Change. Therefore, the address data input to the controller 220 becomes '101'.

In this case, the controller 220 may adjust an operating frequency of the driving control signal with reference to a table stored in the memory 230. For example, the controller 220 may move the operating frequency of the drive control signal from 46.1Mhz to 38Mhz.

Subsequently, in the period <D4>, the voltage V1 of the signal applied to the first antenna unit 110 changes smaller than the reference voltage Vref of the voltage comparator Vcomp. Meanwhile, the frequency F1 of the signal applied to the second antenna unit 120 is smaller than the reference frequency Fref1 of the first frequency comparator Fcmop1 and greater than the reference frequency Fref2 of the second frequency comparator Fcmop2. Is maintained. Accordingly, the address data input to the controller 220 is '001'.

In this case, the controller 220 may adjust the voltage level (or voltage amplitude) of the driving control signal with reference to the table stored in the memory 230. For example, the controller 220 may lower the voltage level (or voltage amplitude) of the driving control signal from 450 mV to 250 mV.

11 and 12 are merely examples, and the number of tables stored in the memory 230 and the comparator included in the comparator 210 may be modified in various ways.

In summary, by referring to the table stored in the memory 230 based on the address data received from the comparator 210, the controller 220 controls the voltage of the drive control signal output from the timing controller 200. The level (or voltage amplitude) and operating frequency can be adjusted.

13 and 14 illustrate an operation result of a display apparatus according to an exemplary embodiment of the present invention.

Referring to FIG. 13, in the case of <A>, the voltage level (or voltage amplitude) of the driving control signal output from the timing controller 200 is located in an abnormal operation region. This indicates that the driving control signal is out of the normal operation area due to noise caused by an external communication signal or an internal communication signal. In this case, a screen defect may occur in the display device.

In order to solve this problem, the antenna unit 100 detects an external communication signal or an internal communication signal and transmits it to the comparator 210. Subsequently, the comparator 210 transmits the address data determined using the predetermined reference value to the controller 220. Subsequently, the controller 220 may adjust the voltage level (or voltage amplitude) of the driving control signal with reference to the memory unit 230 storing an adjustment value corresponding to the address data.

In the case of <B>, the controller 220 adjusts the voltage level (or voltage amplitude) of the drive control signal. When the voltage level (or voltage amplitude) of the drive control signal is increased, the drive control signal may be included in the normal operation region. Through this, the screen defect phenomenon due to the noise according to the communication signal can be eliminated.

Referring to FIG. 14, in the case of <A>, the driving frequency of the driving control signal output from the timing controller 200 may be included in the communication band B1 of the display device. In this case, the wireless reception rate of the display device may decrease.

In order to solve this problem, the antenna unit 100 detects an external communication signal or an internal communication signal and transmits it to the comparator 210. Subsequently, the comparator 210 transmits the address data determined using the predetermined reference value to the controller 220. Subsequently, the controller 220 may adjust the driving frequency of the driving control signal with reference to the memory 230 storing the adjustment value corresponding to the address data.

In the case of <B>, the controller 220 adjusts the driving frequency of the driving control signal. For example, when the driving frequency of the driving control signal is out of the communication band B1 of the display device, noise generated in the communication band B1 may be reduced. As a result, the interference between the driving frequency of the driving control signal and the communication band B1 may be reduced, and thus the wireless reception rate of the display apparatus may be improved.

Therefore, the display device of the present invention can solve the problem that a screen failure occurs due to interference with an external communication signal or an internal communication signal. Through this, the sensitivity of the communication signal of the display device can be lowered. In addition, the phenomenon that the communication reception rate of the display device is lowered can be reduced. Therefore, the driving stability of the display device can be improved.

In addition, the display device of the present invention by using a signal line on a printed circuit board (PCB) as an antenna, the cost required to have an additional antenna can be reduced. In addition, the size of the display apparatus may be reduced by providing a pattern operating as an antenna on the non-display area of the display panel.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by.

100: antenna 200: controller
210: comparison unit 215: signal terminal unit
220: control unit 230: memory unit
300: data driving circuit 310: source drive IC
400: gate driving circuit 600: communication unit

Claims (19)

A display panel having a plurality of pixels;
A source drive IC providing a data voltage to the pixel;
A timing controller providing a drive control signal to the source drive IC; And
An antenna unit for connecting the timing controller and the source drive IC,
The timing controller,
Adjusting the voltage level or operating frequency of the drive control signal output from the timing controller based on the voltage or frequency received from the antenna unit
Display device.
According to claim 1,
The antenna unit includes an antenna signal line to which any one of a plurality of the drive control signal is applied,
The antenna signal line has one end connected to the timing controller and the other end connected to the source drive IC.
Display device.
The method of claim 2,
The antenna signal line includes a closed loop pattern formed between the one end and the other end.
Display device.
The method of claim 2,
The antenna signal line includes a toggle pattern that is formed between the one end and the other end and is repeatedly curved at a predetermined interval.
Display device.
According to claim 1,
The timing controller,
A comparison unit for comparing a voltage or frequency of the signal applied to the antenna unit with a predetermined reference value;
A memory unit for storing a table indicating a relationship between an output value of the comparison unit and an adjustment value for a voltage level or an operating frequency of the drive control signal;
And a controller configured to adjust a voltage level or an operating frequency of the driving control signal with reference to the table.
Display device.
The method of claim 5,
The timing controller further includes a signal terminal unit for receiving a signal applied to the antenna unit,
The signal terminal unit and the comparison unit are connected in parallel between the antenna unit and the control unit.
Display device.
The method of claim 5,
The comparison unit
And a voltage comparator for comparing the voltage of the signal applied to the antenna unit with a predetermined reference voltage.
Display device.
The method of claim 5,
The comparison unit
A first frequency comparator for comparing a frequency of a signal applied to the antenna unit with a first predetermined reference frequency;
Further comprising a second frequency comparator for comparing the frequency of the signal applied to the antenna unit with a second predetermined reference frequency,
The first reference frequency is set differently from the second reference frequency
Display device.
The method of claim 5,
The comparator includes a voltage comparator, first and second frequency comparators,
The antenna unit may include different first and second antenna units,
The voltage comparator is connected to the first antenna unit,
The first and second frequency comparators are connected to the second antenna unit.
Display device.
According to claim 1,
The timing controller, the source drive IC and the antenna unit are formed on the same printed circuit board (PCB).
Display device.
A display panel divided into a display area including a pixel array and a non-display area different from the display area;
A printed circuit board (PCB) spaced apart from the display panel;
A flexible circuit film connecting the display panel and the printed circuit board;
A source drive IC disposed on the printed circuit board or the flexible circuit film and providing a data voltage to the pixel array;
A timing controller disposed on the printed circuit board and configured to provide a driving control signal to the source drive IC; And
An antenna unit disposed on the non-display area and connected to one end of the timing controller,
The timing controller,
Adjusting the voltage level or operating frequency of the drive control signal output from the timing controller based on the voltage or frequency received from the antenna unit
Display device.
The method of claim 11, wherein
The antenna unit may include a closed loop pattern formed along an outer circumferential surface of the non-display area.
Display device.
The method of claim 11, wherein
The antenna unit may include a toggle pattern in which bending is repeated at a predetermined interval in the non-display area.
Display device.
The method of claim 11, wherein
Further comprising a communication module disposed in the non-display area,
The antenna unit is disposed adjacent to the communication module in the non-display area to detect a radio signal generated from the communication module.
Display device.
The method of claim 11, wherein
The timing controller,
A comparison unit for comparing a voltage or frequency of the signal applied to the antenna unit with a predetermined reference value;
A memory unit for storing a table indicating a relationship between an output value of the comparison unit and an adjustment value for a voltage level or an operating frequency of a drive control signal;
And a controller configured to adjust a voltage level or an operating frequency of the driving control signal with reference to the table.
Display device.
The method of claim 15,
The timing controller further includes a signal terminal unit for receiving a signal applied to the antenna unit,
The signal terminal unit and the comparison unit are connected in parallel between the antenna unit and the control unit.
Display device.
The method of claim 15,
The comparison unit
A voltage comparator for comparing the voltage of the signal applied to the antenna unit with a predetermined reference voltage;
A first frequency comparator for comparing a frequency of a signal applied to the antenna unit with a first predetermined reference frequency;
And a second frequency comparator for comparing the frequency of the signal applied to the antenna unit with a second predetermined reference frequency.
Display device.
The method of claim 17,
The antenna unit may include different first and second antenna units,
The voltage comparator is connected to the first antenna unit,
The first and second frequency comparators are connected to the second antenna unit.
Display device.
The method of claim 18,
The first antenna unit is disposed on one side of the non-display area, and the second antenna unit is disposed on the other side of the non-display area.
Display device.

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