KR20200002122A - Databus circuit for eeprom - Google Patents

Abstract

The present invention relates to a technology which increases a speed of erasure and program operation with regard to an EEPROM cell array for a micro controller unit (MCU). The present invention provides a data bus circuit of an EEPROM which comprises: an EEPROM cell array (210); a bit line control unit (220) having a bit line switch circuit unit (221) which is divided into 32 parts with regard to the EEPROM cell array (210) and allowing each of the bit line switch circuit units (221) to have 32 bit line switch circuits so as to perform switching operation for selective connections between the bit line and a data line; and a data line sense amplifier unit (230) having a local data line sensing structure having a data line sense amplifier (231) which is divided into 32 parts with regard to the EEPROM cell array (210).

Description

DATABUS CIRCUIT FOR EEPROM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data bus circuit applied to an EPIROM for a micro controller unit (MCU). In particular, the erase and program operations of an Ipyrom cell array may be performed using a dual program voltage. It is about an Ipyrom data bus circuit.

Non-volatile memory having high-speed read operation of 25 MHz or more is required in a micro controller unit (MCU) such as a wireless charger or a USB type-C. It is a built-in nonvolatile memory of 1Mb or less for MCU that functions to update information in real time, store security data, or store command codes. It is mainly referred to as EEPROM Intellectual Property (hereinafter referred to as 'IIPROM'). Is used).

Key features of the 512 Kb Y pyrom designed using 0.13 ㎛ BCD process are shown in Table 1 below. As a pyromium cell, a split gate pyromium cell is mainly used. In this column, the control gate (CG) and the select gate (SG) are routed in the row direction and the bit line and source line in the column direction. (SL: Source Line) is routed. The power supply voltage (VDD) used in this pyrom cell has a wide range of 2.2V to 5.5V. The operating mode of this pyrom cell includes read, page erase, page buffer load, and page program modes in normal mode, and erase-verify in verify mode. There is a -read mode and a program-verify-read mode. This pyrom cell array may consist of 512 rows x 1,024 columns, and the page buffer may consist of 1 Kb. In this case, page erase and page program are performed in units of 1Kb, whereas page buffer load and read operations are performed in units of 32 bits because I / O is 32 bits.

FIG. 1 is a block diagram of a data bus circuit of a Y. pyrom according to the related art. As shown in FIG. 1, a Y. pyrom cell array 110, a switch unit 120, a data bus sensing circuit unit 130, and an output buffer unit ( 140).

The data bus sensing circuit unit 130 includes eight data bus sense amplifiers divided into eight Y pyrom cell arrays 110, and each of the data bus sense amplifiers includes sixteen I pyrom sensing circuits.

In response to the data bus sensing circuit unit 130 having such a structure, a switch unit 120 is provided between the EPROM cell array 110 and the data bus sensing circuit unit 130. The switch unit 120 includes eight read data switch units, and each of the read data switch units includes 128 read data switches.

In response to the data bus sensing circuit unit 130, an output buffer unit 140 having an output buffer divided into eight between the data bus sensing circuit unit 130 and the data output terminals DOUT [15: 0] is provided. do.

The parasitic capacitor component present in the data bus DB affects the operating speed of the data bus sensing circuit unit 130. This is mainly due to the interconnect capacitance of the DB and the junction capacitance of the transistor of the BL switch circuit. capacitance) and gate overlap capacitance component.

Therefore, in order to improve the operation speed of the EPROM cell array, it is necessary to reduce the capacitance of the parasitic capacitor present in the data bus to the maximum.

The problem to be solved by the present invention is to transfer the voltage of the bit line to the data line by applying a local parasitic local data line sensing method instead of a distributed parasitic data bus sensing method of the parasitic capacitance of the data bus To save time.

Another object of the present invention is to provide a bit line switch circuit for quickly turning on a switch in a read mode.

Another object of the present invention is to shorten the access time by using a data line clamping circuit in a data bus sense amplifier circuit.

According to an embodiment of the present invention for achieving the above technical problem, a data bus circuit of an Y-pyrom includes: a Y-pyrom cell array: a bit line switch circuit portion divided into 32 for the Y-pyrom cell array, and the bit line switch circuit portion. Each of the bit line control circuit including a 32 bit line switch circuit for performing a switching operation for the selective connection between the bit line and the data line; And a data line sense amplifier divided into 32 parts of the EP-ROM cell array.

The present invention reduces the time to transfer the voltage of the bit line to the data line by applying a local parasitic capacitance data line sensing scheme instead of the large parasitic capacitance data bus sensing scheme of parasitic data bus of the Ipyrom cell. This has the effect of omitting the masks associated with.

According to the present invention, when the bit line switch circuit enters the read mode after turning on the write mode NMOS transistor using the bit line switch disable inversion signal in the standby state, the bit line switch circuit uses the bit line switch selection signal. By turning on the MOS transistor, the operation speed of this transistor is improved.

The present invention can reduce the access time by using the data line clamping circuit instead of precharging the bit line node voltage to VDD-VT.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a data bus circuit of Ipyrom according to the prior art.
Fig. 2 is a block diagram of a data bus circuit of Y. pyrom according to the present invention.
3 is a bit line switch circuit diagram according to the present invention;
4 is a detailed circuit diagram of a disable inversion signal output unit according to the present invention;
5 is a detailed circuit diagram of a selection signal output unit according to the present invention;
6 is a detailed circuit diagram of a data line sense amplifier according to the present invention.
FIG. 7 is a waveform diagram illustrating the results of successive simulations of the erased pyromium cell and the programmed two-pyromium cell in read mode. FIG.
8 and 9 are waveform diagrams showing simulation results of a page erase mode and a program mode according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a data bus circuit of a Y pyrom according to the present invention, and as shown therein, includes a Y pyrom cell array 210, a bit line controller 220, and a data line sense amplifier 230.

The configuration of the Y pyrom cell array 210 is not particularly limited, and the present embodiment will be described with an example consisting of 512 rows x 1,024 columns.

The bit line control unit 220 includes 32 bit line switch circuit units 221 divided into one EPROM cell array 210, and each of the 32 bit line switch circuit units 221 has 32 bit line switches. A circuit is provided. The bit line switch circuit performs a switching operation for selective connection between the bit line BL and the data line DL.

3 is a circuit diagram of one of the 32 bit line switch circuits, the disable inversion signal output unit 310, the bit line connection control unit 320, the selection signal output unit 330, and the selection and clamping unit as shown in FIG. 340 is provided.

The disable inversion signal output unit 310 outputs the bit line switch disable inversion signal BLSW_DISb according to the pump enable signal PUMPEN. The disable inversion signal output unit 310 outputs the bit line switch disable inversion signal BLSW_DISb at 0 V in the program mode, at the 7.7.2 V in the erase mode, and at 3.3 V in the read mode. Output The disable inversion signal output unit 310 performs the erase and program operations on the cells of the Epyrom cell array 210 using the dual program voltage (± 7.25V). Accordingly, -7.25 V is supplied to the bit line BL in the program mode, and 7.25 V is supplied to the bit line BL in the erase mode.

The bit line connection controller 320 includes an NMOS transistor (N-channel MOS transistor) MN1. The NMOS transistor MN1 is turned on or off by the bit line switch disable inversion signal BLSW_DISb. The NMOS transistor MN1 connects the bit line BL to the first node N1 when turned on, and electrically disconnects the bit line BL and the first node N1 when turned off. Do it. In the read mode, since the bit line switch disable inversion signal BLSW_DISb is supplied high (eg, 3.3V), the NMOS transistor MN1 remains on.

In the read mode and the erase mode, the circuit shown in FIG. 4 is used to control the connection operation of the bit line supplied with the voltage through the 5V NMOS transistor MN1. That is, FIG. 4 is a detailed circuit diagram illustrating an implementation of the disable inversion signal output unit 310. As shown in FIG. 4, the first to third amplifiers 311 differentially amplify the pump enable signal PUMPEN in three stages. And an inverting amplifying unit 314 for inverting the output signals of the 312 and 313 and the third amplifying unit 313 to output the bit line switch disable inversion signal BLSW_DISb. The first amplifier 311 includes differentially coupled PMOS transistors (MOS transistors in the P-channel) MP11 and MP12 and NMOS transistors MN11 and MN12 having one terminal (drain) and a gate cross-coupled with each other. The pump enable signal PUMPEN is amplified by the low power supply voltage VLV.

The second amplifier 312 includes PMOS transistors MP13 and MP14 having one terminal (source) and a gate cross-coupled with each other and NMOS transistors MN13 and MN14 that are differentially coupled to each other to provide a high power supply voltage BLSW_HV. By amplifying the output signal of the first amplifier 311.

The third amplifier 313 includes differentially coupled PMOS transistors MP15 and MP16 and NMOS transistors MN15 and MN16 having one terminal (drain) and a gate cross-coupled with each other to form the high power supply voltage BLSW_HV. ) Amplifies the output signal of the second amplifier 312.

The first inverting amplifier 314 includes a PMOS transistor MP17 and an NMOS transistor MN17 connected in series between the high power supply voltage BLSW_HV and the ground voltage VSS. The output signal of 313 is inverted and output as the bit line switch disable inversion signal BLSW_DISb. The ground voltage VSS is connected (shared) to an area of the deep nwell DNW.

The selection signal output unit 330 outputs the bit line switch selection signal BLSW_SEL according to the first and second read control signals.

The selection and clamping unit 340 includes NMOS transistors MN2 and MN3. The NMOS transistor MN2 connects the first node N1 to the data line DL when turned on by the bit line switch selection signal BLSW_SEL. The NMOS transistor MN3 clamps the signal of the first node N1 according to the bit line switch clamp signal BLSW_CLAMP supplied from the outside.

FIG. 5 is a detailed circuit diagram illustrating an implementation of the selection signal output unit 330 and includes a NAND gate ND21, a differential amplifier 331, and an inverted amplifier 332 as shown in FIG. The NAND gate ND21 performs a NAND operation on the first and second read control signals YPRE1_RD and YPRE2_RD supplied from the outside.

The differential amplifier 331 includes PMOS transistors MP21 and MP22 having the other terminal (drain) and the gate cross-coupled with each other, differentially coupled NMOS transistors MN21 and MN22, and an output terminal of the NAND gate ND21 and the N An inverter I21 connected between the gates of the MOS transistor MN22 is provided to amplify the output signal of the NAND gate ND21.

The inverting amplifier stage 332 includes a PMOS transistor MP23 and an NMOS transistor MN23 connected in series between the power supply voltage VDD and the ground voltage VSS to invert the output signal of the differential amplifier 331. The bit line switch selection signal BLSW_SEL is outputted.

As described above, the bit line switch circuit provided in the bit line switch circuit unit 221 performs the switching operation for the selective connection between the bit line BL and the data line DL, and thus, the bit line switch circuit in the standby state. When the enable reverse signal BLSW_DISb is supplied with a DC voltage of 3.3 V to turn on the write mode NMOS transistor MN1 and enter the read mode, the bit line switch select signal BLSW_SEL is used as the read mode NMOS transistor ( By turning on the MN2, the operation speed of the read mode NMOS transistor MN2 is increased.

The data line sense amplifier unit 230 includes 32 data line sense amplifiers 231 divided into one EPROM cell array 210. That is, the data line sensing circuit unit 230 has a local data line sensing structure including one sense amplifier S / A for each of 32 columns of data lines DL. Therefore, compared to the distributed data bus structure of FIG. 1, the capacitance of the parasitic capacitors parasitic at the data bus node may be reduced to about 1/4.

In a typical data line sense amplifier, since the data line DL is precharged to the VDD-VT voltage, it takes a long time to discharge to 0V when the erased cell is read. In view of this, the data line sense amplifiers 231 of the data line sense amplifier unit 230 according to the present invention use the data line clamping circuit instead of precharging the data line DL to the VDD-VT voltage. Clamp to a predetermined voltage (e.g. 0.6V). As a result, in the read mode, the access time was 34.2ns, which is shorter than the reference time limit of 40ns.

FIG. 6 is a detailed circuit diagram illustrating an implementation of the data line sense amplifier. As shown in FIG. 6, the data line clamping circuit 610, the data line pull-up unit 620, the differential sense amplifier 630, and the latch unit 640 are illustrated. It is provided.

The data line clamping circuit 610 clamps the voltage of the data line DL to a predetermined voltage (for example, 0.6V). To this end, the data line clamping circuit 610 includes a NOR gate NOR60 and an NMOS transistor MN60.

The NOR gate NOR60 performs a NO operation on the voltage of the data line DL and the data line clamp inversion signal DL_CLAMPb supplied from the outside. The NMOS transistor MN60 clamps the voltage of the data line DL to a predetermined voltage (for example, 0.6V) according to the output signal of the NOR gate NOR60.

The data line pull-up unit 620 pulls up the data line DL to the low power supply voltage VLV in the read mode. To this end, the data line pull-up unit 620 includes a PMOS transistor MP60.

The PMOS transistor MP60 is turned on by the data line clamp inversion signal DL_CLAMPb in a read mode to pull up the data line DL to the low power supply voltage VLV.

The differential sense amplifier 630 amplifies the difference voltage between the voltage of the data line DL and the reference voltage VREF.

To this end, the differential sense amplifier 630 is a reset node of the PMOS transistor MP61 and the gate to which the sense amplifier enable signal SAEN is applied to a gate connected in parallel between the low power supply voltage VLV and the set node SN. A PMOS transistor MP62 connected to RN; A PMOS transistor MP63 having a gate connected in parallel between the low power supply voltage VLV and the reset node RN connected to the set node SN, and a PMOS transistor to which a sense amplifier enable signal SAEN is applied to the gate. MP64); An NMOS transistor MN61 having one terminal connected to the set node SN and a gate connected to the reset node RN; An NMOS transistor MN62 having one terminal connected to the reset node RN and a gate connected to the set node SN; An NMOS transistor MN63 having one terminal connected to the other terminal of the NMOS transistor MN61 and having a gate connected to the day line DL; An NMOS transistor MN64 having one terminal connected to the other terminal of the NMOS transistor MN62 and a gate connected to a reference voltage VREF; An inverter I60 that inverts and outputs the sense amplifier enable inversion signal SAENb; And an NMOS transistor MN65 having one terminal connected in common to the other terminal of the NMOS transistors MN63 and MN64, the other terminal connected to the ground terminal, and the gate connected to the output terminal of the inverter I60. ).

The differential sense amplifier 630 compares the voltage of the data line DL with the reference voltage VREF while the sense amplifier enable signal SAEN is supplied to the gates of the PMOS transistors MP61 and MP64. Output the differential amplification voltage accordingly. In this case, 'low' is output to the set node SN and 'high' is output to the reset node RN according to the differential amplification result of the sensing voltage and the reference voltage VREF transmitted through the data line DL. 'High' is output to the set node SN and 'low' is output to the reset node RN.

The latch unit 640 latches a signal differentially amplified by the differential sense amplifier 630 and outputs corresponding data to the data output terminal DOUT.

To this end, the latch unit 640 has one terminal connected to the set node SN and the reset node RN, and the other terminal connected to the output terminal of the counter NAND gate, respectively, to form a latch. , (ND61); Inverters I61 and I62 connected in series between the output terminal of the NAND gate ND60 and the data output terminal DOUT, and an inverter connected between the output terminal of the NAND gate ND61 and the state maintaining terminal NC. I63).

Meanwhile, FIG. 7 shows the results of successive simulations of the erased pyromium cells and the programmed two-pyromium cells in the read mode. Here, the simulation conditions were carried out at a temperature of VDD = 2.2V, VLV = 1.35V, SS (slow NMOS slow PMOS) model parameters, 125 ℃. As shown in FIG. 7, the data line DL and the bit line BL are clamped to 0.6V by the data line clamp inversion signal DL_CLAMPb. As the select gate signal SG is activated at 3.3V, the voltages of the data line DL and the read data RD are discharged by the on-current of the Y-pyrom cell in the first read mode cycle. When the data of the EPIROM cell is sufficiently transmitted to the read data RD node, the sense amplifier enable signal SAEN is activated 'high' and the sensing data is output to the data output terminal DOUT. In read mode, the data deletion time and access time of EPROM cells are 35.63ns and 34.51ns, respectively, which both satisfy the 40ns specification.

8 and 9 show simulation results according to the present invention in the page delete mode and the program mode. The cell bias condition of the selected control gate CG, the unselected control gate CG, the selected select gate SG, the unselected select gate SG, and the bit line BL according to the operation mode You can see that it comes out as Simulation conditions were conducted at VDD = 2.2V, VLV = 1.35V, SS (slow NMOS slow PMOS) model parameter, 125 ℃.

Although the preferred embodiment of the present invention has been described in detail above, the scope of the present invention is not limited thereto, and may be implemented in various embodiments based on the basic concept of the present invention defined in the following claims. Such embodiments are also within the scope of the present invention.

210: ypyrom cell array 220: bit line controller
230: data line sense amplifier unit 310: disable inversion signal output unit
311-313: 1-3 amplifier 314: inverted amplifier
320: bit line connection control unit 330: selection signal output unit
331: differential amplifier stage 332: inverted amplifier stage
340: selection and clamping unit

Claims (8)

Ipyrom cell arrays:
32 bit line switch circuit units divided into 32 parts of the EPROM cell array, and each of the bit line switch circuit units includes 32 bit line switch circuits to perform a switching operation for selective connection between a bit line and a data line. A bit line controller; And
And a data line sense amplifier unit having a local data line sensing structure including 32 data line sense amplifiers of the I pyrom cell array.
The circuit of claim 1, wherein the bit line switch circuit comprises:
A disable inversion signal output unit for outputting a bit line switch disable inversion signal according to a pump enable signal;
A bit line connection controller which is turned on by the bit line switch disable inversion signal and connects the bit line to a first node;
A selection signal output unit configured to output a bit line switch selection signal according to the first and second lead control signals; And
And a selection and clamping unit for connecting the first node to the data line by the bit line switch selection signal and clamping the signal of the first node according to the bit line switch clamp signal. Bus circuit.
The display device of claim 2, wherein the disable inversion signal output unit
And performing a erase and program operation on the cells of the Ipyrom cell array by using a dual program voltage.
4. The data bus circuit of claim 3, wherein the dual program voltage is ± 7.25V.
The display device of claim 2, wherein the disable inversion signal output unit
A first and third amplifying units configured to three-step differential amplify the pump enable signal; And
And an inverting amplifier for inverting the output signal of the third amplifier and outputting the inverted signal as the bit line switch disable inversion signal.
The method of claim 2, wherein the selection signal output unit
A NAND gate NAND operation of the first and second lead control signals supplied from the outside;
21 and 22 PMOS transistors having the other terminal and the gate cross-coupled to each other, 21 and 22 NMOS transistors differentially coupled to each other, and a twenty-first inverter connected between an output terminal of the NAND gate and a gate of the 22nd NMOS transistor. A differential amplifier stage for differentially amplifying the output signal of the NAND gate; And
And a twenty-third PMOS transistor and a twenty-third NMOS transistor connected in series between a power supply voltage and a ground voltage, and inverting and outputting the output signal of the differential amplifier stage as the bit line switch selection signal. Ipyrom's data bus circuit.
The method of claim 1, wherein the data line sense amplifier
A data line clamping circuit for clamping the voltage of the data line;
A data line pull-up unit configured to pull up the data line to a low power supply voltage in a read mode;
A differential sense amplifier for amplifying a voltage difference between the voltage of the data line and a reference voltage; And
And a latch unit for latching an output signal of the differential sense amplifier and outputting corresponding data to a data output terminal.
8. The method of claim 7, wherein the data line clamping circuit is
A sixty-nOR gate for performing a NOR operation on the voltage of the data line and the data line clamp inversion signal; And
And a sixty-second NMOS transistor for clamping the voltage of the data line to a predetermined level according to the output signal of the sixty-NOA gate.

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