KR20190131972A - Eye opening measurement circuit calculating difference between sigma levels, receiver including the same, and method for measuring eye opening - Google Patents

Abstract

According to an embodiment of the present invention, a receiver may comprise: a sampler for sampling first voltage levels corresponding to a first logic value of data and second voltage levels corresponding to a second logic value of data based on a sampling clock; an equalizer for receiving and adjusting the first and second voltage levels; a clock and data recovery circuit for restoring the sampling clock based on the first and second voltage levels received from the equalizer; and an eye opening measurement circuit for tracking a first sigma level in units of first steps according to higher voltage levels greater than a first reference voltage level among the first voltage levels, tracking a second sigma level in units of second steps according to lower voltage levels less than a second reference voltage level of the second voltage levels, and calculating the difference between the first and second sigma levels.

Description

EYE OPENING MEASUREMENT CIRCUIT CALCULATING DIFFERENCE BETWEEN SIGMA LEVELS, RECEIVER INCLUDING THE SAME, AND METHOD FOR MEASURING EYE OPENING}

The present invention relates to an eye opening measuring circuit, a receiver comprising the same, and a method for measuring the eye opening, and more particularly, an eye opening measuring circuit for calculating a difference between sigma levels, a receiver comprising the same, and an eye opening. It relates to a method for measuring.

In high speed serial link systems, bits of data may be transmitted serially over a channel. The bandwidth of the channel may be limited due to skin effects, dielectric losses, and the like. To compensate for the limited bandwidth of the channel, each of the transmitter sending data over the channel and the receiver receiving data over the channel may include an equalizer for compensating for channel loss.

An eye diagram of the signal equalized by the equalizer of the transmitter can be identified by probing the output of the transmitter. However, since the eye diagram of the signal equalized by the equalizer of the receiver is processed inside the receiver, it cannot be verified using probing. Therefore, there is a need for a technique that can identify an eye diagram of a signal equalized by an equalizer inside the receiver.

The present invention is to solve the above technical problem, the present invention can provide an eye opening measuring circuit for calculating the difference between the sigma levels, a receiver including the same, and a method for measuring the eye opening.

A receiver according to an embodiment of the present invention is a sampler for sampling first voltage levels corresponding to a first logic value of data and second voltage levels corresponding to a second logic value of data based on a sampling clock. An equalizer for receiving and adjusting first and second voltage levels, a clock and data recovery circuit for restoring the sampling clock based on the first and second voltage levels received from the equalizer, and among the first voltage levels Tracking the first sigma level in units of first steps according to higher voltage levels that are greater than a first reference voltage level, and in units of second steps according to lower voltage levels that are less than a second reference voltage level among the second voltage levels. Eye opening to track a second sigma level and calculate a difference between the first sigma level and the second sigma level. It includes a measurement circuit.

An eye opening measuring circuit and a receiver including the same according to an embodiment of the present invention track sigma levels in steps of units according to voltage levels of a signal and based on converged sigma levels rather than a minimum voltage level and a maximum voltage level. The eye opening of the signal can be measured. According to the embodiment of the present invention, since the height of the eye opening may be prevented from being reduced due to the instantaneous error or noise, the resistance to the instantaneous error or the noise may be improved.

1 is a block diagram illustrating a transceiver according to an embodiment of the present invention.
2 is a block diagram illustrating the receiver of FIG. 1 in more detail.
3 and 4 show eye diagrams of voltage levels input to the eye opening measurement circuit of FIG. 2 in accordance with the NRZ signaling scheme.
FIG. 5 is a flowchart illustratively illustrating how the eye opening measurement circuit of FIG. 2 tracks a minimum sigma level and a maximum sigma level. FIG.
6 and 7 exemplarily show results of measuring heights of an eye opening by the eye opening measuring circuit of FIG. 2 according to the flowchart of FIG. 5.
8 is a flowchart illustrating a method of calculating the height of an eye opening by the eye opening measuring circuit of FIG. 2.
9 is a block diagram illustrating an exemplary eye opening measurement circuit of FIG. 2 based on a PAM-4 signaling scheme.
10 is a block diagram illustrating an example of the eye opening measurement circuit of FIG. 2 based on an NRZ signaling scheme.
FIG. 11 is a block diagram illustrating an electronic device including an SoC to which a receiver is applied and another SoC communicating with the SoC according to an embodiment of the present disclosure.

In the following, embodiments of the present invention will be described clearly and in detail, such that those skilled in the art can easily implement the present invention.

1 is a block diagram illustrating a transceiver according to an embodiment of the present invention. The transceiver 10 may include a transmitter 11 and a receiver 13 in communication with each other over a channel 12. The transmitter 11 may include a serializer SER for converting parallel data into serial data, and the receiver 13 converts serial data transmitted from the transmitter 11 through the channel 12 into parallel data. It may include a parallelizer (DES). The transceiver 10 including a serializer SER and a parallelizer DES may be referred to as a data transmission / reception circuit, a serializer / deserializer (SERDES) circuit, a high speed data transmission system, and the like.

The transmitter 11 may transmit a signal according to data to the receiver 13 through the channel 12. The transmitter 11 may further include an equalizer EQ for compensating for channel loss in addition to the serializer SER. For example, the voltage levels of the signal equalized or adjusted by the equalizer EQ of the transmitter 11 probe the path connecting the output of the transmitter 11 and the input of the channel 12. Can be confirmed.

In an embodiment, the transmitter 11 may transmit a signal by using a non-return-to-zero (NRZ) signaling method or a four-level pulse amplitude modulation (PAM-4) signaling method. In the NRZ signaling scheme, the transmitter 11 may transmit a signal having voltage levels corresponding to the first and second logical values of data (eg, 0b and 1b). In the PAM-4 signaling scheme, the transmitter 11 may transmit a signal having voltage levels corresponding to first to fourth logic values (eg, 00b, 01b, 10b, and 11b) of data. Compared to the NRZ signaling scheme at the same data rate, in the PAM-4 signaling scheme, the bandwidth of the transmitter 11 can be increased by twice but the difference between voltage levels is reduced by three times. can do.

The transmission scheme of the transmitter 11 is not limited to the above examples. For example, according to various transmission schemes of the transmitter 11 such as PAM-8, PAM-16, etc., the voltage levels of the signal output from the transmitter 11 may correspond to four or more logic values. Referring to the signal output from the output terminal of the transmitter 11 of FIG. 1, waveforms in which bits of data transmitted in series are superimposed may resemble an eye shape. In general, the height of the eye opening can be measured to evaluate the transmit / receive performance of the transceiver 10.

The channel 12 may be an electrical path connecting the transmitter 11 and the receiver 13 for communication between the transmitter 11 and the receiver 13. For example, channel 12 may comprise a trace or coaxial cable of a printed circuit board (PCB). The channel 12 may exacerbate the high frequency content of the high speed random data propagating through the channel 12 due to skin effects, dielectric losses, and the like. That is, channel loss may occur in a signal transmitted through the channel 12. In addition, channel 12 can cause impedance discontinuities (mismatches) due to connectors and other physical interfaces between boards and cables. Impedance discontinuity in channel 12 may appear as a notch in the frequency response of channel 12. In addition, each of the bits of data passing through the channel 12 may interfere with the next bit due to channel loss or bandwidth limitation, and a bit error rate (BER) increases as neighboring symbols overlap each other, that is, ISI. (inter symbol interference) may occur.

In FIG. 1, eye diagrams of a signal of data output at the output of transmitter 11 and not through channel 12 are shown. Although not shown, the horizontal axis of the eye diagrams may represent time and the vertical axis of the eye diagrams may represent voltage levels. The height of the eye opening of the NRZ signaling scheme may be H1 and the height of the eye opening of the PAM-4 signaling scheme may be H2 (about one third of H1). Here, the unit of the height of the eye opening may be a voltage level. In FIG. 1, eye diagrams of the signal output at the output of transmitter 11 and passed through channel 12 (ie, received at the input of receiver 13) are further shown. The height of the eye opening of the NRZ signaling scheme may be H1 ′ and the height of the eye opening of the PAM-4 signaling scheme may be H2 ′. The heights of the eye openings can be reduced due to channel loss. For example, H1 may decrease to H1 'and H2 may decrease to H2'.

Receiver 13 may receive a signal of data over channel 12. The receiver 13 may further include an equalizer EQ having characteristics opposite to that of the channel 12 in order to compensate for channel loss in addition to the parallelizer DES. For example, channel 12 may have a characteristic of a frequency response such as a low pass filter and the equalizer EQ of receiver 13 may be of a frequency response such as a high pass filter. Can have characteristics.

Eye diagrams at the output of the transmitter 11 and eye diagrams at the input of the receiver 13 are respectively shown in FIG. 1. As described above, how much the transmitter 11 compensated for channel loss can be confirmed by probing the eye diagram at the output of the transmitter 11. On the other hand, even if the receiver 13 compensates for the channel loss of the received signal, it cannot be confirmed through probing how much the receiver 13 compensated for the channel loss. Therefore, there is a need for a circuit that can determine how much the channel loss has been compensated for by the receiver 13 and that can be implemented inside the receiver 13, i.

2 is a block diagram illustrating the receiver of FIG. 1 in more detail. FIG. 2 will be described with reference to FIG. 1. The receiver 100 includes an analog front end (AFE) 110, a sampler 120, an equalizer 130, a clock and data recovery circuit (CDR, 140), a phase locked loop (PLL, 150), an eye opening measurement circuit 160 ), A decoder 170, and a logic circuit 180.

The analog front end 110 may receive a signal transmitted over the channel 12 and transmit or provide the signal to the sampler 120. For example, the analog front end 110 may be an analog signal processing circuit including at least one amplifier such as a low noise amplifier (LNA), a variable gain amplifier (VGA), and the like, which amplifies a received signal.

The sampler 120 may receive a signal processed by the analog front end 110. The sampler 120 may sample voltage levels of the signal based on the sampling clock SCLK. More specifically, in the NRZ signaling scheme, the sampler 120 corresponds to voltage levels corresponding to a first logical value of data (eg, 0b) and a second logical value of data (eg, 1b). The voltage levels can be sampled. In the PAM-4 signaling scheme, the sampler 120 has voltage levels corresponding to a first logical value (eg, 00b) of data, and a voltage level corresponding to a second logical value (eg, 01b) of data. For example, voltage levels corresponding to a third logic value (eg, 10b) of data and voltage levels corresponding to a fourth logic value (eg, 11b) of data may be sampled. The sampler 120 may provide the equalizer 130 with voltage levels sampled in the form of analog signals or in the form of digital signals. For example, the sampler 120 may include at least one analog-to-digital converter (ADC) for converting a signal received from the analog front end 110 into a digital signal based on the sampling clock SCLK. . As shown in FIG. 2, the number of samplers 120 may be at least one.

The equalizer 130 may receive voltage levels of a signal corresponding to logic values of the data. Equalizer 130 may adjust the received voltage levels to compensate for channel loss. That is, the equalizer 130 may increase the height of the eye opening by removing or suppressing noise, jitter, ISI, etc. due to the channel 12 and compensating for channel loss. For example, the equalizer 130 may include a decision-feedback equalizer (DFE) that is a nonlinear equalizer and a feed-forward equalizer (FFE) that is a linear equalizer.

For example, it is assumed that the unit interval (UI, ie, 1-bit interval) of the signal transmitted through the channel 12 is T. In the impulse response of channel 12, postcursors may occur at times corresponding to integer multiples of T, such as T, 2T, 3T, etc., due to the ISI of channel 12 described above. The DFE of the equalizer 130 may multiply the magnitudes of the postcursors (eg, DFE coefficients) by the voltage levels of the received signal and add the respective multiplication results. The equalizer 130 can then suppress the ISI due to postcursors by subtracting the addition result to the voltage level of the newly received signal. The DFE of equalizer 130 may include as many taps as the number of DFE coefficients and may be referred to as n-tap DFE (n is a natural number). For example, the DFE of the equalizer 130 may include a slicer or flip flop, a multiplier, and an adder for decision.

The FFE of the equalizer 130 may remove precursors and postcursors outside the time range that the DFE can compensate. That is, the FFE may complement the DFE. The FFE of equalizer 130 may delay the received signals, multiply the delayed signals by FFE coefficients, add multiplication results, and provide the addition result to the DFE. Since the FFE of the equalizer 130 is disposed in the receiver 100, the FFE coefficients can be adaptively adjusted based on the signal received over the channel 12. Of course, the DFE coefficients can also be adaptively adjusted similarly to the FFE coefficients. The FFE of equalizer 130 may include as many taps as the number of FFE coefficients and may be referred to as m-tap FFE. m is a natural number and may be the same as or different from n. For example, the FFE of equalizer 130 may include delay cells, multipliers, and adders that delay the signal.

The clock and data recovery circuit 140 may receive voltage levels of the output data DOUT from the equalizer 130. The voltage levels of the output data DOUT may be equalized or adjusted based on the operation of the equalizer 130 described above. Clock and data recovery circuitry 140 may receive clocks with multi-phases provided from phase locked loop 150. The clock and data recovery circuit 140 may generate, adjust, or restore the sampling clock SCLK based on clocks having voltage levels and multi-phases of the output data DOUT. The sampling clock SCLK may also be referred to as a recovery clock. The signal provided from the analog front end 110 may be sampled by the sampler 120 at the rising edge or the falling edge of the sampling clock SCLK.

The clock and data recovery circuit 140 may adjust the sampling point of the sampler 120 by adjusting the phase of the sampling clock SCLK. For example, clock and data recovery circuit 140 mixes clocks with multi-phases provided from phase locked loop 150 based on voltage levels equalized or adjusted by equalizer 130. It may include a phase interpolator.

Phase locked loop 150 may generate clocks with multi-phases and provide clocks to clock and data recovery circuit 140. For example, the phase locked loop 150 may include a phase detector (PD), a loop filter, a voltage controlled oscillator (VCO) or a digitally controlled oscillator (DCO) that compares one of the generated clocks with a reference clock. have. Here, the reference clock may be received from the outside of the receiver 100 or may be generated inside the receiver 100.

The eye opening measuring circuit 160 may measure the height of the eye opening after the equalizer 130 and the clock and data recovery circuit 140 are locked. For example, the coefficients (FFE coefficients or DFE coefficients) of the equalizer 130 after locking may be fixed and the phase of the sampling clock SCLK output from the clock and data recovery circuit 140 after locking. The change may be within a predetermined range. The height of the eye opening measured by the eye opening measurement circuit 160 may be used to determine how the equalizer 130 and the clock and data recovery circuit 140 remove noise, jitter, ISI, etc. and compensate for channel loss. have.

The eye opening measurement circuit 160 may receive voltage levels of the output data DOUT from the equalizer 130. In addition, the eye opening measuring circuit 160 may receive a reference voltage level from the equalizer 130. The reference voltage level may be a center level or an average level of voltage levels corresponding to any one of the logic values of the output data DOUT.

In the NRZ signaling scheme, each of a center level of voltage levels corresponding to the first logic value 0b of the output data DOUT and a center level of voltage levels corresponding to the second logic value 1b of the output data DOUT is It may be a reference voltage level. For example, the reference voltage level, which is the center level of the voltage levels corresponding to the second logic value 1b, may correspond to the magnitude of the main cursor of the impulse response of the channel 12 or the C0 of the equalizer 130. have. The eye opening measuring circuit 160 uses the reference voltage level C0 of the voltage levels provided from the equalizer 130 and corresponding to the second logic value 1b, so as to correspond to the voltage level corresponding to the first logic value 0b. Their reference voltage level (-C0) can be calculated.

In the PAM-4 signaling scheme, the center level of voltage levels corresponding to the first logic value 00b of the output data DOUT, and the center level of voltage levels corresponding to the second logic value 01b of the output data DOUT. , The center level of the voltage levels corresponding to the third logic value 10b of the output data DOUT, and the center level of the voltage levels corresponding to the fourth logic value 11b of the output data DOUT, respectively, are reference voltage levels. Can be. For example, the reference voltage level, which is the center level of the voltage levels corresponding to the third logic value 10b, may correspond to the magnitude of the main cursor of the impulse response of the channel 12 or the C0 of the equalizer 130. have. The eye opening measurement circuit 160 uses the reference voltage level C0 of the voltage levels provided from the equalizer 130 and corresponding to the third logic value 10b, so as to correspond to the voltage level corresponding to the first logic value 00b. Reference voltage level (-3C0), reference voltage level (-C0) of voltage levels corresponding to second logic value (01b), and reference voltage level (3C0) of voltage levels corresponding to fourth logic value (11b). Can be calculated.

Voltage levels corresponding to any one of the logic values of the output data DOUT may be distributed around the reference voltage level. The eye opening measuring circuit 160 according to an embodiment of the present invention does not measure the height of the eye opening based on the minimum and maximum levels of these voltage levels. Instead, the eye opening measurement circuit 160 sets the height of the eye opening based on the minimum sigma level Sigma_Min greater than the minimum level and less than the reference voltage level and the maximum sigma level Sigma_Max less than the maximum level and greater than the reference voltage level. It can be measured. The deviation from the minimum sigma level Sigma_Min from the reference voltage level and the deviation from the maximum sigma level Sigma_Max from the reference voltage level may be the same or different. 3 to 8, a method in which the eye opening measuring circuit 160 calculates the minimum sigma level Sigma_Min, the maximum sigma level Sigma_Max, and the height of the eye opening will be described.

The decoder 170 may receive voltage levels of the output data DOUT provided from the equalizer 130. The decoder 170 may decode voltage levels of the output data DOUT into symbols. Decoder 170 may provide the symbols to logic circuit 180.

Logic circuit 180 may receive and process symbols from decoder 170. For example, the logic circuit 180 may process a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), and a vision processing unit (VPU) to process symbols. unit, and at least one of a neural processing unit (NPU). In addition, the logic circuit 180 may include homogeneous multi-core processors or heterogeneous multi-core processors.

The logic circuit 180 may receive the height of the eye opening from the eye opening measurement circuit 160. The logic circuit 180 may adjust or optimize the equalizer 130 and the clock and data recovery circuit 140 based on the height of the eye opening. For example, the logic circuit 180 supplies tuning information to the equalizer 130 and the clock and data recovery circuit 140 for training the equalizer 130 and the clock and data recovery circuit 140. Can provide. For example, according to tuning information (or one or more signals for tuning), the coefficients of the equalizer 130 (eg, FFE coefficients, DFE coefficients), the coefficients of the clock and data recovery circuit 140. And the like can be changed. If the logic circuit 180 determines that the height of the eye opening is insufficient, the logic circuit 180 may adjust the equalizer 130 and the clock and data recovery circuit 140 to improve the height of the eye opening.

In some embodiments, all or some of the components 110, 120, 130, 140, 150, 160, 170, and 180 of the receiver 100 may include a system on chip (SoC), an application specific integrated circuit (ASIC), It may be implemented in a field programmable gate array (FPGA). In addition, the receiver 100 includes package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), and Die in Waffle Pack. , Die in Wafer Form, chip on board, COB (ceramic dual in-line package), metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline integrated circuit (SOIC), SSOP (shrink) Various packages such as small outline package (TSOP), thin small outline package (TSOP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), and wafer-level processed stack package (WSP) It can be implemented using.

3 and 4 show eye diagrams of voltage levels input to the eye opening measurement circuit of FIG. 2 in accordance with the NRZ signaling scheme. 3 and 4 will be described together and will be described with reference to FIGS. 1 and 2. Although not shown, the horizontal axis of the eye diagrams of FIGS. 3 and 4 may represent time and the vertical axis of the eye diagrams of FIGS. 3 and 4 may represent voltage levels.

Referring to FIGS. 3 and 4, a plurality of voltage levels may be distributed based on the center levels C0 and -C0. It is assumed that the dispersion of the voltage levels of FIG. 3 is less than the distribution of the voltage levels of FIG. 4 and the standard deviation of the voltage levels of FIG. 3 is smaller than the standard deviation of the voltage levels of FIG. 4.

The eye opening measurement circuit 160 may measure the height of the eye opening of the eye diagram of FIG. 3. If the eye opening measurement circuit 160 measures the height of the eye opening based on the minimum and maximum levels of voltage levels, the height of the eye opening may be H3. When the eye opening measuring circuit 160 measures the height of the eye opening based on the above-described minimum sigma level SigmaMin and the maximum sigma level Sigma_Max, the height of the eye opening may be similar to H3. According to the above assumption, since the distribution of the voltage levels of FIG. 3 is smaller than the distribution of the voltage levels of FIG. 4, the difference between the plurality of voltage levels and the minimum level and the difference between the plurality of voltage levels and the maximum level may be small. Thus, in the case of FIG. 3, the eye opening based on the height and minimum sigma level Sigma_Min and the maximum sigma level Sigma_Max measured by the eye opening measuring circuit 160 based on the minimum level and the maximum level. There may be little difference between the heights of the eye openings measured by the measurement circuit 160.

The eye opening measurement circuit 160 may measure the height of the eye opening of the eye diagram of FIG. 4. Unlike the eye diagram of FIG. 3, in the eye diagram of FIG. 4, the difference between the majority and minimum levels of voltage levels and the difference between the majority and maximum levels of voltage levels may be larger than that of FIG. 3 due to instantaneous error or noise. .

If the eye opening measuring circuit 160 measures the height of the eye opening based on the minimum level Level_Min and the maximum level Level_Max of the voltage levels, the height of the eye opening may be H4. When the eye opening measuring circuit 160 measures the height of the eye opening based on the aforementioned minimum sigma level Sigma_Min and the maximum sigma level Sigma_Max, the height of the eye opening may be H5 higher than H4. The logic circuit 180 optimizes for the equalizer 130 and the clock and data recovery circuit 140 based on the height H4 of the eye opening or the height H5 of the eye opening provided from the eye opening measurement circuit 160. Assume that we can perform

Since the height H4 of the eye opening is smaller than the height H5 of the eye opening, the degree of optimization for the equalizer 130 and the clock and data recovery circuit 140 based on the height H4 of the eye opening is determined by the eye opening. It may be greater than the degree of optimization for equalizer 130 and clock and data recovery circuit 140 based on height H5. However, since the height H4 of the eye opening is due to an instantaneous error or noise, the eye opening measuring circuit 160 increases the height of the eye opening based on the minimum level (Level_Min) and the maximum level (Level_Max) of the voltage levels. When measured by H4, the logic circuit 180 excessively optimizes the equalizer 130 and the clock and data recovery circuit 140. That is, the logic circuit 180 can unnecessarily adjust the equalizer 130 and the clock and data recovery circuit 140 and this adjustment is the height of the eye opening formed by a number of voltage levels except the minimum and maximum levels. Can have a negative impact on

In summary, the minimum level Level_Min and the maximum level Level_Max may not represent a plurality of voltage levels, but the minimum sigma level Sigma_Min and the maximum sigma level Sigma_Max may represent a plurality of voltage levels. The eye opening measuring circuit 160 according to an embodiment of the present invention has a minimum of the voltage levels instead of the minimum level (Level_Min) and the maximum level (Level_Max) of the voltage levels in order to have a tolerance against instantaneous error or noise. The height of the eye opening may be measured based on the sigma level Sigma_Min and the maximum sigma level Sigma_Max. Accordingly, the logic circuit 180 may adjust or optimize the equalizer 130 and the clock and data recovery circuit 140 based on the height H5 of the eye opening rather than the height H4 of the eye opening. The logic circuit 180 may not make unnecessary adjustments to the equalizer 130 and the clock and data recovery circuit 140 due to instantaneous errors or noise. Hereinafter, a method in which the eye opening measurement circuit 160 tracks the minimum sigma level Sigma_Min and the maximum sigma level Sigma_Max will be described.

FIG. 5 is a flowchart illustratively illustrating how the eye opening measurement circuit of FIG. 2 tracks a minimum sigma level and a maximum sigma level. FIG. FIG. 5 will be described with reference to FIG. 2.

In operation S110, the eye opening measuring circuit 160 may sequentially receive voltage levels of a signal corresponding to logic values of the output data DOUT sequentially output from the equalizer 130. For the NRZ signaling scheme, the eye opening measurement circuit 160 may receive first voltage levels corresponding to the first logic value 0b and second voltage levels corresponding to the second logic value 1b. For the PAM-4 signaling scheme, the eye opening measurement circuit 160 may include first voltage levels corresponding to the first logic value 00b, second voltage levels corresponding to the second logic value 01b, and third. Third voltage levels corresponding to the logic value 10b and fourth voltage levels corresponding to the fourth logic value 11b may be received.

In operation S120, the eye opening measuring circuit 160 may compare the received voltage level with the reference voltage level. The received voltage level corresponds to the second logic value 1b of the NRZ signaling scheme and the reference voltage level corresponds to the center level C0 or the received voltage level corresponds to the third logic value 10b of the PAM-4 signaling scheme. In this case, the reference voltage level is the center level C0. Of course, the eye opening measurement circuit 160 may compare the received voltage level corresponding to the other logic value with another center level (ie, step S120) and steps S121 to S124, steps S126 to S129 after step S120. , And S130 may be performed.

In an embodiment, the reference voltage level C0 may be calculated by the equalizer 130 and provided from the equalizer 130. The equalizer 130 may accumulate equalized voltage levels while receiving a signal of data before the eye opening measurement circuit 160 starts to operate. The equalizer 130 may calculate the reference voltage level C0 by calculating an average of the accumulated voltage levels. The equalizer 130 may calculate not only the reference voltage level CO but other reference voltage levels in a similar manner. In another embodiment, the eye opening measuring circuit 160 accumulates the voltage levels equalized by the equalizer 130 and calculates an average of the accumulated voltage levels before performing the operation S110 to calculate the reference voltage level C0. Can be calculated The eye opening measuring circuit 160 may further calculate another reference voltage level using the reference voltage level C0. In another embodiment, the reference voltage level C0 may be programmed in the eye opening measuring circuit 160 in advance. Other reference voltage levels may also be programmed into the eye opening measurement circuit 160 in advance.

If the received voltage level is greater than the reference voltage level C0, step S121 may be performed. In operation S121, the received voltage level may be compared with the current maximum sigma level Sigma_Max. Here, the current maximum sigma level Sigma_Max may be a sigma level set according to a previously received voltage level. When the flowchart of FIG. 5 is performed for the first time, the current maximum sigma level Sigma_Max may be any level previously set above the reference voltage level C0.

If the received voltage level is greater than the current maximum sigma level (Sigma_Max), in step S122, the eye opening measuring circuit 160 may increase the current maximum sigma level (Sigma_Max) by a step unit (for example, 1mV). have. If the received voltage level is smaller than the current maximum sigma level Sigma_Max, in operation S123, the eye opening measuring circuit 160 may decrease the current maximum sigma level Sigma_Max by a step unit. By performing the steps S122 and S123 repeatedly, the maximum sigma level Sigma_Max may converge to any level larger than the reference voltage level C0 and smaller than the maximum level of the upper voltage levels. For example, the maximum sigma level Sigma_Max may converge to an average level of higher voltage levels.

In summary, the eye opening measuring circuit 160 may track or calculate the maximum sigma level Sigma_Max in step units according to higher voltage levels greater than the reference voltage level C0. The eye opening measuring circuit 160 may increase or decrease the current maximum sigma level Sigma_Max by a step unit based on a result of comparing the received voltage level with the current maximum sigma level Sigma_Max. Even if a maximum voltage level due to an instantaneous error or noise is received by the eye opening measuring circuit 160, the eye opening measuring circuit 160 may increase the maximum sigma level Sigma_Max by only steps. The maximum sigma level Sigma_Max may represent a plurality of upper voltage levels except the maximum voltage level due to an instantaneous error or noise. Thus, the resistance of the eye opening measurement circuit 160 to instantaneous errors or noise can be improved.

In operation S124, the eye opening measuring circuit 160 may increase the maximum counter value Counter_Max. For example, the eye opening measuring circuit 160 may include a counter that increases the maximum counter value Counter_Max.

If the received voltage level is smaller than the reference voltage level C0, step S126 may be performed. In operation S126, the received voltage level may be compared with the current minimum sigma level Sigma_Min. Here, the current minimum sigma level Sigma_Min may be a sigma level set according to a previously received voltage level. When the flowchart of FIG. 5 is performed for the first time, the current minimum sigma level Sigma_Min may be any level set in advance below the reference voltage level C0.

If the received voltage level is greater than the current minimum sigma level (Sigma_Min), in step S127, the eye opening measuring circuit 160 may increase the current minimum sigma level (Sigma_Min) by a step unit (for example, 1mV). have. If the received voltage level is smaller than the current minimum sigma level Sigma_Min, in operation S128, the eye opening measuring circuit 160 may decrease the current minimum sigma level Sigma_Min by a step unit. By performing the steps S127 and S128 repeatedly, the minimum sigma level Sigma_Min may converge to any level smaller than the reference voltage level C0 and greater than the minimum level of the lower voltage levels. For example, the minimum sigma level Sigma_Min may converge to an average level of lower voltage levels.

In summary, the eye opening measuring circuit 160 may track or calculate the minimum sigma level Sigma_Min in step units according to lower voltage levels lower than the reference voltage level CO. The eye opening measuring circuit 160 may increase or decrease the current minimum sigma level Sigma_Min by steps based on a result of comparing the received voltage level with the minimum sigma level Sigma_Min. Even when a minimum voltage level due to an instantaneous error or noise is received by the eye opening measuring circuit 160, the eye opening measuring circuit 160 may reduce the minimum sigma level Sigma_Min by only steps. The minimum sigma level Sigma_Min may represent a plurality of lower voltage levels except the minimum voltage level due to an instantaneous error or noise. Thus, the resistance of the eye opening measurement circuit 160 to instantaneous errors or noise can be improved.

In an embodiment, the step units of steps S122, S123, S126, and S127 may be the same or different from each other. Step units of steps S122, S123, S126, and S127 may be set by the logic circuit 180 in advance.

In operation S129, the eye opening measuring circuit 160 may increase the minimum counter value Counter_Min. For example, the eye opening measuring circuit 160 may include a counter that increases the minimum counter value Counter_Min.

In operation S130, the eye opening measuring circuit 160 may determine whether the maximum counter value Counter_Max and the minimum counter value Counter_Min are finished. More specifically, the eye opening measuring circuit 160 may determine whether the maximum counter value Counter_Max, which is the output of the counter, has reached the target value, and whether the minimum counter value Counter_Min, which is the output of the counter, has reached the target value. . If the maximum counter value Counter_Max and the minimum counter value Counter_Min are not finished, the eye opening measuring circuit 160 may repeatedly perform the steps S110, S120, S121 to S124, S126 to S129, and S130. For example, the eye opening measurement circuit 160 may include S110, S120, S121 to S124, and S126 such that the maximum sigma level Sigma_Max may represent upper voltage levels and the minimum sigma level Sigma_Min may represent lower voltage levels. Steps S129 to S130 may be repeatedly performed. The target value may be set in advance such that the maximum sigma level Sigma_Max represents the upper voltage levels and the minimum sigma level Sigma_Min represents the lower voltage levels.

6 and 7 exemplarily show results of measuring heights of an eye opening by the eye opening measuring circuit of FIG. 2 according to the flowchart of FIG. 5. 6 and 7 will be described together and will be described with reference to FIGS. 2 and 5. Although not shown, the horizontal axis of the eye diagrams of FIGS. 6 and 7 may represent time and the vertical axis of the eye diagrams of FIGS. 6 and 7 may represent voltage levels.

In FIG. 6, an eye diagram of the PAM-4 signaling scheme is shown. The eye opening measurement circuit 160 may track the first to sixth sigma levels Sigma1 to Sigma6 by repeatedly performing all the steps of FIG. 5. The first sigma level Sigma1 may be a maximum sigma level that represents a plurality of higher voltage levels corresponding to the first logic value 00b and greater than the reference voltage level -3C0. The second sigma level Sigma2 may be a minimum sigma level that represents a plurality of lower voltage levels corresponding to the second logic value 01b and smaller than the reference voltage level -C0. The third sigma level Sigma3 may be a maximum sigma level that represents a plurality of higher voltage levels corresponding to the second logic value 01b and larger than the reference voltage level −C0. The fourth sigma level Sigma4 may be a minimum sigma level corresponding to the third logic value 10b and representing a plurality of lower voltage levels smaller than the reference voltage level C0. The fifth sigma level Sigma5 may be the third. It may be the maximum sigma level that corresponds to the logic value 10b and represents a plurality of higher voltage levels that are greater than the reference voltage level C0. The sixth sigma level Sigma6 may be a minimum sigma level that represents a plurality of lower voltage levels corresponding to the fourth logic value 11b and smaller than the reference voltage level 3C0.

In FIG. 5, the eye opening measuring circuit 160 tracks the fourth sigma level Sigma4 and the fifth sigma level Sigma5. As described above, the eye opening measuring circuit 160 may track other sigma levels Sigma1 to Sigma3 and Sigma6, similarly to the fourth sigma level Sigma4 and the fifth sigma level Sigma5.

In another embodiment, unlike the illustration of FIG. 6, the eye opening measuring circuit 160 may measure the height of the eye opening of the signal based on the NRZ signaling scheme. In this case, the eye opening measuring circuit 160 has a higher voltage level corresponding to the first logic value 0b and larger than the reference voltage level -C0, similarly to the first to sixth sigma levels Sigma1 to Sigma6. It is possible to track the maximum sigma level representative of the majority of these and the minimum sigma level representative of the majority of the lower voltage levels corresponding to the second logic value 1b and smaller than the reference voltage level C0.

The voltage levels near the reference voltage level C0, the fourth sigma level Sigma4, and the fifth sigma level Sigma5 of FIG. 6 are enlarged in FIG. 7. The voltage levels of FIG. 7 may correspond to the third logic value 10b.

Referring to FIG. 7, upper voltage levels greater than the reference voltage level C0 may correspond to about 50% of all voltage levels corresponding to the third logic value 10b. Lower voltage levels less than the reference voltage level C0 may correspond to about 50% of all voltage levels corresponding to the third logic value 10b. Upper voltage levels greater than the maximum sigma level Sigma_Max (the fifth sigma level Sigma5 of FIG. 6) may correspond to about 25% of all voltage levels corresponding to the third logic value 10b. The upper voltage levels smaller than the maximum sigma level Sigma_Max and higher than the reference voltage level C0 may correspond to about 25% of all voltage levels corresponding to the third logic value 10b. That is, the maximum sigma level Sigma_Max may converge to an average of upper voltage levels. Lower voltage levels smaller than the minimum sigma level Sigma_Min (the fourth sigma level Sigma4 of FIG. 6) may correspond to about 25% of all voltage levels corresponding to the third logic value 10b. Lower voltage levels greater than the minimum sigma level Sigma_Min and less than the reference voltage level C0 may correspond to about 25% of all voltage levels corresponding to the third logic value 10b. That is, the minimum sigma level Sigma_Min may converge to an average of lower voltage levels.

Distributions of voltage levels divided based on the maximum sigma level Sigma_Max may be about 25% and about 75%, and the maximum sigma level Sigma_Max may correspond to 0.75 sigma. Similarly, distributions of voltage levels divided by the minimum sigma level Sigma_Min may also be about 25% and about 75% and the minimum sigma level Sigma_Max may correspond to 0.75 sigma.

However, distributions of voltage levels divided based on the maximum sigma level Sigma_Max and distributions of voltage levels divided based on the minimum sigma level Sigma_Min are merely exemplary values. The eye opening measurement circuit 160 may track the maximum sigma level Sigma_Max and the minimum sigma level Sigma_Min different from those shown in FIG. 7. In addition, the eye opening measuring circuit 160 has a maximum sigma such that the deviation between the maximum sigma level Sigma_Max and the reference voltage level C0 and the deviation between the minimum sigma level Sigma_Min and the reference voltage level C0 are the same or different from each other. The level Sigma_Max and the minimum sigma level Sigma_Min can be tracked.

8 is a flowchart illustrating a method of calculating the height of an eye opening by the eye opening measuring circuit of FIG. 2. FIG. 8 will be described with reference to FIGS. 2, 5, and 6.

Operation S140 may be performed after the maximum counter value Counter_Max and the minimum counter value Counter_Min are determined by the eye opening measurement circuit 160 in operation S130 of FIG. 5. In operation S140, the steps of FIG. 5 may be repeatedly performed to calculate the height of the eye opening based on the tracked maximum sigma level Sigma_Max and minimum sigma level Sigma_Min.

For example, referring back to FIG. 6, the eye opening measurement circuit 160 calculates the difference between the first sigma level Sigma1 and the second sigma level Sigma2 to determine the first and second logic values 00b and 01b. The height of the eye opening between) can be calculated by H6. The eye opening measuring circuit 160 calculates the height of the eye opening between the second and third logic values 01b and 10b as H7 by calculating a difference between the third sigma level Sigma3 and the fourth sigma level Sigma4. Can be. The eye opening measuring circuit 160 calculates the height of the eye opening between the third and fourth logic values 10b and 11b as H8 by calculating a difference between the fifth sigma level Sigma5 and the sixth sigma level Sigma6. Can be.

Referring back to FIG. 8, after the heights of the eye openings are calculated by performing steps S140 to S170 repeatedly, the eye opening measuring circuit 160 may calculate an average of the heights of the eye openings. The eye opening measurement circuit 160 may further improve the resistance to instantaneous errors or noise by calculating the average of the heights of the eye openings.

More specifically, in operation S150, the eye opening measuring circuit 160 may accumulate the height of the eye opening measured in operation S140 (that is, the difference between sigma levels). In operation S160, the eye opening measuring circuit 160 may determine whether the period counter value Counter_prd is finished. For example, the eye opening measuring circuit 160 may determine whether the period counter value Counter_prd has reached the target value. The period counter value Counter_prd may indicate the number of repetitions of steps S140 to S170 and the target value may indicate the number of times that the heights of the eye openings should be accumulated in order to calculate an average of the heights of the eye openings. The target value may be a predetermined value. If the period counter value Counter_prd is not finished, in step S170, the eye opening measuring circuit 160 may increase the period counter value Counter_prd. The eye opening measurement circuit 160 may include a counter that increases the period counter value Counter_prd. Of course, step S170 may be performed after step S150. After step S170, the eye opening measuring circuit 160 may measure the height of the new eye opening in step S140, accumulate the height of the new eye opening in step S150, and perform step S160 again. . That is, steps S140 to S170 may be repeatedly performed until the period counter value Counter_prd is finished. In addition, in order to perform the step S140 repeatedly, all the steps of FIG. 5 may also be repeatedly performed.

When the period counter value Counter_prd is finished, in step S180, the eye opening measuring circuit 160 may divide the heights of the eye openings accumulated through the steps S140 to S170 by the period counter value Counter_prd. The eye opening measurement circuit 160 may add all heights of the eye openings generated through the steps S140 to S170, and divide the cumulative result (ie, the addition result) by the periodic counter value Counter_prd.

The eye opening measurement circuit 160 may accumulate heights of the eye opening between the first and second logic values 00b and 01b and calculate an average of the accumulated heights. The eye opening measuring circuit 160 may accumulate heights of the eye opening between the second and third logic values 01b and 10b and calculate an average of the accumulated heights. The eye opening measuring circuit 160 may accumulate heights of the eye opening between the third and fourth logic values 10b and 11b and calculate an average of the accumulated heights. The above example relates to a PAM-4 signaling scheme. In the case of the NRZ signaling scheme, the eye opening measuring circuit 160 may accumulate heights of the eye opening between the first and second logic values 0b and 1b and calculate an average of the accumulated heights in steps S140 to S180. .

In step S190, the eye opening measuring circuit 160 measures the average of the heights of the eye openings between the first and second logic values 00b and 01b, and the eye opening between the second and third logic values 01b and 10b. A minimum average of the heights and the average of the heights of the eye openings between the third and fourth logical values 10b and 11b may be determined. The eye opening measurement circuit 160 may provide the minimum average to the logic circuit 180. Step S190 relates to a PAM-4 signaling scheme. In the case of the NRZ signaling scheme, the eye opening measuring circuit 160 does not perform step S190, and calculates an average of heights of the eye openings between the first and second logic values 0b and 1b calculated in step S180. 180).

9 is a block diagram illustrating an exemplary eye opening measurement circuit of FIG. 2 based on a PAM-4 signaling scheme. 9 will be described with reference to FIGS. 2, 5, 6, and 8. The eye opening measurement circuit 260 may include a multiplexer 261, a PAM-4 demultiplexer 262, a difference calculator 263, an average calculator 264, and a determination circuit 265.

The multiplexer 261 can receive voltage levels of the output data DOUT provided from the equalizer 130. The multiplexer 261 may perform step S110 of FIG. 5. Here, voltage levels of the output data DOUT provided from the equalizer 130 may be provided through at least one channel between the equalizer 130 and the eye opening measuring circuit 260. The multiplexer 261 may multiplex the voltage levels of the output data DOUT according to the first to fourth logic values 00b, 01b, 10b, and 11b of the output data DOUT. That is, the multiplexer 261 provides the PAM-4 demultiplexer 262 with voltage levels corresponding to the first logic value 00b and the PAM-4 demultiplexer 262 with voltage levels corresponding to the second logic value 01b. ) Provide the voltage levels corresponding to the third logic value 10b to the PAM-4 demultiplexer 262, and supply the voltage levels corresponding to the fourth logic value 11b to the PAM-4 demultiplexer 262. Can be provided as

The PAM-4 demultiplexer 262 may demultiplex voltage levels corresponding to the first through fourth logic values 00b, 01b, 10b, and 11b. The PAM-4 demultiplexer 262 may perform the steps S120 to S130 of FIG. 5. For example, PAM-4 demultiplexer 262 may include a comparator that compares the received voltage level with a reference voltage level, a comparator that compares the received voltage level with the current maximum sigma level, and compares the received voltage level with the current minimum sigma level. Comparator, an adder (or subtractor) that increases or decreases the maximum sigma level by a staff unit, and an adder (or subtractor) that increases or decreases the minimum sigma level by a staff unit. The PAM-4 demultiplexer 262 tracks the first to sixth sigma levels Sigma1 to Sigma6 according to steps S120 to S130, and calculates the intermediate result of tracking and the final result of tracking by the first of the difference calculator 263. It may be updated or stored in the sixth registers 263_1 to 263_6.

The difference calculator 263 may include first to sixth registers 263_1 to 263_6 and first to third adders 263_7 to 263_9. As described above, the first to sixth registers 263_1 to 263_6 may store the first to sixth final sigma levels Sigma1 to Sigma6 updated by the PAM-4 demultiplexer 262. Unlike the illustrated in FIG. 9, the first to sixth registers 263_1 to 263_6 may be included in the PAM-4 demultiplexer 262.

The difference calculator 263 may perform step S140 of FIG. 8. The difference calculator 263 may calculate the difference between the maximum sigma level and the minimum sigma level. More specifically, the first adder 263_7 calculates the difference between the first and second sigma levels Sigma1, Sigma2 and the height of the eye opening between the first and second logic values 00b, 01b (Fig. (See H6 in 6). The second adder 263_8 calculates the difference between the third and fourth sigma levels Sigma3 and Sigma4 and the height of the eye opening between the second and third logic values 01b and 10b (see H7 in FIG. 6). Can be calculated. The third adder 263_9 calculates the difference between the fifth and sixth sigma levels Sigma5 and Sigma6 and the height of the eye opening between the third and fourth logic values 10b and 11b (see H8 in FIG. 6). Can be calculated. For example, the first to third adders 263_7 to 263_9 may be subtractors that calculate a difference between sigma levels.

The average calculator 264 may include first to third accumulators 264_1 to 264_3 and first to third dividers 264_4 to 264_6. Each of the first to third accumulators 264_1 to 264_3 may perform step S150 of FIG. 8. The first accumulator 264_1 may accumulate or add heights of the eye opening between the first and second logic values 00b and 01b. The second accumulator 264_2 may accumulate or add heights of the eye opening between the second and third logic values 01b and 10b. The third accumulator 264_3 may accumulate or add heights of the eye opening between the third and fourth logic values 10b and 11b.

Each of the first to third dividers 264_4 to 264_6 may perform step S180. The first divider 264_4 divides the cumulative result of the first accumulator 264_1 by K (the period counter value Counter_prd or the cumulative number of times in FIG. 8), and the eye between the first and second logic values 00b and 01b. A first average A1 of heights of the opening can be calculated. The second divider 264_5 may divide the cumulative result of the second accumulator 264_2 by K and calculate a second average A2 of heights of the eye opening between the second and third logic values 01b and 10b. . The third divider 264_6 may divide the cumulative result of the third accumulator 264_3 by K and calculate a third average A3 of the heights of the eye openings between the third and fourth logic values 10b and 11b. .

The determination circuit 265 may perform step S190 of FIG. 8. The determination circuit 265 may provide the logic circuit 180 with the minimum average among the first to third averages A1 to A3. For example, the determination circuit 265 may include at least one comparator for comparing the first to third averages A1 to A3.

10 is a block diagram illustrating an example of the eye opening measurement circuit of FIG. 2 based on an NRZ signaling scheme. FIG. 10 will be described with reference to FIGS. 2, 5, 8, and 9. The eye opening measurement circuit 360 may include a multiplexer 361, an NRZ demultiplexer 362, a difference calculator 363, and an average calculator 364.

The multiplexer 361 can operate similarly to the multiplexer 261 of FIG. 9. The multiplexer 361 may multiplex the voltage levels of the output data DOUT according to the first and second logic values 0b and 1b of the output data DOUT. The multiplexer 361 may perform step S110 of FIG. 5. The multiplexer 361 may provide the voltage levels corresponding to the first logic value 0b to the NRZ demultiplexer 362 and the voltage levels corresponding to the second logic value 1b to the NRZ demultiplexer 362. .

The NRZ demultiplexer 362 may operate similar to the PAM-4 demultiplexer 262 of FIG. 9. The NRZ demultiplexer 362 may demultiplex the voltage levels corresponding to the first and second logic values 0b, 1b. The NRZ demultiplexer 362 may perform the steps S120 to S130 of FIG. 5. For example, NRZ demultiplexer 362 includes a comparator that compares the received voltage level with a reference voltage level, a comparator that compares the received voltage level with a current maximum sigma level, and a comparator that compares the received voltage level with a current minimum sigma level. , An adder (or subtractor) that increases or decreases the maximum sigma level by a staff unit, and an adder (or subtractor) that increases or decreases the minimum sigma level by a staff unit. The NRZ demultiplexer 362 tracks the first and second sigma levels Sigma1, Sigma2 in accordance with steps S120 through S130, and calculates the intermediate result of tracking and the final result of tracking by the first and the second of the difference calculator 363. It may be updated or stored in the two registers 363_1 and 363_2.

The difference calculator 363 may operate similar to the difference calculator 263 of FIG. 9. The difference calculator 363 may include first and second registers 363_1 and 363_2 and an adder 363_3. As described above, the first and second registers 363_1 and 363_2 may store the first and sixth final sigma levels Sigma1 and Sigma2 updated by the NRZ demultiplexer 362. Unlike the one shown in FIG. 10, the first and second registers 363_1 and 363_2 may be included in the NRZ demultiplexer 362.

The difference calculator 363 may perform step S140 of FIG. 8. The difference calculator 363 may calculate the difference between the maximum sigma level and the minimum sigma level. More specifically, the adder 363_3 may calculate the difference between the first and second sigma levels Sigma1 and Sigma2 and calculate the height of the eye opening between the first and second logic values 0b and 1b. . Adder 363_3 may be a subtractor that calculates the difference between sigma levels.

The average calculator 364 may operate similar to the average calculator 264 of FIG. 9. The average calculator 364 may include an accumulator 364_1 and a divider 364_2. The accumulator 364_1 may perform step S150 of FIG. 8. The accumulator 364_1 may accumulate or add heights of the eye opening between the first and second logical values 0b and 1b. The divider 364_2 may perform step S180. The divider 364_2 divides the cumulative result of the accumulator 364_1 by K (period counter value Counter_prd or the cumulative number in FIG. 8) and the heights of the heights of the eye opening between the first and second logical values 0b and 1b. The average A can be calculated. The eye opening measuring circuit 360 may not include the discriminating circuit 265 of FIG. 9 and may provide the average A of the heights of the eye openings directly to the logic circuit 180.

FIG. 11 is a block diagram illustrating an electronic device including an SoC to which a receiver is applied and another SoC communicating with the SoC according to an embodiment of the present disclosure. The electronic device 1000 may include a first SoC 1100 and a second SoC 1300.

In an embodiment, the first and second SoCs 1100 and 1300 may communicate with each other based on an open system interconnection (OSI) seven-layer structure proposed by an international standard organization. have. For example, each of the first and second SoCs 1100 and 1300 may include an application layer (AL), a presentation layer (PL), a session layer (SL), and a transport layer (TL); transport layer), a network layer (NL), a data link layer (DL), and a physical layer (PHY).

Each of the layers of the first and second SoCs 1100 and 1300 may communicate logically or physically with layers corresponding to each other. Application layer (AL), presentation layer (PL), session layer (SL), transport layer (TL), network layer (NL), data link layer (DL), and physical layer (PHY) of the first SoC 1100. Each of the application layer (AL), presentation layer (PL), session layer (SL), transport layer (TL), network layer (NL), data link layer (DL), and physical layer (2) of the second SoC 1300. PHY) can communicate logically or physically with each.

In an embodiment, the physical layer (PHY) of the first SoC 1100 may include a transmitter 1110. The transmitter 1110 may be implemented in a physical layer (PHY) of the first SoC 1100. The transmitter 1110 may be the transmitter 11 of FIG. 1. The physical layer (PHY) of the second SoC 1300 may include a receiver 1310. The receiver 1310 may be implemented in a physical layer (PHY) of the second SoC 1300. The receiver 1310 may be the receiver 100 of FIG. 2 including the receiver 13 of FIG. 1 or the eye opening measurement circuit 160.

The transmitter 1110 of the first SoC 1100 may transmit a signal to the receiver 1310 of the second SoC 1300 through the channel 1200. Channel 1200 may be channel 12 of FIG. 1. The receiver 1310 may include the eye opening measuring circuit 160 of FIG. 2 and the eye opening measuring circuit 160 of FIG. 2 may measure the height of the eye opening based on the maximum sigma level and the minimum sigma level. .

The above description is specific examples for practicing the present invention. In addition to the embodiments described above, the present invention will include embodiments that can be easily changed or simply changed in design. In addition, the present invention will also include techniques that can be easily modified and carried out using the above-described embodiments.

10: transceiver 11: transmitter
12: channel 13: receiver
100: receiver 110: analog front end
120: sampler 130: equalizer
140: clock and data recovery circuit 150: phase locked loop
160: eye opening measurement circuit 170: decoder
180: logic circuit

Claims (10)

A sampler for sampling first voltage levels corresponding to a first logic value of data and second voltage levels corresponding to a second logic value of the data based on a sampling clock;
An equalizer for receiving and adjusting the first and second voltage levels;
A clock and data recovery circuit for restoring the sampling clock based on the first and second voltage levels received from the equalizer; And
Tracking a first sigma level in units of first steps according to higher voltage levels greater than a first reference voltage level of the first voltage levels, and lower voltage levels less than a second reference voltage level of the second voltage levels. And an eye opening measuring circuit for tracking a second sigma level in units of second steps and calculating a difference between the first sigma level and the second sigma level. The method of claim 1,
The first reference voltage level is a center level of the first voltage levels, and
And the second reference voltage level is a center level of the second voltage levels. The method of claim 1,
The first sigma level converged by the eye opening measurement circuit is greater than the first reference voltage level and less than the maximum level of the upper voltage levels and the second sigma level converged by the eye opening measurement circuit is the first sigma level. A receiver less than two reference voltage levels and greater than a minimum level of the lower voltage levels. The method of claim 3, wherein
The first sigma level converged by the eye opening measurement circuit is an average level of the upper voltage levels and the second sigma level converged by the eye opening measurement circuit is an average level of the lower voltage levels. The method of claim 1,
The eye opening measurement circuit is:
Compare the higher voltage levels with the first sigma level and increase or decrease the first sigma level by the first step unit based on comparison results, and
And comparing the lower voltage levels with the second sigma level and increasing or decreasing the second sigma level by the second step unit based on comparison results. The method of claim 1,
The eye opening measurement circuit is:
Further tracking first sigma levels in units of the first step according to the higher voltage levels,
Further tracking second sigma levels in units of the second step according to the lower voltage levels,
Further calculate differences between the first sigma levels and the second sigma levels, and
A receiver for calculating an average of the differences. The method of claim 6,
And a logic circuit for adjusting the equalizer and the clock and data recovery circuit based on the average. The method of claim 1,
And the eye opening measuring circuit operates after the equalizer and the clock and data recovery circuit are locked to receive the data. Tracking first sigma levels in units of first steps according to higher voltage levels greater than a first reference voltage level among the first voltage levels corresponding to the first logic value of the data, and corresponding to the second logic value of the data. A demultiplexer for tracking second sigma levels in units of second steps according to lower voltage levels smaller than a second reference voltage level among the second voltage levels;
A difference calculator for calculating differences between the first sigma levels and the second sigma levels; And
An eye opening measuring circuit comprising an average calculator for calculating an average of the differences. A method of measuring eye opening of a receiver receiving data through a channel:
Receiving first voltage levels corresponding to a first logic value of the data and second voltage levels corresponding to a second logic value of the data;
Comparing the first voltage levels with a first reference voltage level that is a center level of the first voltage levels and comparing the second voltage levels with a second reference voltage level that is a center level of the second voltage levels;
Compare the first sigma level with higher voltage levels greater than the first reference voltage level to adjust the first sigma level and the second of the second sigma level and the second voltage levels. Adjusting the second sigma level by comparing lower voltage levels that are less than a reference voltage level; And
Calculating a difference between the first sigma level and the second sigma level,
The first sigma level is greater than the first reference voltage level and less than a maximum level of the upper voltage levels and the second sigma level is less than the second reference voltage level and greater than a minimum level of the lower voltage levels. Method for measuring the opening.

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