KR20190131459A - Multi-Channel Communication Method and Multi-Channel Communication Apparatus using the Same - Google Patents

Abstract

According to an embodiment of the present invention, a multi-channel communication apparatus for transmitting data from a transmitting side to a receiving side using a plurality of channels comprises: a transmission side for transmitting a synchronization signal and a data signal; a channel including a synchronization channel for transmitting a synchronization signal and a plurality of data channels for transmitting a data signal; and a reception side for restoring a clock from the synchronization signal, adjusting a phase of a clock to form a plurality of channel-specific sampling clocks, and sampling a data signal with the sampling clocks.

Description

Multi-Channel Communication Method and Multi-Channel Communication Apparatus using the Same}

The present technology relates to a multichannel communication method and a multichannel communication device.

According to the conventional multi-channel communication method, a phase locked loop and / or a clock data recovery unit is arranged on a receiving side for each channel to synchronize the clock with the clock from a signal provided by the transmitting side. Data was formed.

Since the phase locked loop and / or clock data recovery unit consumes a large amount of power and a large area is required to form the phase locked loop and / or clock data recovery unit, the resource consumption is large when forming the phase locked loop and / or clock data recovery unit for each data transmission channel.

The present embodiment is to solve this problem, in the multi-channel communication method and multi-channel communication apparatus using the same, it is possible to reduce the die size (die size) required to form as compared to the prior art, it is possible to drive at low power A multichannel communication method and a multichannel communication apparatus using the same are provided.

In the multi-channel communication apparatus according to the present embodiment, a communication apparatus for transmitting data from a transmitting side to a receiving side using a plurality of channels includes: a transmitting side transmitting a sync signal and a data signal, a sink channel transmitting data and a sync signal A channel comprising a plurality of data channels for transmitting a signal; And a receiving side for recovering a clock from the sink signal, adjusting a phase of the clock to form a plurality of channel-specific sampling clocks, and sampling a data signal with the sampling clocks.

The multi-channel communication method according to the present embodiment includes the steps of: transmitting a sync signal by a transmitting side, receiving a sync signal to form receiving sampling clocks for each channel, and data provided by the transmitting side as a receiving sampling clock; Sample output to include.

According to the present embodiment, since the number of clock data recovery units or phase locked loops is formed to be smaller than the number of channels for transmitting data, and the received sampling clocks of the remaining channels are formed therefrom, it is effective in terms of area (die size effective). In addition, it is possible to more economically implement a multi-channel communication device.

1 is a block diagram showing an outline of a multi-channel communication apparatus according to the present embodiment.
2 is a flowchart showing an outline of a multi-channel communication method according to the present embodiment.
3 is a diagram schematically illustrating a method of forming a reception sampling clock.
4 is a block diagram illustrating an outline of a multi-channel communication apparatus according to another embodiment.

Hereinafter, a multichannel communication method and a multichannel communication apparatus using the same will be described with reference to the accompanying drawings. 1 is a block diagram showing an outline of a multi-channel communication apparatus according to the present embodiment, and FIG. 2 is a flow chart showing an outline of the multi-channel communication method according to the present embodiment. 1 and 2, the multi-channel communication apparatus according to the present embodiment is provided with a transmitting side 10 for transmitting a sync signal (sync) and data, a sync signal (sync) and data, The receiving side 20 forms a reception sampling clock for each channel from the sync signal sync and samples the data and outputs the plurality of channels Ch.s, Ch.a,. .., Ch.n).

In the embodiment illustrated in FIG. 1, the sync signal sync may be a data signal sampled with a transmission sampling clock t_clk. The sync signal sync is transmitted to the receiving side 20 through the sync channel Ch.s, and the receiving side 20 may restore the clock using the sync signal sync. In an embodiment not shown, the sync signal sync may be a transmit sampling clock t_clk. The transmitting side 10 may transmit a clock signal to the receiving side 20, and the receiving side 20 may recover the clock using a phase locked loop (PLL).

The transmitter 10 includes a sync signal transmitter 110 for transmitting a sync signal to the receiver 20, a clock provider 120 for providing a transmission sampling clock, and a data transmitter for transmitting data to the receiver 20. 130.

The clock provider 120 forms a transmission sampling clock t_clk for sampling data to be transmitted and provides the received signal to the sink signal transmitter 110 and the data transmitter 130. In one embodiment, the clock provider 110 may include a phase locked loop.

The data transmitter 130 receives data to be transmitted from an internal circuit (not shown), receives a sampling unit 132 that samples the data with a transmission sampling clock t_clk, and data that is sampled by the sampling unit 132 and receives the data. Transmit buffers TBa, ..., TBn provided to the transmission channel. For example, the transmission buffers TBa,..., TBn receive data, amplify voltage and / or current, and provide the data to the receiving side 20 through a data transmission channel.

The sampling unit 132 receives the transmission sampling clock t_clk provided by the clock provider 110 and samples the data provided by the internal circuit into the transmission sampling clock t_clk. According to the illustrated embodiment, the sampling unit 132 may include a serializer (not shown). The serializer (not shown) receives parallel data from an internal circuit and serializes it. The sampling unit 132 samples the serialized data with the transmission sampling clock t_clk and provides it to the transmission buffer transmission buffers TBa, ..., TBn.

In another embodiment, not shown, the sampling unit 132 receives the serial data from the internal circuit, samples it with the transmission sampling clock t_clk, and provides it to the transmission buffers TBa, ..., TBn. The transmission buffers TBa, ..., TBn output the provided data to the receiving side 20 via the data channels Ch.a, ..., Ch.n.

The sync signal transmitter 110 provides a sync signal sync to the receiver 20 through a sync channel Ch.s. According to the illustrated embodiment, the sync signal transmitter 110 receives the sampler 122 that samples the data with the transmission sampling clock t_clk, and the data sampled by the sampler 122 and provides the sample data to the data transmission channel. Sink transmit buffers (TBs).

In the illustrated embodiment, the sampling unit 122 may include a serializer (not shown). The serialization unit (not shown) receives parallel data from an internal circuit, serializes it, and samples a transmission sampling clock t_clk to form a sync signal sync. In another embodiment, not shown, the data sampling unit 122 receives the serial data from the internal circuit, samples it with the transmission sampling clock t_clk, and provides it to the transmission buffer transmission buffers TBa, ..., TBn. . According to another embodiment, the sync signal transmitter 110 may output the transmit sampling clock t_clk provided by the clock provider 120 as a sync signal to the receiver 20. The sync transmission buffer TBs outputs the provided sync signal to the receiving side 20 through the sync channel Ch.s (S100). For example, the sink transmission buffer TBs receives the sink signal, amplifies the voltage and / or current, and provides the sink signal to the receiving side 20 through the sink channel Ch.

In one embodiment, there may be a case where the transmitting side 10 and the receiving side 20 are driven for the first time, or the clock recovery fails at the receiving side 20. The sync signal transmitter 110 may transmit a pattern in which the clock restorer 210 may restore the clock as a sync signal sync. For example, the pattern capable of restoring the clock may be a mutually predetermined pattern at the transmitting side 10 and the receiving side 20, and may be sampled by the transmission sampling clock t_clk to the receiving side 20. Can be sent. As another example, the pattern capable of restoring the clock may be a transmission sampling clock t_clk.

In another embodiment, when the receiver 20 succeeds in clock recovery, the sink signal transmitter 110 samples the data provided from the internal circuit into the transmission sampling clock t_clk and receives the receiver 20 through the sink channel S. ) Can be sent.

The plurality of channels Ch.s, Ch.a,..., Ch.n receive the sync signal output from the sync buffer TBs and provide the sync signal to the sync receive buffer RBs of the receiver 20. The sink channel Ch.s and the data output from the transmission buffers Tba, ..., Tbn of the transmitting side 10 are received, and the receiving buffers Rba, ..., Rbn of the receiving side 20 are received. Data channels Ch.a, ..., Ch.b).

The receiving side 20 receives the sink signal from the sink channel Ch.s and recovers the clock, and a clock recovery unit 210 and a sampling clock forming unit 220 for adjusting the phase of the restored clock to form a sampling clock. And a data receiver 230 that receives data through the data channels Ch.a,..., Ch. N and samples and outputs the data to a sampling clock.

The clock recovery unit 210 includes a sink reception buffer RBs that receives a sync signal from the sink channel Ch.s, and a clock recovery circuit 212 that restores the clock CLK.

In the embodiment illustrated by FIG. 1, the sink receive buffers RBs receive the sink signal, amplify the voltage and / or current, and provide it to the clock recovery circuit 212. The clock recovery circuit 212 includes a clock data recovery circuit (CDR), and the clock data recovery circuit restores a clock using a sync signal, and samples the data included in the sync signal into a restored clock. Can be provided. In another embodiment, not shown, the clock recovery unit 210 includes a phase locked loop, and the phase locked loop recovers a clock using a sync signal and provides a restored clock CLK. Can be.

The sampling clock forming unit 220 adjusts a phase from the clock CLK restored by the clock recovery unit 210 to form the reception sampling clocks RxCLKa, ..., RxCLKn.

The transmission sampling clock t_clk of the transmitting side 10 and the clock CLK restored by the receiving side 20 may be clock signals formed by the clock provider 120 or clocks recovered from the clock side 120. 10) and phase skew by electrical environmental differences including voltage differences provided to the receiving side 20, process differences forming the transmitting side 10 and the receiving side 20, temperature differences and transmitted path differences. (phase skew) occurs. When the data output by the reception buffers Rba, ..., Rbn are sampled by the restored clock CLK, the transmitted data and the sampled data may not match each other due to phase skew.

The sampling clock forming unit 220 may remove the influence of the phase skew by performing phase adjustment. 3 is an exemplary timing diagram for explaining a phase adjusting process in one data channel. Referring to FIG. 3, the transmitter 10 transmits a training pattern r_ts to the receiver 20 through a data channel on which phase adjustment is to be performed, and transmits a sync signal through the sync channel. The training pattern r_ts is sampled and transmitted with the transmission sampling clock t_clk and has a mutually predetermined sequence between the transmitting side 10 and the receiving side 20.

The clock recovery unit 210 restores the clock CLK from the sync signal and provides the clock CLK to the sampling clock forming unit 220. The sampling clock forming unit 220 forms a preliminary clock pre_clk _a having _a phase phi a from the provided clock and provides it to the data sample unit 232. The data sample unit 232 samples the training pattern r_ts received with the provided preliminary clock pre_clk _a .

As shown in FIG. 3, since the rising edge of the preliminary clock pre_clka where the data sampler 232 performs sampling is within the bit transition period of the pattern r_ts, a result of sampling the pattern r_ts is obtained. There is no guarantee of matching the transmitted training pattern.

The sampling clock forming unit 220 adjusts the phase of the clock clk to form a preliminary clock pre_clk _b having a phi _b phase and provide it to the data sample unit 232. Since the rising edge of the preliminary clock pre_clkb in which the data sample unit 232 performs sampling is located outside the bit transition period of the pattern pattern r_ts, the sampled result and the training pattern r_ts coincide with each other.

The sampling clock forming unit 220 forms preliminary clocks while sequentially changing the phase of the clock clk, and sequentially provides the formed preliminary clock to the data sample unit 232. The data sample unit 232 samples the pattern r_ts using the provided preliminary clock, determines whether the data sample coincides with a predetermined training pattern, and forms a reception sampling clock (S200).

3, the preliminary clock (pre_clk _k) of φ _k the phase, so the rising edge leaves the bit transition period of the pattern (r_ts) position data sample unit 232 may effectively sample the pattern (r_ts) . However, the preliminary clock pre_clk _{k + 1} having a φ _{k + 1} phase cannot effectively sample the pattern r_ts since the rising edge is located within the bit transition period of the pattern r_ts.

In an embodiment, the sampling clock forming unit 220 may have a preliminary clock pre_clk _b having a _b th phase φ _b to effectively sample the pattern, and a preliminary clock pre_clk having a k th phase φ _k . _k ) selects one of the receiver sampling clocks RxCLK and samples the data provided by the receiver.

In another embodiment, the sampling clock forming unit 220 may grasp the phase range of the preliminary clock capable of effectively sampling the pattern, and select the preliminary clock having the center phase of the phase range as the reception sampling clock r_clk. . For example, if the phases of the preliminary clock capable of effectively sampling the pattern are three consecutive first phases φ1, second phases φ2, and third phases φ3, the transmitting side may have a second phase ( The preliminary clock having φ2) can be selected as the reception sampling clock.

As another example, if the phase of the preliminary clock that can effectively sample the pattern is four consecutive first phases φ1, second phases φ2, third phases φ3, and fourth phases φ4, One of the second phase φ2 and the third phase φ3 positioned in the center may be selected to be selected as the reception sampling clock.

In one embodiment, the phase adjustment step may be performed sequentially for each data channel. As an example, the sampling clock forming unit 220 may perform phase adjustment with a data sample unit of one channel and then phase adjust with a data sample unit of another channel.

In another embodiment, the phase adjustment step may be performed together in a plurality of data channels. For example, the sampling clock forming unit 220 provides a preliminary clock having the same phase to the plurality of data sample units. The sampling clock forming unit 220 may select a phase of the sampling clock for each channel by comparing the results sampled for each channel and the training pattern.

4 is a block diagram schematically illustrating another embodiment of the receiving side 20. Referring to FIG. 4, the clock data recovery circuit 212 may form a plurality of clocks having different phases from the sync signal, and may provide them to the respective data sample units 232a,..., 232n. have.

The data sample sections 232a, ..., 232n sample the training pattern with clocks having different phases provided. The data sample sections 232a, ..., 232n and the clock recovery section 210 select a clock having a phase that can effectively sample the training pattern as the reception sampling clock, similarly to the embodiment described above. The sample units 232a,..., 232n may provide a reception sampling clock selected for each channel.

The phase of the sampling clock formed through the above-described process may be changed by conditions such as process, temperature, voltage, and the like, and may be the same or different for each channel. However, the frequencies may be the same.

In the case where the transmitting side 10 is a timing controller in the display and the receiving side 20 is a display driver, the forming of the receiving sampling clocks may be performed in a blank period which is repeated periodically.

Receiving buffers Rba, ..., Rbn are voltages and / or currents of signals transmitted from the transmitting side 10 to the plurality of channels Ch.s, Ch.a, ..., Ch.n. Amplification is provided to the sampling units 232a, ..., 232n. The sampling units 232a,..., 232n may restore the data by sampling the provided data with a sampling clock for each channel (S300).

The prior art has a phase locked loop for forming a transmission sampling clock for each channel for transmitting data and a clock data recovery circuit for recovering the clock from the transmitted data. As the number of channels increased, the die area for forming the phase locked loop and clock data recovery circuitry increased.

However, according to the present embodiment, the transmission sampling clock formed by one clock forming unit is shared for a plurality of channels, and one clock data recovery unit restores the clock and forms the reception sampling clock for each channel. Thus, the advantage is that the die area can be reduced by eliminating the need for forming the phase locked loop and the clock data recovery circuit by the number of channels.

Although described with reference to the embodiments shown in the drawings to aid the understanding of the present invention, this is an embodiment for the implementation, it is merely exemplary, those skilled in the art from various modifications and equivalents therefrom It will be appreciated that other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the appended claims.

10: transmitting side 20: receiving side
TB1, TB2, TBn: transmit buffer RB1, RB2, RB3: receive buffer
Ch.1, Ch.2, Ch.3: Channel CDR: Clock Data Restoration Unit
PA: Phase adjuster PCa, PCn: Sampling section

Claims (18)

A communication device for transmitting data from a transmitting side to a receiving side using a plurality of channels, the communication apparatus comprising:
A transmitting side for transmitting the sink signal and the data signal;
A channel including a sink channel for transmitting the sink signal and a plurality of data channels for transmitting the data signal; And
A phase locked loop (PLL) for recovering a clock from the sync signal; adjusting a phase of the recovered clock to form the plurality of channel-specific sampling clocks; Communication device comprising a receiving side for sampling. The method of claim 1,
The data signal is sampled with the transmit sampling clock;
And the sync signal comprises a data signal sampled with the transmit sampling clock. The method of claim 1,
The data signal is sampled with the transmit sampling clock;
And the sink signal comprises the transmit sampling clock. The method of claim 1,
The transmitting side,
A clock forming unit forming a transmission sampling clock;
And a data transmitter for providing the data signal sampled with the transmission sampling clock to the receiving side. The method of claim 4, wherein
The transmitting side,
And a sync signal transmitter for providing a sync signal, the data sampled by the transmission sampling clock, to the receiving side. The method of claim 4, wherein
The transmitting side,
And a sync signal transmitter for providing a sync signal which is the transmit sampling clock to the receiver. The method according to any one of claims 5 and 6,
The sync signal transmitter further includes a sync buffer amplifying the sync signal and providing the sync signal to the sync channel.
And the data transmitter further comprises a data transmission buffer for amplifying the data signal and providing the data signal to the data channel. The method of claim 1,
The receiving side
A sampling clock forming unit configured to form a reception sampling clock for each data channel from the restored clock;
And a data sample unit configured to sample data received by the reception sampling clock for each channel. The method of claim 1
The receiving side
A clock recovery unit providing a plurality of clocks having different phases recovered from the sync signal;
And a data sample unit configured to sample the received data by using any one selected from the plurality of clocks as a reception sampling clock. The method of claim 8,
The sampling clock forming unit,
And adjust the phase of the recovered clock to form the received sampling clock. The method of claim 9,
And the clock recovery unit selects one of the plurality of clocks and provides the received sampling clock to the data sample unit. A communication method for transmitting data from a transmitting side to a receiving side using a plurality of channels, the communication method comprising:
Transmitting a sync signal by the transmitting side;
Receiving a sync signal by a phase locked loop (PLL) on a receiving side to form reception sampling clocks for each channel; and
Sampling data provided by a transmitting side with the received sampling clock. The method of claim 12,
The data transmitted from the transmitting side to the receiving side is data sampled by the transmitting side with a transmission sampling clock.
The step of transmitting the sync signal,
And transmit the transmission sampling clock to be aquatic. The method of claim 12,
The data transmitted from the transmitting side to the receiving side is data sampled by the transmitting side with a transmission sampling clock.
The step of transmitting the sync signal,
And transmit the sampled data with the transmission sampling clock. The method of claim 12,
The receiving side receiving the sync signal to form reception sampling clocks for each channel may include:
And adjusting the phase of the received sync signal to form the received sampling clocks for each channel. The method of claim 12,
Forming the channel-specific received sampling clocks,
Communication method sequentially performed for each of the plurality of channels. The method of claim 12,
Forming the channel-specific received sampling clocks,
And communicating together for the plurality of channels. The method of claim 12,
The receiving side receiving the sync signal to form reception sampling clocks for each channel may include:
Forming a plurality of clocks having different phases from the received sync signal by the receiving side;
Selecting a clock having a phase from among a plurality of clocks having a different phase.

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