KR20190130954A - Semiconductor package - Google Patents

Abstract

According to the present invention, a semiconductor package includes a substrate; a semiconductor chip mounted on the substrate; a passive element mounted on the substrate; a conductive structure provided on the substrate; and an interposer substrate disposed on the semiconductor chip, the passive element, and the conductive structure and electrically connected to the conductive structure. The height of the passive element may be greater than the height of the semiconductor chip. The electrical properties of the semiconductor package can be improved.

Description

Semiconductor Package {Semiconductor package}

The present invention relates to semiconductor packages, more particularly stacked semiconductor packages comprising an interposer substrate.

The semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. In general, a semiconductor package is generally mounted on a printed circuit board and electrically connected to each other using bonding wires or bumps. Due to the development of the electronics industry, various researches for improving reliability and durability of semiconductor packages have been conducted. High speed, high capacity, and small size of semiconductor packages are becoming more important.

An object of the present invention is to provide a semiconductor package with improved electrical characteristics.

The present invention relates to a semiconductor package. According to the present invention, a semiconductor package includes a semiconductor chip mounted on a substrate; Passive elements; Conductive structures; And an interposer substrate disposed on the semiconductor chip, the passive element, and the conductive structure, and electrically connected to the conductive structure, wherein the height of the passive element may be greater than the height of the semiconductor chip.

According to the present invention, a semiconductor package includes a semiconductor chip and a passive element mounted on an upper surface of a substrate; Interposer substrates on semiconductor chips and passive devices; Conductive structures of substrate and interposer substrate; A bottom solder connection between the substrate and the conductive structure; And an upper solder connection interposed between the conductive structure and the interposer substrate.

According to the present invention, a semiconductor package includes a substrate; A semiconductor chip and a passive element mounted on an upper surface of the substrate; A conductive structure on the substrate; An interposer substrate disposed on the semiconductor chip, the passive element, and the conductive structure; And a lower solder connection portion provided between the substrate and the conductive structure to connect with the substrate and the conductive structure, wherein the upper surface of the passive element may be disposed at a level higher than that of the semiconductor chip.

According to the present invention, conductive structures are provided between the lower substrate and the interposer substrate so that the distance between the lower substrate and the interposer substrate can be large enough to provide a passive element. Accordingly, the passive element can be mounted on the lower substrate. The electrical path between the passive element and the semiconductor chip can be shortened. The conductive structures have a fine pitch, so that the semiconductor package can be miniaturized.

1A is a plan view illustrating a lower semiconductor package according to example embodiments.
FIG. 1B is a cross-sectional view taken along the line II ′ of FIG. 1A.
FIG. 1C is an enlarged view of region A of FIG. 1B.
2A is a plan view illustrating a lower semiconductor package according to example embodiments.
FIG. 2B corresponds to an enlarged view of region A ′ of FIG. 2A.
3 is a diagram for describing a semiconductor package according to example embodiments.
4A is a plan view illustrating a semiconductor package according to example embodiments.
4B is a cross-sectional view taken along the line II ′ of FIG. 4A.
5A is a plan view illustrating a lower semiconductor package according to example embodiments.
FIG. 5B is a cross-sectional view taken along the line II-II ′ of FIG. 5A.
FIG. 5C is a cross-sectional view taken along line III-III ′ of FIG. 5A.
6A is a plan view illustrating a semiconductor package according to example embodiments.
FIG. 6B is a cross-sectional view taken along the line II-II ′ of FIG. 6A.
FIG. 6C is a cross-sectional view taken along line III-III ′ of FIG. 6A.
7A to 7C are diagrams for describing a method of manufacturing a lower semiconductor package according to embodiments.
8A is a plan view illustrating a lower semiconductor package according to example embodiments.
8B and 8C are diagrams for describing a method of manufacturing a lower semiconductor package according to embodiments.
9A is a plan view illustrating a lower semiconductor package according to example embodiments.
9B and 9C are diagrams for describing a method of manufacturing a lower semiconductor package according to embodiments.
10A is a diagram for describing a semiconductor module according to example embodiments.
10B is a diagram for describing a semiconductor module according to example embodiments.
10C and 10D are diagrams for describing a semiconductor module according to example embodiments.
11A is a plan view illustrating a first lower semiconductor package in accordance with embodiments.
FIG. 11B is a cross-sectional view taken along line IV-IV ′ of FIG. 11A.
11C is a plan view illustrating a first semiconductor package according to example embodiments.
FIG. 11D is a cross-sectional view taken along the line IV-IV ′ of FIG. 11C.
12A is a plan view illustrating a second semiconductor package according to example embodiments.
12B is a cross-sectional view taken along the line VV ′ of FIG. 12A.
13A is a plan view illustrating a semiconductor module according to example embodiments.
FIG. 13B is a cross-sectional view taken along the line VI-VI ′ of FIG. 13A.

In this specification, like reference numerals may refer to like elements throughout. Hereinafter, a semiconductor package, a method of manufacturing a semiconductor package, and a semiconductor module according to the inventive concept will be described.

1A is a plan view illustrating a lower semiconductor package according to example embodiments. FIG. 1B is a cross-sectional view taken along the line II ′ of FIG. 1A. FIG. 1C is an enlarged view of region A of FIG. 1B.

1A, 1B, and 1C, the lower semiconductor package 10 may include a lower substrate 100, semiconductor chips 110 and 120, a passive element 310, a conductive structure 400, and an interposer substrate. 600 may be included. The lower substrate 100 may have a first side surface 100a and a second side surface 100b facing each other. The lower substrate 100 may have a first region R1 and a second region R2 in plan view. The first region R1 of the lower substrate 100 may be closer to the first side surface 100a than the second region R2. For example, a printed circuit board (PCB) having a circuit pattern may be used as the lower substrate 100. The lower substrate 100 may include a substrate pad 110 and a wiring 155. The substrate pads 110 may be exposed on the upper surface 100u of the lower substrate 100. The wiring 155 is provided in the lower substrate 100 and may be connected to the substrate pads 110. The solid line in the lower substrate 100 schematically shows the wiring 155 in the lower substrate 100. The external terminals 150 may be provided on the bottom surface of the lower substrate 100. The external terminals 150 may include at least one of solder balls, bumps, and pillars. The external terminals 150 may include metal, for example. The external terminals 150 may be connected to the substrate pads 110 through the wiring 155.

The semiconductor chips 110 and 120 may be mounted on the upper surface 100u of the lower substrate 100. The semiconductor chips 110 and 120 may include a first semiconductor chip 210 and a second semiconductor chip 220. The first semiconductor chip 210 may be provided on the upper surface 100u of the first region R1 of the lower substrate 100. The first semiconductor chip 210 may include integrated circuits having different functions therein. The first semiconductor chip 210 may include logic circuits and a memory circuit. The first semiconductor chip 210 may include a logic chip that calculates and processes data. For example, the first semiconductor chip 210 may be any one of a system on chip (SOC), a modem chip, a ModAP chip, an application processor (AP) chip, and a communication processor (CP) chip. have. The first connector 251 may be interposed between the substrate pad 110 and the first semiconductor chip 210. The first semiconductor chip 210 may be electrically connected to the lower substrate 100 through the first connector 251. In this specification, the electrical connection with the substrate may mean that the electrical connection with the wiring in the substrate. Electrically connected to the semiconductor chip may mean that the semiconductor chip is electrically connected to the integrated circuits of the semiconductor chip through the chip pad of the semiconductor chip. The first connector 251 may include solder balls, pillars, bumps, or ball grid arrays. The height H1 of the lower semiconductor package 10 may be defined as including the height of the first connector 251. In the present specification, the height of a component may mean a maximum distance of the component measured in a direction perpendicular to the upper surface 100u of the lower substrate 100.

The second semiconductor chip 220 may be provided on the top surface 100u of the second region R2 of the lower substrate 100. The second semiconductor chip 220 may be spaced apart from the first semiconductor chip 210. The second semiconductor chip 220 may be a kind of semiconductor chip different from the first semiconductor chip 210. The second semiconductor chip 220 functions differently from the first semiconductor chip 210 and may have a different size. For example, the second semiconductor chip 220 may include a power management integrated circuit (PMIC) therein to function as a power management chip. The second connector 252 may be interposed between the lower substrate 100 and the second semiconductor chip 220. The second connector 252 may include solder balls, pillars, bumps, or ball grid arrays. The second semiconductor chip 220 may be electrically connected to the lower substrate 100 through the second connector 252. The height H2 of the mounted second semiconductor chip 220 may be defined as including the height of the second connector 252.

The passive element 310 may be mounted on the upper surface 100u of the lower substrate 100. The passive element 310 may be spaced apart from the first semiconductor chip 210 and the second semiconductor chip 220 in a plan view. The passive element 310 may include any one of an inductor, a resistor, and a capacitor. The first connection terminal 351 may be provided between the lower substrate 100 and the passive element 310 to be any one of the substrate pads 110. The first connection terminal 351 may include solder or bumps. The first connection terminal 351 may include a conductive material such as metal. The passive element 310 may be connected to the lower substrate 100 through the first connection terminal 351.

The passive element 310 may include a plurality of passive elements 310 spaced apart from each other. The passive elements 310 may be homogeneous or heterogeneous. When the passive elements 310 include heterogeneous passive elements 310, one of the passive elements 310 includes an inductor and the other of the passive elements 310 includes a capacitor. can do.

At least one height H3 of the mounted passive devices 310 may be greater than the height H1 of the mounted first semiconductor chip 210 and the height H2 of the second semiconductor chip 220. In this case, the height H3 of the mounted passive elements 310 may be defined as including the height of the first connection terminal 351. At least one of the upper surfaces 310a of the passive elements 310 may be provided at a level higher than the upper surface 210a of the first semiconductor chip 210 and the upper surface 220a of the second semiconductor chip 220. . The planar arrangement, shape, and number of passive elements 310 are not limited to those shown and may be variously modified.

An interposer substrate 600 may be provided on the first semiconductor chip 210, the second semiconductor chip 220, the passive devices 310, and the conductive structure 400. The lower surface of the interposer substrate 600 may face the first semiconductor chip 210, the second semiconductor chip 220, and the passive devices 310. The interposer substrate 600 may include an insulating layer 610, a lower pad 621, a conductive pattern 623, and an upper pad 622. The insulating layer 610 may include a plurality of insulating layers 610 as shown in FIG. 1C. 1C and 2B, a single insulating layer 610 is illustrated for simplicity, but the present invention is not limited thereto. The lower pad 621 may be exposed on the bottom surface of the interposer substrate 600. The conductive pattern 623 may include a wiring portion and a via portion. The wiring portion may be provided between the insulating layers 610. The via portion may penetrate at least one of the insulating layers 610. The upper pad 622 may be exposed on the top surface 600u of the interposer substrate 600. The upper pad 622 may be connected to the lower pad 621 through the conductive pattern 623. Accordingly, the arrangement of the upper pads 622 may be more free. For example, the upper pad 622 may not be aligned in a vertical direction with the lower pad 621, the conductive structure 400, and the substrate pad 110 that are electrically connected. The vertical direction may mean a direction perpendicular to the upper surface 100u of the lower substrate 100. The upper pad 622 may function as a terminal for connecting with another package or device. In this specification, the electrical connection with the interposer substrate 600 may refer to the electrical connection with the upper pad 622 of the interposer substrate 600. The upper pad 622 may include a signal pad 622A and a power pad 622B electrically separated from each other as shown in FIG. 1B.

The conductive structure 400 may be interposed between the lower substrate 100 and the interposer substrate 600. The lower solder connection part 451 may be provided between the lower substrate 100 and the lower surface of the conductive structure 400 to connect to the substrate pad 110 and the conductive structure 400. The conductive structure 400 may be electrically connected to the lower substrate 100 through the lower solder connector 451. The lower solder connection 451 may include a solder material. The solder material may include tin, silver, and / or bismuth. The lower solder joint 451 may include a material different from that of the conductive structure 400. For example, the conductive structure 400 may include at least one selected from a metal, for example, copper, aluminum, gold, lead, stainless steel, iron, and alloys thereof. The conductive structure 400 may have a higher melting point than the lower solder connection 451. The height H of the conductive structure 400 may be greater than the thickness of the lower solder joint 451.

An upper solder connection part 452 may be interposed between the upper surface 400a of the conductive structure 400 and the interposer substrate 600 to connect to the conductive structure 400 and the lower pad 621. The interposer substrate 600 may be electrically connected to the lower substrate 100 through the conductive structure 400. The upper solder connection 452 may include a solder material. The conductive structure 400 may include a material different from the upper solder connector 452. The conductive structure 400 may have a higher melting point than the upper solder connection 452. The height H of the conductive structure 400 may be greater than the thickness of the upper solder joint 452.

When the interposer substrate 600 and the lower substrate 100 are connected by a single solder ball or directly bonded solder balls, the solder balls or bonded solder balls may have a relatively low height. In this case, the distance between the lower substrate 100 and the interposer substrate 600 is small, so that the passive element 310 may be difficult to be provided on the upper surface 100u of the lower substrate 100. For example, the passive element 310 may be provided outside the lower semiconductor package 10. In this case, the length of the electrical passage connected to the passive element 310 may be increased. If the solder balls or bonded solder balls are formed to have a large height, the diameter and pitch of the solder balls or bonded solder balls may increase.

According to embodiments, each of the conductive structures 400 may be a pin or a metal pillar. The conductive structure 400 may have a columnar shape such as a cylinder or a polygonal column. The conductive structure 400 may be relatively uniform and have a small diameter. The diameter at the bottom of each conductive structure 400 may be substantially equal to the diameter at the top of the conductive structure 400 and the diameter at the middle portion of the conductive structure 400. The pitch P of the conductive structures 400 may be small. The pitch P of the conductive structures 400 may be approximately 0.01 mm to 0.5 mm. Accordingly, the lower semiconductor package 10 may be miniaturized.

Since a fin or metal pillar is used as the conductive structures 400, each of the conductive structures 400 may have a relatively large height H. For example, the height H of the conductive structure 400 may be equal to or greater than the height H3 of the passive elements 310. The height H of the conductive structure 400 may be greater than the height H1 of the first semiconductor chip 210 and the height H2 of the second semiconductor chip 220. In this case, the height H of the conductive structure 400 may be defined as the distance between the upper surface 400a and the lower surface of the conductive structure 400. The top surface 400a of the conductive structure 400 may be provided at the same level or higher than the top surfaces 310a of the passive elements 310. The upper surface 400a of the conductive structure 400 may be provided at a level higher than the upper surface 210a of the first semiconductor chip 210 and the upper surface 220a of the second semiconductor chip 220. Accordingly, the distance D between the lower substrate 100 and the interposer substrate 600 may increase. The spacing D between the lower substrate 100 and the interposer substrate 600 may be large enough that the passive elements 310 are provided between the lower substrate 100 and the interposer substrate 600. The passive elements 310 may be electrically connected to at least one of the first semiconductor chip 210 and the second semiconductor chip 220 through the lower substrate 100. The passive elements 310 may be electrically connected to the interposer substrate 600 through the lower substrate 100 and the conductive structures 400. As the passive element 310 is provided on the upper surface 100u of the lower substrate 100, the passive element 310 and the first semiconductor chip 210, the passive element 310 and the second semiconductor chip 220, And the length of the electrical passage between the passive element 310 and the interposer substrate 600 may be reduced. Electrical characteristics of the lower semiconductor package 10 may be improved. Hereinafter, the electrical connection and the conductive structures 400 of the lower semiconductor package 10 will be described in more detail.

The conductive structure 400 may include first conductive structures 410 and second conductive structures 420. The first conductive structures 410 may be provided on the first region R1 of the lower substrate 100. The first conductive structures 410 may be disposed closer to the first semiconductor chip 210 than the second conductive structures 420. The first conductive structures 410 may be provided adjacent to the first side surface 100a of the lower substrate 100. The first conductive structures 410 may be disposed closer to the first semiconductor chip 210 than the second structures 420. It may be provided adjacent to the first side surface 100a of the lower substrate 100. The first conductive structures 410 may be arranged in rows parallel to the first direction in a plan view, and the first direction may be parallel to the first side surface 100a of the lower substrate 100. The planar arrangement and arrangement of the first conductive structures 410 may be variously modified. For example, the number of columns of the first conductive structures 410 may vary.

The first conductive structures 410 may include signal structures. The signal structure can perform the function of transferring electrical signals, such as data signals, between any two components. For example, at least some of the first conductive structures 410 may be connected to the signal pad 622A to function as a signal path between the first semiconductor chip 210 and the interposer substrate 600. For example, the first semiconductor chip 210 and the signal may be transferred to the signal pad 622A through the first conductive structures 410 and the lower substrate 100. Since the first conductive structures 410 are disposed adjacent to the first semiconductor chip 210, the length of the signal path between the first semiconductor chip 210 and the upper pad 622 may be reduced.

For example, the first conductive structure 410 may further include a power structure, and the total number of signal structures among the first conductive structures 410 may be greater than the number of species of power structures among the first conductive structures 410. have. As another example, the first conductive structure 410 may include a signal structure but may not include a power structure. The first conductive structure 410 may further include a ground structure. The grounding structure can perform the function of transferring a ground voltage between two components.

The second conductive structures 420 may be provided on the second region R2 of the lower substrate 100. The second conductive structures 420 may be disposed closer to the second semiconductor chip 220 than the first conductive structures 410. The second conductive structures 420 may have the same shape as the first conductive structures 410 and may include the same material. However, arrangement, electrical connection, and function of the second conductive structures 420 may be different from those of the first conductive structures 410. For example, the second conductive structures 420 can function as power supply structures. The power supply structure can supply or transfer power from one component to another. The second conductive structures 420 may be electrically connected to the power pad 622B to function as a power passage between the second semiconductor chip 220 and the interposer substrate 600. Can be. The power passage may mean a power supply passage. For example, the power output from the second semiconductor chip 220 may be transferred to the power pad 622B through the lower substrate 100 and the second conductive structures 420. The length of the power passage between the second semiconductor chip 220 and the upper pad 622 includes the second semiconductor structures 220 as the power management semiconductor chip, and the second conductive structures 420 include the power structures. Can be reduced. Accordingly, power integrity (PI) of the lower semiconductor package 10 may be improved. The second conductive structures 420 may be insulated from the first conductive structures 410.

For example, the second conductive structures 420 may include a power structure but may not include a signal structure. As another example, the second conductive structure 420 may further include a signal structure. In this case, the total number of power structures among the second conductive structures 420 may be greater than the number of species of signal structures among the second conductive structures 420.

The second conductive structures 420 may be provided adjacent to the second side surface 100b of the lower substrate 100. The second conductive structures 420 may be arranged in rows parallel to the second side surface 100b in a plan view. The planar arrangement and arrangement of the second conductive structures 420 may be variously modified. For example, the number of columns of the second conductive structures 420 may vary.

The upper pad 622 may be electrically connected to any one of the first semiconductor chip 210, the second semiconductor chip 220, and the passive devices 310 through the conductive structures 400 and the lower substrate 100. Can be.

The lower molding layer 500 may fill the gap between the lower substrate 100 and the interposer substrate 600. The lower molding layer 500 may be provided on the upper surface 100u of the lower substrate 100 to seal the first semiconductor chip 210, the second semiconductor chip 220, and the passive elements 310. . The lower molding layer 500 may include an upper surface 210a of the first semiconductor chip 210, an upper surface 220a of the second semiconductor chip 220, upper surfaces 310a of the passive elements 310, and a conductive structure 400. Sidewalls) and a bottom surface of the interposer substrate 600. The lower molding layer 500 may further seal at least one of the first connector 251, the second connector 252, and the first connector 251. The lower molding layer 500 may include an insulating polymer such as an epoxy molding compound (EMC). As another example, the underfill material may include a gap between the lower substrate 100 and the first semiconductor chip 210, a gap between the lower substrate 100 and the second semiconductor chip 220, and the lower substrate 100 and the third semiconductor. The gap between the chips 720 may be further provided in at least one gap.

Although not shown, an electronic device may be further provided on the upper surface 100u of the lower substrate 100. The electronic device may include an oscillator such as a crystal oscillator or a real-time clock.

2A is a plan view illustrating a lower semiconductor package according to example embodiments. FIG. 2B corresponds to an enlarged view of region A ′ of FIG. 2A.

2A and 2B, the lower semiconductor package 11 is connected to the lower substrate 100, the first semiconductor chip 210, the second semiconductor chip 220, and the lower molding layer 500. 450 may be included. The connection structure 450 may be provided between the lower substrate 100 and the interposer substrate 600. The connection structure 450 may include a base layer 409 and a conductive structure 400 ′. The base layer 409 may include stacked base layers 409. The base layers 409 may include an insulating material. For example, the base layers 409 may include an insulating polymer or a silicon containing insulating material.

The conductive structure 400 ′ may be provided in the base layers 409. By providing the connection structure 450, the conductive structure 400 ′ may be provided between the interposer substrate 600 and the lower substrate 100. The conductive structure 400 ′ may include the first conductive pad 401, the conductive wiring 403, the conductive vias 404, and the second conductive pad 402 as shown in FIG. 2B. The first conductive pad 401 may be provided on the bottom surface of the connection structure 450. The conductive wiring 403 may be interposed between the base layers 409. The conductive vias 404 pass through the base layers 409 and may be connected to the conductive wiring 403. The second conductive pad 402 is disposed on the top surface of the connection structure 450 and may be connected to any one of the conductive vias 404. The second conductive pad 402 may be electrically connected to the first conductive pad 401 through the conductive vias 404 and the conductive wiring 403. The second conductive pad 402 may not be aligned with the first conductive pad 401 in a vertical direction. The conductive structure 400 ′ may include a metal such as copper.

The lower solder connection part 451 may be provided between the lower substrate 100 and the conductive structure 400 ′ to connect to any one of the substrate pads 110 and the first conductive pad 401. The upper solder connector 452 may be interposed between the conductive structure 400 ′ and the interposer substrate 600 to connect with the second conductive pad 402 and the lower pad 621. The conductive structure 400 ′ may have a higher melting point than the lower solder connectors 451 and the upper solder connectors 452.

According to embodiments, as the connection structure 450 is provided, the upper solder connection 452 may be more freely disposed and designed. For example, the upper solder joint 452 may not be aligned with the lower solder joint 451 in a vertical direction. Accordingly, the degree of freedom of placement of the upper pad 622 may be further increased.

3 is a diagram for describing a semiconductor package according to example embodiments, and corresponds to a cross section taken along the line II ′ of FIG. 1A.

Referring to FIG. 3, the semiconductor package 30 may include a lower semiconductor package 10 and an upper semiconductor package 20. In this case, the lower semiconductor package 10 described with reference to FIGS. 1A to 1C may be used. Unlike shown, the lower semiconductor package 11 described with reference to FIGS. 2A and 2B may be used.

The upper semiconductor package 20 may be provided on the lower semiconductor package 10. The upper semiconductor package 20 may include, for example, an upper substrate 710, a third semiconductor chip 720, and an upper molding layer 730. A printed circuit board or redistribution layer may be used as the upper substrate 710. Metal pads 715 may be provided on the bottom surface of the upper substrate 710. The third semiconductor chip 720 may be mounted on the top surface of the upper substrate 710. The third semiconductor chip 720 may be a kind of semiconductor chip different from the first semiconductor chip 210 and the second semiconductor chip 220. For example, the third semiconductor chip 720 may function as a memory chip to store data in integrated circuits. Integrated circuits of the third semiconductor chip 720 may include a memory circuit. The memory chip may include a DRAM chip, an SRAM chip, an MRAM chip, and / or a NAND flash memory chip. The third semiconductor chip 720 may be connected to the upper substrate 710 through the third connector 725. The third connector 725 may include a bonding wire and may be provided on the third semiconductor chip 720. The third connector 725 may include a metal such as gold (Au). As another example, the third connector 725 may be provided between the upper substrate 710 and the second semiconductor chip 220, and may include solder, bump, ball grid array, or pillar. The third semiconductor chip 720 may be electrically connected to the metal pad 715 through the third connector 725 and the internal wiring 705 in the upper substrate 710. The solid line in the upper substrate 710 schematically shows the internal wiring 705. Unlike shown, a plurality of third semiconductor chips 720 may be provided on the upper substrate 710. An upper molding layer 730 may be provided on the upper substrate 710 to cover the third semiconductor chip 720. The upper molding layer 730 may include an epoxy molding compound.

The conductive terminal 750 may be interposed between the interposer substrate 600 and the upper semiconductor package 20. The conductive terminal 750 is provided on the upper pad 622 and may be connected to the metal pads 715. The metal pad 715 may be connected to the upper pad 622 through the conductive terminal 750. The conductive terminal 750 may include solder or bumps. The conductive terminal 750 may be formed by a reflow process. The conductive terminal 750 may include a metal. According to embodiments, since the interposer substrate 600 is provided, a degree of freedom in arranging the conductive terminals 750 may be provided. For example, the conductive terminal 750 may not be aligned in a vertical direction with the corresponding one of the conductive structures 400.

The third semiconductor chip 720 may receive a signal from the first semiconductor chip 210 through the conductive terminal 750, the upper pad 622, and the first conductive structures 410. The upper semiconductor package 20 may receive power output from the second semiconductor chip 220 through the conductive terminal 750, the upper pad 622, and the second conductive structures 420. Electrically connected to the semiconductor package 20 may mean that the semiconductor package 20 is electrically connected to the third semiconductor chip 720.

The width W of the upper semiconductor package 20 may be smaller than the width of the lower semiconductor package 10. For example, the width W of the upper semiconductor package 20 may be smaller than the width of the interposer substrate 600. Accordingly, at least a portion of the upper surface of the interposer substrate 600 may not overlap with the upper semiconductor package 20 in plan view.

4A is a plan view illustrating a semiconductor package according to example embodiments. 4B is a cross-sectional view taken along the line II ′ of FIG. 4A.

4A and 4B, the semiconductor package 31 may include a lower semiconductor package 12 and an upper semiconductor package 20. The lower substrate 100 may have a center region R10 and an edge region R20 in plan view. As shown in FIG. 4A, the edge region R20 of the lower substrate 100 may be adjacent to the first side surface 100a, the second side surface 100b, the third side surface 100c, and the fourth side surface 100d of the substrate. have. The third side surface 100c may be adjacent to the first side surface 100a. The fourth side surface 100d may be opposite to the third side surface 100c. In a plan view, the center region R10 of the lower substrate 100 may be surrounded by the edge region R20.

The conductive structures 400 may be provided on the edge region R20 of the lower substrate 100. For example, the first conductive structures 410 and the second conductive structures 420 may be provided on the edge region R20 of the lower substrate 100. An arrangement and electrical connection of the first conductive structures 410 and the second conductive structures 420 on the edge region R20 of the lower substrate 100 may be similar to those described with reference to FIGS. 1A and 1B.

The center region R10 of the lower substrate 100 may be configured to provide the first semiconductor chip 210, the second semiconductor chip 220, and the passive devices 310. At least one of the conductive structures 400 may be provided on the center region R10 of the lower substrate 100. For example, the conductive structures 400 may be formed between the first semiconductor chip 210 and the second semiconductor chip 220, between the first semiconductor chip 210 and the passive devices 310, and the second semiconductor chip 220. ) And between passive elements 310, or between passive elements 310. The first conductive structures 410 and the second conductive structures 420 may be provided on the center region R10 of the lower substrate 100. As another example, one of the first conductive structure 410 and the second conductive structure 420 may not be provided in the center region R10.

The upper semiconductor package 20 may include an upper substrate 710, a third semiconductor chip 720, and an upper molding layer 730 as described with reference to FIG. 3. However, a plurality of third semiconductor chips 720 may be provided. The third semiconductor chip 720 may be connected to the upper metal pads 716 through the third connector 725. Upper metal pads 716 may be provided on the upper surface of the upper substrate 710 to be connected to the internal wiring 705 of the upper substrate 710. At least some of the upper metal pads 716 may overlap the lower substrate 100 and the center region R10 in plan view. The third semiconductor chips 720 may be electrically connected to the lower substrate 100 through the conductive structures 400 on the center region R10. Since the conductive structures 400 are provided on the center region R10, the length of the electrical passage between the third semiconductor chip 720 and the lower substrate 100 may be further reduced. In addition, the internal wiring 705 of the upper substrate 710 may be designed more freely.

The lower substrate 100, the first semiconductor chip 210, the second semiconductor chip 220, the passive elements 310, the interposer substrate 600, and the lower molding layer 500 are illustrated in FIGS. 1A and 1B. It may be substantially the same as described.

5A is a plan view illustrating a lower semiconductor package according to example embodiments. FIG. 5B is a cross-sectional view taken along the line II-II ′ of FIG. 5A. FIG. 5C is a cross-sectional view taken along line III-III ′ of FIG. 5A.

5A, 5B, and 5C, the lower semiconductor package 13 may include the lower substrate 100, the first semiconductor chip 210, the second semiconductor chip 220, the passive devices 310, and the conductive material. The structures 400, the lower molding layer 500, and the interposer substrate 600 may be included.

The conductive structures 400 may include first conductive structures 410 and second conductive structures 420. The first conductive structures 410 are provided on the first region R1 of the lower substrate 100 and include the first sub conductive structures 411, the second sub conductive structures 412, and the third sub substrates. Conductive structures 413. The first sub-conducting structures 411 may be closer to the third side surface 100c than the fourth side surface 100d of the lower substrate 100. The first sub conductive structures 411 may be arranged in rows parallel to the second direction. The second direction may be parallel to the third side surface 100c of the lower substrate 100. The first sub conductive structures 411 may include signal structures. The signal structures may be memory signal structures that carry memory signals. For example, the first sub conductive structures 411 may further include a ground structure. As another example, the first sub conductive structures 411 may further include a power supply structure, and the total number of signal structures among the first sub conductive structures 411 may be a total of the power structure among the first sub conductive structures 411. It may be more than the number. As another example, the first sub conductive structures 411 may not include a power structure.

The second sub-conducting structures 412 may be adjacent to the fourth side surface 100d of the lower substrate 100, for example. The second sub conductive structures 412 may be arranged in rows parallel to the second direction. The second sub conductive structures 412 may function differently from the first sub conductive structures 411, and may have different electrical connection relationships. The second sub conductive structures 412 may include power structures. As another example, the second sub conductive structures 412 may further include a signal structure in addition to the power structures, and the total number of the power structures among the second sub conductive structures 412 is the second sub conductive structures 412. It may be greater than the total number of heavy signal structures. The second sub conductive structures 412 may be electrically separated from the first sub conductive structures 411.

The third sub conductive structures 413 may be disposed closer to the first semiconductor chip 210 than the first and second sub conductive structures 412. The third sub-conducting structures 413 may be disposed between the first semiconductor chip 210 and the passive devices 310, between the first semiconductor chip 210 and the second semiconductor chip 220, or the passive devices 310. Can be provided between. As another example, the third sub conductive structures 413 may not be provided.

Arrangement of the first to third sub-structures 411, 412, 413 is not limited to the illustrated and may be variously modified. For example, the first sub-conducting structures 411 or the second sub-conducting structures 412 are provided adjacent to the first side surface 100a of the lower substrate 100, and the first sub-conductive structures 411 may be provided. Can be aligned along side 100a.

The second conductive structures 420 may be provided on the second region R2 of the lower substrate 100. At least some of the second conductive structures 420 may be disposed adjacent to the third side surface 300c or the fourth side surface 300d of the lower substrate 100. Other portions of the second conductive structures 420 may be provided adjacent to the second semiconductor chip 220. For example, another portion of the second conductive structures 420 may be disposed between the second semiconductor chip 220 and the first semiconductor chip 210, any one of the passive devices 310, and the second semiconductor chip 220. ) Or between passive elements 310. The second conductive structures 420 may include power structures. The external voltage may be transferred to the second semiconductor chip 220 through the external terminals 150 and the lower substrate 100. In the process of transferring the voltage from the lower substrate 100 to the second semiconductor chip 220, it may further pass through at least one of the passive elements 310. Thereafter, the power converted by the second semiconductor chip 220 may be transferred to the second upper pad 622 through the second conductive structure 420. In this case, the power converted by the second semiconductor chip 220 may be transferred to the second conductive structure 420 via another one of the passive elements 310. According to embodiments, the second semiconductor chip 220 functions as a power semiconductor chip, and the second conductive structures 420 include power structures, such that the external terminals 150 and the second upper pads 622 are provided. The length of the power passage in between can be reduced. As the passive elements 310 are provided on the second region R2 of the lower substrate 100, the length of the power passage between the external terminals 150 and the second upper pad 622 may be further reduced. have. The arrangement of the second conductive structures 420 is not limited to the illustrated and may be variously modified. For example, the second conductive structures 420 may be adjacent to and aligned along the second side surface 100b of the lower substrate 100 in a plan view.

The upper pad 622 is exposed on the upper surface of the interposer substrate 600 and may function as terminals of the lower semiconductor package 13. The upper pad 622 may be provided in plurality. Some of the upper pads 622 may be electrically connected to the conductive structures 400. At least two of the upper pads 622 may be electrically connected to each other through the conductive pattern 623.

6A is a plan view illustrating a semiconductor package according to example embodiments. FIG. 6B is a cross-sectional view taken along the line II-II ′ of FIG. 6A. FIG. 6C is a cross-sectional view taken along line III-III ′ of FIG. 6A.

6A and 6B, the semiconductor package 30 may include an upper passive element 320 in addition to the lower semiconductor package 13 and the upper semiconductor package 20. The lower semiconductor package 13 may be the same as described with reference to FIGS. 5A to 5C.

The upper semiconductor package 20 may be provided on the lower semiconductor package 13. The upper semiconductor package 20 may include an upper substrate 710, a third semiconductor chip 720, and an upper molding layer 730 as described with reference to FIG. 2. The width of the upper semiconductor package 20 may be smaller than the width of the interposer substrate 600. The upper semiconductor package 20 is provided on the first region R1 of the lower substrate 100, but may not be provided on the second region R2. The upper semiconductor package 20 may not overlap a portion of the upper surface of the interposer substrate 600.

The conductive terminal 750 may be provided between any one of the upper pads 622 and the metal pad 715 to connect to the upper pad 622 and the metal pad 715. Accordingly, the upper semiconductor package 20 may be electrically connected to the conductive structures 400 through the interposer substrate 600. Signals of the first semiconductor chip 210 may be transmitted and received to the third semiconductor chip 720 through the first sub-conductive structures 411. Since the first sub-conducting structures 411 overlap the upper semiconductor package 20, the signal path between the upper semiconductor package 20 and the first semiconductor chip 210 and between the external terminal and the upper semiconductor package 20. The length can be further reduced. The second sub conductive structures 412 may function as a power passage of the third semiconductor chip 720. Since the second conductive structures 420 overlap the upper semiconductor package 20, the length of the power passage between the upper semiconductor package 20 and the second conductive structures 420 may be further reduced.

The upper passive element 320 may be mounted on the top surface of the interposer substrate 600. The upper passive element 320 may overlap the second region R2 of the lower substrate 100 in plan view. The upper passive element 320 may be laterally spaced apart from the upper semiconductor package 20. The upper passive element 320 may include any one of an inductor, a resistor, and a capacitor. The second connection terminal 352 may be provided between the interposer substrate 600 and the upper passive element 320. The second connection terminal 352 may include solder or bumps. The second connection terminal 352 may include a metal such as tin, silver, and / or bismuth. The second connection terminal 352 may be connected to the other one of the upper pads 622. Accordingly, the upper passive element 320 may be electrically connected to the interposer substrate 600. The upper passive element 320 may be electrically connected to the upper semiconductor package 20 through the interposer substrate 600 or may be electrically connected to the lower semiconductor package 10. For example, the power converted by the second semiconductor chip 220 may be the upper semiconductor package through the passive elements 310, the second conductive structures 420, the interposer substrate 600, and the upper passive element 320. 20 may be passed.

The upper passive element 320 may have a relatively large height H4. For example, the height H4 of the mounted upper passive element 320 may be greater than the height H3 of the passive element 310. The height H4 of the mounted upper passive element 320 may be greater than the distance D between the lower substrate 100 and the interposer substrate 600. The height H4 of the mounted upper passive element 320 may be greater than the height H5 of the mounted upper semiconductor package 20. In this case, the height H4 of the mounted upper passive element 320 may include the height of the second connection terminal 352. The height H5 of the mounted upper semiconductor package 20 may include the height of the conductive terminal 750. For example, the height H5 of the upper semiconductor package 20 may include the height of the conductive terminal 750, the height of the upper substrate 710, and the height of the upper molding layer 730. According to embodiments, the width and arrangement of the upper semiconductor package 20 may be adjusted so that the upper passive element 320 may be further mounted on the lower semiconductor package 13. Accordingly, the length of the power passage between the upper passive element 320 and the second semiconductor chip 220 may be further reduced. The upper passive element 320 may be provided in plurality, but is not limited thereto.

7A to 7C are diagrams for describing a method of manufacturing a lower semiconductor package according to example embodiments, and correspond to cross sections taken along line II-II ′ of FIG. 5A.

Referring to FIG. 7A, conductive structures 400 may be attached on a bottom surface of the interposer substrate 600. The lower pad 621 may be provided in plural on the lower surface of the interposer substrate 600. The conductive structures 400 may be provided on the bottom surface of the interposer substrate 600 such that the conductive structures 400 are aligned with the lower pads 621, respectively. A plurality of upper solder connectors 452 may be formed between the conductive structures 400 and the lower pads 621, respectively. The conductive structures 400 may be physically and electrically connected to the interposer substrate 600 through the upper solder connectors 452. The upper solder joints 452 may be performed by a soldering process or a thermocompression process by heat treatment. The heat treatment may be performed at a temperature equal to or higher than the melting point of the upper solder joints 452. The melting point of the conductive structure 400 may be higher than the heat treatment temperature. The shape of the conductive structure 400 may be maintained during the heat treatment process.

Referring to FIG. 7B, the first semiconductor chip 210, the second semiconductor chip 220, and the passive devices 310 may be mounted on the lower substrate 100. The mounting of the first semiconductor chip 210 may be performed by a surface mounting technique or a reflow process using ultraviolet rays. As another example, the mounting of the first semiconductor chip 210 may be performed by a bonding process using heat or a laser. The mounting of the second semiconductor chip 220 may be performed by a surface mounting technique or a reflow process using ultraviolet rays. Mounting of passive elements 310 may be performed by surface mount techniques. The mounting order of the first semiconductor chip 210, the second semiconductor chip 220, and the passive devices 310 may be variously modified.

Referring to FIG. 7C, the interposer substrate 600 includes the first semiconductor chip 210, the second semiconductor chip 220, and the passive devices so that the conductive structures 400 face the lower substrate 100. 310 may be provided. In this case, the interposer substrate 600 to which the conductive structures 400 described with reference to FIG. 7A are connected may be used. The conductive structures 400 may be aligned with the substrate pads 110, respectively. The conductive structures 400 may be spaced apart from the first semiconductor chip 210, the second semiconductor chip 220, and the passive devices 310 in a plan view.

A plurality of lower solder connectors 451 may be formed between the conductive structures 400 and the substrate pads 110, respectively. The formation of the lower solder joints 451 may be performed by a soldering process or a thermocompression process by heat treatment. The conductive structures 400 may be physically and electrically connected to the lower substrate 100 by the lower solder connectors 451. The heat treatment may be performed at a temperature equal to or higher than the melting point of the lower solder joints 451. The conductive structure 400 may have a melting point greater than the heat treatment temperature, and thus maintain the shape of the conductive structure 400 during the heat treatment process.

Referring back to FIGS. 5A and 5B, a lower molding layer 500 may be formed to fill the gap between the lower substrate 100 and the interposer substrate 600. The lower molding layer 500 may be formed by injection and curing of a molding material. The lower molding layer 500 may be disposed between the first semiconductor chip 210 and the interposer substrate 600, between the second semiconductor chip 220 and the interposer substrate 600, and the passive element 310 and the interposer substrate ( Gaps between 600 may be further filled. Thereafter, the external terminals 150 may be formed on the bottom surface of the lower substrate 100. Accordingly, the lower semiconductor package 13 described with reference to FIGS. 5A and 5B may be manufactured.

8A is a plan view illustrating a lower semiconductor package according to example embodiments. 8B and 8C are diagrams for describing a method of manufacturing a lower semiconductor package according to embodiments, corresponding to cross-sections taken along the line II ′ of FIG. 1A of FIG. 8A.

8A and 8B, a coupling structure 470 may be provided on the bottom surface of the interposer substrate 600. The coupling structure 470 may include the conductive structures 400 and the fixing part 480. The fixing part 480 may have a plate shape. The fixing part 480 may include a plastic or a polymer. The fixing part 480 may have first holes 481 and second holes 482 penetrating therein. The conductive structures 400 may be inserted into the first holes 481 of the fixing part 480. Accordingly, the conductive structures 400 may be provided on the substrate together with the fixing part 480. The second hole 482 of the fixing part 480 may be spaced apart from the first holes 481. The conductive structures 400 may not be provided in the second hole 482.

The conductive structures 400 may be connected to the interposer substrate 600. The connection of the conductive structures 400 and the interposer substrate 600 may include forming upper solder connections 452, respectively, between the conductive structures 400 and the lower pads 621. While the conductive structures 400 are connected to the interposer substrate 600, the pitch and arrangement of the conductive structures 400 can be easily controlled by the fixing part 480. The conductive structures 400 may include first conductive structures 410 and second conductive structures 420 as described above with reference to FIGS. 1A and 1B.

8A and 8C, the first semiconductor chip 210, the second semiconductor chip 220, and the passive elements 310 may be mounted on the lower substrate 100. The interposer substrate 600 may be provided on the first semiconductor chip 210, the second semiconductor chip 220, and the passive devices 310 so that the conductive structures 400 face the lower substrate 100. Can be. In this case, the semiconductor chip, the second semiconductor chip 220, and the passive elements 310 may be provided in the second hole 482 of the fixing part 480. The first semiconductor chip 210, the second semiconductor chip 220, and the passive elements 310 may be spaced apart from the fixing part 480. Lower solder connectors 451 may be formed between the conductive structures 400 and the substrate pads 110, respectively, to connect the conductive structures 400 to the lower substrate 100.

Thereafter, the lower molding layer 500 may be formed to fill the gap between the lower substrate 100 and the interposer substrate 600. The lower molding layer 500 may cover the top, bottom, and sidewalls of the fixing part 480. The lower molding layer 500 may include a material different from the fixing part 480. The external terminals 150 may be formed on the bottom surface of the lower substrate 100. Accordingly, manufacture of the lower semiconductor package 14 may be completed.

The upper semiconductor package 20 described with reference to FIG. 3 may be mounted on the lower semiconductor package 14 of FIGS. 8A to 8C to manufacture a semiconductor package.

9A is a plan view illustrating a lower semiconductor package according to example embodiments. 9B and 9C are diagrams for describing a method of manufacturing a lower semiconductor package according to example embodiments, and correspond to cross sections taken along line II ′ of FIG. 9A.

9A and 9B, a coupling structure 470 may be provided on the bottom surface of the interposer substrate 600. The coupling structure 470 may include the conductive structure 400 and the fixing part 480. Coupling structure 470 may be similar to that described in FIGS. 8A-8B. However, the coupling structure 470 may be provided in plurality, and the fixing part 480 of each coupling structure 470 may not have the second hole 482. One of the coupling structures 470 may be provided on the first region R1 of the lower substrate 100. Another one of the coupling structures 470 may be provided on the second region R2 of the lower substrate 100.

Upper solder connectors 452 may be formed between the conductive structures 400 and the interposer substrate 600 to connect the conductive structures 400 to the interposer substrate 600. The conductive structures 400 may include first conductive structures 410 and second conductive structures 420 as shown in FIGS. 1A and 1B.

9A and 9C, the first semiconductor chip 210, the second semiconductor chip 220, and the passive devices 310 may be mounted on the lower substrate 100. The interposer substrate 600 may be provided on the first semiconductor chip 210, the second semiconductor chip 220, and the passive elements 310 so that the coupling structures 470 face the lower substrate 100. Can be. In this case, the coupling structures 470 may be spaced apart from the first semiconductor chip 210, the second semiconductor chip 220, and the passive devices 310. Lower solder connections 451 may be formed between the conductive structures 400 and the substrate pads 110, respectively.

The lower molding layer 500 may be formed to fill the gap between the lower substrate 100 and the interposer substrate 600. The lower molding layer 500 may cover the top, bottom, and sidewalls of each fixing part 480. The external terminals 150 may be formed on the bottom surface of the lower substrate 100. Accordingly, the lower semiconductor package 15 may be manufactured. The lower semiconductor package 15 may include a plurality of coupling structures 470.

The upper semiconductor package 20 described with reference to FIG. 3 may be mounted on the lower semiconductor package 15 manufactured as shown in FIGS. 9A to 9C to manufacture a semiconductor package.

10A and 10B are diagrams for describing a semiconductor module according to example embodiments, and correspond to a cross section taken along line II-II ′ and a cross section taken along line III-III ′ of FIG. 6A. 10C and 10D are diagrams for describing a semiconductor module according to example embodiments, and correspond to a cross section taken along line II-II ′ and a cross section taken along line III-III ′ of FIG. 6A.

10A and 10B, the semiconductor modules 1 and 2 may include a board 1000 and a semiconductor package 31. A printed circuit board may be used as the board 1000. For example, the semiconductor package 31 described with reference to FIGS. 6A and 6B may be mounted on the board 1000 to manufacture the semiconductor modules 1 and 2. Unlike illustrated, the semiconductor package 30 of FIG. 3 or the semiconductor package 31 of FIGS. 4A and 4B may be mounted on the board 1000. As another example, a semiconductor package is manufactured by stacking an upper semiconductor package 20 on a lower semiconductor package 14 of FIGS. 8A to 8C or a lower semiconductor package 15 manufactured as shown in FIGS. 9A to 9C. The package may be mounted on the board 1000. The board 1000 may have connection pads 1500 on its top surface. The external terminals 150 may be connected to the connection pads 1500. The semiconductor package 32 may be electrically connected to the board 1000 through the external terminals 150.

The height H3 of the passive elements 310 and the height H4 of the upper passive elements 320 may be relatively large. When the passive elements 310 and the upper passive elements 320 are directly mounted on the board 1000 substrate, the passive elements 310 and the upper passive elements 320 may be packaged through the board 1000. (32) can be connected. In this case, the length of the electrical connection passages of the semiconductor modules 1 and 2 may be increased.

According to embodiments, since the conductive structures 400 are used, passive elements 310 may be provided between the lower substrate 100 and the interposer substrate 600. Accordingly, the length of the electrical passage between the first to third semiconductor chips 210, 220, and 720 and the passive elements 310 may be reduced. As the upper passive elements 320 are provided on the interposer substrate 600, between the upper passive elements 320 and the lower semiconductor package 13, or between the upper passive elements 320 and the upper semiconductor package 20. The length of the electrical passage between the can be reduced. The semiconductor modules 1 and 2 may have improved electrical characteristics. The semiconductor modules 1 and 2 can be miniaturized.

As shown in FIGS. 10A and 10B, a separate underfill layer 800 may not be provided between the lower semiconductor package 13 and the upper semiconductor package 20.

10C and 10D, an underfill film 800 may be further provided in the gap between the lower semiconductor package 13 and the upper semiconductor package 20 to seal the conductive terminals 750. The underfill film 800 may include an insulating polymer. The underfill film 800 may have a thermal conductivity greater than that of air. During operation of the lower semiconductor package 13, heat generated in the lower semiconductor package 13 may be discharged to the outside faster through the underfill film 800. Similarly, during operation of the upper semiconductor package 20, heat generated in the upper semiconductor package 20 may be discharged to the outside faster through the underfill film 800. The underfill film 800 may protect the external terminals 150.

According to the embodiments, since the width of the upper semiconductor package 20 is smaller than the interposer substrate 600 as shown in FIG. 10C, the underfill layer 800 may be disposed between the interposer substrate 600 and the upper semiconductor package 20. It can be easily formed. The underfill layer 800 may not extend into a gap between the interposer substrate 600 and the upper passive element 320.

According to the embodiments, since the distance D between the lower substrate 100 and the interposer substrate 600 is large, the lower semiconductor package 13 may have a relatively large height. Although a lower underfill film (not shown) is formed between the board 1000 and the semiconductor package 32, a separate underfill film 800 may be formed between the lower semiconductor package 13 and the upper semiconductor package 20. . The underfill layer 800 may not extend between the board 1000 and the semiconductor package 32. The underfill film 800 may be formed after the semiconductor package 32 is mounted on the board 1000.

11A is a plan view illustrating a first lower semiconductor package in accordance with embodiments. FIG. 11B is a cross-sectional view taken along line IV-IV ′ of FIG. 11A.

11A and 11B, the first lower semiconductor package 16 may include a first lower substrate 101, a first semiconductor chip 210, first conductive structures 410, and first passive elements 311. ), And a first interposer substrate 600 ′. The first lower substrate 101, the first semiconductor chip 210, and the first conductive structures 410 may include the lower substrate 100, the first semiconductor chip 210, and the first substrate of the example of FIGS. 5A to 5C. Each of the conductive structures 410 may be substantially the same. The first passive elements 311 may be substantially the same as described in the example of the passive elements 310 on the first region R1 of the lower substrate 100 of FIGS. 5A to 5C. For example, the height H3 ′ of at least one of the mounted first passive elements 311 may be greater than the height H1 of the mounted first semiconductor chip 210. At least one top surface 311a of the first passive elements 311 may be provided at a higher level than the top surface 210a of the first semiconductor chip 210.

The first conductive structures 410 may have substantially the same electrical connection relationship as described in the example of the first conductive structures 410 of FIGS. 5A to 5C. For example, the first conductive structures 410 may include first sub conductive structures 411, second sub conductive structures 412, and third sub conductive structures 413. The first sub conductive structures 411 may be disposed adjacent to one side 101c of the first lower substrate 101 and may include signal structures. The second sub conductive structures 412 may be disposed adjacent to the other side 101d of the first lower substrate 101. One side 101c of the first lower substrate 101 may face the other side 101d. The third sub conductive structures 413 may be provided between the first semiconductor chip 210 and the first passive elements 311 or between the first passive elements 311. The third sub-conducting structures 413 may be provided in the center area of the first lower substrate 101 in a plan view. As another example, the third sub conductive structures 413 may not be provided. The first conductive structures 410 may function as an electrical path between the first lower substrate 101 and the first interposer substrate 600 ′.

The height H 'of the first conductive structure 410 may be greater than the height H3' of the passive elements 310 and the height H1 of the first semiconductor chip 210. The top surface 410a of the first conductive structure 410 may be provided at a level higher than the top surfaces 311a of the first passive elements 311 and the top surface 210a of the first semiconductor chip 210.

First lower solder connectors 451 ′ are provided between the first lower substrate 101 and the first conductive structures 410, and the first upper solder connectors 452 ′ are provided between the first conductive structures 410. ) And the first interposer substrate 600 ′. The first lower solder connectors 451 ′ and the first upper solder connectors 452 ′ may be the same as the lower solder connectors 451 and the upper solder connectors 452 described with reference to FIGS. 1A and 1B, respectively. .

The first interposer substrate 600 ′ may include a first insulating layer 610 ′, a first lower pad 621 ′, a first conductive pattern 623 ′, and a first upper pad 622 ′. have. The first insulating layer 610 ′, the first lower pad 621 ′, the first conductive pattern 623 ′, and the first upper pad 622 ′ may include the insulating layer 610 described with reference to FIGS. 1A through 1C, The lower pad 621, the conductive pattern 623, and the upper pad 622 may be similar to each other. The first interposer substrate 600 ′ may be electrically connected to the first semiconductor chip 210 or the first passive elements 311 through the conductive structures 400 and the first lower substrate 101.

A first lower molding layer 510 may be provided between the first lower substrate 101 and the first interposer substrate 600 ′ to seal the first semiconductor chip 210 and the first passive element 311. have. The first lower molding layer 510 may cover sidewalls of the first conductive structures 410. The first lower molding layer 510 may include an epoxy molding compound.

First external terminals 151 may be provided on the bottom surface of the first lower substrate 101. The first external terminals 151 may be substantially the same as the external terminals 150 described with reference to FIGS. 1A and 1B. The first semiconductor package 41 may not include the second semiconductor chip 220.

11C is a plan view illustrating a first semiconductor package according to example embodiments. FIG. 11D is a cross-sectional view taken along the line IV-IV ′ of FIG. 11C.

11C and 11D, the first semiconductor package 41 may include a first lower semiconductor package 16 and a first upper semiconductor package 21. The first lower semiconductor package 16 may be the same as described with reference to FIGS. 11A and 11B. The first upper semiconductor package 21 may be stacked on the first lower semiconductor package 16. The first upper semiconductor package 21 may include an upper substrate 710, a third semiconductor chip 720, and an upper molding layer 730 that are substantially the same as described with reference to FIGS. 3 and 5A through 5C. The first upper semiconductor package 21 may have a smaller planar area than the first lower semiconductor package 16. For example, the first upper semiconductor package 21 may have a smaller width than the first lower semiconductor package 16. Here, the width of the component may mean the spacing of the component in a direction parallel to one side 101c of the lower substrate 101. The first upper semiconductor package 21 may have a length equal to or smaller than the first lower semiconductor package 16.

Each conductive terminal 750 may be interposed between the first upper pad 622 ′ and the metal pad 715. The first upper semiconductor package 21 may be electrically connected to the first lower semiconductor package 16 through the conductive terminal 750. The third semiconductor chip 720 may include the first external terminals 151, the first semiconductor chip 210, and the first passive device through the first interposer substrate 600 ′ and the first conductive structures 410. It may be electrically connected to at least one of the 311.

12A is a plan view illustrating a second semiconductor package according to example embodiments. 12B is a cross-sectional view taken along the line VV ′ of FIG. 12A.

12A and 12B, the second semiconductor package 42 may include a second lower semiconductor package 17 and upper passive elements 320. The second lower semiconductor package 17 may include the second external terminals 152, the second lower substrate 102, the second semiconductor chip 220, the second conductive structures 420, and the second passive elements 312. ), A second lower molding layer 520, and a second interposer substrate 600 ″. The second lower substrate 102, the second external terminals 152, the second semiconductor chip 220, and the second conductive structures 420 are examples of FIGS. 5A, 5B, 6A, and 6B. The lower substrate 100, the second semiconductor chip 220, and the second conductive structures 420 described above may be substantially the same. The second passive elements 312 may be substantially the same as the passive elements 310 on the second region R2 of the lower substrate 100 described in the examples of FIGS. 5A, 5B, 6A, and 6B, respectively. Can be. For example, at least one of the top surfaces 312a of the second passive elements 312 may be provided at a higher level than the top surface 220a of the second semiconductor chip 220. At least one height H3 ″ of the mounted second passive elements 312 may be greater than the height H2 of the mounted second semiconductor chip 220.

At least some of the second conductive structures 420 may be disposed adjacent to one side 101c and the other side 101d of the first lower substrate 101. One side 101c and the other side 101d of the lower substrate 100 may face each other. Other portions of the second conductive structures 420 may be provided adjacent to the second semiconductor chip 220. For example, another portion of the second conductive structures 420 may be provided between any one of the second passive elements 312 and the second semiconductor chip 220 or between the second passive elements 312. have. The top surface 420a of the second conductive structures 420 may be provided at the same level or higher than the top surfaces 312a of the second passive elements 312 and the top surface 220a of the second semiconductor chip 220. Can be. The height H of the second conductive structures 420 may be equal to or greater than the height H3 ″ of the mounted second passive elements 312.

Second lower solder connectors 451 ″ are provided between the second lower substrate 102 and the second conductive structures 420, and the second upper solder connectors 452 ″ are formed on the second conductive structures. It may be provided between 420 and the second interposer substrate 600 ″. The second lower solder connectors 451 ″ and the second upper solder connectors 452 ″ may be the same as the lower solder connectors 451 and the upper solder connectors 452 described with reference to FIGS. 1A and 1B, respectively. Can be.

The second conductive structures 420 may include power structures. The external voltage may be transferred to the second conductive structure 420 through the second external terminals 152, the second lower substrate 102, the second passive elements 312, and the second semiconductor chip 220. Can be.

The second interposer substrate 600 ″ may include second insulating layers 610 ″, second lower pads 621 ″, second conductive patterns 623 ″, and second upper pads 622 ′. May include '). The second insulating layers 610 ″, the second lower pad 621 ″, the second conductive pattern 623 ″, and the second upper pad 622 ″ are respectively insulated from FIGS. 1A and 1B. It may be similar to that described in layers 610, lower pad 621, conductive pattern 623, and upper pad 622. However, the second interposer substrate 600 ″ may be connected to the second conductive structures 420. The second upper pad 622 ″ of the second interposer substrate 600 ″ may function as a power transfer pad.

The second lower molding layer 520 fills the gap between the second lower substrate 102 and the second interposer substrate 600 ″, and the second semiconductor chip 220 and the second passive elements 312 are filled with each other. It can be sealed.

The upper passive element 320 may be provided on the second lower semiconductor package 17. For example, the upper passive element 320 may be mounted on the top surface of the second interposer substrate 600 ″. The second connection terminal 352 may be interposed between the second interposer substrate 600 ″ and the upper passive element 320 to connect with the second upper pad 622. The upper passive element 320 may include the second semiconductor chip 220, the second passive elements 312 through the interposer substrate 600, the second conductive structure 420, and the first lower substrate 101. It may be connected to at least one of the second external terminals 152. The upper passive element 320 may overlap at least one of the second conductive structures 420 in a plan view. Accordingly, between the upper passive element 320 and the second semiconductor chip 220, between the upper passive element 320 and the second passive elements 312, or between the upper passive element 320 and the second external terminals ( The length of the electrical passage between 152 can be reduced. The electrical passage may be a power passage. The height H4 of the mounted upper passive element 320 may be greater than the distance D ′ between the second lower substrate 102 and the second interposer substrate 600 ″.

13A is a plan view illustrating a semiconductor module in accordance with embodiments. FIG. 13B is a cross-sectional view taken along the line VI-VI ′ of FIG. 13A.

13A and 13B, the semiconductor module 3 may include a board 1000, a first semiconductor package 41, and a second semiconductor package 42. The board 1000 may have first connection pads 1510 and second connection pads 1520 on the top surface thereof. The second connection pads 1520 may be spaced apart from the first connection pads 1510. One of the second connection pads 1520 may be electrically connected to any one of the first connection pads 1510 through a connection line 1005 in the board 1000.

The first semiconductor package 41 may be the same as described with reference to FIGS. 11C and 11D. The first external terminals 151 may be connected to the first connection pads 1510 by the reflow process, and thus the first semiconductor package 41 may be mounted on the board 1000.

The second semiconductor package 42 may be the same as described with reference to FIGS. 12A and 12B. The second semiconductor package 42 may be spaced apart from the first semiconductor package 41. The second external terminals 152 may be connected to the second connection pads 1520 by the reflow process, so that the second semiconductor package 42 may be mounted on the board 1000. The first semiconductor package 41 and the second semiconductor package 42 may be electrically connected to each other through the connection wiring 1005 of the board 1000. For example, the voltage converted by the second semiconductor chip 220 of the second semiconductor package 42 may be transferred to the second semiconductor chip 220 or the third semiconductor chip of the first semiconductor package 41 through the board 1000. 720 may be supplied.

After the first semiconductor package 41 is mounted on the board 1000, an underfill pattern 801 may be formed between the first lower semiconductor package 16 and the first upper semiconductor package 21. The underfill pattern 801 may seal the conductive terminal 750. The underfill pattern 801 may not extend onto the bottom surface of the first lower substrate 101. The underfill pattern 801 may include an insulating polymer and may have a higher thermal conductivity than air. As another example, the underfill pattern 801 may not be formed.

The detailed description of the invention is not intended to limit the invention to the disclosed embodiments, and may be used in various ways without departing from the spirit of the invention. The appended claims should be construed to include other embodiments.

Claims (20)

Board;
A semiconductor chip mounted on the substrate;
A passive element mounted on the substrate;
A conductive structure provided on the substrate; And
An interposer substrate disposed on the semiconductor chip, the passive element, and the conductive structure and electrically connected to the conductive structure;
And a height of the passive element is greater than a height of the semiconductor chip.
The method of claim 1,
The semiconductor package further comprising a solder connection interposed between the conductive structure and the interposer substrate. The method of claim 2,
The melting point of the conductive structure is larger than the melting point of the solder connection. The method of claim 1,
And a height of the conductive structure is greater than a height of the passive element. The method of claim 1,
The semiconductor chip is:
A first semiconductor chip including logic circuits; And
And a second semiconductor chip spaced apart from the first semiconductor chip and including power management integrated circuits. The method of claim 5,
The conductive structure is:
Signal structures disposed adjacent to the first semiconductor chip; And
And power supply structures disposed closer to the second semiconductor chip than the signal structures. The method of claim 1,
And a top package disposed on the interposer substrate. The method of claim 1,
The semiconductor package further comprises an upper passive element mounted on the interposer substrate. The method of claim 8,
And a height of the mounted upper passive element is greater than a gap between the substrate and the interposer substrate. The method of claim 8,
Further comprising a top package mounted on the interposer substrate,
The upper passive element is a semiconductor package spaced apart from the upper package. The method of claim 1,
The conductive structure is provided in plurality,
At least one of the conductive structures is provided between the semiconductor chip and a passive element or between the passive elements.
Board;
A semiconductor chip mounted on an upper surface of the substrate;
A passive element mounted on the upper surface of the substrate;
An interposer substrate provided on the semiconductor chip and the passive element;
A conductive structure interposed between the substrate and the interposer substrate;
A lower solder connection portion interposed between the substrate and the conductive structure; And
And a top solder connection interposed between the conductive structure and the interposer substrate.
The method of claim 12,
The upper surface of the passive element is a semiconductor package disposed at a level higher than the upper surface of the semiconductor chip. The method of claim 12,
And the conductive structure has a larger melting point than the lower and upper solder connections. The method of claim 12,
The semiconductor chip is:
A first semiconductor chip; And
A semiconductor package comprising a second semiconductor chip that performs a different function than the first semiconductor chip. The method of claim 15,
Further comprising a top package mounted on an upper surface of the interposer substrate, the upper package including a third semiconductor chip,
And the third semiconductor chip performs a different function from the first semiconductor chip and the second semiconductor chip. The method of claim 12,
Further comprising an upper passive element mounted on the upper surface of the interposer substrate,
And a height of the upper passive element is greater than a height of the passive element.
Board;
A semiconductor chip mounted on an upper surface of the substrate;
A passive element mounted on the upper surface of the substrate;
A conductive structure provided on the substrate;
An interposer substrate disposed on the semiconductor chip, the passive element, and the conductive structure and electrically connected to the conductive structure; And
A lower solder connection portion provided between the substrate and the conductive structure to connect with the substrate and the conductive structure;
The upper surface of the passive element is a semiconductor package disposed at a level higher than the upper surface of the semiconductor chip. The method of claim 18,
And a top surface of the conductive structure is provided at a higher level than the top surface of the passive element. The method of claim 18,
And a top solder connection portion interposed between the conductive structure and the interposer substrate.

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