KR20190122130A - Storage device and operating method thereof - Google Patents

Abstract

The present technique relates to an electronic device. According to the present technique, a memory controller for controlling a memory device with the improved operation performance of a cache program comprises: a command queue sequentially storing command to be performed by the memory device; a cache program determining unit determining whether a second command to be performed after a first command is a program command when the first command, which is a program command stored in the command queue, is provided to the memory device; and a program operation controlling unit controlling the memory device to perform a program operation according to the first command as a normal program operation or cache program operation according to whether the second command is the program command.

Description

Storage device and its operation method {STORAGE DEVICE AND OPERATING METHOD THEREOF}

The present invention relates to an electronic device, and more particularly, the present invention relates to a storage device and a method of operating the same.

The storage device is a device that stores data under the control of a host device such as a computer or a smartphone. The storage device may include a memory device in which data is stored and a memory controller controlling the memory device. Memory devices are classified into volatile memory devices and non-volatile memory devices.

Volatile memory devices store data only when power is supplied, and stored data is destroyed when power is cut off. Volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

Nonvolatile memory devices are memory devices that do not lose data when their power source is interrupted.They are Read Only Memory (ROM), Programmable ROM (EPROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM), and Flash. Memory (Flash Memory).

An embodiment of the present invention provides a storage device having an improved cache program operating performance and a method of operating the same.

According to an embodiment of the present disclosure, a memory controller controlling a memory device may include: a command queue that sequentially stores commands to be executed by the memory device; and a first command that is a program command stored in the command queue is provided to the memory device. The memory device performs a program operation according to the first command as a normal program operation or a cache program operation according to a cache program determination unit that determines whether a second command to be executed next is a program command and whether the second command is a program command. It includes a program operation control unit for controlling to.

An operating method of a memory controller including a command queue that controls a memory device and sequentially stores commands to be executed by the memory device may include a program corresponding to a first command that is a program command stored in the command queue. A program operation according to the first command is executed by the memory device according to a step of providing a program start command instructing an operation to the memory device and whether the second command to be performed after the first command is a program command. Control to perform as.

According to an embodiment of the present disclosure, a storage device sequentially stores a memory device including a plurality of memory cells and commands to be executed by the memory device, and provides the memory device with a first command that is a program command among the commands to be executed. And a memory controller that controls the memory device to perform a program operation according to the first command as a normal program operation or a cache program operation, depending on whether the second command to be executed after the first command is a program command.

According to the present technology, a storage device having improved cache program operating performance and a method of operating the same are provided.

1 is a diagram for describing a storage device according to an exemplary embodiment.
FIG. 2 is a diagram for describing a structure of the memory device of FIG. 1.
3 is a diagram illustrating an example embodiment of a memory cell array of FIG. 2.
FIG. 4 is a circuit diagram illustrating one memory block BLKa among the memory blocks BLK1 to BLKz of FIG. 3.
FIG. 5 is a circuit diagram illustrating another example embodiment of one of the memory blocks BLK1 to BLKz of FIG. 3.
6 is a diagram illustrating an operation of a memory device and a memory controller according to an exemplary embodiment.
FIG. 7 is a diagram for describing the command queue of FIG. 6.
8 is a diagram for explaining a normal program operation and a cache program operation.
9 is a diagram for describing a program operation according to an exemplary embodiment.
10 is a diagram for describing a program operation, according to another exemplary embodiment.
FIG. 11A is a diagram for describing a normal program operation of FIG. 10.
FIG. 11B is a diagram for describing a cache program operation of FIG. 10.
12 is a flowchart illustrating an operation of a memory controller according to an exemplary embodiment.
FIG. 13 is a flowchart for describing an operation of a memory controller of FIG. 12 in detail.
14 is a flowchart illustrating an operation of a memory device according to an embodiment.
FIG. 15 is a diagram for describing another embodiment of the memory controller of FIG. 1.
16 is a block diagram illustrating a memory card system to which a storage device is applied according to an exemplary embodiment of the inventive concept.
17 is a block diagram illustrating a solid state drive (SSD) system to which a storage device is applied according to an embodiment of the present invention.
18 is a block diagram illustrating a user system to which a storage device is applied according to an exemplary embodiment of the inventive concept.

Specific structural to functional descriptions of embodiments according to the inventive concept disclosed in the specification or the application are only illustrated for the purpose of describing embodiments according to the inventive concept, and according to the inventive concept. The examples may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

Embodiments according to the concept of the present invention may be variously modified and may have various forms, and specific embodiments will be illustrated in the drawings and described in detail in the present specification or application. However, this is not intended to limit the embodiments in accordance with the concept of the present invention to a particular disclosed form, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and / or second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another, for example, without departing from the scope of rights in accordance with the inventive concept, and the first component may be called a second component and similarly The second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as "comprise" or "have" are intended to indicate that there is a stated feature, number, step, action, component, part, or combination thereof, one or more other features or numbers. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

In describing the embodiments, descriptions of technical contents which are well known in the technical field to which the present invention belongs and are not directly related to the present invention will be omitted. This is to more clearly communicate without obscure the subject matter of the present invention by omitting unnecessary description.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram for describing a storage device according to an exemplary embodiment.

Referring to FIG. 1, the storage device 50 may include a memory device 100 and a memory controller 200 that controls an operation of the memory device. The storage device 50 stores data under the control of the host 300, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game machine, TV, tablet PC or in-vehicle infotainment system. Device.

The storage device 50 may be manufactured as any one of various types of storage devices according to a host interface which is a communication method with the host 300. For example, the storage device 50 may be a multimedia card in the form of SSD, MMC, eMMC, RS-MMC, micro-MMC, secure digital in the form of SD, mini-SD, micro-SD. Card, universal storage bus (USB) storage, universal flash storage (UFS), storage device in the form of a personal computer memory card international association (PCMCIA) card, storage device in the form of a peripheral component interconnection (PCI) card, PCI-E ( The storage device may be configured as any one of various types of storage devices such as a storage device in the form of a PCI express card, a compact flash card, a smart media card, a memory stick, and the like.

The storage device 50 may be manufactured in any one of various types of package forms. For example, the storage device 50 may include a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), and a wafer- It can be manufactured in any one of a variety of package types such as level fabricated package (WSP), wafer-level stack package (WSP).

The memory device 100 may store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells that store data.

Each of the memory cells includes a single level cell (SLC) storing one data bit, a multi level cell (MLC) storing two data bits, and a triple level cell storing three data bits. (Triple Level Cell; TLC) or Quad Level Cell (QLC) capable of storing four data bits.

The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. One memory block may include a plurality of pages. In an embodiment, the page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. The memory block may be a unit for erasing data. In an embodiment, the memory device 100 may include DDR Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), and RDRAM. (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND, NOR flash memory, Resistive random access memory (RRAM), Phase change memory (phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc.) This can be In the present specification, for convenience of description, it is assumed that the memory device 100 is a NAND flash memory.

The memory device 100 is configured to receive a command and an address from the memory controller 200 and to access a region selected by the address of the memory cell array. That is, the memory device 100 may perform a command-in operation on the area selected by the address. For example, the memory device 100 may perform a write operation (program operation), a read operation, and an erase operation. In the program operation, the memory device 100 will program data in the area selected by the address. In the read operation, the memory device 100 will read data from the area selected by the address. In the erase operation, the memory device 100 will erase the data stored in the area selected by the address.

The memory device 100 may perform a normal program operation. The normal program operation may be a program operation in which the memory device 100 stores data received from the memory controller 200 in a memory cell array. In the normal program operation, while the memory device 100 performs a program operation for storing data in the memory cell array, the memory device 100 may not receive new data from the memory controller 200. Therefore, the memory device 100 may receive new data from the memory controller 200 after the program operation for storing data in the memory cell array is completed.

The memory device 100 may perform a cache program operation. In the cache program operation, while the memory device 100 performs a program operation of storing data in the memory cell array, the memory device 100 may receive new data from the memory controller 200. Thus, when storing continuous write data, the cache program operation may be performed faster than the normal program operation.

In an embodiment, the memory device 100 may include a program operation processor 131.

The program operation processor 131 may perform a program operation of storing data received from the memory controller 200 in a memory cell array in response to a program start command provided by the memory controller 200. When performing a program operation, the program operation processor 131 may perform a normal program operation or a cache program operation according to a program type command provided by the memory controller 200.

The memory controller 200 controls the overall operation of the storage device 50.

When power is applied to the storage device 50, the memory controller 200 may execute firmware (FW). When the memory device 100 is a flash memory device, the memory controller 200 may execute firmware such as a flash translation layer (FTL) for controlling communication between the host 300 and the memory device 100. have.

In an embodiment, the memory controller 200 receives data and a logical block address (LBA) from the host 300, and stores the logical block address of the memory cells in which the data included in the memory device 100 is to be stored. It can be converted into a physical block address (PBA) representing an address.

The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation according to a request of the host 300. During a program operation, the memory controller 200 may provide a program command, a physical block address, and data to the memory device 100. In a read operation, the memory controller 200 may provide a read command and a physical block address to the memory device 100. In an erase operation, the memory controller 200 may provide an erase command and a physical block address to the memory device 100.

In an embodiment, the memory controller 200 may generate a program command, an address, and data by itself regardless of a request from the host 300 and transmit the program command, address, and data to the memory device 100. For example, the memory controller 200 may store commands, addresses, and data in a memory device to perform background operations, such as a program operation for wear leveling and a program operation for garbage collection. 100 can be provided.

In an embodiment, the memory controller 200 may control at least two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method in order to improve operating performance. The interleaving method may be an operation method of overlapping an operation period of at least two memory devices 100.

In an embodiment, the memory controller 200 may include a command queue 210, a cache program determiner 220, and a program operation controller 230.

The command queue 210 may sequentially store a plurality of commands to be executed by the memory device 100. The stored command may be any one of a read command, a program command, and an erase command. The command may be generated at the request of the host 300. Commands stored in the command queue 210 may be performed by the memory device 100 in the order in which they are generated. That is, commands stored in the command queue 210 may be managed in a first in first out (FIFO) manner.

The cache program determiner 220 may determine whether a command to be executed after the program command provided to the memory device 100 is a program command among consecutive commands sequentially stored in the command queue 210. The cache program determiner 220 may generate command information indicating whether a command to be performed after a program command provided to the memory device 100 is a program command. The cache program determiner 220 may provide the generated command information to the program operation controller 230.

The program operation controller 230 may determine whether a command stored in the command queue 210 is a program command. If the stored command is a program command, the program operation controller 230 may provide a program start command according to the program command to the memory device 100. The program operation controller 230 may provide a program type command corresponding to the program start command to the memory device 100.

The program start command may be a command for instructing the memory device 100 to perform a program operation for storing data. The program type command may be a command indicating whether a program operation to be performed by the memory device 100 is a normal program operation or a cache program operation.

In an embodiment, the program type command may indicate the first type if the program operation to be performed by the memory device 100 is a normal program operation. The program type command may indicate the second type if a program operation to be performed by the memory device 100 is a cache program operation.

The program operation controller 230 may provide the program start command, the address of the memory device 100 in which data is to be stored, the data, and the program type command to the memory device 100 in order. In another embodiment, the order in which the program start command and the data are provided to the memory device 100 may be reversed.

For example, the program operation controller 230 may store a program start command according to the first command, which is a program command, when the first command among the consecutive first and second commands sequentially stored in the command queue 210 is a program command. To the device 100. The second command may be a command to be performed by the memory device 100 after the first command.

The program operation controller 230 may receive command information indicating whether the second command is a program command from the cache program determiner 220. The program operation controller 230 may control the memory device 100 to perform a cache program operation when the second command is a program command according to the command information. The program operation controller 230 may control the memory device 100 to perform a normal program operation when the second command is a read command or an erase command according to the command information.

In detail, the program operation controller 230 may determine a program type command corresponding to the program start command according to the command information. The program operation controller 230 may determine that the program type command indicates the first type if the second command is a read command or an erase command according to the command information. The program operation controller 230 may determine that the program type command indicates the second type if the second command is a program command according to the command information.

The program operation controller 230 may provide the determined program type command to the memory device 100. The memory device 100 may perform a program operation according to the first command as a normal program operation or a cache program operation according to the provided program type command.

According to an embodiment, when the received program type command indicates a first type, the memory device 100 may perform a normal program operation during a program operation according to the first command. Therefore, after the memory device 100 completes the normal program operation according to the first command, the program operation controller 230 may provide the memory device 100 with data to be stored according to another program command.

When the provided program type command indicates the second type, the memory device 100 may perform a cache program operation during a program operation according to the first command. Accordingly, the program operation controller 230 may provide the memory device 100 with data to be stored according to the second command while the memory device 100 performs the cache program operation according to the first command.

The host 300 is a USB (Universal Serial Bus), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnection (PCI), PCIe ( PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), Dual In-line Memory Module (DIMM), Registered DIMM ) And the storage device 50 may be communicated using at least one of various communication schemes such as a Load Reduced DIMM (LRDIMM).

FIG. 2 is a diagram for describing a structure of the memory device of FIG. 1.

Referring to FIG. 2, the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and control logic 130.

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 121 through row lines RL. The memory blocks BLK1 to BLKz are connected to the read and write circuit 123 through the bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are nonvolatile memory cells. The plurality of memory cells are defined as one page of memory cells connected to the same word line. That is, the memory cell array 110 is composed of a plurality of pages. According to an embodiment of the present disclosure, each of the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 may include a plurality of dummy cells. At least one dummy cell may be connected in series between the drain select transistor and the memory cells and between the source select transistor and the memory cells.

Each of the memory cells of the memory device 100 includes a single level cell (SLC) for storing one data bit and a multi level cell (MLC) for storing two data bits. ), A triple level cell (TLC) storing three data (DATA) bits or a quad level cell (QLC) capable of storing four data DATA bits.

The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

The peripheral circuit 120 drives the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

The address decoder 121 is connected to the memory cell array 110 through the row lines RL. The row lines RL may include drain select lines, word lines, source select lines, and a common source line. According to an embodiment of the present invention, the word lines may include normal word lines and dummy word lines. According to an embodiment of the present disclosure, the row lines RL may further include a pipe select line.

The address decoder 121 is configured to operate in response to the control of the control logic 130. The address decoder 121 receives an address ADDR from the control logic 130.

The address decoder 121 is configured to decode the block address among the received addresses ADDR. The address decoder 121 selects at least one memory block among the memory blocks BLK1 to BLKz according to the decoded block address. The address decoder 121 is configured to decode the row address RADD among the received addresses ADDR. The address decoder 121 may select at least one word line of the selected memory block by applying voltages provided from the voltage generator 122 to at least one word line WL according to the decoded row address RADD. .

In a program operation, the address decoder 121 may apply a program voltage to selected word lines and apply a pass voltage having a level lower than the program voltage to unselected word lines. In the program verify operation, the address decoder 121 may apply a verify voltage to selected word lines and apply a verify pass voltage at a level higher than the verify voltage to unselected word lines.

In the read operation, the address decoder 121 may apply a read voltage to selected word lines and apply a read pass voltage having a level higher than the read voltage to unselected word lines.

According to an embodiment of the present disclosure, the erase operation of the memory device 100 is performed in units of memory blocks. The address ADDR input to the memory device 100 during the erase operation includes a block address. The address decoder 121 may decode the block address and select one memory block according to the decoded block address. In the erase operation, the address decoder 121 may apply a ground voltage to word lines input to the selected memory block.

According to an embodiment of the present disclosure, the address decoder 121 may be configured to decode a column address among the transferred addresses ADDR. The decoded column address may be passed to the read and write circuit 123. In exemplary embodiments, the address decoder 121 may include components such as a row decoder, a column decoder, an address buffer, and the like.

The voltage generator 122 is configured to generate a plurality of operating voltages Vop by using an external power supply voltage supplied to the memory device 100. The voltage generator 122 operates under the control of the control logic 130.

In an embodiment, the voltage generator 122 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operating voltage of the memory device 100.

In an embodiment, the voltage generator 122 may generate a plurality of operating voltages Vop by using an external power supply voltage or an internal power supply voltage. The voltage generator 122 may be configured to generate various voltages required by the memory device 100. For example, the voltage generator 122 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of non-select read voltages.

The voltage generator 122 includes a plurality of pumping capacitors for receiving an internal power supply voltage to generate a plurality of operating voltages Vop having various voltage levels, and in response to the control of the control logic 130. The pumping capacitors will be selectively activated to generate a plurality of operating voltages Vop.

The generated operating voltages Vop may be supplied to the memory cell array 110 by the address decoder 121.

The read and write circuit 123 includes first to m th page buffers PB1 to PBm. The first to m th page buffers PB1 to PBm are connected to the memory cell array 110 through the first to m th bit lines BL1 to BLm, respectively. The first to m th page buffers PB1 to PBm operate under the control of the control logic 130.

The first to m th page buffers PB1 to PBm communicate with the data input / output circuit 124 and the data DATA. In programming, the first to m th page buffers PB1 to PBm receive data DATA to be stored through the data input / output circuit 124 and the data lines DL.

In the program operation, when the program pulse is applied to the selected word line, the first to m th page buffers PB1 to PBm receive data DATA to be stored through the data input / output circuit 124. Is transferred to the selected memory cells through the bit lines BL1 to BLm. Memory cells of the selected page are programmed according to the transferred data DATA. The memory cell connected to the bit line to which the program allowable voltage (eg, the ground voltage) is applied will have an elevated threshold voltage. The threshold voltage of the memory cell connected to the bit line to which the program inhibit voltage (eg, the power supply voltage) is applied will be maintained. In the program verifying operation, the first to m th page buffers PB1 to PBm read the data DATA stored in the memory cells through the bit lines BL1 to BLm from the selected memory cells.

In the read operation, the read and write circuit 123 reads data DATA from the memory cells of the selected page through the bit lines BL, and reads the read data DATA from the first to m th page buffers PB1. ~ PBm).

In an erase operation, the read and write circuit 123 may float the bit lines BL. In an embodiment, the read and write circuit 123 may include a column select circuit.

In an embodiment, in the cache program operation, a program operation in which data DATA stored in some page buffers among the plurality of page buffers included in the read and write circuit 123 is stored in the memory cell array 110 is performed. The other page buffers among the plurality of page buffers may receive and store new data DATA from the data input / output circuit 124.

In an embodiment, the read and write circuit 123 may include page buffers and cache page buffers. The cache page buffers may temporarily store data DATA input from the memory controller 200 during a cache program operation. That is, while the program operation in which data DATA stored in the page buffers is stored in the memory cell array 110 is performed, the cache page buffers may temporarily store data DATA input from the memory controller 200. . When the program operation is completed, the data DATA stored in the page buffers may be deleted. Once the program operation is completed, the page buffers may receive and store data DATA stored in the cache page buffers.

The data input / output circuit 124 is connected to the first to m th page buffers PB1 to PBm through the data lines DL. The data input / output circuit 124 operates under the control of the control logic 130.

The data input / output circuit 124 may include a plurality of input / output buffers (not shown) that receive the input data DATA. In the program operation, the data input / output circuit 124 receives data DATA to be stored from an external controller (not shown). The data input / output circuit 124 outputs the data DATA transferred from the first to m th page buffers PB1 to PBm included in the read and write circuit 123 to the external controller during the read operation.

The sensing circuit 125 generates a reference current in response to a permission bit (VRYBIT) signal generated by the control logic 130 in a read operation or a verify operation, and senses a sensing voltage VPB received from the read and write circuit 123. ) And the reference voltage generated by the reference current may be output to the control logic 130.

The control logic 130 may be connected to the address decoder 121, the voltage generator 122, the read and write circuit 123, the data input / output circuit 124, and the sensing circuit 125. The control logic 130 may be configured to control overall operations of the memory device 100. The control logic 130 may operate in response to a command CMD transmitted from an external device.

The control logic 130 may control the peripheral circuit 120 by generating various signals in response to the command CMD and the address ADDR. For example, the control logic 130 may receive the operation signal OPSIG, the row address RADD, the read and write circuit control signal PBSIGNALS and the enable bit VRYBIT in response to the command CMD and the address ADDR. Can be generated. The control logic 130 outputs the operation signal OPSIG to the voltage generator 122, the row address RADD to the address decoder 121, and the read and write control signals to the read and write circuit 123. The allowable bit VRYBIT may be output to the sensing circuit 125. In addition, the control logic 130 may determine whether the verification operation passes or fails in response to the pass or fail signal PASS / FAIL output by the sensing circuit 125.

In an embodiment, the control logic 130 may include a program operation processor 131.

The program operation processor 131 may receive a program start command CMD, a program type command CMD, and an address ADDR of the memory cell array 110 to store program data from the memory controller 200.

In response to the received program start command CMD, the program operation processor 131 reads the program data DATA input from the data input / output circuit 124 to the memory cell array 110 through the read and write circuit 123. The program operation to save can be performed.

In detail, the program operation processor 131 may transfer the program data DATA received by the data input / output circuit 124 to the plurality of page buffers included in the read and write circuit 123 through the data lines DL. Can be. The plurality of page buffers may store program data DATA received from the data input / output circuit 124. The plurality of page buffers may be electrically connected to the memory cell array 110 through the memory cell array 110 and the bit lines BL. The program operation processor 131 may perform a program operation for storing the program data DATA stored in the plurality of page buffers in the memory cell array 110 based on the received address ADDR.

The program operation processor 131 may perform a normal program operation or a cache program operation according to the received program type command CMD during a program operation of storing the program data DATA in the memory cell array 110.

When the program operation processor 131 performs the normal program operation, after the program operation for storing the program data DATA in the memory cell array 110 is completed, the read and write circuit 123 reads the new program data DATA. Can be controlled to receive. When the program operation processor 131 performs the cache program operation, while the program operation for storing the program data DATA in the memory cell array 110 is performed, the read and write circuit 123 reads the new program data DATA. Can be controlled to receive.

3 is a diagram illustrating an example embodiment of a memory cell array of FIG. 2.

Referring to FIG. 3, the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block has a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. The plurality of memory cells are arranged along the + X direction, the + Y direction, and the + Z direction. The structure of each memory block is described in more detail with reference to FIGS. 4 and 5.

FIG. 4 is a circuit diagram illustrating one memory block BLKa among the memory blocks BLK1 to BLKz of FIG. 3.

Referring to FIG. 4, the memory block BLKa includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the plurality of cell strings CS11 ˜ CS1m and CS21 ˜ CS2m may have a 'U' shape. Within the memory block BLKa, m cell strings are arranged in a row direction (ie, + X direction). In FIG. 5, two cell strings are shown arranged in a column direction (ie, + Y direction). However, it will be understood that three or more cell strings may be arranged in a column direction as a convenience of description.

Each of the cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain. And a selection transistor DST.

Each of the selection transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. In some embodiments, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. In an embodiment, a pillar for providing a channel layer may be provided in each cell string. In an embodiment, pillars for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

The source select transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

In an embodiment, source select transistors of cell strings arranged in the same row are connected to source select lines extending in the row direction, and source select transistors of cell strings arranged in different rows are connected to different source select lines. In FIG. 4, source select transistors of the cell strings CS11 to CS1m of the first row are connected to the first source select line SSL1. Source select transistors of the cell strings CS21 to CS2m of the second row are connected to the second source select line SSL2.

In another embodiment, the source select transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected between the source select transistor SST and the drain select transistor DST.

The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and p + 1 to nth memory cells MCp + 1 to MCn. The first to pth memory cells MC1 to MCp are sequentially arranged in a direction opposite to the + Z direction, and are connected in series between the source select transistor SST and the pipe transistor PT. The p + 1 to nth memory cells MCp + 1 to MCn are sequentially arranged in the + Z direction, and are connected in series between the pipe transistor PT and the drain select transistor DST. The first to pth memory cells MC1 to MCp and the p + 1 to nth memory cells MCp + 1 to MCn are connected through a pipe transistor PT. Gates of the first to nth memory cells MC1 to MCn of each cell string are connected to the first to nth word lines WL1 to WLn, respectively.

The gate of the pipe transistor PT of each cell string is connected to the pipeline PL.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp + 1 to MCn. The cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m of the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m of the second row are connected to the second drain select line DSL2.

Cell strings arranged in the column direction are connected to bit lines extending in the column direction. In FIG. 4, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m th column are connected to the m th bit line BLm.

Memory cells connected to the same word line in the cell strings arranged in the row direction constitute one page. For example, the memory cells connected to the first word line WL1 among the cell strings CS11 to CS1m of the first row constitute one page. The memory cells connected to the first word line WL1 of the cell strings CS21 to CS2m of the second row form another page. By selecting one of the drain select lines DSL1 and DSL2, cell strings arranged in one row direction will be selected. By selecting any one of the word lines WL1 to WLn, one page of the selected cell strings may be selected.

In another embodiment, even bit lines and odd bit lines may be provided instead of the first to m th bit lines BL1 to BLm. The even-numbered cell strings of the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction are connected to the even bit lines, respectively, and the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction. The odd-numbered cell strings may be connected to the odd bit lines, respectively.

In an embodiment, at least one or more of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce an electric field between the drain select transistor DST and the memory cells MCp + 1 to MCn. As more dummy memory cells are provided, the reliability of the operation on the memory block BLKa is improved while the size of the memory block BLKa is increased. As fewer memory cells are provided, the size of the memory block BLKa may be reduced while the reliability of the operation of the memory block BLKa may be reduced.

In order to efficiently control at least one dummy memory cell, each of the dummy memory cells may have a required threshold voltage. Before or after an erase operation on the memory block BLKa, program operations on all or some of the dummy memory cells may be performed. When the erase operation is performed after the program operation is performed, the threshold voltages of the dummy memory cells control the voltages applied to the dummy word lines connected to the dummy memory cells so that the dummy memory cells may have the required threshold voltages. .

FIG. 5 is a circuit diagram illustrating another example embodiment of one of the memory blocks BLK1 to BLKz of FIG. 3.

Referring to FIG. 5, the memory block BLKb includes a plurality of cell strings CS11 ′ through CS1 m ′ and CS21 ′ through CS2 m ′. Each of the plurality of cell strings CS11 'to CS1m' and CS21 'to CS2m' extends along the + Z direction. Each of the plurality of cell strings CS11 'to CS1m' and CS21 'to CS2m' includes at least one source select transistor SST and a first layer stacked on a substrate (not shown) under the memory block BLK1 '. To n-th memory cells MC1 to MCn and at least one drain select transistor DST.

The source select transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn. Source select transistors of cell strings arranged in the same row are connected to the same source select line. Source select transistors of the cell strings CS11 'to CS1m' arranged in the first row are connected to the first source select line SSL1. Source select transistors of the cell strings CS21 'to CS2m' arranged in the second row are connected to the second source select line SSL2. In another embodiment, the source select transistors of the cell strings CS11 'to CS1m' and CS21 'to CS2m' may be commonly connected to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. Gates of the first to nth memory cells MC1 to MCn are connected to the first to nth word lines WL1 to WLn, respectively.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings CS11 'to CS1m' of the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21 'to CS2m' of the second row are connected to the second drain select line DSL2.

As a result, the memory block BLKb of FIG. 5 has an equivalent circuit similar to that of the memory block BLKa of FIG. 4 except that the pipe transistor PT is excluded from each cell string.

In another embodiment, even bit lines and odd bit lines may be provided instead of the first to m th bit lines BL1 to BLm. The even-numbered cell strings among the cell strings CS11 'to CS1m' or CS21 'to CS2m' arranged in the row direction are connected to the even bit lines, and the cell strings CS11 'to CS1m arranged in the row direction. The odd-numbered cell strings of 'or CS21' to CS2m 'may be connected to the odd bit lines, respectively.

In an embodiment, at least one or more of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell may be provided to reduce an electric field between the drain select transistor DST and the memory cells MC1 ˜ MCn. As more dummy memory cells are provided, the reliability of the operation on the memory block BLKb is improved while the size of the memory block BLKb is increased. As fewer memory cells are provided, the size of the memory block BLKb may be reduced while the reliability of an operation on the memory block BLKb may be reduced.

In order to efficiently control at least one dummy memory cell, each of the dummy memory cells may have a required threshold voltage. Before or after an erase operation on the memory block BLKb, program operations on all or some of the dummy memory cells may be performed. When the erase operation is performed after the program operation is performed, the threshold voltages of the dummy memory cells control the voltages applied to the dummy word lines connected to the dummy memory cells so that the dummy memory cells may have the required threshold voltages. .

6 is a diagram illustrating an operation of a memory device and a memory controller according to an exemplary embodiment.

Referring to FIG. 6, the memory device 100 may include a program operation processor 131.

The program operation processor 131 may perform a program operation for storing data received from the program operation controller 230 in the memory device 100 in response to a program start command provided by the program operation controller 230. The program start command may be a command for instructing the program operation processor 131 to perform a program operation.

The program operation processor 131 may perform a normal program operation or a cache program operation according to a program type command provided by the program operation control unit 230. The program type command may be a command indicating whether the program operation to be performed is a normal program operation or a cache program operation in response to the program start command.

In an embodiment, the program type command may indicate the first type if the program operation to be performed is a normal program operation. The program type command may indicate the second type if the program operation to be performed is a cache program operation.

If the received program type command indicates the first type, the program operation processor 131 may perform a normal program operation during a program operation according to the program start command. The program operation processor 131 may receive new data DATA to be stored in the memory device 100 from the program operation controller 230 after the program operation is completed when the normal program operation is performed.

If the received program type command indicates the second type, the program operation processor 131 may perform a cache program operation during a program operation according to the program start command. When performing a cache program operation, the program operation processor 131 may receive new data DATA to be stored in the memory device 100 from the program operation controller 230 while the program operation is performed.

In an embodiment, the memory controller 200 may include a command queue 210, a cache program determiner 220, and a program operation controller 230.

The command queue 210 may sequentially store a plurality of commands to be executed by the memory device 100. The stored command may be any one of a read command, a program command, and an erase command. The command may be generated at the request of the host 300. Commands stored in the command queue 210 may be performed by the memory device 100 in the order in which they are generated. That is, commands stored in the command queue 210 may be managed in a first in first out (FIFO) manner.

The cache program determiner 220 may determine whether a command to be executed after the program command provided to the program operation processor 131 among the consecutive commands sequentially stored in the command queue 210 is a program command. The cache program determiner 220 may generate command information indicating whether a command to be executed next is a program command. The cache program determiner 220 may provide the generated command information to the program operation controller 230.

The program operation controller 230 may determine whether a command stored in the command queue 210 is a program command. If the stored command is a program command, the program operation controller 230 may provide a program operation command according to the program command to the program operation processor 131. The program operation controller 230 may provide the program operation processor 131 with a program type command corresponding to the program start command.

The program start command may be a command for instructing the program operation processor 131 to perform a program operation for storing data. The program type command may be a command indicating whether the program operation to be performed by the program operation processor 131 is a normal program operation or a cache program operation.

In an embodiment, the program type command may indicate the first type if the program operation to be performed by the program operation processor 131 is a normal program operation. The program type command may indicate the second type if the program operation to be performed by the program operation processor 131 is a cache program operation.

The program operation controller 230 may provide the program operation processor 131 in order of a program start command, an address of the memory device 100 in which data is to be stored, data, and a program type command. In another embodiment, the order in which the program start command and the program data are provided to the program operation processor 131 may be reversed.

For example, the program operation controller 230 may program the program start command according to the first command, which is a program command, if the first command among the consecutive first and second commands sequentially stored in the command queue 210 is a program command. It may be provided to the operation processor 131. The second command may be a command to be performed by the memory device 100 after the first command.

The program operation controller 230 may receive command information indicating whether the second command is a program command from the cache program determiner 220. The program operation controller 230 may control the program operation processor 131 to perform a cache program operation when the second command is a program command according to the command information. The program operation controller 230 may control the program operation processor 131 to perform a normal program operation when the second command is a read command or an erase command according to the command information.

The program operation controller 230 may determine a program type command corresponding to the program start command according to the command information.

For example, the program operation controller 230 may determine that the program type command indicates the first type if the second command is a read command or an erase command according to the command information. The program operation controller 230 may determine that the program type command indicates the second type if the second command is a program command according to the command information. The program operation controller 230 may provide the determined program type command to the program operation processor 131. The program operation processor 131 may perform a program operation according to the first command as a normal program operation or a cache program operation according to the provided program type command.

In an embodiment, if the provided program type command indicates the first type, the program operation processor 131 may perform a normal program operation during a program operation according to the first command. Therefore, after the program operation processor 131 completes the normal program operation according to the first command, the program operation control unit 230 may provide the program operation processing unit 131 with data to be stored according to another program command. .

If the provided program type command indicates the second type, the program operation processor 131 may perform a cache program operation during a program operation according to the first command. Therefore, the program operation controller 230 may provide the program operation processor 131 with data to be stored according to the second command while the program operation processor 131 performs the cache program operation according to the first command.

FIG. 7 is a diagram for describing the command queue of FIG. 6.

Referring to FIG. 7, the command queue may sequentially store commands to be performed by the memory device described with reference to FIG. 1. In an embodiment, the command queue may store first to third commands CMD1 to CDM3. The number of commands stored in the command queue is not limited to this embodiment. Each of the first to third commands CMD1 to CMD3 may be one of a read command, an erase command, and a program command.

Commands stored in the command queue may be managed in a first in first out (FIFO) manner. Therefore, the commands sequentially input and stored in the command queue may be output from the command queue in the input order. For example, the first command CMD1 may be input to the command queue first and output from the command queue first. The second command CMD2 may be input to the command queue secondly and output from the command queue secondly. The third command CMD3 may be input to the command queue thirdly and output from the command queue thirdly.

In an embodiment, the first command CMD1 may be a program command. In this case, a program start command may be provided to the memory device according to the first command CMD1. A program type command corresponding to the program start command may be provided to the memory device.

8 is a diagram for explaining a normal program operation and a cache program operation.

Referring to FIG. 8, the first page buffer and the second page buffer may be part of a plurality of page buffers included in the read / write circuit described with reference to FIG. 2. Each of the first page buffer and the second page buffer may be configured in plural. The memory cell array may include a plurality of memory cells. In FIG. 8, both the first command and the second command may be program commands.

FIG. (A) is a diagram for describing a normal program operation according to an exemplary embodiment.

Program data to be stored according to the first command may be input and stored in the first page buffer. A program operation in which program data stored in a first page buffer is stored in a memory cell array may be performed. The first page buffer may newly receive program data after a program operation is completed. Therefore, when the normal program operation is performed, program data to be stored according to the second command may be input and stored in the first page buffer after the program operation according to the first command is completed.

FIG. (B) is a diagram illustrating a cache program operation according to an embodiment.

Unlike the normal program operation of FIG. (A), while the program operation according to the first command is performed, program data to be stored according to the second command may be input and stored in the second page buffer. The second page buffer may be a cache page buffer used during a cache program operation. When the program operation in which the program data to be stored according to the first command stored in the first page buffer is stored in the memory cell array is completed, the program data to be stored according to the second command stored in the second page buffer is transferred to the first page buffer. Can be.

In the normal program operation, after the program operation for storing data is completed, the next program data may be input. In the cache program operation, the next program data may be input while the program operation is performed. Therefore, in the cache program operation, as compared with the normal program operation, the total program time may be shortened within the range where the next program data input time and the program operation time overlap. That is, when performing a program operation on consecutive write data, the cache program operation may have better data write performance than the normal program operation.

9 is a diagram for describing a program operation according to an exemplary embodiment.

Referring to FIG. 9, in (a), the first command and the second command may be program commands. After the first command and the second command are sequentially input to the command queue, the first command may be provided to the memory device.

Since the first controller and the second command, which are program commands consecutive to the command queue, are input, the memory controller may set the first command as a cache program command and provide the first command to the memory device. The memory controller may provide the second command to the memory device while the cache program operation according to the first command is performed. The memory controller may provide the memory device with data to be stored according to the second command while the cache program operation is performed.

In (b), the first command and the second command may be program commands. After the first command is input to the command queue, the first command may be provided to the memory device.

 Since only the first command is input to the command queue, the memory controller may set the first command as a normal program command and provide the first command to the memory device. The second command may be input to the command queue after the first command is provided to the memory device. Therefore, after providing the first command to the memory device, the memory controller cannot control the memory device to perform the program operation according to the first command as the cache program operation.

The memory controller cannot provide the second command to the memory device while the normal program operation according to the first command is performed. That is, the memory controller may provide the second command to the memory device after the normal program operation is completed. The memory controller may provide data to be stored according to the second command to the memory device after the normal program operation is completed.

10 is a diagram for describing a program operation, according to another exemplary embodiment.

Referring to FIG. 10, it may be a first command program command. After the first command is input to the command queue, the first command may be provided to the memory device.

 Since the first controller is input to the command queue, the memory controller may provide a program start command corresponding to the first command to the memory device. The program start command may be a command for instructing a program operation to store data. After providing the program start command, the memory controller may provide the memory device with data to be stored according to the first command.

 After providing the data to be stored according to the first command to the memory device, the memory controller may provide a program type command corresponding to the first command to the memory device. The program type command may indicate a first type if the program operation indicated by the program start command is a normal program operation and a second type if the cache program operation is performed.

In an embodiment, the second command may be input to the command queue after a program start command corresponding to the first command is provided to the memory device. The second command may be a program command to be performed by the memory device after the first command. The memory controller may determine a program type command corresponding to the first command according to whether the second command is a program command.

Therefore, even if the second command is input after the program start command corresponding to the first command, the memory controller may control the memory device to perform the program operation according to the first command as the cache program operation.

Specifically, when the second command is input to the command queue before the program type command corresponding to the first command is provided to the memory device, the memory controller sets the program type command corresponding to the first command to indicate the second type. Can be. The memory device may perform a cache program operation because the received program type command indicates the second type.

The memory controller may provide the memory device with a program start command corresponding to the second command, data to be stored according to the second command, and a program type command corresponding to the second command while the cache program operation according to the first command is performed. Can be. The memory controller may provide the memory device with data to be stored according to the second command while the cache program operation is performed.

According to the embodiment of FIG. 10, even after program data to be stored according to the first command is provided to the memory device, depending on whether the second command is a program command, the program operation according to the first command may be a normal program operation or a cache program operation. It can be performed as.

Therefore, in order to perform the cache program operation, the first command is provided to the memory device after waiting for the first and second commands to be input to the command queue. Delays occurring in the cache program command setting step can be reduced.

In addition, since the normal program operation according to the embodiment of FIG. 9 is performed by the cache program operation according to the embodiment of FIG. 10, the overall program time for continuous write data may be shortened.

FIG. 11A is a diagram for describing a normal program operation of FIG. 10.

Referring to FIG. 11A, the command queue may sequentially store first to third commands to be executed by the memory device. The first and third commands may be program commands. The second command may be a read command.

The memory controller may provide the memory device with a program start command, an address, data, and a program type command in accordance with the first command stored in the command queue. The program start command PGM Initiation CMD may be a command for instructing a program operation for storing data. The program type command PGM Type CMD may indicate the first type PGM Type CMD1 if the program operation indicated by the program start command is a normal program operation, and the second type PGM Type CMD2 if the program operation is a cache program operation.

Since the second command to be executed after the first command is a read command rather than a program command, the memory controller may determine that a program type command corresponding to the first command indicates the first type.

When the memory device receives a program type command corresponding to the first command, the memory device may perform a program operation on data to be stored according to the first command. The memory device may perform a normal program operation because a program type command indicates a first type.

The memory controller cannot provide the second command to the memory device while the normal program operation according to the first command is performed. After the normal program operation according to the first command is completed, the memory controller may provide the second command to the memory device.

The memory device may perform a read operation in response to the second command which is a read command.

When the read operation according to the second command is completed, the memory controller may control the memory device to perform a program operation according to the third command in the same manner as described above.

FIG. 11B is a diagram for describing a cache program operation of FIG. 10.

Referring to FIG. 11B, the command queue may sequentially store first to third commands to be executed by the memory device, as compared with FIG. 11A. The first to third commands may be program commands.

The memory controller may provide the memory device with a program start command, an address, data, and a program type command in accordance with the first command stored in the command queue.

Since the second command to be executed after the first command is a program command, the memory controller may determine that a program type command corresponding to the first command indicates the second type. Since the received program type command indicates the second type, the memory device may perform a program operation according to the first command as a cache program operation.

The memory controller may provide the second command to the memory device while the cache program operation according to the first command is performed.

In more detail, the memory controller may provide a program start command, an address, data, and a program type command according to the second command while the cache program operation according to the first command is performed. The data at this time may be data to be stored according to the second command.

In a similar manner, since the third command to be executed after the second command is a program command, the program type command corresponding to the second command may be determined to indicate the second type. Since the received program type command indicates the second type, the memory device may perform a program operation according to the second command as a cache program operation.

The memory controller may provide the third command to the memory device while the cache program operation according to the second command is performed. The memory controller may provide a program start command, an address, data, and a program type command according to the third command while the cache program operation according to the second command is performed. The data at this time may be data to be stored according to the third command.

In the memory controller, if a new command is not input to the command queue after the third command, or if the input command is not a program command (if the input command is a read command or an erase command), the program type command corresponding to the third command is the first command. You can decide to indicate the type.

Since the program type command corresponding to the third command indicates the first type, the memory device may perform a program operation according to the third command as a normal program operation. Therefore, after the normal program operation is completed, the memory controller may provide a newly input command to the memory device.

12 is a flowchart illustrating an operation of a memory controller according to an exemplary embodiment.

Referring to FIG. 12, in operation S1201, the memory controller may provide a first command among consecutive first commands and second commands to a memory device. The first command may be a program command. The second command may be a command to be performed after the first command by the memory device.

In operation S1203, the memory controller may determine whether the second command is a program command. If it is determined that the second command is a program command, the process proceeds to step S1205 and otherwise, step S1207.

In operation S1205, even after providing data to be stored according to the first command, the memory controller may control the memory device to perform a program operation according to the first command as a cache program operation. Therefore, the memory controller may provide data to be stored according to the second command to the memory device while the memory device performs a program operation according to the first command.

In operation S1207, after providing data to be stored according to the first command, the memory controller may control the memory device to perform a program operation according to the first command as a normal program operation. Therefore, the memory controller may provide the second command to the memory device after the program operation according to the first command is completed.

FIG. 13 is a flowchart for describing an operation of the memory controller of FIG. 12.

Referring to FIG. 13, in operation S1301, the memory controller may provide a program start command corresponding to the first command to the memory device. The first command may be a program command.

In operation S1303, the memory controller may provide data to be stored according to the first command to the memory device.

In operation S1305, the memory controller may determine whether a second command, which is an order after the first command, is a program command. The second command may be a command to be performed after the first command by the memory device. If it is determined that the second command is a program command, the flow proceeds to step S1307. If the second command is a read command or an erase command, the flow proceeds to step S1311.

In operation S1307, the memory controller may set a program type command corresponding to the first command to the first type and provide the same to the memory device. The program type command may indicate a first type if the program operation indicated by the program start command is a normal program operation, and may indicate a second type if the program operation command is a cache program operation.

In operation S1309, the memory controller may provide data according to the second command while the memory device performs a cache program operation according to the first command.

In operation S1311, the memory controller may set a program type command corresponding to the first command to the second type and provide the same to the memory device.

In operation S1313, when the normal program operation according to the first command performed by the memory device is completed, the memory controller may provide a second command to the memory device.

14 is a flowchart illustrating an operation of a memory device according to an embodiment.

Referring to FIG. 14, in operation S1401, the memory device may receive a program start command corresponding to a first command that is a program command from a memory controller. The program start command may be a command for instructing a program operation.

In operation S1403, the memory device may receive data to be stored according to the first command from the memory controller.

In operation S1405, the memory device may receive a program type command corresponding to the first command from the memory controller. The program type command may indicate the first type if the program operation according to the program start command is a normal program operation, and indicate the second type if the program operation is a cache program operation.

In operation S1407, the memory device may determine whether the type indicated by the program type command is the second type. As a result of the determination, if the type indicated by the program type command is the second type, the process proceeds to step S1409;

In operation S1409, the memory device may perform a cache program operation. Accordingly, the memory device may receive data to be stored according to the second command from the memory controller while performing a program operation for storing data to be stored according to the first command. The second command may be a command to be performed after the first command by the memory device.

In operation S1411, the memory device may perform a normal program operation. Therefore, while the memory device performs a program operation for storing data to be stored according to the first command, the memory device cannot receive data to be stored according to the program command to be performed next to the first command from the memory controller.

That is, after the program operation for storing data to be stored according to the first command is completed, the memory device may receive data to be stored according to the next program command to be stored from the memory controller.

FIG. 15 is a diagram for describing another embodiment of the memory controller of FIG. 1.

Referring to FIG. 15, the memory controller 1000 is connected to a host and a memory device. In response to a request from a host, the memory controller 1000 is configured to access the memory device. For example, the memory controller 1000 is configured to control write, read, erase, and background operations of the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the host. The memory controller 1000 is configured to drive firmware for controlling the memory device.

The memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction unit 1030, a host interface 1040, and a buffer control circuit 1050. ), A memory interface 1060, and a bus 1070.

The bus 1070 may be configured to provide a channel between components of the memory controller 1000.

The processor unit 1010 may control overall operations of the memory controller 1000 and perform logical operations. The processor unit 1010 may communicate with an external host through the host interface 1040 and may communicate with a memory device through the memory interface 1060. In addition, the processor unit 1010 may communicate with the memory buffer unit 1020 through the buffer controller 1050. The processor unit 1010 may control the operation of the storage device by using the memory buffer unit 1020 as an operation memory, a cache memory, or a buffer memory.

The processor unit 1010 may perform a function of a flash translation layer (FTL). The processor unit 1010 may convert a logical block address (LBA) provided by a host into a physical block address (PBA) through a flash translation layer (FTL). The flash translation layer FTL may receive a logical block address LBA by using a mapping table and convert the logical block address LBA into a physical block address PBA. There are several methods of mapping the address of the flash translation layer depending on the mapping unit. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

The processor unit 1010 is configured to randomize the data received from the host. For example, the processor unit 1010 will randomize the data received from the host by using the seeding seed. The randomized data is provided to the memory device as data to be stored and programmed into the memory cell array.

The processor unit 1010 is configured to derandomize data received from the memory device during a read operation. For example, the processor unit 1010 may derandomize data received from the memory device using the derandomizing seed. The derandomized data will be output to the host.

In an embodiment, the processor unit 1010 may perform randomization and derandomize by driving software or firmware.

The memory buffer unit 1020 may be used as an operating memory, a cache memory, or a buffer memory of the processor unit 1010. The memory buffer unit 1020 may store codes and commands executed by the processor unit 1010. The memory buffer unit 1020 may store data processed by the processor unit 1010. The memory buffer unit 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

The error correction unit 1030 may perform error correction. The error correction unit 1030 may perform error correction encoding based on data to be written in the memory device through the memory interface 1060. The error correction encoded data may be transferred to the memory device through the memory interface 1060. The error correction unit 1030 may perform error correction decoding (ECC decoding) on data received from the memory device through the memory interface 1060. In exemplary embodiments, the error correction unit 1030 may be included in the memory interface 1060 as a component of the memory interface 1060.

The host interface 1040 is configured to communicate with an external host under the control of the processor unit 1010. The host interface 1040 includes a Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnection (PCI), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), Dual In-line Memory Module (DIMM), RDIMM (Registered) And communication using at least one of various communication schemes such as Load Reduced DIMM (LRDIMM).

The buffer controller 1050 is configured to control the memory buffer unit 1020 under the control of the processor unit 1010.

The memory interface 1060 is configured to communicate with the memory device under the control of the processor unit 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory device through a channel.

In exemplary embodiments, the memory controller 1000 may not include the memory buffer unit 1020 and the buffer controller 1050.

In exemplary embodiments, the processor 1010 may control operations of the memory controller 1000 using codes. The processor unit 1010 may load codes from a nonvolatile memory device (for example, read only memory) provided in the memory controller 1000. As another example, the processor unit 1010 may load codes from the memory device through the memory interface 1060.

For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may transmit data in the memory controller 1000, and the control bus may be configured to transmit control information such as a command and an address in the memory controller 1000. The data bus and the control bus are separated from each other and may not interfere or affect each other. The data bus may be connected to the host interface 1040, the buffer controller 1050, the error correction unit 1030, and the memory interface 1060. The control bus may be connected to the host interface 1040, the processor unit 1010, the buffer controller 1050, the memory buffer unit 1020, and the memory interface 1060.

16 is a block diagram illustrating a memory card system to which a storage device is applied according to an exemplary embodiment of the inventive concept.

Referring to FIG. 16, the memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 may be configured to control read, write, erase, and background operations of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory controller 2100 may be implemented in the same manner as the memory controller 200 described with reference to FIG. 1.

In exemplary embodiments, the memory controller 2100 may include components such as random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit. Can be.

The memory controller 2100 may communicate with an external device through the connector 2300. The memory controller 2100 may communicate with an external device (eg, a host) according to a specific communication standard. For example, the memory controller 2100 may include a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnection (PCI), a PCI-E (PCI-express), and an advanced technology attachment (ATA). ), Serial-ATA, Parallel-ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), Firewire, Universal Flash Storage (UFS), WIFI, Bluetooth, It is configured to communicate with an external device through at least one of various communication standards such as NVMe. In exemplary embodiments, the connector 2300 may be defined by at least one of the various communication standards described above.

For example, the memory device 2200 may include an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), and a STT-MRAM. It may be configured with various nonvolatile memory devices such as a spin-torque magnetic RAM.

The memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device, such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), and a smart media card (SM, SMC). ), Memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro, eMMC), SD cards (SD, miniSD, microSD, SDHC), general-purpose flash storage (UFS), and the like.

17 is a block diagram illustrating a solid state drive (SSD) system to which a storage device is applied according to an embodiment of the present invention.

Referring to FIG. 17, the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges a signal SIG with the host 3100 through the signal connector 3001, and receives a power PWR through the power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

According to an embodiment of the present disclosure, the SSD controller 3210 may perform a function of the memory controller 200 described with reference to FIG. 1.

The SSD controller 3210 may control the plurality of flash memories 3221 ˜ 322n in response to the signal SIG received from the host 3100. In exemplary embodiments, the signals SIG may be signals based on an interface between the host 3100 and the SSD 3200. For example, the signal (SIG) can be a universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-express), or Advanced Technology Attachment (ATA). , Serial-ATA, Parallel-ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), WIFI, Bluetooth, NVMe It may be a signal defined by at least one of the interfaces such as.

The auxiliary power supply 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power supply 3230 may receive the power PWR from the host 3100 and charge it. The auxiliary power supply 3230 may provide power to the SSD 3200 when the power supply from the host 3100 is not smooth. For example, the auxiliary power supply 3230 may be located in the SSD 3200 or may be located outside the SSD 3200. For example, the auxiliary power supply 3230 may be located on the main board, and may provide auxiliary power to the SSD 3200.

The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or metadata of the flash memories 3321 to 322n. For example, you can temporarily store a mapping table. The buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, or the like, or nonvolatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

18 is a block diagram illustrating a user system to which a storage device is applied according to an exemplary embodiment of the inventive concept.

Referring to FIG. 18, the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may drive components included in the user system 4000, an operating system (OS), or a user program. In exemplary embodiments, the application processor 4100 may include controllers, interfaces, a graphics engine, and the like that control components included in the user system 4000. The application processor 4100 may be provided as a system-on-chip (SoC).

The memory module 4200 may operate as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 includes volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR3 SDRAM, LPDDR3 SDRAM, or nonvolatile random access memory such as PRAM, ReRAM, MRAM, FRAM, etc. can do. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package on package (POP) and provided as one semiconductor package.

The network module 4300 may communicate with external devices. For example, the network module 4300 may include code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), and long term evolution (LTE). ), Wireless communication such as Wimax, WLAN, UWB, Bluetooth, Wi-Fi, and the like. In exemplary embodiments, the network module 4300 may be included in the application processor 4100.

The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100. Alternatively, the storage module 4400 may transmit data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 may be a nonvolatile semiconductor memory device such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash, a NOR flash, or a NAND flash having a three-dimensional structure. Can be implemented. In exemplary embodiments, the storage module 4400 may be provided as a removable drive such as a memory card, an external drive, or the like of the user system 4000.

In exemplary embodiments, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may operate in the same manner as the memory device 100 described with reference to FIG. 1. The storage module 4400 may operate in the same manner as the storage device 50 described with reference to FIG. 1.

The user interface 4500 may include interfaces for inputting data or commands to the application processor 4100 or for outputting data to an external device. In exemplary embodiments, the user interface 4500 may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, a piezoelectric element, and the like. have. The user interface 4500 may include user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an active matrix OLED (AMOLED) display, an LED, a speaker, a motor, and the like.

In the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, although the present invention has been described with reference to the limited embodiments and the drawings, the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

In the above-described embodiments, all steps may optionally be subject to performance or to be omitted. In addition, in each embodiment, the steps need not necessarily occur in order and may be reversed. On the other hand, the embodiments of the present specification disclosed in the specification and drawings are merely presented specific examples to easily explain the technical contents of the present specification and help the understanding of the present specification, and are not intended to limit the scope of the present specification. That is, it will be apparent to those skilled in the art that other modifications based on the technical spirit of the present disclosure may be implemented.

On the other hand, in the present specification and drawings have been described with respect to preferred embodiments of the present invention, although specific terms are used, it is merely used in a general sense to easily explain the technical details of the present invention and to help understanding of the invention, It is not intended to limit the scope of the invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.

50: storage device
100: memory device
131: program operation processing unit
200: memory controller
210: command queue
220: cache program determination unit
230: program operation control unit
300: host

Claims (20)

A memory controller for controlling a memory device,
A command queue that sequentially stores commands to be executed by the memory device;
A cache program determination unit determining whether a second command to be executed after the first command is a program command when a first command which is a program command stored in the command queue is provided to the memory device; And
And a program operation controller configured to control the memory device to perform a program operation according to the first command as a normal program operation or a cache program operation according to whether the second command is a program command. The method of claim 1, wherein the cache program determination unit,
Generating command information indicating whether the second command is a program command,
The program operation control unit,
And a program start command for instructing a program operation corresponding to the first command to the memory device, and determining a program type command corresponding to the first command and providing the program type command to the memory device according to the command information. The method of claim 2, wherein the program type command is:
And a first type in which the program operation is a normal program operation or a second type in which the program operation is a cache program operation. The method of claim 3, wherein the program operation control unit,
And a program start command, an address of the memory device storing data to be stored according to the first command, data to be stored according to the first command, and a program type command. The method of claim 3, wherein the program operation control unit,
And if the second command is a read command or an erase command, determine that a program type command corresponding to the first command indicates the first type. The method of claim 5, wherein the program operation control unit,
And after the program operation according to the first command is completed, providing the second command to the memory device. The method of claim 3, wherein the program operation control unit,
And if the second command is a program command, determines that a program type command corresponding to the first command indicates the second type. The method of claim 7, wherein the program operation control unit,
The memory controller provides data to be stored according to the second command to the memory device while a program operation according to the first command is performed. A method of operating a memory controller including a command queue that controls a memory device and sequentially stores commands to be performed by the memory device.
Providing a program start command to the memory device instructing a program operation corresponding to a first command which is a program command stored in the command queue; And
Controlling the memory device to perform a program operation according to the first command as a normal program operation or a cache program operation according to whether a second command to be executed after the first command is a program command. How it works. The method of claim 9, wherein the controlling step,
Determining a program type command corresponding to the first command according to whether the second command is a program command; And
Providing a program type command corresponding to the first command to the memory device;
The program type command is
And a command for indicating one of a first type in which the program operation is a normal program operation and a second type in which the program operation is a cache program operation. The method of claim 10, wherein the determining of the program type command comprises:
If the second command is a read command or an erase command, determine that the program type command indicates the first type; and if the second command is a program command, determine that the program type command indicates the second type How the memory controller works. The method of claim 11,
If the program type command indicates the first type, after the program operation according to the first command is completed, providing the second command to the memory device. The method of claim 11,
If the program type command indicates the second type, while the program operation according to the first command is performed, providing data to be stored according to the second command to the memory device; How it works. A memory device including a plurality of memory cells; And
Sequentially storing commands to be executed by the memory device, providing a first command which is a program command among the commands to be executed to the memory device, and whether the second command to be performed after the first command is a program command And a memory controller configured to control the memory device to perform a program operation according to the first command as a normal program operation or a cache program operation. The method of claim 14, wherein the memory controller,
A program start command for instructing a program operation corresponding to the first command and data to be stored according to the first command are provided to the memory device, and depending on whether the second command is a program command, Determine a corresponding program type command and provide it to the memory device;
The program type command is
And a first type in which the program operation is a normal program operation or a second type in which the program operation is a cache program operation. The method of claim 15, wherein the memory controller,
And the program type command indicates the first type if the second command is a read command or an erase command, and the program type command indicates the second type if the second command is a program command. The method of claim 16, wherein the memory device,
First page buffers connected through the plurality of memory cells and bit lines and configured to store data to be stored according to the first command;
Second page buffers respectively corresponding to the first page buffers and storing data to be transferred to the first page buffers; And
And a program operation processor configured to perform a program operation of storing data stored in the first page buffers in the plurality of memory cells when receiving a program type command corresponding to the first command. The method of claim 17, wherein the program operation processing unit,
If the program type command indicates the first type, after the program operation is completed, data to be stored according to a program command to be performed after the first command among the commands to be executed is stored in the first page buffers. Storage device to store. The method of claim 17, wherein the program operation processing unit,
And storing the data to be stored according to the second command in the second page buffers while the program type command indicates the second type. The method of claim 19, wherein the program operation processing unit,
And storing data to be stored according to the second command stored in the second page buffers in the first page buffers when the program operation is completed.

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