KR20190120120A - Integrated circuit devices and fabricated method thereof - Google Patents

Abstract

An integrated circuit device and a method of manufacturing the same are provided. The integrated circuit device includes a first fin type transistor and a second fin type transistor of the same conductivity type formed on a substrate. A first thickness of a first source/drain of the first fin type transistor is different from a second thickness of a second source/drain of the second fin type transistor. The amount of current can be controlled by adjusting the thickness of the source/drain.

Description

Integrated circuit devices and fabrication method

The present invention relates to an integrated circuit device and a method of manufacturing the same.

One of the scaling techniques for increasing the density of integrated circuit devices, which forms a fin or nanowire-shaped silicon body on a substrate and forms a gate over the surface of the silicon body. Multi-gate transistors have been proposed.

Since the multi-gate transistor uses a three-dimensional channel, it is easy to scale. In addition, the current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, it is possible to effectively suppress the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage.

An object of the present invention is to provide an integrated circuit device capable of controlling the amount of current by adjusting the thickness of the source / drain.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing an integrated circuit device capable of controlling the amount of current by adjusting the thickness of a source / drain.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

An aspect of the integrated circuit device of the present invention for solving the above problems includes a first fin type transistor and a second fin type transistor of the same conductivity type formed on a substrate, wherein the first source / The first thickness of the drain is different from the second thickness of the second source / drain of the second fin-type transistor.

Alternatively, the distance from the first bottom of the first fin of the first fin transistor to the first interface of the first fin and the first source / drain is a first distance, and The distance from the second bottom of the second pin to the second interface of the second pin and the second source / drain may be a second distance, and the first distance and the second distance may be different from each other.

The first source / drain and the second source / drain have the same first lattice constant, and the first stress that the first source / drain provides to the first channel of the first fin-type transistor is The second source / drain may be different from the second stress applied to the second channel of the second fin-type transistor.

The first channel and the second channel may include a second lattice constant different from the first lattice constant.

The first fin type transistor and the second fin type transistor may be PMOS transistors, and the first source / drain and the second source / drain may include SiGe, and the first channel and the second channel may include Si.

The first fin type transistor and the second fin type transistor are NMOS transistors, the first source / drain and the second source / drain may include SiC, and the first channel and the second channel may include Si.

Impurity concentrations of the first source / drain may be different from impurity concentrations of the second source / drain.

Another aspect of the integrated circuit device of the present invention for solving the above problems is a substrate having a first region and a second region defined; A first fin-type transistor formed in the first region, the first fin, a first gate electrode crossing the first fin on the first fin, and a first fin formed in the first fin on both sides of the first gate electrode. A first fin type transistor comprising a first recess and the first source / drain formed in the first recess; And a second fin-type transistor formed in the second region, the second fin, a second gate electrode crossing the second fin on the second fin, and formed in the second fin on both sides of the second gate electrode. And a second fin-type transistor comprising a second recess and the second source / drain formed in the second recess, wherein the first thickness of the first source / drain is a first thickness of the second source / drain. 2 different from the thickness.

The depth of the first recess and the depth of the second recess are different from each other.

The first fin-type transistor further includes a first spacer disposed on sidewalls of the first gate electrode, and the second fin-type transistor further includes a second spacer disposed on sidewalls of the second gate electrode. The thickness of the first spacer and the thickness of the second spacer may be the same.

The first fin-type transistor and the second fin-type transistor are transistors of the same conductivity type as each other, and the impurity concentration of the first source / drain and the impurity concentration of the second source / drain may be different from each other.

The semiconductor device may further include a first stress film formed on the first fin transistor and a second stress film formed on the second fin transistor, wherein the first stress film and the second stress film may be formed of the same material.

The first region may be an SRAM forming region, the second region may be a logic region, and the first thickness of the first source / drain may be thinner than the second thickness of the second source / drain.

The first fin transistor includes a plurality of first fins spaced apart and parallel to each other, the first gate electrode intersects the plurality of first fins, and the second fin transistor is spaced apart and parallel to each other And a plurality of second fins, and the second gate electrode may cross the plurality of second fins.

The first source / drain and the second source / drain may have the same first lattice constant, and the first fin and the second fin may include a second lattice constant different from the first lattice constant. Can be.

Another aspect of the integrated circuit device of the present invention for solving the above problems is a substrate in which the first block and the second block is defined; At least one first fin-type transistor formed in the first block; At least one second fin-type transistor formed in the second block; And a first thickness of the first source / drain of the first fin-type transistor may be different from a second thickness of the second source / drain of the second fin-type transistor.

Another aspect of the integrated circuit device of the present invention for solving the above problems is a substrate defining a logic region and an SRAM region; A first fin transistor formed in the logic region, the first fin transistor comprising a first fin, a first recess formed in the first fin, and a first source / drain formed in the first recess; And a second fin transistor formed in the SRAM region, the second fin transistor comprising a second fin, a second recess formed in the second fin, and a second source / drain formed in the second recess. The depth of the first recess and the depth of the second recess may be different from each other.

The depth of the first recess may be deeper than the depth of the second recess.

Another aspect of the integrated circuit device of the present invention for solving the above problems comprises a first nanowire transistor and a second nanowire transistor of the same conductivity type formed on a substrate, the first source of the first nanowire transistor The first thickness of the / drain may be different from the second thickness of the second source / drain of the second nanowire transistor.

Another aspect of the integrated circuit device of the present invention for solving the above problems includes a first nanowire transistor and a second nanowire transistor formed on a substrate, the first nanowire transistor is a plurality of vertically stacked And a first source / drain electrically connected to one nanowire and n of the plurality of first nanowires, where n is a natural number, and the second nanowire transistor includes a plurality of second stacked vertically. The nanowires may include a second source / drain electrically connected to m of the plurality of second nanowires, wherein m is a natural number different from n.

The n first nanowires may be n sequentially from the first nanowire disposed above, and the m second nanowires may be m sequentially from the second nanowire disposed above.

The plurality of first nanowires may be stacked in k pieces (where k is a natural number), and the plurality of second nanowires may also be stacked in k pieces.

One aspect of an integrated circuit device of the present invention for solving the other problem is to provide a substrate in which a first region and a second region are defined, forming a first fin in the first region, Forming two fins, forming a first gate electrode crossing the first fin in the first region, forming a second gate electrode crossing the second fin in the second region, and forming the first region A first recess is formed in the first fin on both sides of the first gate electrode, and a second recess is formed in the second fin on both sides of the second gate electrode in the second region. The depth of the set and the depth of the second recess may be formed to be different from each other.

Other specific details of the invention are included in the detailed description and drawings.

1 is a perspective view illustrating an integrated circuit device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1.
3 is a cross-sectional view taken along the line BB and CC of FIG. 1.
4 is a cross-sectional view for describing an integrated circuit device according to a second exemplary embodiment of the present invention.
5 is a cross-sectional view for describing an integrated circuit device according to a third exemplary embodiment of the present invention.
6 is a cross-sectional view for describing an integrated circuit device according to a fourth exemplary embodiment of the present invention.
7 is a cross-sectional view for describing an integrated circuit device according to a fifth exemplary embodiment of the present invention.
8 is a cross-sectional view for describing an integrated circuit device according to a sixth embodiment.
9A and 9B are a circuit diagram and a layout diagram for describing an integrated circuit device according to a seventh embodiment of the present invention.
FIG. 9C illustrates only the plurality of fins and the plurality of gate electrodes in FIG. 9B.
FIG. 9D is a cross-sectional view taken along the lines DD and EE of FIG. 9B.
10A is a conceptual diagram illustrating an integrated circuit device according to an eighth embodiment of the present invention.
10B is a conceptual diagram illustrating an integrated circuit device according to an eighth embodiment of the present invention.
10C is a conceptual diagram illustrating an integrated circuit device according to an eighth embodiment of the present invention.
11A is a conceptual diagram illustrating an integrated circuit device according to a ninth embodiment of the present invention.
11B is a conceptual diagram illustrating an integrated circuit device according to a tenth embodiment of the present invention.
12 is an exploded perspective view illustrating an integrated circuit device according to an eleventh embodiment of the present invention.
13A is a conceptual diagram illustrating an integrated circuit device according to a twelfth embodiment of the present invention.
13B is a conceptual diagram illustrating an integrated circuit device according to a twelfth embodiment of the present invention.
14 to 26 are diagrams illustrating intermediate steps for describing a method of manufacturing an integrated circuit device according to a first exemplary embodiment of the present invention.
27 to 29, a manufacturing method of a pin usable in a manufacturing method of an integrated circuit device according to some exemplary embodiments of the present disclosure will be described.
30 is a block diagram of an electronic system including an integrated circuit device according to some embodiments of the present disclosure.
31 and 32 are exemplary semiconductor systems to which an integrated circuit device may be applied, according to some embodiments of the inventive concepts.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

When one element is referred to as being "connected to" or "coupled to" with another element, when directly connected to or coupled with another element or through another element in between This includes all cases. On the other hand, when one device is referred to as "directly connected to" or "directly coupled to" with another device indicates that no other device is intervened. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

Although the first, second, etc. are used to describe various elements, components and / or sections, these elements, components and / or sections are of course not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first device, the first component, or the first section mentioned below may be a second device, a second component, or a second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

1 is a perspective view illustrating an integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1. 3 is a cross-sectional view taken along the line BB and CC of FIG. 1.

1 to 3, the first fin transistor 101 is formed in the first region I, and the second fin transistor 201 is formed in the second region II. The first region I and the second region II may be spaced apart from each other or may be connected to each other. For example, the first region I may be an SRAM formation region, and the second region II may be a logic region. Alternatively, the first region I may be a region where a pull up transistor of the SRAM is formed, and the second region II may be a region where a pull down transistor or a pass transistor of the SRAM is formed. have.

The stress applied to the channel of the first fin transistor 101 and the stress applied to the channel of the second fin transistor 201 are different from each other. Specifically, when an appropriate stress is applied to the channel, the mobility of the carrier may be improved and the amount of current may increase. Depending on how close the stress is to the channel, the amount of strain on the channel can vary. In the present invention, in order to adjust the magnitude of the stress, the first thickness T1 of the first source / drain 161 of the first fin-type transistor 101 and the second source / drain of the second fin-type transistor 201 ( The second thickness T2 of 261 is adjusted to be different from each other. This will be described later in detail.

The first fin transistor 101 may include a first fin F1, a first gate electrode 147, a first recess 125, a first source / drain 161, and the like.

The first fin F1 may extend long along the second direction Y1. The first fin F1 may be part of the substrate 101 or may include an epitaxial layer grown from the substrate 101. The device isolation layer 110 may cover the side surface of the first fin F1.

The first gate electrode 147 may be formed on the first fin F1 to cross the first fin F1. The first gate electrode 147 may extend in the first direction X1.

The first gate electrode 147 may include metal layers MG1 and MG2. As illustrated in the first gate electrode 147, two or more metal layers MG1 and MG2 may be stacked. The first metal layer MG1 adjusts the work function, and the second metal layer MG2 fills the space formed by the first metal layer MG1. For example, the first metal layer MG1 may include at least one of TiN, TaN, TiC, and TaC. In addition, the second metal layer MG2 may include W or Al. Alternatively, the first gate electrode 147 may be made of Si, SiGe, or the like, not metal. The first gate electrode 147 may be formed through, for example, a replacement process (that is, the first gate electrode 147 may be a gate last structure). . Alternatively, although not shown, for example, the first gate electrode 147 may have a gate first structure.

The first gate insulating layer 145 may be formed between the first fin F1 and the first gate electrode 147. As illustrated in FIG. 2, the first gate insulating layer 145 may be formed on the top and side surfaces of the first fin F1. In addition, the first gate insulating layer 145 may be disposed between the first gate electrode 147 and the device isolation layer 110. The first gate insulating layer 145 may include a high dielectric material having a higher dielectric constant than that of the silicon oxide layer. For example, the first gate insulating layer 145 may include HfO 2, ZrO 2, or Ta 2 O 5.

The first recess 125 may be formed in the first fin F1 on both sides of the first gate electrode 147.

The first source / drain 161 is formed in the first recess 125. The first source / drain 161 may be in the form of an elevated source / drain. In addition, the first source / drain 161 and the first gate electrode 147 may be insulated by the spacer 151.

When the first fin-type transistor 101 is a PMOS transistor, the first source / drain 161 may include a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than Si, for example, SiGe. The compressive stress material may apply compressive stress to the first fin F1 to improve the mobility of carriers in the channel region.

In contrast, when the first fin-type transistor 101 is an NMOS transistor, the first source / drain 161 may be the same material as the substrate 100 or a tensile stress material. For example, when the substrate 100 is Si, the first source / drain 161 may be Si or a material having a lattice constant smaller than Si (eg, SiC).

The spacer 151 may include at least one of a nitride film and an oxynitride film.

The substrate 101 may be made of one or more semiconductor materials selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. In addition, a silicon on insulator (SOI) substrate may be used.

The second fin transistor 201 may include a second fin F2, a second gate electrode 247, a second recess 225, a second source / drain 261, and the like. The second gate electrode 247 crosses the second fin F2 on the second fin F2, and the second recess 225 is in the second fin F2 on both sides of the second gate electrode 247. And a second source / drain 261 may be formed in the second recess 225. The second fin-type transistor 201 is generally similar to the first fin-type transistor 101, and will be described based on differences.

In FIG. 1, for convenience of description, the first fin F1 and the second fin F2 are elongated in parallel along the second directions Y1 and Y2, but the present invention is not limited thereto. For example, the first fin F1 may be elongated along the second direction Y1, and the second fin F2 may be elongated along the first direction X2.

Similarly, although the first gate electrode 147 and the second gate electrode 247 are long side by side in the first direction X1 and X2, they are not limited thereto. For example, the first gate electrode 147 may be elongated along the first direction X1, and the second fin F2 may be elongated along the second direction Y2.

The first fin transistor 101 and the second fin transistor 201 may be of the same conductivity type (eg, P type or N type). Alternatively, the first fin-type transistor 101 may be of a first conductivity type (eg, P-type), and the second fin-type transistor 201 may be of a second conductivity type (eg, N-type).

Unexplained reference numeral 201 is a substrate, 245 is a second gate insulating film, 251 is a second spacer, MG3 is a third metal layer, and MG4 is a fourth metal layer.

The first recess 125 and the second recess 225 may be filled with a metal rather than a semiconductor material. That is, the first source / drain 161 and the second source / drain 261 may be metal materials, not semiconductor materials such as Si, SiGe, and SiC.

Referring to FIG. 3, as described above, the first thickness T1 of the first source / drain 161 of the first fin-type transistor 101 may correspond to the second source / drain of the second fin-type transistor 201. 261 is different from the second thickness T2. As shown, the first thickness T1 may be thinner than the second thickness T2.

In other words, the first interface 163 of the first fin F1 and the first source / drain 161 from the first bottom 162 of the first fin F1 of the first fin-type transistor 101. ) Is the first distance D1 and the second fin F2 and the second source / drain 261 from the second bottom 262 of the second fin F2 of the second fin-type transistor 201. The distance to the second interface 263 is the second distance D2. The first distance D1 and the second distance D2 may be different from each other. Here, the "distance of a and b" means the shortest distance of a and b. As shown, the second distance D2 may be shorter than the first distance D1.

In other words, the depth of the first recess 125 of the first fin-type transistor 101 and the depth of the second recess 225 of the second fin-type transistor 201 may be different from each other. The first source / drain 161 may be formed in the first recess 125, and the second source / drain 261 may be formed in the second recess 225. Therefore, when the depth of the first recess 125 and the depth of the second recess 225 are different from each other, the first thickness T1 and the second source / drain 261 of the first source / drain 161 may be different. The second thickness of) may be formed differently.

The thickness of the device isolation film 110 is D1 (see FIG. 2). As illustrated, the first recess 125 may be formed up to an upper surface of the device isolation layer 110, and the second recess 225 may be formed deeper than an upper surface of the device isolation layer 110. The second recess 225 is deeper than the first recess 125.

For example, when the first fin transistor 101 and the second fin transistor 201 are both P-type transistors, the substrate 100 is Si and the first source / drain 161 and the second source / drain 261 ) May be SiGe. In this case, since SiGe has a larger lattice constant than Si, the first source / drain 161 exerts a compressive stress on the channel of the first fin-type transistor 101, and the second source / drain 261 is the second fin-type transistor. Compression stress may be applied to the channel of 201. However, since the first thickness T1 of the first source / drain 161 is thinner than the second thickness T2 of the second source / drain 261, the volume of the first source / drain 161 may be reduced. Is less than the volume of the second source / drain 261. Therefore, the compressive stress applied to the channel of the first fin-type transistor 101 by the first source / drain 161 is less than the compressive stress applied to the channel of the second fin-type transistor 201 by the first source / drain 161. Can be. Therefore, the driving current amount of the second fin transistor 201 may be greater than the driving current amount of the first fin transistor 101.

If the fins are very thin (eg, 20 nm or less), the usual photo process may not be available to form the fins. For example, a sidewall image transfer (SIT) process may be used in which pins having a constant width are repeatedly formed. In such a case, it is difficult to adjust the effective channel width. That is, in the case of a general planar transistor, the amount of current can be easily adjusted by easily changing the channel width using a photo process. However, in the case of the fin-type transistor using the pin generated through the SIT process, it is difficult to control the amount of current because the channel width is fixed.

However, in the integrated circuit device according to the first embodiment of the present invention, by adjusting the thicknesses T1 and T2 of the sources / drains 161 and 261, the amount of current of the fin transistors 101 and 201 can be easily adjusted.

4 is a cross-sectional view for describing an integrated circuit device according to a second exemplary embodiment of the present invention. For convenience of description, the following description will focus on differences from the integrated circuit device according to the first embodiment of the present invention.

Referring to FIG. 4, when the thickness of the device isolation layer 110 is D1 (see FIG. 2), the first recess 125 is formed to be above the upper surface of the device isolation layer 110, and the second recess ( 225 may be formed deeper than the top surface of the device isolation layer 110. The second recess 225 is deeper than the first recess 125.

The third thickness T3 of the first source / drain 161 of the first fin transistor 102 is different from the second thickness T2 of the second source / drain 261 of the second fin transistor 202. different. The third thickness T3 may be thinner than the aforementioned first thickness T1 (see FIG. 3).

The distance from the first bottom 162 of the first fin F1 of the first fin transistor 102 to the first interface 163 of the first fin F1 and the first source / drain 161 is third. The second interface 263 of the second fin F2 and the second source / drain 261 from the second bottom 262 of the second fin F2 of the second fin-type transistor 202. The distance to is the second distance D2. The third distance D3 and the second distance D2 may be different from each other. The third distance D3 may be longer than the aforementioned first distance D1 (see FIG. 3).

5 is a cross-sectional view for describing an integrated circuit device according to a third exemplary embodiment of the present invention. For convenience of description, the following description will focus on differences from the integrated circuit device according to the first embodiment of the present invention.

Referring to FIG. 5, when the thickness of the device isolation layer 110 is D1 (see FIG. 2), both the first recess 125 and the second recess 225 may be larger than the top surface of the device isolation layer 110. Can be deeply formed. In addition, the second recess 225 is deeper than the first recess 125.

The fourth thickness T4 and the second thickness T2 may be different from each other. The fourth thickness T4 may be thicker than the aforementioned first thickness T1 (see FIG. 3). However, the fourth thickness T4 is thinner than the second thickness T2.

The fourth distance D4 and the second distance D2 may be different from each other. The fourth distance D4 may be shorter than the aforementioned first distance D1 (see FIG. 3). In addition, the fourth distance D4 may be longer than the second distance D2.

6 is a cross-sectional view for describing an integrated circuit device according to a fourth exemplary embodiment of the present invention. For convenience of description, the following description will focus on differences from the integrated circuit device according to the first embodiment of the present invention.

Referring to FIG. 6, a first stress film 169 may be formed on the first fin-type transistor 104, and a second stress film 269 may be formed on the second fin-type transistor 204.

The first stress film 169 and the second stress film 269 may be, for example, SiN films. Whether the SiN film is subjected to tensile stress or compressive stress is determined according to the ratio of N-H bonding and Si-H bonding in the SiN film. For example, when the ratio of N-H bonding / Si-H bonding is about 1 to 5, tensile stress may be given, and about 5 to 20 may give compressive stress.

For example, when the first fin-type transistor 104 and the second fin-type transistor 204 are the same PMOS transistor, the amount of driving current of the second fin-type transistor 202 may be greater than that of the first fin-type transistor 102. have. Due to the influence of the first stress film 169 and the second stress film 269, the amount of current of the first fin transistor 102 and the second fin transistor 202 may also be increased.

7 is a cross-sectional view for describing an integrated circuit device according to a fifth exemplary embodiment of the present invention. For convenience of description, the following description will focus on differences from the integrated circuit device according to the first embodiment of the present invention.

Referring to FIG. 7, the stress that the first spacer 151 exerts on the channel of the first fin-type transistor 105 and the stress that the second spacer 251 imposes on the channel of the second fin-type transistor 205 may be different from each other. have. For example, materials used in the first spacer 151 and the second spacer 251 may be different from each other. For example, the insulating layers 151a and 151b of the first spacer 151 and the insulating layer 251b of the second spacer 251 may not be materials that stress the channel. However, the second spacer 251d may be a material that applies stress to the channel of the second fin-type transistor 203a. As a result, the driving current amount of the first fin transistor 105 and the driving current amount of the second fin transistor 205 can be adjusted differently.

8 is a cross-sectional view for describing an integrated circuit device according to a sixth embodiment. For convenience of description, the following description will focus on differences from the integrated circuit device according to the first embodiment of the present invention.

Referring to FIG. 8, the first fin-type transistor 106 and the second fin-type transistor 206 are transistors of the same conductivity type, and impurity concentrations of the first source / drain 161 formed in the first recess 125 are shown. And impurity concentrations of the second source / drain 261 formed in the second recess 225 are different from each other. For example, when the impurity concentration of the second source / drain 261 is higher than the impurity concentration of the first source / drain 161, the resistance of the second source / drain 261 is the first source / drain 161. It may be less than the resistance of. Therefore, the driving current amount of the second fin-type transistor 206 may be greater than the driving current amount of the first fin-type transistor 106. That is, the amount of driving current may be adjusted by adjusting the impurity concentrations of the first and second sources / drains 161 and 261.

9A and 9B are a circuit diagram and a layout diagram for describing an integrated circuit device according to a seventh embodiment of the present invention. FIG. 9C illustrates only a plurality of pins and a plurality of gate electrodes in FIG. 9B, and FIG. 9D. Is a cross-sectional view taken along the lines DD and EE of FIG. 9B. While integrated circuit devices in accordance with some embodiments of the present invention described above are applicable to any device using a fin transistor, FIGS. 9A-9D illustrate an SRAM by way of example.

First, referring to FIG. 9A, an integrated circuit device according to a seventh embodiment of the present invention includes a pair of inverters INV1 and INV2 connected in parallel between a power node Vcc and a ground node Vss. It may include a first pass transistor PS1 and a second pass transistor PS2 connected to output nodes of each of the inverters INV1 and INV2. The first pass transistor PS1 and the second pass transistor PS2 may be connected to the bit line BL and the complementary bit line BL /, respectively. Gates of the first pass transistor PS1 and the second pass transistor PS2 may be connected to the word line WL.

The first inverter INV1 includes a first pull-up transistor PU1 and a first pull-down transistor PD1 connected in series, and the second inverter INV2 includes a second pull-up transistor PU2 and a second pull-down connected in series. And a transistor PD2. The first pull-up transistor PU1 and the second pull-up transistor PU2 may be PMOS transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NMOS transistors.

In addition, an input node of the first inverter INV1 is connected to an output node of the second inverter INV2 so that the first inverter INV1 and the second inverter INV2 form one latch circuit. The input node of the second inverter INV2 is connected to the output node of the first inverter INV1.

9B to 9D, the first fin 310, the second fin 320, the third fin 330, and the fourth fin 340 spaced apart from each other in one direction (eg, FIG. It extends in the vertical direction of 9). The second fin 320 and the third fin 330 may have a shorter extension length than the first fin 310 and the fourth fin 340.

In addition, the first gate electrode 351, the second gate electrode 352, the third gate electrode 353, and the fourth gate electrode 354 extend in the other direction (for example, the left and right directions in FIG. 9). And intersect the first fins 310 to the fourth fins 340. In detail, the first gate electrode 351 may completely cross the first fin 310 and the second fin 320, and may partially overlap the end of the third fin 330. The third gate electrode 353 may completely cross the fourth fin 340 and the third fin 330, and may partially overlap the end of the second fin 320. The second gate electrode 352 and the fourth gate electrode 354 are formed to intersect the first fin 310 and the fourth fin 340, respectively.

As shown, the first pull-up transistor PU1 is defined around the region where the first gate electrode 351 and the second fin F2 cross each other, and the first pull-down transistor PD1 is the first gate electrode 351. ) Is defined around the region where the first fin F1 crosses, and the first pass transistor PS1 is defined around the region where the second gate electrode 352 and the first fin F1 cross each other. The second pull-up transistor PU2 is defined around the region where the third gate electrode 353 and the third fin 330 cross each other, and the second pull-down transistor PD2 is the third gate electrode 353 and the fourth fin. A second pass transistor PS2 is defined around an area where the 340 crosses, and a second pass transistor PS2 is defined around an area where the fourth gate electrode 354 and the fourth fin 340 intersect.

Although not clearly illustrated, recesses are formed at both sides of a region where the first to fourth gate electrodes 351 to 354 and the first to fourth fins 310, 320, 330, and 340 cross each other, and a recess is formed. Source / drain may be formed within.

In addition, a plurality of contacts 350 may be formed.

In addition, the shared contact 361 connects the second pin 320, the third gate line 353, and the wiring 371 at the same time. The shared contact 362 connects the third pin 330, the first gate line 351, and the wiring 372 at the same time.

The first pull-up transistor PU1, the first pull-down transistor PD1, the first pass transistor PS1, the second pull-up transistor PU2, the second pull-down transistor PD2, and the second pass transistor PS2 are all fins. It may be implemented as a transistor and may have the above-described configuration using FIGS. 1 to 8.

For example, it may have a configuration as shown in FIG. 9D. The first pull-up transistor PU1 includes a second fin 320, a first gate electrode 351 crossing the second fin 320, and second fins 320 on both sides of the first gate electrode 351. It may include a first recess 321a formed in the first recess 321a and a first source / drain 321 formed in the first recess 321a. The first pull-down transistor PD1 includes a first fin 310, a first gate electrode 351 crossing the first fin 310, and first fins 310 on both sides of the first gate electrode 351. A second recess 311a formed in the second recess 311a and a second source / drain 311 formed in the second recess 311a may be included.

In this case, the thickness of the first source / drain 321 of the first pull-up transistor PU1 may be different from that of the second source / drain 311 of the first pull-down transistor PD1. For example, in order to reduce current consumption, the first pull-up transistor PU1 may reduce the amount of current. Therefore, the thickness of the first source / drain 321 of the first pull-up transistor PU1 may be thinner than the thickness of the second source / drain 311 of the first pull-down transistor PD1.

The first pass transistor PS1 includes the first fin 310, the second gate electrode 352 crossing the first fin 310, and the first fin 310 on both sides of the second gate electrode 352. And a third recess formed in the third recess, and a third source / drain formed in the third recess. As shown, the second source / drain and the third source / drain share one node with each other. The thickness of the first source / drain 321 of the first pull-up transistor PU1 may be different from that of the third source / drain of the first pass transistor PS1.

On the other hand, forming recesses of the first pull-up transistor PU1 and the second pull-up transistor PU2 in the first region I, and first pull-down transistor PD1 and the first pull-down transistor in the second region II. Forming a recess of the second pull-down transistor PD2, the first pass transistor PS1, and the second pass transistor PS2 may be performed in a separate process.

By doing in this way, the drive current amount of the first pull-up transistor PU1 (and / or the second pull-up transistor PU2) can be relatively reduced compared to the other transistors PD1, PD2, PS1, and PS2.

10A is a conceptual diagram illustrating an integrated circuit device according to an eighth embodiment of the present invention.

Referring to FIG. 10A, in the integrated circuit device according to the eighth embodiment of the present invention, the fin transistor 411 is disposed in the logic region 410, and the fin transistor 421 is disposed in the SRAM formation region 420. Can be.

Similar to the one described with reference to FIGS. 1 to 8, the fin transistor 411 includes a first fin, a first recess formed in the first fin, and a first source / drain formed in the first recess, The second fin-type transistor 421 includes a second fin, a second recess formed in the second fin, and a second source / drain formed in the second recess. Here, the depth of the first recess and the depth of the second recess may be different from each other. That is, the thickness of the first source / drain and the depth of the second source / drain may be different from each other. Alternatively, the stress of the channel of the fin transistor 411 and the stress of the channel of the fin transistor 421 may be adjusted differently.

In particular, the depth of the first recess may be deeper than the depth of the second recess. This is because the fin transistor 411 formed in the logic region 410 may require higher performance (ie, speed) than the fin transistor 421 formed in the SRAM formation region 420.

In FIG. 10A, the logic region 410 and the SRAM forming region 420 are illustrated by way of example, but are not limited thereto. For example, the present invention can also be applied to an area in which a memory different from the logic area 410 is formed (for example, DRAM, MRAM, RRAM, PRAM, etc.).

10B is a conceptual diagram illustrating an integrated circuit device according to an eighth embodiment of the present invention.

Referring to FIG. 10B, in the integrated circuit device according to the eighth embodiment of the present invention, different pin-type transistors 412 and 422 may be disposed in the logic region 410.

That is, the thickness of the source / drain of the fin transistor 412 may be different from the thickness of the source / drain of the fin transistor 422. Alternatively, the stress of the channel of the fin transistor 412 and the stress of the channel of the fin transistor 422 may be adjusted differently.

10C is a conceptual diagram illustrating an integrated circuit device according to an eighth embodiment of the present invention.

Referring to FIG. 10C, in the integrated circuit device according to the eighth embodiment of the present invention, a plurality of blocks (eg, BLK1 and BLK2) are defined on a substrate. Here, different pin-type transistors may be disposed for each of the blocks BLK1 and BLK2. As illustrated, at least one pin F5 and F6 may be disposed in each block BLK1 and BLK2. The thickness of the source / drain of the fin transistor disposed in the block BLK1 may be different from the thickness of the source / drain of the fin transistor arranged in the block BLK2. Alternatively, the stress of the channel of the pin-type transistor arranged in the block BLK1 and the stress of the channel of the pin-type transistor arranged in the block BLK2 can be adjusted differently.

11A is a conceptual diagram illustrating an integrated circuit device according to a ninth embodiment of the present invention. For convenience of description, the following description will focus on differences from the integrated circuit device according to the first embodiment of the present invention.

Referring to FIG. 11A, in the integrated circuit device according to the ninth embodiment of the present invention, the amount of current of the fin transistors 107 and 107a may be adjusted by controlling the number of pins F11, F12, F21 and F22 used. .

The fin transistor 107 includes a plurality of first fins F11 and F12 spaced apart from each other and arranged in parallel. The first gate electrode 147 may be disposed to intersect the plurality of first fins F1. The fin transistor 107a includes a plurality of second fins F21 and F22 spaced apart from each other and arranged in parallel. The second gate electrode 247 may be disposed to cross the plurality of second fins F2.

The thickness of the source / drain of the fin transistor 107 may be different from the thickness of the source / drain of the fin transistor 107a.

When the number of the fins F11 and F12 used by the fin transistor 107 increases, the amount of current can be increased. In other words, if the current amount of the pin-type transistor is j when one pin is used, the current amount of the pin-type transistor is 2j when two pins F11 and F12 are used. In addition, as described above, the amount of current of the fin transistor 107a can be adjusted to be somewhat different from the amount of current of the fin transistor 107. For example, the current amount of the fin transistor 107a may be about 2j + α or about 2j−α.

Therefore, according to the ninth embodiment of the present invention, it is possible to implement the fin-type transistors 107 and 107a having various kinds of current amounts.

11B is a conceptual diagram illustrating an integrated circuit device according to a tenth embodiment of the present invention. For convenience of explanation, the following description will focus on differences from the integrated circuit device according to the ninth embodiment of the present invention.

Referring to FIG. 11B, in the integrated circuit device according to the tenth exemplary embodiment, the pin-type transistor 109 is controlled by adjusting the number of pins F1a, F1b, F2a, F2b, F3a, F3b, F4a, and F4b. 108, 107, 101 can adjust the amount of current.

The fin transistors 109 and 109a use four fins F1a and F2a. If the current amount of the pin-type transistor is j when one pin is used, the current amount of the pin-type transistor 109 using the four pins F1a is 4j. It may also be about 4j + α or 4j−α of the fin transistor 109a.

The fin transistors 108 and 108a use three fins F1b and F2b. The amount of current in the fin transistor 108 using the three fins F1b is 3j. It may also be about 3j + α or 3j−α of the fin transistor 108a.

The fin transistors 107 and 107a use two fins F1c and F2c. The current amount of the fin transistor 107 using the two fins F2b is 2j. It may also be about 2j + α or 2j−α of the fin transistor 107a.

The fin transistors 101 and 101a use one pin F1d and F2d. The current amount of the fin transistor 101 using one pin F1d is j. It may also be about j + α or j−α of the fin transistor 101a.

Therefore, according to the tenth embodiment of the present invention, it is possible to implement the fin transistors 109, 109a, 108, 108a, 107, 107a, 101, 101a having various kinds of current amounts.

12 is an exploded perspective view illustrating an integrated circuit device according to an eleventh embodiment of the present invention. For convenience of description, the following description will focus on differences from the integrated circuit device according to the first embodiment of the present invention.

Referring to FIG. 12, an integrated circuit device according to an eleventh embodiment of the present invention includes a first nanowire transistor 1101 and a second nanowire transistor 1201. Nanowire transistors are also called gate all around devices. The first and second nanowire transistors 1101 and 1201 use nanowires n1 and n2 instead of fins (see F1 and F2 in FIGS. 1 to 3).

Specifically, the first nanowire transistor 1101 may include a first nanowire n1, a first gate electrode 147 and a first gate crossing the first nanowire n1 on the first nanowire n1. Both sides of the electrode 147 may include a first source / drain 161 formed in the first nanowire n1.

The second nanowire transistor 1201 includes a second nanowire n2, a second gate electrode 247, and a second gate electrode 247 that cross the second nanowire n2 on the second nanowire n2. 2) may include a second source / drain 261 formed in the second nanowire n2.

Cross sections of the first and second nanowires n1 and n2 are illustrated in a circular shape, but the present invention is not limited thereto. For example, the cross-sections of the first and second nanowires n1 and n2 may be elliptical, rectangular, square, or the like.

The thickness of the first source / drain 161 of the first nanowire transistor 1101 may be different from the thickness of the second source / drain 261 of the second nanowire transistor 1201.

13A is a conceptual diagram illustrating an integrated circuit device according to a twelfth embodiment of the present invention. For convenience of explanation, the following description will focus on differences from the integrated circuit device according to the eleventh embodiment of the present invention.

Referring to FIG. 13A, in the integrated circuit device according to the twelfth embodiment of the present invention, the first nanowire transistor 1102 and the second nanowire transistor 1202 are stacked in a plurality of vertical nanowires n11 and n12. , n21, n22). In the drawings, a structure in which two nanowires are stacked by way of example is not limited thereto. For example, three or more nanowires may be laminated.

Specifically, the first nanowire transistor 1102 includes a plurality of first nanowires n11 and n12 stacked vertically and n of the plurality of first nanowires n11 and n12 (where n is a natural number). A first source / drain 161 electrically connected to (eg, one). That is, only one first nanowire n12 may be used.

The second nanowire transistor 1202 includes a plurality of second nanowires n21 and n22 stacked vertically and m of a plurality of second nanowires n21 and n22 (where m is a natural number different from n). A second source / drain 261 electrically connected to (eg, two). That is, two second nanowires n21 and n22 may be used.

By varying the number of nanowires n11, n12, n21, n22 to be used, the amount of driving current can be adjusted. For example, if the current amount of the first nanowire transistor 1102 using one nanowire is j, the current amount of the second nanowire transistor 1202 using two nanowires is 2j.

13B is a conceptual diagram illustrating an integrated circuit device according to a twelfth embodiment of the present invention. For convenience of explanation, the following description will focus on differences from the integrated circuit device according to the twelfth embodiment of the present invention.

Referring to FIG. 13B, the first nanowire transistor 1103 and the second nanowire transistor 1203 include three or more nanowires n11 to n14 and n21 to n24 stacked vertically. The number of first nanowires n11 to n14 included in the first nanowire transistor 1103 and the number of second nanowires n21 to n24 included in the second nanowire transistor 1203 may be the same. have.

Specifically, the first nanowire transistor 1103 may include n (eg, two of the plurality of first nanowires n11 ˜ n14 and vertically stacked first nanowires n11 ˜ n14). (n13, n14) and the first source / drain 161 electrically connected. That is, only two first nanowires n13 and n14 may be used.

In particular, the n first nanowires n11 to n14 to be used are n pieces sequentially from the first nanowires n14 arranged at the top. In Fig. 13B, two are used from the top, and n14 and n13 are used.

The second nanowire transistor 1203 includes a plurality of second nanowires n21 to n24 stacked vertically and m (for example, three) of the plurality of second nanowires n21 to n24 (n22). , a second source / drain 261 electrically connected to n23, n24. That is, three second nanowires n22, n23, and n24 may be used.

In particular, the m second nanowires n21 to n24 to be used may be m sequentially from the second nanowire n24 disposed at the top. In Fig. 13B, three are used from the top, and n24, n23 and n22 are used.

The number of first nanowires n11 to n14 included in the first nanowire transistor 1103 and the number of second nanowires n21 to n24 included in the second nanowire transistor 1203 may be the same. have. In FIG. 13B, four stacked first nanowires n11 to n14 and second nanowires n21 to n24 are provided.

By varying the number of nanowires n11 to n14 and n21 to n24 to be used, the amount of driving current can be adjusted. If the current amount of the first nanowire transistor 1102 using two nanowires is 2j, the current amount of the second nanowire transistor 1202 using three nanowires is 3j.

In the integrated circuit device according to the twelfth embodiment and the twelfth embodiment of the present invention, when the first source / drain 161 and the second source / drain 261 are formed, the recesses are exposed at different depths. By varying the number of nanowires, the number of nanowires used can be adjusted accordingly.

Hereinafter, referring to FIGS. 14 to 26 and 1 to 3, a method of manufacturing an integrated circuit device according to a first embodiment of the present invention will be described.

14 to 26 are diagrams illustrating intermediate steps for describing a method of manufacturing an integrated circuit device according to a first exemplary embodiment of the present invention. 14 to 20 illustrate only the first fin transistor (see 101 in FIG. 1). This is because in the processes of FIGS. 14 to 20, the manufacturing processes of the first fin transistor 101 and the second fin transistor (see 201 of FIG. 1) are substantially the same. 21 to 26 separately illustrate the first fin transistor 101 and the second fin transistor 201. 22 and 25 are cross-sectional views taken along the line AA of Figs. 21 and 24, respectively. 23 and 26 are cross-sectional views taken along the lines B-B and C-C of FIG. 24, respectively.

Referring to FIG. 14, a first fin F1 is formed in the first region I.

Specifically, after the mask pattern 2103 is formed on the substrate 100, an etching process is performed to form the first fin F1. The first fin F1 may extend along the second direction Y1. The trench 121 is formed around the first fin F1. The mask pattern 2103 may be formed of a material including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

Referring to FIG. 15, an isolation layer 110 filling the trench 121 is formed. The device isolation layer 110 may be formed of a material including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

Referring to FIG. 16, the upper portion of the device isolation layer 110 is recessed to expose the upper portion of the first fin F1. The recess process may include a selective etching process. The mask pattern 2103 may be removed before the device isolation layer 110 is formed or after the recess process.

Meanwhile, a part of the first fin F1 protruding from the device isolation layer 110 may be formed by an epi process. Specifically, after the isolation layer 110 is formed, a part of the first fin F1 is formed by an epitaxial process of seeding the upper surface of the first fin F1 exposed by the isolation layer 110 without a recess process. Can be.

In addition, the doping for adjusting the threshold voltage may be performed on the first pin F1. When the fin transistor 101 is an NMOS transistor, the impurity may be boron (B). When the fin transistor 101 is a PMOS transistor, the impurity may be phosphorus (P) or arsenic (As).

Referring to FIG. 17, an etching process is performed using the mask pattern 2104, and the dummy gate insulating layer 141 and the first dummy gate electrode which cross the first fin F1 and extend in the first direction X1. 143 is formed.

For example, the dummy gate insulating layer 141 may be a silicon oxide layer, and the first dummy gate electrode 143 may be polysilicon.

Referring to FIG. 18, a first spacer 151 is formed on the sidewall of the first dummy gate electrode 143 and the sidewall of the first fin F1.

For example, the first spacer 151 may be formed by performing an etch back process after forming an insulating film on the resultant product on which the first dummy gate electrode 143 is formed. The first spacer 151 may expose the top surface of the mask pattern 2104 and the top surface of the first fin F1. The first spacer 151 may be a silicon nitride film or a silicon oxynitride film.

Referring to FIG. 19, an interlayer insulating layer 155 is formed on a resultant on which the first spacer 151 is formed. The interlayer insulating layer 155 may be a silicon oxide layer.

Next, the interlayer insulating film 155 is planarized until the top surface of the first dummy gate electrode 143 is exposed. As a result, the mask pattern 2104 may be removed and the top surface of the first dummy gate electrode 143 may be exposed.

Referring to FIG. 20, the dummy gate insulating layer 141 and the first dummy gate electrode 143 are removed. As the dummy gate insulating layer 141 and the first dummy gate electrode 143 are removed, the trench 123 exposing the device isolation layer 110 is formed.

21 to 23, a first gate insulating layer 145 and a first gate electrode 147 are formed in the trench 123.

The first gate insulating layer 145 may include a high dielectric material having a higher dielectric constant than that of the silicon oxide layer. For example, the first gate insulating layer 145 may include HfO 2, ZrO 2, or Ta 2 O 5. The first gate insulating layer 145 may be substantially conformally formed along the sidewalls and the bottom surface of the trench 123.

The first gate electrode 147 may include metal layers MG1 and MG2. As illustrated in the first gate electrode 147, two or more metal layers MG1 and MG2 may be stacked. The first metal layer MG1 adjusts the work function, and the second metal layer MG2 fills the space formed by the first metal layer MG1. For example, the first metal layer MG1 may include at least one of TiN, TaN, TiC, and TaC. In addition, the second metal layer MG2 may include W or Al. Alternatively, the first gate electrode 147 may be made of Si, SiGe, or the like, not metal.

In the same manner as described above, the second gate insulating layer 245 and the second gate electrode 247 are formed in the second region II. The second gate electrode 247 may include metal layers MG3 and MG4.

24 to 26, the first recess 125 is formed in the first fin F1 on both sides of the first gate electrode 147 in the first region I, and the second region is in the second region II. The second recess 225 is formed in the second fin F2 on both sides of the gate electrode 247.

In this case, the depth of the first recess 125 of the first fin-type transistor 101 and the depth of the second recess 225 of the second fin-type transistor 201 may be formed to be different from each other. Forming the first recess 125 and forming the second recess 225 may proceed separately.

For example, etching is performed using a first mask exposing the first region I and not exposing the second region II. Thereafter, etching may be performed using a second mask exposing the second region II and not exposing the first region I. FIG. The etching method may be formed by using dry etching or by combining wet etching and dry etching.

Referring again to FIGS. 1 through 3, the first source / drain 161 is formed in the first recess 125, and the second source / drain 261 is formed in the second recess 225. . For example, the first source / drain 161 may be in the form of an elevated source / drain.

In addition, forming the first source / drain 161 and the second source / drain 261 can be formed by an epi process. In addition, depending on whether the first fin transistor 101 and the second fin transistor 201 are PMOS or NMOS transistors, the materials of the first source / drain 161 and the second source / drain 261 may vary.

In addition, if necessary, impurities may be in-situ doped during the epi-process.

In addition, if necessary, the first recess 125 and the second recess 225 may be filled with a metal rather than a semiconductor material.

Hereinafter, with reference to FIGS. 27 to 29, a manufacturing method of a pin usable in a manufacturing method of an integrated circuit device according to some exemplary embodiments of the present disclosure will be described. 27 to 29 may be a method of forming the plurality of fins illustrated in FIG. 11A. For example, it may be a SIT (Sidewall Image Transfer) process. 27 to 29 exemplarily illustrate a method of manufacturing two pins, but are not limited thereto.

Referring to FIG. 27, a sacrificial pattern 501 is formed on the substrate 100. Subsequently, a mask layer 505 is formed on the substrate 100 on which the sacrificial pattern 501 is formed. The mask layer 505 may be formed conformally along the upper surface of the substrate 100 on which the sacrificial pattern 501 is formed. The sacrificial pattern 501 and the mask layer 505 may be formed of a material that is mutually etch-selective. For example, the mask layer 505 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, photoresist, spin on glass (SOG), or spin on hard mask (SOH). The sacrificial pattern 501 may be formed of a material different from the mask layer 505 among the above materials.

In addition, the sacrificial pattern 501 and the mask layer 505 may include a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition, or a spin. It may be formed by at least one selected from the coating method.

Referring to FIG. 28, a mask pattern 506 having a spacer shape is formed on sidewalls of the sacrificial pattern 501 using an etch back process. Next, the sacrificial pattern 501 is removed. The mask pattern 506 may have substantially the same width. The trench 511 may be formed between the mask patterns 506.

Referring to FIG. 5, the substrate 100 is etched using the mask pattern 506 as an etch mask. As a result, fins F11 and F12 having a constant width can be formed. By the etching process, trenches 512 may be formed between adjacent fins F11 and F12. By the etching process, the upper portion of the mask pattern 506 may be etched together so that the upper portion of the mask pattern 506 may be rounded.

Removing the mask pattern 506 completes a plurality of fins F11 and F12 spaced apart from one another and having a constant width.

30 is a block diagram of an electronic system including an integrated circuit device according to some embodiments of the present disclosure.

Referring to FIG. 30, an electronic system 1100 according to an embodiment of the present invention may include a controller 1110, an input / output device 1120, an I / O, a memory device 1130, an interface 1140, and a bus ( 1150, bus). The controller 1110, the input / output device 1120, the memory device 1130, and / or the interface 1140 may be coupled to each other through the bus 1150. The bus 1150 corresponds to a path through which data is moved.

 The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing functions similar thereto. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The memory device 1130 may store data and / or commands. The interface 1140 may perform a function of transmitting data to or receiving data from the communication network. The interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired / wireless transceiver. Although not shown, the electronic system 1100 may further include a high speed DRAM and / or an SRAM as an operation memory for improving the operation of the controller 1110. The pin type transistor according to the exemplary embodiments of the present invention may be provided in the memory device 1130 or as part of the controller 1110, the input / output device 1120, and the I / O.

 The electronic system 1100 may include a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, and a digital music player. music player, memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

31 and 32 are exemplary semiconductor systems to which an integrated circuit device may be applied, according to some embodiments of the inventive concepts. FIG. 31 is a tablet PC, and FIG. 32 shows a notebook. At least one of the integrated circuit devices 1 to 8 according to embodiments of the present invention may be used in a tablet PC, a notebook computer, or the like. It will be apparent to those skilled in the art that the integrated circuit device according to some embodiments of the present invention may be applied to other integrated circuit devices that are not illustrated.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

101: first fin transistor F1: first fin
D1: first distance 125: first recess
147: First gate electrode 161: First source / drain
201: second fin transistor F2: second fin
D2: second distance 225: second recess
247: second gate electrode 261: second source / drain

Claims (20)

A substrate comprising a first region and a second region;
A first nanowire transistor comprising a first source / drain and disposed in the first region of the substrate; And
A second nanowire transistor comprising a second source / drain and disposed in the second region of the substrate,
The first source / drain has a first thickness,
And the second source / drain has a second thickness, wherein the second thickness is different from the first thickness. According to claim 1,
The first nanowire transistor includes K first nanowires stacked vertically with each other,
The second nanowire transistor includes L second nanowires stacked vertically with each other.
K and L are integers greater than one. The method of claim 2,
K and L are the same integrated circuit device. The method of claim 2,
The cross-sectional shape of the K first nanowires and the cross-sectional shape of the L second nanowires are elliptical or rectangular. The method of claim 3, wherein
The first source / drain is connected by M nanowires out of K first nanowires,
The second source / drain is connected by N nanowires out of L second nanowires,
M and N are positive integers. The method of claim 5,
M and N are different integrated circuit devices. According to claim 1,
A first gate electrode disposed in the first region of the substrate;
A second gate electrode disposed in the second region of the substrate;
The first gate electrode includes a first metal layer and a second metal layer formed on the first metal layer.
And the second gate electrode includes a third metal layer and a fourth metal layer formed on the third metal layer. According to claim 1,
A first gate insulating film disposed in the first region of the substrate;
A second gate insulating layer disposed in the second region of the substrate;
And the first gate insulating layer includes a high dielectric material having a higher dielectric constant than silicon oxide. A substrate comprising a first region and a second region;
A first transistor disposed in the first region of the substrate and including a first source / drain and K nanowires; And
A second transistor disposed in the second region of the substrate, the second transistor comprising a second source / drain and K nanowires,
The first source / drain has a first thickness,
The second source / drain has a second thickness different from the first thickness,
The first source / drain is connected to M nanowires among the K nanowires of the first transistor,
The second source / drain is connected to N nanowires of the K nanowires of the second transistor,
K is an integer greater than 1, M is a positive integer, and N is a positive integer different from M. The method of claim 9,
Wherein the first region is a logic region and the second region is an SRAM region. The method of claim 9,
And the first and second regions are logic regions. The method of claim 9,
And said first transistor is a PMOS transistor. The method of claim 9,
Wherein each of said first transistor and said second transistor is an NMOS transistor. A substrate comprising a first region and a second region;
A first fin transistor disposed in the first region of the substrate and including a first source / drain and a first channel; And
A second fin transistor disposed in the second region of the substrate and including a second source / drain and a second channel;
The first source / drain has a first thickness,
The second source / drain has a second thickness different from the first thickness,
A lower surface of the first source / drain is higher than an upper surface of the substrate,
A lower surface of the second source / drain is higher than the upper surface of the substrate;
Wherein each of said first channel and said second channel comprises silicon. The method of claim 14,
And the first region is a logic region and the second region is an SRAM region. The method of claim 14,
And the first fin type transistor is a pull up transistor, and the second fin type transistor is a pull down transistor or a pass transistor. The method of claim 14,
And said first fin transistor is a PMOS transistor. The method of claim 14,
Wherein each of the first fin transistor and the second fin transistor is a PMOS transistor. The method of claim 14,
The first stress applied to the first channel of the first fin-type transistor by the first source / drain is the second stress provided to the second channel of the second fin-type transistor by the second source / drain. And other integrated circuit devices. The method of claim 14,
And the first fin type transistor comprises a first fin having a width of 20 nm or less.

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