KR20190081072A - Light emitting display device and method for driving the same - Google Patents

Abstract

The present invention relates to a light emitting display device capable of detecting shorted high and low potential voltage lines and a method for driving the same. According to one embodiment of the present invention, the light emitting display device comprises: a display panel including pixels connected to sensing lines; a display panel driving unit configured to sense sensing voltages from the pixels through the sensing lines and convert the sensing voltages into sensing data, which is digital data, to output the sensing data; and a timing control unit configured to receive the sensing data from the display panel driving unit wherein the pixels are divided into a plurality of groups. The timing control unit outputs an error sensing signal of a first logic level voltage when a difference between sensing data of pixels of a first group of the plurality of groups and sensing data of pixels of a second group of the plurality of groups is equal to or greater than a threshold value or outputs an error sensing signal of a second logic level voltage when the difference is lower than the threshold value.

Description

TECHNICAL FIELD [0001] The present invention relates to a light emitting display device and a method of driving the same,

The present invention relates to a light emitting display and a driving method thereof.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. As display devices, various display devices such as a liquid crystal display (LCD) and a light emitting display (LED) are used. Among them, the light emitting display device can be classified into an organic light emitting display device using an organic light emitting layer as a light emitting element and a light emitting diode display device using a micro light emitting diode as a light emitting element. The light emitting display device can be driven at a low voltage, is thin, has excellent viewing angle, and has a high response speed.

The light emitting display includes a display panel in which a plurality of pixels are arranged in a matrix form. The display panel is supplied with the scan signals from the scan driver circuit to drive each of the pixels, and receives the data voltages from the data driver circuit. Further, the display panel is supplied with a plurality of power supply voltages from the power supply unit.

When a crack occurs in the light emitting display device due to an external impact, the power supply lines of the display panel may be short-circuited to each other. For example, a high potential voltage line supplied with a high potential voltage from a power supply unit and a low potential voltage line supplied with a low potential voltage from the power supply unit may be shorted to each other. In this case, an overcurrent flows from the high-potential power supply line to the low-potential power supply line, and a burnt in which the display panel is burned due to the overcurrent may occur.

The present invention provides a light emitting display device capable of detecting a short circuit between a high potential voltage line and a low potential voltage line and a driving method thereof.

The solutions according to the embodiments of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

A light emitting display according to an exemplary embodiment of the present invention includes a display panel including pixels connected to sensing lines, sensing voltages from pixels through sensing lines, converting sensing voltages into digital data sensing data, And a timing controller for receiving the sensing data from the display panel driver. The pixels are divided into a plurality of groups. The timing controller outputs an error detection signal of the first logic level voltage when the difference between the sensing data of the pixels of the first group among the plurality of groups and the sensing data of the pixels of the second group among the plurality of groups is equal to or greater than a threshold value, And outputs an error detection signal of the second logic level voltage when the difference is smaller than the threshold value.

A method of driving a light emitting display according to an exemplary embodiment of the present invention includes the steps of sensing sensing voltages from pixels through sensing lines, converting sensing voltages into digital data sensing data and outputting the sensed voltages, Outputting the error detection signal of the first logic level voltage when the difference between the sensing data of the pixels of the first group and the sensing data of the pixels of the second group among the pixels is equal to or greater than the threshold value, And outputs the error detection signal of the second logic level voltage when the difference between the sensing data of the two groups of pixels is smaller than the threshold value.

The embodiments of the present invention analyze the first sensing data sensed in the first sensing mode or the second sensed data sensed in the second sensing mode and determine whether the first power supply voltage line supplied with the high potential voltage and the first power supply voltage line A short circuit between the first electrode and the second electrode can be detected, and when a short circuit is detected, an error detection signal can be output to cut off the supply of the main power. As a result, the embodiments of the present invention can prevent an overcurrent from flowing from the first power supply voltage line to the second electrode, thereby preventing the display panel from burning out.

1 is a perspective view illustrating a light emitting display according to an embodiment of the present invention.
2 is a block diagram illustrating a light emitting display according to an embodiment of the present invention.
3 is a circuit diagram showing the pixel of FIG. 2 in detail.
4 is a waveform diagram showing a scan signal and a sensing signal supplied to the pixel in the display mode, first and second switch control signals supplied to the first and second switches, and a gate voltage and a source voltage of the driving transistor .
FIG. 5 is a diagram showing waveforms of a scan signal and a sensing signal supplied to a pixel in the first sensing mode, first and second switch control signals supplied to the first and second switches, and a gate voltage and a source voltage of the driving transistor, .
FIG. 6 is a graph showing waveforms of a scan signal and a sensing signal supplied to a pixel in the second sensing mode, first and second switch control signals supplied to the first and second switches, and a gate voltage and a source voltage of the driving transistor, .
FIG. 7 is a plan view illustrating a first substrate of a light emitting display according to an embodiment of the present invention. Referring to FIG.
8 is a cross-sectional view showing an example of a light emitting display device in a display area and a non-display area.
9 illustrates an example of first sensing data sensed from pixels of a first group and first sensing data sensed from pixels of a second group when the first power supply voltage line and the second electrode are short-circuited at point A FIG.
10 is an example showing first sensing data sensed from pixels of the first group and first sensing data sensed from pixels of the second group when the first power supply voltage line and the second electrode are short-circuited at point B FIG.
11 is a flowchart illustrating a method of driving a light emitting display according to an embodiment of the present invention.

Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

1 is a perspective view illustrating a light emitting display according to an embodiment of the present invention. 2 is a block diagram illustrating a light emitting display according to an embodiment of the present invention.

Referring to FIGS. 1 and 2, the light emitting display according to one embodiment of the present invention may be an organic light emitting display using an organic light emitting diode as a light emitting element, or a micro light emitting display using a micro light emitting diode as a light emitting element.

The light emitting display according to an exemplary embodiment of the present invention includes a display panel 110, a data driver 120, a flexible film 122, a scan driver 130, a source circuit board 140, a first flexible cable 150 The control circuit board 160, the timing control unit 170, the memory 180, the voltage supply unit 190, the system-on-chip 200, the system circuit board 210, and the second flexible cable 220 do.

The display panel 110 may include a first substrate 111 and a second substrate 112. The first substrate 111 may be formed of a glass substrate or a plastic film, and the second substrate 112 may be formed of a glass substrate, a plastic film, a sealing film, or a barrier film.

The display panel 110 includes a display area AA and a non-display area NDA provided around the display area AA. The display area AA is an area where pixels P are formed to display an image. In the display panel 110, the data lines D1 to Dm, m are positive integers of 2 or more, reference voltage lines R1 to Rp, p is a positive integer of 2 or more, scan lines S1 to Sn, n Is a positive integer of 2 or more), and the sensing signal lines SE1 to SEn are provided. The data lines D1 to Dm and the reference voltage lines R1 to Rp may intersect the scan lines S1 to Sn and the sensing signal lines SE1 to SEn. The data lines D1 to Dm and the reference voltage lines R1 to Rp may be parallel to each other. The scan lines S1 to Sn and the sensing signal lines SE1 to SEn may be parallel to each other.

Each of the pixels P includes one of the data lines D1 to Dm, one of the reference voltage lines R1 to Rp, one of the scan lines S1 to Sn, and one of the sensing signal lines SE1 to SEn, respectively. Each of the pixels P of the display panel 10 may include a light emitting element EL and a plurality of transistors for supplying current to the light emitting element EL as shown in FIG. A detailed description of each of the pixels P of the display panel 10 will be given later with reference to FIG.

The data driver 120 and the scan driver 130 may be referred to as a display panel driver.

The data driver 120 may include at least one source driver IC (integrated circuits) 121 as shown in FIG. Although the data driver 120 includes eight source drive ICs 121 in FIG. 2, the number of the source drive ICs 121 is not limited thereto.

Each source drive IC 121 may be mounted on each flexible film 122. Each flexible film 122 may be a tape carrier package or a chip on film. Each flexible film 122 can be bent or bent. Each flexible film 122 may be attached to the lower substrate 111 and the source circuit board 140. Each flexible film 122 may be attached to the first substrate 111 by a tape automated bonding (TAB) method using an anisotropic conductive film, Lines. ≪ / RTI >

Each of the source drive ICs 121 may include a data voltage supply unit 121A, an analog digital converter (ADC) 121B, and a switching unit 121C, as shown in FIG.

A data voltage supply unit 121A is connected to the data lines to supply data voltages. The data voltage supply unit 121A receives the digital data and the data timing control signal DCS from the timing control unit 170. [ The digital data may be either the compensated video data (CVDATA), the first and second sensing digital data (PDATA1, PDATA2).

The data voltage supplier 121A receives the compensated video data (CVDATA) in the display mode and converts the compensated video data (CVDATA) into the luminescent data voltages according to the data timing control signal (DCS) and applies them to the data lines. The display mode is a mode in which pixels P emit light to display an image. The light emission data voltage is a voltage for causing the light emitting element EL of the pixel P to emit light at a predetermined luminance.

The data voltage supply unit 121A receives the first sensing digital data PDATA1 in the electron mobility sensing mode and converts the first sensing digital data PDATA1 into the first sensing data voltage in accordance with the data timing control signal DCS To the data lines. The electron mobility sensing mode is a sensing mode for sensing the source voltage of the driving transistor DT according to the first sensing data voltage to compensate for the electron mobility of the driving transistor of each of the pixels P. [

The data voltage supply unit 121A receives the second sensing digital data PDATA2 in the threshold voltage sensing mode and converts the second sensing digital data PDATA2 into the second sensing data voltage in accordance with the data timing control signal DCS Data lines. The threshold voltage sensing mode is a sensing mode for sensing the source voltage of the driving transistor according to the second sensing data voltage to compensate the threshold voltage of the driving transistor of each of the pixels P. [

Hereinafter, the electron mobility sensing mode is referred to as a first sensing mode and the threshold voltage sensing mode is referred to as a second sensing mode for convenience of explanation.

The ADC 121B converts the voltages sensed from the reference voltage lines in the first sensing mode and the second sensing mode into digital data sensing data SD1 / SD2 and outputs the digital data sensing data SD1 / SD2 to the timing controller 170. The ADC 121B converts the voltages sensed from the reference voltage lines into the first sensing data SD1 in the first sensing mode and outputs the first sensing data SD1 to the timing controller 170. [ The ADC 121B converts the voltages sensed from the reference voltage lines into the second sensing data SD2 in the second sensing mode and outputs the second sensing data SD2 to the timing controller 170. [

The switching unit 121C switches the connection between the reference voltage lines and the voltage supply 190 and switches the connection between the reference voltage lines R1 to Rz and the ADC 140. [ 3, the switching unit 121C includes a first switch SW1 connected between each reference voltage line and the voltage supply unit 190, a second switch SW1 connected between each reference voltage line and the ADC 121B, (SW2).

The scan driver 130 includes a scan signal output unit 131 and a sensing signal output unit 132. The scan signal output unit 131 is connected to the scan lines S1 to Sn to apply scan signals. The scan signal output unit 131 generates scan signals according to a scan timing control signal SCS input from the timing controller 170 and applies the scan signals to the scan lines S1 to Sn.

The sensing signal output unit 132 is connected to the sensing signal lines SE1 to SEn to apply sensing signals. The sensing signal output unit 132 generates sensing signals according to the sensing timing control signal SENCS input from the timing controller 170 and applies the sensing signals to the sensing signal lines SE1 to SEn.

The scan signal output unit 131 and the sensing signal output unit 132 may include a plurality of transistors and may be formed directly in the non-display area NDA of the display panel 110 in a gate driver in panel (GIP) manner. Alternatively, the scan signal output unit 131 and the sensing signal output unit 132 may be mounted on a gate flexible film formed in the form of a driving chip and attached to the first substrate 111 of the display panel 110 have. In this case, the scan signal output unit 131 and the sensing signal output unit 132 may be formed in a chip form like an integrated circuit.

The source circuit board 140 may include first connectors 151 for connection to the first flexible cables 150. The source circuit board 140 may be connected to the first flexible cables 150 through the first connectors 151. [ The source circuit board 50 may be a flexible printed circuit board or a printed circuit board.

The control circuit board 160 may include second connectors 152 for connection to the first flexible cables 150. The control circuit board 160 may be connected to the first flexible cables 150 through the second connectors 152.

1, the source circuit board 140 and the control circuit board 160 are connected to a plurality of first flexible cables 150 through a plurality of first connectors 151 and a plurality of second connectors 152 However, the present invention is not limited thereto. That is, each of the source circuit board 140 and the control circuit board 160 may be connected to one first flexible cable 150 through one first connector 151 and one second connector 152.

The timing controller 170 receives the digital video data VDATA and timing signals from the system-on-chip 200. The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing controller 170 generates control signals for controlling the operation timings of the data voltage supplier 121A, the scan signal output unit 131, and the sensing signal output unit 132. [ The control signals include a data timing control signal DCS for controlling the operation timing of the data voltage supply unit 121A, a scan timing control signal SCS for controlling the operation timing of the scan signal output unit 131, And a sensing timing control signal (SENCS) for controlling the operation timing of the unit (132).

The timing controller 170 may control the light emitting display device to one of a display mode, a first sensing mode, and a second sensing mode.

The display mode is a mode for emitting pixels P by supplying emission data voltages according to the compensation video data (CVDATA) to the pixels (P).

The first sensing mode supplies the first sensing data voltage according to the first sensing digital data PDATA1 to the pixels P and supplies predetermined voltages of the pixels P through the reference voltage lines R1 to Rp Sensing mode. Specifically, the first sensing mode is a mode for sensing the source voltage of the driving transistor according to the first sensing data voltage as the first sensing data SD1 to compensate the electron mobility of the driving transistor of each of the pixels P . The first sensing mode may be performed or omitted before displaying the image on the display panel 110 as soon as the light emitting display is turned on. Further, when the display panel 110 is displaying an image, the first sensing mode is used to sense the source voltages of the driving transistors of some pixels of the display panel 110 during the vertical blank period to the first sensing data SD1 .

The second sensing mode supplies a second sensing data voltage according to the second sensing digital data PDATA2 to the pixels P and supplies predetermined voltages of the pixels P through the reference voltage lines R1 to Rp Sensing mode. Specifically, the second sensing mode is a mode for sensing the source voltage of the driving transistor according to the second sensing data voltage with the second sensing data SD2 to compensate the threshold voltage of the driving transistor of each of the pixels P. The second sensing mode may be performed or omitted before the light emitting display is turned off.

The timing controller 170 converts the digital video data VDATA into the compensated video data CVDATA using the compensation data CDATA stored in the memory 180 in the display mode. The timing control unit 170 outputs the compensated video data CVDATA and the data timing control signal DCS to the data voltage supply unit 121A in the display mode and supplies the scan timing control signal SCS to the scan signal output unit 131 And outputs the sensing timing control signal SENCS to the sensing signal output section 132. [

The timing control unit 170 outputs the first sensing digital data PDATA1 and the data timing control signal DCS stored in the memory 180 to the data voltage supply unit 121A in the first sensing mode and supplies the scan timing control signal SCS To the scan signal output unit 131 and outputs the sensing timing control signal SENCS to the sensing signal output unit 132. [ The timing controller 170 can receive the first sensing data SD1 from the ADC 121B in the first sensing mode and generate new compensation data CDATA according to the first sensing data SD1, ). That is, the timing controller 170 updates the compensation data CDATA stored in the memory 180 by reflecting the first sensing data SD1 sensed in the first sensing mode. The first sensing data SD1 is data obtained by converting the source voltage of the driving transistor according to the first sensing data voltage from the ADC 121B to digital data in each pixel P in the first sensing mode.

The timing control unit 170 outputs the second sensing digital data PDATA2 and the data timing control signal DCS stored in the memory 180 to the data voltage supply unit 121A in the second sensing mode and supplies the scan timing control signal SCS To the scan signal output unit 131 and outputs the sensing timing control signal SENCS to the sensing signal output unit 132. [ The second sensing digital data PDATA2 is different from the first sensing digital data PDATA1. The timing controller 170 receives the second sensing data SD2 from the ADC 121B in the second sensing mode and generates new compensation data CDATA in accordance with the second sensing data SD2, . That is, the timing controller 170 updates the compensation data CDATA stored in the memory 180 by reflecting the second sensing data SD2 sensed in the second sensing mode. The second sensing data SD2 is data obtained by converting the source voltage of the driving transistor corresponding to the second sensing data voltage from the ADC 121B to digital data in each pixel P in the second sensing mode.

In addition, the timing controller 170 may receive a turn-on signal of the display device that indicates whether the display device is turned on from the system-on-chip 200. [ When the turn-on signal of the display device is input, the timing controller 170 drives the display panel driver in the first sensing mode before displaying the image. In addition, the timing controller 170 outputs a drive end signal to the system on chip 200 when the second sensing mode ends.

The timing controller 170 may control the first sensing data SD1 or the second sensing data SD2 of the first group of pixels P and the first sensing data SD1 of the pixels P of the second group, The error detection signal EDS of the first logic level voltage is output to the system on chip 200 when the difference between the second sensing data SD2 is equal to or greater than the threshold value, And outputs a voltage error detection signal (EDS) to the system on chip 200. That is, when a large difference occurs between the first sensing data SD1 or the second sensing data SD2 between the pixels P of the first group and the pixels P of the second group , It may determine that there is a short circuit between the first power supply voltage line and the second power supply voltage line and output the error detection signal EDS to the system on chip 200 accordingly. A detailed description of the error detection signal (EDS) output of the timing control unit 170 will be given later with reference to FIG.

The timing controller 170 controls the first switch SW1 of the switch unit 121C of the data driver 120 and the first switch control signal SCS1 for controlling the second switch SW2. 2 switch control signal SCS2.

The memory 180 stores the first sensing digital data PDATA1, the second sensing digital data PDATA2, and the compensation data CDATA. The timing controller 170 reads the first sensing digital data PDATA1, the second sensing digital data PDATA2 and the compensation data CDATA from the memory 180 and outputs the first sensing data SD1, It is possible to write new compensation data CDATA calculated by using the second sensing data SD2. Memory 180 may include volatile memories and non-volatile memory. The volatile memory may be a DDR memory, and the nonvolatile memory may be a NAND flash memory.

The voltage supplying unit 190 generates a reference voltage VREF from the main power supplied from the main power supplying unit 230 of the system circuit board 210 and supplies the reference voltage VREF to the source driving ICs 121 of the data driving unit 120. In addition, the power supply unit 190 generates a first power voltage EVDD corresponding to a high potential voltage and a second power voltage EVSS corresponding to a low potential voltage from the main power source MV, And supplies the driving voltages to the source drive ICs 121A, the scan signal output unit 131, the sensing signal output unit 132, the timing control unit 170, and the memory 180. [

The timing control unit 170, the memory 180, and the voltage supply unit 190 may be mounted on the control circuit board 160. In this case, the timing control unit 170 and the voltage supply unit 190 may be formed in a chip form like an integrated circuit. The control circuit board 160 may be a flexible printed circuit board or a printed circuit board.

The system-on-chip 200 can convert the digital video data (CVDATA) input from the outside into the resolution of the light emitting display device and output the converted video data to the timing controller 170. The system-on-chip 200 may perform various image quality processing algorithms on the digital video data (CVDATA) as well as the resolution conversion of the inputted digital video data (CVDATA), and then output the resultant to the timing controller 170. In addition, the system-on-chip 200 may output a turn-on signal indicating whether the display device is turned on, together with the digital video data (CVDATA), to the timing controller 170.

The system-on-chip 200 receives the drive end signal from the timing controller 170. In this case, the system-on-chip 200 may block the main power supply unit 230 from outputting the main power supply MV. The system on chip 200 outputs a shutdown signal BS of the first logic level voltage to the main power supply unit 230 when receiving the error detection signal EDS of the first logic level voltage from the timing control unit 170 So that the main power supply 230 can be prevented from outputting the main power MV. When the system on chip 200 receives the error detection signal EDS of the second logic level voltage from the timing controller 170, the system on chip 200 outputs the shutoff signal BS of the second logic level voltage to the main power supply 230, And does not block the main power supply 230 from outputting the main power MV.

The system on chip 200 and the main power supply 230 may be mounted on the system circuit board 210. In this case, the system-on-chip 200 and the main power supply unit 230 may be formed in a chip form like an integrated circuit. The system circuit board 210 may be a flexible printed circuit board or a printed circuit board.

The control circuit board 160 may include third connectors 221 for connection to the second flexible cables 220. [ The control circuit board 160 may be connected to the second flexible cables 220 through the third connectors 221. The system circuit board 210 may include fourth connectors 222 for connection to the second flexible cables 220. The system circuit board 210 may be connected to the second flexible cables 220 through the fourth connectors 222. [

1 illustrates that the control circuit board 160 and the system circuit board 210 are connected to the plurality of flexible cables 220 through the plurality of third connectors 221 and the plurality of fourth connectors 222 , But is not limited thereto. That is, the control circuit board 160 and the system circuit board 210 may be connected to one second flexible cable 220 through one third connector 221 and one fourth connector 222.

3 is a circuit diagram showing the pixel of FIG. 2 in detail.

In FIG. 3, for the sake of convenience of explanation, a data line Dj (j is a positive integer satisfying 1? J? M) data line Dj, a u (u is a positive integer satisfying 1? A pixel P connected to a line Ru, a kth (k is a positive integer satisfying 1? K? N) scan line Sk and a kth sensing signal line SEk, a data voltage supply unit 121A Only the first switch SW1 and the second switch SW2 of the ADC 121B and the switching unit 121C are shown.

3, the pixel P of the display panel 10 includes a light emitting element EL, a driving transistor DT, a first switching transistor ST1, a second switching transistor ST2, and a capacitor Cst ).

The light emitting element EL emits light in accordance with the current supplied through the driving transistor DT. The light emitting device EL may be implemented as an organic light emitting diode or a micro light emitting diode. When the light emitting device EL is implemented as an organic light emitting diode, the light emitting device EL includes an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer ), And a cathode electrode. In the light emitting device EL, when a voltage is applied to the anode electrode and the cathode electrode, holes and electrons move to the organic light emitting layer through the hole transporting layer and the electron transporting layer, respectively. The anode electrode of the light emitting element EL is connected to the source electrode of the driving transistor DT and the cathode electrode can be connected to the second power supply line VSL to which a low potential voltage lower than the high potential voltage is supplied.

The driving transistor DT adjusts the current flowing from the first power supply line (EVL) supplied with the first power supply voltage to the light emitting element (EL) according to the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first switching transistor ST1, the source electrode thereof is connected to the anode electrode of the light emitting element EL, and the drain electrode thereof is connected to the first And may be connected to a power supply line (EVL).

The first switching transistor ST1 is turned on by the kth scan signal of the kth scan line Sk to connect the jth data line Dj to the gate electrode of the driving transistor DT. The first electrode of the first switching transistor T1 is connected to the kth scan line Sk and the first electrode of the first switching transistor T1 is connected to the gate electrode of the first driving transistor DT1. .

The second switching transistor ST2 is turned on by the kth sensing signal of the kth sensing signal line SEk to connect the u th reference voltage line Ru to the source electrode of the driving transistor DT. The gate electrode of the second switching transistor ST3 is connected to the kth sensing signal line SEk and the first electrode thereof is connected to the u th reference voltage line Ru and the second electrode is connected to the source of the driving transistor DT Can be connected to the electrode.

It should be noted that the first electrode of each of the first and second switching transistors ST1 and ST2 may be a source electrode and the second electrode may be a drain electrode. That is, the first electrode of each of the first and second switching transistors ST1 and ST2 may be a drain electrode, and the second electrode may be a source electrode.

The capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor DT. The capacitor Cst stores the difference voltage between the gate voltage of the driving transistor DT and the source voltage.

The driving transistor DT and the first and second switching transistors ST1 and ST2 may be formed of a thin film transistor. Although the driving transistor DT and the first and second switching transistors ST1 and ST2 are formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in FIG. 3, the present invention is not limited thereto. shall. The driving transistor DT and the first and second switching transistors ST1 and ST2 may be formed of a P-type MOSFET. In this case, the timing charts of Figs. 4, 5, and 6 can be appropriately modified to match the characteristics of the P-type MOSFET.

4 is a waveform diagram showing a scan signal and a sensing signal supplied to the pixel in the display mode, first and second switch control signals supplied to the first and second switches, and a gate voltage and a source voltage of the driving transistor .

Referring to FIG. 4, one frame period in the display mode may include a first period t1 and a second period t2. The first period t1 is a period in which the light emission data voltage EVdata is supplied to the gate electrode of the driving transistor DT and the source electrode is initialized to the reference voltage VREF. The second period t2 is a period during which the light emitting element EL emits light in accordance with the current Ids of the driving transistor DT. The first period t1 may be one horizontal period. One horizontal period indicates a period during which the data voltages are supplied to the pixels P of one horizontal line.

The kth scan signal SCANk of the kth scan line Sk and the kth sensing signal SENSk of the kth sensing signal line SEk are supplied as the gate-on voltage Von during the first period t1, And is supplied to the gate-off voltage Voff during the second period t2. The first and second switching transistors ST1 and ST2 of the pixel P may be turned on by the gate on voltage Von and turned off by the gate off voltage Voff.

The first switch control signal SCS1 may be supplied to the first logic level voltage V1 during the first period t1 and the second period t2. The second switch control signal SCS2 may be supplied to the second logic level voltage V2 during the first period t1 and the second period t2. Each of the first and second switches SW1 and SW2 may be turned on by a first logic level voltage and turned off by a second logic level voltage. Accordingly, during the first period t1 and the second period t2 of the display mode, the first switch SW1 is turned on by the first switch control signal SCS1 of the first logic level voltage V1 , And the second switch SW2 is turned off by the second switch control signal SCS2 of the second logic level voltage V2. Therefore, in the display mode, the reference voltage VREF is supplied from the reference voltage supply circuit 190 to the u th reference voltage line Ru.

Hereinafter, the operation of the pixel P during the first period t1 and the second period t2 of the display mode will be described in detail with reference to FIG. 3 and FIG.

First, during the first period t1, the first switching transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk. During the first period t1, the second switching transistor ST2 is turned on by the kth sensing signal SENSk of the gate-on voltage Von supplied to the kth sensing signal line SEk. The light emitting data voltage EVdata of the jth data line Dj is supplied to the gate electrode of the driving transistor DT due to the turn-on of the first switching transistor ST1 during the first period t1. The reference voltage VREF of the u th reference voltage line Ru is supplied to the source electrode of the driving transistor DT due to the turn-on of the second switching transistor ST2 during the first period t1.

Second, during the second period t2, the first switching transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage Voff supplied to the k-th scan line Sk. During the second period t2, the second switching transistor ST2 is turned off by the kth sensing signal SENSk of the gate-off voltage Voff supplied to the kth sensing signal line SEk.

The current Ids corresponding to the voltage difference between the gate voltage Vg and the source voltage Vs of the driving transistor DT flows to the light emitting element EL during the second period t2. As a result, the light emitting element EL emits light. Hereinafter, for convenience of explanation, "current Ids flowing through the driving transistor DT" in accordance with the voltage difference between the gate voltage Vg and the source voltage Vs of the driving transistor DT is referred to as " (Ids) ".

As described above, one embodiment of the present invention supplies the emission data voltage (EVdata) to the pixel P in the display mode. The emission data voltage EVdata is a data voltage generated according to the compensated video data CVDATA that compensates the digital video data DATA using the compensation data CDATA. As a result, according to one embodiment of the present invention, the light emitting device EL of the pixel P emits light in accordance with the threshold voltage of the driving transistor DT and the current Ids of the driving transistor DT, can do. Thus, one embodiment of the present invention can increase the luminance uniformity of the pixels P.

FIG. 5 is a diagram showing waveforms of a scan signal and a sensing signal supplied to a pixel in the first sensing mode, first and second switch control signals supplied to the first and second switches, and a gate voltage and a source voltage of the driving transistor, .

Referring to FIG. 5, one frame period in the first sensing mode may include first to third periods t1 'to t3'. The first period t1 'is a period for initializing the source electrode of the driving transistor DT to the reference voltage VREF. The second period t2 'is a period for applying the first sensing data voltage SVdata1 to the gate electrode of the driving transistor DT and sensing the source voltage of the driving transistor DT. The third period t3 'is a rest period.

The kth scan signal SCANk of the kth scan line Sk is supplied as the gate-on voltage Von during the second period t2 '. The kth sensing signal SENSk of the kth sensing signal line SEk is supplied as the gate-on voltage Von during the first period t1 'and the second period t2'.

The first switch control signal SCS1 is supplied to the first logic level voltage V1 during the first period t1 'and the second logic level voltage V1 during the second period t2' and the third period t3 ' (V2). The second switch control signal SCS2 is supplied to the second logic level voltage V2 during the first period t1 'and the third period t3', and during the second period t2 ' (V1).

Hereinafter, the operation of the pixel P in the first sensing mode will be described in detail with reference to FIGS.

First, during the first period t1 ', the first switching transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage Voff supplied to the k-th scan line Sk , The second switching transistor ST2 is turned on by the kth sensing signal SENSk of the gate-on voltage Von supplied to the kth sensing signal line SEk. During the first period t1 ', the first switch SW1 is turned on by the first switch control signal SCS1 of the first logic level voltage V1 and the second switch SW2 is turned on by the second logic level And is turned off by the second switch control signal SCS2 of the voltage V2.

The reference voltage VREF is supplied from the reference voltage supply circuit 190 to the u th reference voltage line Ru due to the turn-on of the first switch SW1 during the first period t1 '. The reference voltage VREF of the u th reference voltage line Ru is supplied to the source electrode of the driving transistor DT due to the turn-on of the second switching transistor ST2 during the first period t1 '. That is, the source electrode of the driving transistor DT is initialized to the reference voltage VREF.

Secondly, during the second period t2 ', the first switching transistor ST1 is turned on by the kth scan signal SCANk of the gate-on voltage Von supplied to the kth scan line Sk , The second switching transistor ST2 is turned on by the kth sensing signal SENSk of the gate-on voltage Von supplied to the kth sensing signal line SEk. During the second period t2 ', the first switch SW1 is turned off by the first switch control signal SCS1 of the second logic level voltage V2 and the second switch SW2 is turned off by the first logic level And is turned on by the second switch control signal SCS2 of the voltage V1.

The reference voltage VREF is not supplied to the u th reference voltage line Ru due to the turn-off of the first switch SW1 during the second period t2 '. Also, the reference voltage line Ru is connected to the ADC 121B due to the turn-on of the second switch SW2 during the second period t2 '. The second sensing data voltage SVdata2 is supplied to the gate electrode of the driving transistor DT due to the turn-on of the first switching transistor ST1 during the second period t2 '. The second sensing data voltage SVdata2 is lower than the first sensing data voltage SVdata1. The source electrode of the driving transistor DT is connected to the ADC 121B through the u th reference voltage line Ru due to the turn-on of the second switching transistor ST2 during the second period t2 '.

Since the voltage difference (Vgs = SVdata2-VREF) between the gate electrode and the source electrode of the driving transistor DT is larger than the threshold voltage (Vth) of the driving transistor DT during the second period t2 ' (DT) flows current.

At this time, the current of the driving transistor DT can be defined as shown in Equation (2).

&Quot; W "is the channel width of the driving transistor DT," L "is the capacitance of the driving transistor DT, Quot; means the channel length of the driving transistor DT.

Since the current of the driving transistor DT is proportional to the electron mobility K of the driving transistor DT as shown in Equation 1, the rising amount of the source voltage Vs of the driving transistor DT during the second period t2 ' Is proportional to the electron mobility K of the driving transistor DT. That is, the greater the electron mobility of the driving transistor DT, the greater the amount of rise of the source voltage Vs of the driving transistor DT during the second period t2 '.

5 shows the relationship between the electron mobility K of the driving transistor DT and the electron mobility K of the driving transistor DT during the second period t2 ' Is defined as?. The source voltage of the driving transistor DT rises to "VREF + alpha" according to the electron mobility K as shown in FIG. Therefore, the voltage at which the electron mobility K of the driving transistor DT is reflected is sensed to the source electrode of the driving transistor DT during the second period t2 '.

Third, the first switching transistor ST1, the second switching transistor ST2, the first switch SW1, and the second switch SW2 are both turned off during the third period t3 '.

As described above, the embodiment of the present invention can sense the source voltage "VREF + alpha" of the driving transistor in which the electron mobility K of the driving transistor DT is reflected in the first sensing mode.

FIG. 6 is a graph showing waveforms of a scan signal and a sensing signal supplied to a pixel in the second sensing mode, first and second switch control signals supplied to the first and second switches, and a gate voltage and a source voltage of the driving transistor, .

Referring to FIG. 5, one frame period in the first second sensing mode may include first through fourth periods t1 '' to t4 ''. The first period t1 is a period for initializing the source electrode of the driving transistor DT to the reference voltage VREF. The second period t2 " (SVdata1). The third period t3 "is a period for sensing the source voltage of the driving transistor DT. The fourth period t4" is the idle period.

The kth scan signal SCANk of the kth scan line Sk is supplied as the gate-on voltage Von during the second period t2 '' and the third period t3 ''. The kth sensing signal SENSk of the kth sensing signal line SEk is supplied to the gate-on voltage Von during the first to third periods t1 'to t3' '. The first and second switching transistors ST1 and ST2 of the pixel P may be turned on by the gate on voltage Von and turned off by the gate off voltage Voff.

The first switch control signal SCS1 is supplied to the first logic level voltage V1 during the first period t1 ", and the second logic level voltage V2 during the second to fourth periods t2 & The second switch control signal SCS2 is supplied to the second logic level voltage V2 during the first period t1 ", the second period t2" and the fourth period t4 " Is supplied to the first logic level voltage V1 during the third period t3 ". Each of the first and second switches SW1, SW2 is turned on by the first logic level voltage, Can be turned off by a voltage.

Hereinafter, the operation of the pixel P in the second sensing mode will be described in detail with reference to FIG. 3 and FIG.

First, during the first period t1 ", the first switching transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage Voff supplied to the k-th scan line Sk The second switching transistor ST2 is turned on by the kth sensing signal SENSk of the gate-on voltage Von supplied to the kth sensing signal line SEk. During the first period t1 ' 1 switch SW1 is turned on by the first switch control signal SCS1 of the first logic level voltage V1 and the second switch SW2 is turned on by the second switch control of the second logic level voltage V2 And is turned off by the signal SCS2.

The reference voltage VREF is supplied to the u th reference voltage line Ru from the reference voltage supply circuit 190 due to the turn-on of the first switch SW1 during the first period t1 & the reference voltage VREF of the u-th reference voltage line Ru is supplied to the source electrode of the driving transistor DT due to the turn-on of the second switching transistor ST2 during the period t1 ". That is, the source electrode of the driving transistor DT is initialized to the reference voltage VREF.

Second, during the second period t2 ", the first switching transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk The second switching transistor ST2 is turned on by the kth sensing signal SENSk of the gate-on voltage Von supplied to the kth sensing signal line SEk. During the second period t2 ' 1 switch SW1 is turned off by the second switch control signal SCS2 of the second logic level voltage V2 and the second switch SW2 is turned off by the second switch control of the second logic level voltage V2 And is turned off by the signal SCS2.

The reference voltage VREF is not supplied to the u th reference voltage line Ru due to the turn-off of the first switch SW1 during the second period t2 ". Further, during the second period t2 " 1 switching transistor ST1 is turned on, the first sensing data voltage SVdata1 is supplied to the gate electrode of the driving transistor DT.

Since the voltage difference (Vgs = SVdata1-VREF) between the gate electrode and the source electrode of the driving transistor DT is greater than the threshold voltage of the driving transistor DT during the second period t2 ", the driving transistor DT The source voltage of the driving transistor DT is set to "SVdata1-Vth1" as shown in FIG. 5, so that the current flows until the voltage difference Vgs between the gate electrode and the source electrode reaches the threshold voltage Vth1. The threshold voltage of the driving transistor DT is sensed to the source electrode of the driving transistor DT during the second period t2 ".

Third, during the third period t3 ", the first switching transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk The second switching transistor ST2 is turned on by the kth sensing signal SENSk of the gate-on voltage Von supplied to the kth sensing signal line SEk. During the third period t3 " 1 switch SW1 is turned off by the second switch control signal SCS2 of the second logic level voltage V2 and the second switch SW2 is turned off by the second switch control of the first logic level voltage V1 And is turned on by the signal SCS2.

The u th reference voltage line Ru is connected to the ADC 121B due to the turn-on of the second switch SW2 during the third period t3 ". During the third period t3 ", the second switching transistor ST2), the source electrode of the driving transistor DT is connected to the ADC 121B via the u < th > reference voltage line Ru. Therefore, the ADC 121B can sense the source voltage of the driving transistor DT, that is, "SVdata1-Vth1".

Fourth, the first switching transistor ST1, the second switching transistor ST2, the first switch SW1, and the second switch SW2 are both turned off during the fourth period t4 ".

As described above, the embodiment of the present invention can sense the source voltage "SVdata1-Vth1" of the driving transistor DT in which the threshold voltage Vth1 of the driving transistor DT is reflected in the second sensing mode.

FIG. 7 is a plan view illustrating a first substrate of a light emitting display according to an embodiment of the present invention. Referring to FIG.

7, only the first substrate 111, the display area DA, the pad areas PA, the first power supply voltage lines VDDL, and the second electrode 263 Respectively.

Referring to FIG. 7, a display area DA for displaying an image including pixels P is formed on a first substrate 111. Each of the pixels P may include first through fourth sub-pixels SP1, SP2, SP3, and SP4. For example, the first through fourth sub-pixels SP1, SP2, SP3, and SP4 may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. Although FIG. 7 illustrates that each of the pixels P includes four sub-pixels, the embodiments of the present invention are not limited thereto. For example, each of the pixels P may include only three sub-pixels. In this case, the three sub-pixels may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

The first power supply voltage lines VDDL include horizontal lines HL and vertical lines VL. Each of the vertical lines VL may be formed to intersect each of the sub-pixels SP1, SP2, SP3, SP4 in the display area DA. To this end, each of the vertical lines VL may be formed in a first direction (Y-axis direction) in parallel with the data lines D1 to Dm in the display area DA. Thus, each of the sub-pixels SP1, SP2, SP3, and SP4 can receive the first power source voltage VDD1 from any one of the vertical lines VL.

The horizontal lines HL are aligned in the second direction (X-axis direction) in parallel with the scan lines S1 to Sn in the non-display region, in order to connect the vertical lines VL formed in the first direction (Y- As shown in FIG. The horizontal lines HL may be formed on one side of the display area DA in which the pad area PA is formed. Further, the vertical lines VL may be connected in common to at least one horizontal line HL. In FIG. 7, four vertical lines VL are connected to each other by one horizontal line HL formed in the second direction (X-axis direction) in the non-display area, but the embodiments of the present invention are not limited thereto .

The pixels P may be divided into a plurality of groups. The pixels P may be divided based on one horizontal line HL and vertical lines VL connected to one horizontal line HL. For example, in FIG. 7, pixels P including sub-pixels SP1, SP2, SP3, and SP4 connected to vertical lines VL connected to a horizontal line HL formed on the left- (P) of the group G1. 7, pixels P including sub-pixels SP1, SP2, SP3, and SP4 connected to vertical lines VL connected to a horizontal line HL formed second from the left are referred to as second (P) of the group G1. 7, the pixels P including the sub-pixels SP1, SP2, SP3, and SP4 connected to the vertical lines VL connected to the horizontal line HL formed on the rightmost side are referred to as s Is defined as pixels (P) of a group (Gs) of two or more positive integers).

The second electrode 263 may be a cathode electrode, and thus the second power source voltage may be applied to the second electrode 263. And the second electrode 263 may be arranged to cover the display area DA.

On the other hand, the distance between the first power supply voltage line (VDDL) and the second electrode 263 in the region where the first power supply voltage line (VDDL) and the second electrode 263 overlap with each other in the non- One power supply voltage line VDDL and the second electrode 263 may be short-circuited. When the first power supply voltage VDD and the second electrode 263 are short-circuited, the first power supply voltage VDD is a high potential and the second power supply voltage VSS is a low potential voltage, A leakage current may flow from the first power supply voltage of the voltage line VDDL to the second electrode 263. [ As a result, the potential of the first power supply voltage VDD can be lowered. Hereinafter, this will be described in detail with reference to FIG.

8 is a cross-sectional view showing an example of a light emitting display device in a display area and a non-display area.

Referring to FIG. 8, a thin film transistor layer may be formed on the first substrate 111. The thin film transistors 210, the scan lines S1 to Sn, the data lines D1 to Dm, the initialization voltage lines VIL, the first power source voltage lines VDDLs, and the like are formed in the thin film transistor layer .

Each of the thin film transistors 210 includes an active layer 211, a gate electrode 212, a source electrode 213, and a drain electrode 214. An active layer 211 is formed on the first substrate 111. The active layer 211 may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. As the silicon-based semiconductor material, amorphous silicon or polycrystalline silicon may be used.

The active layer 211 may include a source region and a drain region including p-type or n-type impurities, and a channel formed between the source region and the drain region, And a lightly doped region between the adjacent source and drain regions.

A light shielding layer for shielding external light incident on the active layer 211 may be formed between the first substrate 111 and the active layer 211. [

A gate insulating layer 220 may be formed on the active layer 211. The gate insulating film 220 may be formed of an inorganic film, for example, a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), or a multilayer film thereof.

A gate electrode 212, scan lines, and initialization voltage lines VRL may be formed on the gate insulating layer 220. The gate electrode 212, the scan lines, and the initialization voltage lines VRL may be formed of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium Nd), and copper (Cu), or an alloy thereof.

An interlayer insulating layer 230 may be formed on the gate electrode 212, the scan lines, and the initialization voltage lines. The interlayer insulating film 230 may be formed of a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), or a multilayer film thereof.

A source electrode 213, a drain electrode 214, data lines, and first power supply voltage lines VDDL may be formed on the interlayer insulating layer 230. Each of the source electrode 213 and the drain electrode 214 may be connected to the active layer 211 through a contact hole passing through the gate insulating film 220 and the interlayer insulating film 230. The source electrode 213, the drain electrode 214, the data lines, and the first power supply voltage lines VDDL are formed of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au) , Nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

A protective film 240 for insulating the thin film transistor 220 may be formed on the source electrode 213, the drain electrode 214, the data lines, and the first high potential voltage lines VDDL. The protective film 240 may be formed of a silicon nitride film (SiN _x ).

The planarization layer 250 may be formed on the passivation layer 240 to flatten a step due to the thin film transistor 210. The planarization layer 250 may be formed of an organic layer such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. have.

The light emitting elements and the banks 264 are formed on the planarization film 250 and the light transmissive film 251. The light emitting device may include a first electrode 261, a light emitting layer 262, and a second electrode 263. The first electrode 261 may be an anode electrode, and the second electrode 263 may be a cathode electrode.

The first electrode 261 may be formed on the flattening film 250 at the flat portion FA. The first electrode 261 may be connected to the source electrode 213 or the drain electrode 214 of the thin film transistor 210 through the contact hole passing through the protective film 240 and the planarization film 250. The first electrode 261 is formed of a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, / ITO). ≪ / RTI > The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

The banks 264 may be formed on the planarizing film 250. Specifically, the bank 264 may be formed so as to cover a part of the first electrode 261 disposed on the planarization film 250. The bank 264 may define the light emitting regions of each of the sub-pixels SP1, SP2, SP3, and SP4. That is, the first electrode 261, the light emitting layer 262, and the second electrode 263 are sequentially stacked so that holes from the first electrode 261 and electrons from the second electrode 263 are emitted from the light- And the light emitting layer 262 may be a light emitting region. The region where the bank 264 is formed may be a non-light emitting region.

A spacer may be formed on the bank 264. The bank 264 and the spacer are formed of an organic film such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, .

A light emitting layer 262 is formed on the first electrode 261. The light emitting layer 262 may include a hole transport layer (HTL), an organic light emitting layer, and an electron transport layer (ETL). The hole transport layer serves to smoothly transfer the holes injected from the first electrode 261 to the organic light emitting layer. The organic light emitting layer may be formed of an organic material including phosphorescent or fluorescent materials. The electron transport layer functions to smoothly transfer electrons injected from the second electrode 263 to the organic light emitting layer. The light emitting layer 262 may include a hole injection layer (HIL), a hole blocking layer (HBL), an electron injection layer (EIL), and an electron transport layer in addition to the hole transport layer, And may further include an electron blocking layer (EBL).

In addition, the light emitting layer 262 may be formed in a tandem structure of two stacks or more. In this case, each of the stacks may include a hole transporting layer, an organic light emitting layer, and an electron transporting layer. When the light emitting layer 262 is formed in a tandem structure of two stacks or more, a charge generating layer may be formed between the stacks. The charge generation layer may include an n-type charge generation layer located adjacent to the bottom stack and a p-type charge generation layer formed on the n-type charge generation layer and located adjacent to the top stack. The n-type charge generation layer injects electrons into the lower stack, and the p-type charge generation layer injects holes into the upper stack. The n-type charge generation layer may be an organic layer doped with an alkali metal such as Li, Na, K, or Cs, or an alkaline earth metal such as Mg, Sr, Ba, or Ra to an organic host material having electron transporting ability. The p-type charge generating layer may be an organic layer doped with an organic host material capable of hole transporting.

The light emitting layer 262 may be formed in each of the light emitting regions EA. In this case, the light emitting layer 262 may be divided into a red light emitting layer for emitting red light, a green light emitting layer for emitting green light, and a blue light emitting layer for emitting blue light for each light emitting region EA. However, the embodiments of the present invention are not limited thereto, and the light emitting layer 262 may be a common layer commonly formed in the light emitting regions EA, and in this case, it may be a white light emitting layer that emits white light. When the light emitting layer 262 is formed as a common layer in the light emitting regions EA, color filters are required.

The second electrode 263 is formed on the light emitting layer 262. The second electrode 263 may be formed to cover the light emitting layer 262. The second electrode 263 may be a common layer formed commonly to the pixels.

The second electrode 263 may be formed of a transparent conductive material such as ITO or IZO or a transparent conductive material such as magnesium (Mg), silver (Ag), or magnesium (Mg) (Semi-transmissive Conductive Material). When the second electrode 263 is formed of a semitransparent metal material, the efficiency of outgoing light can be increased by a microcavity. A capping layer may be formed on the second electrode 263.

A sealing film 280 is formed on the light emitting element layer. The sealing film 280 serves to prevent oxygen or moisture from permeating the light emitting layer 262 and the second electrode 263. For this purpose, the sealing film 280 may comprise at least one inorganic film 281, 283. At least one of the inorganic films 281 and 283 may be formed of at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, and titanium oxide.

The sealing film 280 is formed to have a sufficient thickness to serve as a particle cover layer for preventing particles from being injected into the light emitting layer 282 and the second electrode 283 And may include one organic film 282. The organic layer 282 may be formed of a transparent material to allow light emitted from the light emitting layer 262 to pass therethrough. The organic film may be an organic material capable of passing at least 99% of light emitted from the light emitting layer 262, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin resin or a polyimide resin, but the present invention is not limited thereto.

6, a first inorganic film 281 is formed on the second electrode 283, an organic film 282 is formed on the first inorganic film 281, a second inorganic film 282 is formed on the organic film 282, The film 283 is formed, but the embodiments of the present invention are not limited thereto.

An adhesive layer 290 for bonding the sealing film 280 and the upper substrate 300 may be disposed on the sealing film 280. The adhesive layer 290 may be a transparent adhesive film or a transparent adhesive resin. The second substrate 120 may be a sealing film or a barrier film.

8, the first power supply voltage line VDDL is formed on the interlayer insulating layer 230 like the source electrode 214 and the drain electrode 215. However, the embodiments of the present invention are not limited thereto . For example, the first power supply voltage line VDDL may be formed on the gate insulating layer 220 like the gate electrode 211 in the non-display area NDA, or may be formed on the first substrate 111 and the active layer The first substrate 111 may be formed as a light shielding layer.

Since the planarization layer 250 is not formed in the non-display area NDA as shown in FIG. 8, the distance between the first power supply voltage line VDDL and the second electrode 263 is shortened, And the second electrode 263 may be short-circuited. When the first power supply voltage VDD and the second electrode 263 are short-circuited, the first power supply voltage VDD is a high potential and the second power supply voltage VSS is a low potential voltage, A leakage current may flow from the first power supply voltage of the voltage line VDDL to the second electrode 263. [ As a result, the potential of the first power supply voltage VDD can be lowered.

9 illustrates an example of first sensing data sensed from pixels of a first group and first sensing data sensed from pixels of a second group when the first power supply voltage line and the second electrode are short-circuited at point A FIG.

9, when the first power supply voltage line VDDL connected to the pixels P of the first group G1 is short-circuited with the second electrode 263 at the point A, the pixels of the first group G1 The first sensing data SD1 sensed from the first group G2 and the first sensing data SD1 sensed from the pixels of the second group G2 are shown. In FIG. 9, the X-axis represents the horizontal lines on which the pixels P are arranged, and the Y-axis represents the first sensing data SD1. The first horizontal line on the X axis corresponds to the horizontal line closest to the pad area PA and the nth horizontal line corresponds to the horizontal line farthest from the pad area PA.

Referring to FIG. 9, the point A may be defined as a point outside the other side corresponding to the opposite side of one side of the display area DA in which the pad area PA is formed. The first power supply voltage VDD is supplied to the first power supply voltage line VDDL through the pads of the pad region PA. Therefore, when the first power supply voltage line VDDL is short-circuited with the second electrode 263 from the other side of the display area DA, the first power supply voltage VDD1 is supplied from one side of the display area DA And it can be lowered toward the side. The first sensing data SG1 which is sensed from the pixels P of the first group G1 in which the first power supply voltage line VDDL is short-circuited to the second electrode 263 at the point A, DA) from one side to the other. In particular, the first sensing data SG1 sensed from the pixels P in the first group G1 and the pixels P sensed from the pixels P in the second group G2 on the other side of the display area DA 1 sensing data SG2 may differ by more than the threshold value TH as shown in FIG. Therefore, the first sensing data SG1 sensed from the pixels P of the first group G1 and the first sensing data SG2 sensed from the pixels P of the second group G2 are compared with each other, (TH), it can be determined that a short circuit has occurred between the first power supply voltage line VDDL1 and the second electrode 263.

10 is an example showing first sensing data sensed from pixels of the first group and first sensing data sensed from pixels of the second group when the first power supply voltage line and the second electrode are short-circuited at point B FIG.

10, when the first power supply voltage line VDDL connected to the pixels P of the second group G2 is shorted to the second electrode 263 at the point B, the pixels of the first group G1 The first sensing data SD1 sensed from the first group G2 and the first sensing data SD1 sensed from the pixels of the second group G2 are shown. In FIG. 10, the X-axis represents horizontal lines on which the pixels P are arranged, and the Y-axis represents the first sensing data SD1. The first horizontal line on the X axis corresponds to the horizontal line closest to the pad area PA and the nth horizontal line corresponds to the horizontal line farthest from the pad area PA.

Referring to FIG. 10, the point B may be defined as a point outside one side of the display area DA in which the pad area PA is formed. The first power supply voltage VDD is supplied to the first power supply voltage line VDDL through the pads of the pad region PA. Accordingly, when the first power supply voltage line VDDL is short-circuited with the second electrode 263 from one side of the display area DA, the first power voltage VDD1 is lowered from one side of the display area DA , And can be lowered from one side to the other side. The first sensing data SG2 sensed from the pixels P of the second group G2 shorted to the second electrode 263 by the first power supply voltage line VDDL at the point B as shown in FIG. May differ from the first sensing data SG1 sensed from the pixels P of the first group G1 on one side or the other side of the display area DA by a threshold TH or more. Therefore, the first sensing data SG1 sensed from the pixels P of the first group G1 and the first sensing data SG2 sensed from the pixels P of the second group G2 are compared with each other, (TH), it can be determined that a short circuit has occurred between the first power supply voltage line VDDL1 and the second electrode 263.

9 and 10 illustrate the first sensing data SD1. However, when the first power supply voltage line VDDL is short-circuited to the second electrode 263 at the A and B points, the second sensing data SD2, Can also be sensed in a form similar to the first sensing data SD1.

11 is a flowchart illustrating a method of driving a light emitting display according to an embodiment of the present invention.

Referring to FIG. 11, first, the timing controller 170 determines whether the current mode is the first sensing mode. (S101 in Fig. 11)

The first sensing digital data PDATA1 and the data timing control signal DCS stored in the memory 180 are output to the data voltage supply unit 121A in the first sensing mode and the scan timing control signal SCS is output to the scan signal output unit 121. [ And outputs the sensing timing control signal SENCS to the sensing signal output section 132. [ Accordingly, the timing controller 170 can receive the first sensing data SD1 from the ADC 121B in the first sensing mode. The first sensing data SD1 supplies the first sensing voltages sensed by the pixels P to the ADC 121B as digital data when the first sensing data voltage is supplied to the pixels P in the first sensing mode It is converted data.

Second, the timing controller 170 analyzes the first sensing data SD1 in the first sensing mode to determine whether the first power supply voltage VDDL and the second electrode 263 are short-circuited. (S102 in Fig. 11)

The timing controller 170 divides the pixels P into a plurality of groups and outputs the first sensing data SG1 and the second group G2 of the pixels P of the first group G1, And the first sensing data SG2 of the pixels P of the pixel P is greater than or equal to the threshold value TH. The difference between the first sensing data SG1 of the pixels P of the first group G1 and the first sensing data SG2 of the pixels P of the second group G2 as shown in Figs. It can be determined that a short circuit has occurred between the first power supply voltage line VDDL and the second electrode 263. The threshold value TH can be predetermined to be an appropriate value through a preliminary experiment.

9 and 10, the second electrode 263 is connected to the first power supply voltage line VDDL shorted to the first power supply voltage line VDDL according to the short circuit position between the first power supply voltage line VDDL and the second electrode 263 The first sensing data SD1 of the pixels P are different. Accordingly, the timing controller 170 controls the timing of the first sensing data SG1 of the pixel P of the first group G1 connected to the same scan line and the first sensing data SG1 of the pixel P of the second group G2, (SG2) is equal to or greater than the threshold value (TH). For example, the timing controller 170 controls the timing of the first sensing data SG1 of the pixel P of the first group G1 connected to the kth scan line and the data of the pixel P of the second group G2 1 sensed data SG2 is equal to or greater than the threshold value TH.

Third, the timing controller 170 determines whether the current mode is the second sensing mode. (S103 in Fig. 11)

And outputs the second sensing digital data PDATA2 and the data timing control signal DCS stored in the memory 180 to the data voltage supply unit 121A in the second sensing mode and supplies the scan timing control signal SCS to the scan signal output unit 121. [ And outputs the sensing timing control signal SENCS to the sensing signal output section 132. [ Accordingly, the timing controller 170 can receive the second sensing data SD2 from the ADC 121B in the second sensing mode. When the second sensing data voltage is supplied to the pixels P in the second sensing mode, the second sensing data SD2 is supplied from the ADC 121B to the second sensing voltages as digital data It is converted data.

Fourth, the timing controller 170 analyzes the second sensing data SD2 in the second sensing mode to determine whether the first power supply voltage VDDL and the second electrode 263 are short-circuited. (S104 in Fig. 11)

The timing controller 170 divides the pixels P into a plurality of groups and outputs the second sensing data of the pixels P of the first group G1 and the second sensing data of the pixels G2 of the second group G2 P is greater than or equal to the threshold value TH. When the difference between the second sensing data of the pixels P of the first group G1 and the second sensing data of the pixels P of the second group G2 is equal to or greater than the threshold value TH as shown in Figs. 9 and 10, , It can be determined that a short circuit has occurred between the first power supply voltage line (VDDL) and the second electrode 263. The threshold value TH can be predetermined to be an appropriate value through a preliminary experiment.

9 and 10, the second electrode 263 is connected to the first power supply voltage line VDDL shorted to the first power supply voltage line VDDL according to the short circuit position between the first power supply voltage line VDDL and the second electrode 263 The second sensing data SD2 of the pixels P are different. The timing control section 170 determines whether the difference between the second sensing data of the pixel P of the first group G1 connected to the same scan line and the second sensing data of the pixel P of the second group G2 exceeds a threshold value (TH) or more. For example, the timing controller 170 may output the second sensing data of the pixel P of the first group G1 connected to the kth scan line and the second sensing data of the pixel P of the second group G2, It is possible to determine whether or not the difference between them is equal to or greater than the threshold value TH.

Fifthly, the timing controller 170 controls the first sensing data SG1 of the pixels P in the first group G1 or the first sensing data SG1 of the pixels P in the second group G2, The error detection signal EDS of the first logic level voltage is output to the system on chip 200 when the difference between the data SG2 or the second sensing data is equal to or greater than the threshold value TH, And outputs the error detection signal (EDS) of the second logic level voltage to the system-on-chip (200). (S105 in Fig. 11)

The system on chip 200 outputs the first logic level voltage shutoff signal BS to the main power supply 230 when the error detection signal EDS of the first logic level voltage is input. The system on chip 200 outputs a shutoff signal BS of the second logic level voltage to the main power supply unit 230 when the error detection signal EDS of the second logic level voltage is inputted from the timing control unit 170 do.

The main power supply unit 230 does not output the main power source MV when the first logic level voltage shutoff signal BS is input. The power supply 190 supplies the first power voltage VDD and the second power voltage VSS as well as the reference voltage VREF to the power supply unit 190. Accordingly, And does not output driving voltages. The main power supply unit 230 outputs a main power (MV) when the second logic level voltage shutoff signal BS is input. The power supply unit 190 supplies the first power voltage VDD and the second power voltage VSS as well as the reference voltage VREF to the power supply unit 190. Therefore, Voltages can be output.

As described above, the embodiments of the present invention analyze the first sensing data SD1 sensed in the first sensing mode or the second sensing data SD2 sensed in the second sensing mode, It is possible to detect a short circuit between the first power supply voltage line VDDL and the second electrode 263 to which the low potential voltage is supplied and to output a fault detection signal EDS when a short circuit is detected, Lt; / RTI > As a result, the embodiments of the present invention can prevent an overcurrent from flowing from the first power supply voltage line (VDDL) to the second electrode 263, so that a burnt in which the display panel 110 is burned .

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

110: display panel 111: lower substrate
112: upper substrate 120: data driver
121: Source drive IC 121A: Data voltage supply unit
121B: Analogue digital converter 121C:
122: flexible film 130: scan driver
131: scan signal output unit 132: sensing signal output unit
140: source circuit board 150: first flexible cable
160: control circuit board 170: timing control unit
180: memory 190: voltage supply
200: system on chip 210: system circuit board
220: second flexible cable 230: main power supply

Claims (13)

A display panel including pixels connected to the sensing lines;
A display panel driver that senses sensing voltages from the pixels through the sensing lines, converts the sensing voltages into digital data sensing data, and outputs the sensing data; And
And a timing controller for receiving the sensing data from the display panel driver,
The pixels are divided into a plurality of groups,
Wherein the timing control unit is configured to output the error detection signal of the first logic level voltage when the difference between the sensing data of the first group of pixels among the plurality of groups and the sensing data of the pixels of the second group among the plurality of groups is equal to or greater than a threshold value, And outputs an error detection signal of a second logic level voltage when the difference is smaller than the threshold value. The method according to claim 1,
A first logic level voltage interrupting signal when the error detection signal of the first logic level voltage is inputted from the timing control unit and a second logic level voltage interrupting signal when the error detection signal of the second logic level voltage is inputted, And a system-on-chip for outputting a blocking signal. 3. The method of claim 2,
And a main power supply unit for outputting the main power when the shutoff signal of the second logic level voltage is inputted without outputting the main power when the shutoff signal of the first logic level voltage is inputted from the system on chip . The method of claim 3,
And a power supply unit for generating and outputting driving voltages for driving the display panel driver and the timing controller using the main power. 5. The method of claim 4,
A control circuit board on which the timing control unit and the power supply unit are mounted;
A system circuit board on which the system on chip and the main power supply unit are mounted; And
And a cable connecting the control circuit board and the system circuit board. The method according to claim 1,
Wherein the display panel further comprises data lines and scan lines intersecting the data lines,
Each of the pixels includes:
A light emitting element; And
And a driving transistor for controlling a driving current supplied to the light emitting element. The method according to claim 6,
When the timing control unit supplies the first sensing digital data to the display panel driving unit in the first sensing mode for sensing the electron mobility of the driving transistor, the display panel driving unit senses the first sensing voltages from the pixels And converting the first sensing voltages into first sensing data, which is digital data, and outputting the first sensing data. 8. The method of claim 7,
Wherein the timing controller is configured to detect an error of the first logic level voltage when the difference between the first sensing data of the first group of pixels connected to the same scan line and the first sensing data of the pixels of the second group is greater than or equal to the threshold value And outputs an error detection signal of the second logic level voltage when the difference is smaller than the threshold value. The method according to claim 6,
When the timing control unit supplies the second sensing digital data to the display panel driving unit in a second sensing mode in which the threshold voltage of the driving transistor is sensed, the display panel driving unit senses second sensing voltages from the pixels, And converts the second sensing voltages into second sensing data, which is digital data, and outputs the second sensing data. 10. The method of claim 9,
The timing control unit may detect an error of the first logic level voltage when the difference between the second sensing data of the first group of pixels connected to the same scan line and the second sensing data of the pixels of the second group is greater than or equal to the threshold value And outputs an error detection signal of the second logic level voltage when the difference is smaller than the threshold value. The method according to claim 1,
Further comprising first power supply voltage lines including the horizontal lines and the vertical lines,
And the plurality of vertical lines are commonly connected to at least one horizontal line. 12. The method of claim 11,
Pixels connected to the vertical lines connected to any one of the horizontal lines are defined as pixels of the first group and pixels connected to the vertical lines connected to the other one of the horizontal lines are connected to the second And the pixels are defined as the pixels of the group. Sensing the sensing voltages from the pixels through the sensing lines;
Converting the sensing voltages into digital data sensing data and outputting the sensed voltages;
Outputting an error detection signal of a first logic level voltage when the difference between the sensing data of the first group of pixels and the sensing data of the pixels of the second group among the pixels is equal to or greater than a threshold value; And
And outputting an error detection signal of a second logic level voltage when the difference between the sensing data of the pixels of the first group and the sensing data of the pixels of the second group is smaller than a threshold value.

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