KR20190075316A - Method and apparatus for high speed delay for real-time PVT(Process, Voltage, Temperature) compensation using delay line - Google Patents

Abstract

A method and an apparatus for high speed delay for real-time PVT compensation using a delay line are disclosed. A delay unit for performing fast delay for real-time PVT (Process, Voltage, Temperature) correction can include a plurality of delay lines for adjusting the delay skew of an input signal and a delay line controller for controlling the plurality of delay lines. Each of the plurality of delay lines includes a data delay line and a reference clock delay line. The data delay line receives and delays data. The reference clock delay line receives a reference clock as an input and delays or corrects the delay value of the data delay line.

Description

TECHNICAL FIELD The present invention relates to a high-speed delay method and apparatus for real-time PVT correction using a delay line,

The present invention relates to a high-speed delay method and apparatus for PVT correction, and more particularly, to a high-speed delay method and apparatus for real-time PVT correction using a delay line.

Conventional delay unit is ineffective in maintaining the accuracy and consistency of delay with simple delays according to the delay value input to the external pin or register. Also, when the delay value changes in real time, the delay value must be re-allocated.

KR 10-2005-0089944

One aspect of the present invention provides a fast delay method for real-time PVT correction using a delay line.

Another aspect of the present invention provides an apparatus for performing a fast delay method for real-time PVT correction using a delay line.

According to an aspect of the present invention, a delay unit for performing a high-speed delay for real-time PVT (Process, Voltage, Temperature) correction includes a plurality of delay lines for adjusting a delay skew of an input signal, Wherein each of the plurality of delay lines includes a data delay line and a reference clock delay line, the data delay line receives and delays data, and the reference clock delay line includes a reference clock delay line, It is possible to receive a clock as an input and provide correction control information for correcting the delay value of the data delay line.

In addition, the reference clock delay line may receive the reference clock and provide the correction control information for correcting a delay value of the data delay line according to PVT (Process, Voltage, Temperature) and a change in the surrounding environment.

And a delay element on each of the reference clock delay line and the data delay line, wherein the delay element includes a plurality of coarse delay elements and a plurality of fine delay elements, , The non-precision delay element outputs a first delayed primary delay signal, and the precision delay element may further delay the primary delay signal to output a secondary delay signal.

The plurality of precision delay elements may include a first precision delay element and a second precision delay element, wherein the first precision delay element includes a first lower precision delay element and a second lower precision delay element, 2 precision delay element includes a third lower precision delay element and a fourth lower precision delay element and wherein the first lower precision delay element and the third lower precision delay element are used to implement an actual delay value, The lower precision delay element and the fourth lower precision delay element may be used to correct delay values due to changes in PVT (Process, Voltage, Temperature) and the surrounding environment.

The delay element further includes a plurality of final tuning delay elements, the plurality of final tuning delay elements each including a first fin tuning delay element, a second final tuning delay element, and a third final tuning delay element, The first and second tuning delay elements compensate for delay values in accordance with changes in PVT (Process, Voltage, Temperature) and the surrounding environment, and the third final tuning delay element Can be used to implement the delay value.

The first tuning delay element receives a control signal (MinimumValue) that implements a minimum delay from the delay line controller, and the second final tuning delay element receives a control signal (MaximumValue) that implements a maximum delay, Can be received from the line controller.

The delay line controller may control the delay value of the delay element according to a phase difference between a reference clock and a feedback clock, which is an output signal passing through a delay line, to zero the phase difference.

The delay line controller includes a coefficient control memory. The coefficient control memory is a common place for temporarily storing the coefficient control data for controlling the variable delay elements of each channel. For efficient memory management, ) ≪ / RTI > units.

The delay line controller further includes a delay value comparison unit (DVCU). The DVCU detects a delay value of each channel when a change in the delay set value is requested, compares the current value with a previous value, Page memory allocation and collection, and the DVCU performs control of a delay source route having various delay value change factors, and when the delay value changes, requests a correction of the delay output and controls the speed and method .

A high-speed delay method for real-time PVT correction using a delay line according to an embodiment of the present invention manages control coefficients of a variable delay line using a single memory on a page basis and provides variable and efficient delay control The accuracy and consistency of the delay can be maintained.

1 is a conceptual diagram illustrating a delay line system according to an embodiment of the present invention.
2 is a conceptual diagram illustrating a multi-channel delay line according to an embodiment of the present invention.
3 is a conceptual diagram illustrating a delay line according to an embodiment of the present invention.
4 is a conceptual diagram illustrating a final tuning delay element according to an embodiment of the present invention.
5 is a conceptual diagram showing a system of a delay line controller.
6 is a conceptual diagram illustrating a coefficient control data memory according to an embodiment of the present invention.
7 is a conceptual diagram illustrating a discontinued page memory according to an embodiment of the present invention.
8 is a conceptual diagram illustrating a memory page descriptor according to an embodiment of the present invention.

The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

The present invention relates to a system for delaying a high-speed signal (DDR5 class GHz signal), and a method of maintaining a constant delay irrespective of changes in PVT (Process, Voltage, and Temperature) using a delay line ≪ / RTI >

The delay system according to the embodiment of the present invention may be configured as a delay line controller having a delay line for each channel and controlling the delay line. The delay line may be constituted by a delay element capable of implementing a variable delay in order to obtain a phase difference between a reference clock and a feedback clock through a delay line and to set the phase difference to zero.

The delay line controller manages the coefficient of the variable delay line using a single page memory unit and maintains the accuracy and consistency of the delay through variable and efficient delay control for each channel.

The delay line is composed of a clock delay line receiving a clock as input and a data delay line receiving a clock signal or a data signal as input, and two of them may operate independently or cooperatively. The clock delay line has a phase detector that compares the difference between the reference clock and the feedback clock when the delay value changes according to the ambient environment such as temperature, and the phase detector which can change the delay according to the input coefficient value A delay line and a clock division block, a clock synthesis block, a final phase detector, and a final tuning delay block constituted by a variable delay element. The data delay line includes a delay line and a signal division block, a signal synthesis block, and a delay line composed of a variable delay element capable of changing a delay according to an input coefficient value. a final phase detector and a final tuning delay block.

 The delay line controller includes a memory allocation function for allocating a coefficient unit memory according to a delay value corresponding to each channel and a memory unit for releasing the coefficient unit memory according to a delay value corresponding to each channel A page pool management unit that includes a memory release function that manages page memory, a memory that is allocated from a page pool management unit according to a change in delay value, An address management unit for generating the coefficient unit memory address, a function for returning the coefficient unit memory address, and an arbitration unit for arbitrating the interchannel memory request to store and read the coefficient control data of the various channels in the memory, , Muxing, DeMuxing, and Direct Memory Access (DMA). A memory control unit or the like.

In realizing a delay line, a clock or a data signal is passed through a plurality of delay elements in order to realize a long time delay.

A plurality of delay elements constitute a delay line. The delay line for each channel is constituted by a clock delay line for receiving a clock as input and a data delay line for receiving a clock or a data signal as inputs. Lt; / RTI >

And may have various input and output paths including a case where one input channel (the number of input signals) is connected to a plurality of output channels (the number of output signals) .

1 is a conceptual diagram illustrating a delay line system according to an embodiment of the present invention.

1, there is a variety of applications, but a delay line 100 is connected in the middle in order to adjust a delay skew of an input signal of a device under test (Device Under Test) 120 in a test device for testing a device, And a signal is supplied to the signal processing unit 120 of FIG.

(Delay On Ethernet) input and a wireless DoM (Delay On Mobile) input, which can be used to control the current position and status of the delay data source. An immediate delay value may be taken as an input to apply the changed value in the delay line controller 140 and generate an associated delay control signal.

2 is a conceptual diagram illustrating a multi-channel delay line according to an embodiment of the present invention.

FIG. 2 is a block diagram of a multi-channel delay line. Each of the delay lines may include a data delay line 200 and a reference clock delay line 220.

The reference clock delay line 220 receives a reference clock and compensates the delay value of the delay line according to PVT (Process, Voltage, Temperature) and the surrounding environment to constitute a delay line having a predetermined delay value, The reference clock is delayed according to the programmed value and the data delay line 200 is supplied with correction control information through the delay line controller 200 so that the data delay line 200 has the corrected correct delay value, (240).

3 is a conceptual diagram illustrating a delay line according to an embodiment of the present invention.

Referring to FIG. 3, a clock division block 300 may convert the frequency of an input reference clock to a lower frequency.

The higher the frequency of the input clock, the faster the operation speed of the delay element, and the overall circuit operates at a high speed, so that the power consumption is large and it is difficult to maintain the accurate delay value.

The frequency of the input clock may be lowered in the clock dividing block 300 and the original frequency may be restored in the clock combining block 320 in the rear part in order to reduce the power consumption as a whole and increase the stability of the system.

The clock dividing block 300 functions to lower the clock frequency and can provide a clock of a lower frequency to the inside to enable the operation of the delay line at a lower frequency. This can reduce the power consumption of the delay units and reduce the area. When low frequencies are used, the circuit can be simplified and the stability can be enhanced. In addition, sub-micron technology should be used to realize a PVT-corrected delay in a small unit of a picosecond of a GHz frequency in a complementary metal-oxide semiconductor (CMOS) The price is rapidly increased and the design becomes complicated. Therefore, it can be compensated by a clock division block.

The delay line element array 340 may include a delay element capable of implementing a plurality of variable delays. The delay element is a circuit capable of receiving a control signal from a delay line controller 360 to implement a variable delay and a control signal is delayed from the delay line controller 360 by an analog or digital signal, Element, and can operate as a controlled delay element (CDE) connected to the element. One delay element may be composed of different delay elements of a coarse delay line (Coarse Delay Line) and a fine delay line (Fine Delay Line).

In addition, each delay element may have a bypass logic with a minimum delay value to implement various delay values. By the bypass logic, some of the various delay elements may be operated by the delay control signal and the remainder may be bypassed. The phase detector 370 can transmit the phase difference of the feedback clock 380, which is an output signal passing through the reference clock and the delay line, to the delay line controller.

At this time, the feedback clock 380 can select one of the outputs of the delay elements of the delay line, and can select an appropriate output in consideration of the frequency of the input reference clock and the delay range that the delay element can realize.

If the value of the delay element is changed by affecting the circuit operation according to the change of the PVT (Process, Voltage, Temperature) and the surrounding environment, the desired delay value can not be realized. Therefore, the phase difference of the feedback clock, which is the output signal passing through the reference clock and the delay line, is generated. The delay line controller 360 can control the delay value of each delay element according to the phase difference to make the phase difference zero.

When the delay value of each delay element is corrected, the delay value of each delay element maintains a constant value regardless of PVT (Process, Voltage, Temperature) and the change of the surrounding environment.

The final tuning delay element can be composed of three delay elements as a block for implementing a smaller unit of delay value.

The two delay elements serve to compensate for the delay value due to changes in PVT (Process, Voltage, Temperature) and the surrounding environment, and the other one can be used to implement the actual delay value.

According to the embodiment of the present invention, the structure of the data delay line can be simply implemented by a structure in which the PVT-corrected coefficient value is obtained in the reference clock delay line and transferred to the data delay line. Thus, the clock delay line can provide its own delay implementation and a PVT corrected control signal on the data delay line.

In addition, a fine delay can be realized using a triple delay element. In the main delay line, each element implements a picosecond to nanosecond delay unit and can set the phase error to zero. If you implement too small a delay in the main delay, the delay line becomes too long. Therefore, in order to implement delays of a few picoseconds in the last triple delay element part, a PVT correction method is also required in this part.

In addition, according to the embodiment of the present invention, the control method of the delay line controller is complicated to be implemented in analog, so that it can be implemented in digital logic and be suitable for mixed design. When the external input delay value is set for the first time after the power is turned on using the memory management method, the PVT-corrected coefficient value is stored through the delay line and the delay line controller. If the delay value is changed afterwards, The control procedure can be reduced. In this case, the time to lock, which is a situation where the phase error becomes almost zero, can be reduced.

4 is a conceptual diagram illustrating a final tuning delay element according to an embodiment of the present invention.

4, the input p of the final delay element 1 (F delay element 1) 400 and the input p of the final delay element 2 (F delay element 2) 450 are arbitrary consecutive Delay element input and output signals. The input of the delay element is equal to the output of the previous stage. There is no need for the last single, but only one delay element difference. Each of the FDE2 420 and the FDE2 410 is constituted by two delay elements (FDE1 410 and FDE2 420) and the first delay element FDE1 410 is used to implement the actual delay value. , Temperature) and the delay value according to the change of the surrounding environment.

The FDE1 410 of the final delay element 1 400 receives the control signal (minimum value) implementing the minimum delay from the delay line controller 490 and the FDE1 460 of the final delay element 2 450 is the maximum (Maximum value) that implements the delay from the delay line controller. The delay line controller 490 receives the phase comparison result signal from the Final Phase Dector 390 to match the phases of the output signals of the final delay element 2 450 and the final delay element 1 400 The FDE1 410 of the final delay element 1 400 and the FDE1 460 of the final delay element 2 450 are set to have a minimum delay and a minimum delay value, respectively, when a control signal (Compensation Control: Coefficient value) The overall delay difference between the final delay element 1 400 and the final delay element 2 450 can be adjusted by the FDE2 420 and 470 with the maximum delay being the difference between PVT (Process, Voltage, Temperature) The delay value of one delay element always coincides with the delay value of the delay line of FIG. The delay line controller supplies the same corrected control signal (Compensation Control: coefficient) obtained in the final delay element 1 400 and the final delay element 2 450 to the FDE2 425 and sends the actual delay value to the FDE1 415 of the final delay element 3 405 to output a stable delay signal irrespective of the PVT and the surrounding environment change.

5 is a conceptual diagram showing a system of a delay line controller.

Coefficient Control Memory is a common place to temporarily store Coefficient Control data for controlling variable delay elements of each channel. It is divided into the size of unit of page size for effective memory management. Can be managed.

Since page memory management is performed, the number of controllable delay elements of each channel is determined according to the page size, and a register size can be used to program the page size to implement various delay times.

The write buffer 520 temporarily stores the coefficient control data of each channel in the coefficient control memory 500 before storing the data in the coefficient control memory 500. [ The number of consecutive writes to a coefficient control memory can be sized to support this.

The address management unit 540 generates and manages the memory address of the storage location of the coefficient control data inputted to control the delay of each channel. The address management unit 540 includes a delay value It is possible to perform the function of allocating or returning the page unit memory from the page pool management unit 560 and performing the address generation for storing the coefficient control data.

The address generated at this time may be discontinuous because the non-contiguous memory area can be allocated or returned depending on the used memory area. The memory controller is a control logic for writing the coefficient control data of each channel to the coefficient control memory and reading it, and is responsible for various input and output channels and DMA functions. The page pool management unit 560 divides the total-scale control memory into page units of a predetermined size and manages a new page according to a request from the address management unit 540 of each channel You can organize your memory management by reallocating pages that you no longer need after allocating or using them. A memory page descriptor 580 may manage a linked list of pages allocated to each channel. The Read Buffer is a buffer for temporarily storing the coefficient control data read from the coefficient control memory before outputting the coefficient control data through each channel. The delay value comparison unit (DVCU) 590 includes a delay value comparison unit (DVCU) 590 for comparing the delay value of each channel by a change request It detects this, compares the current value with the previous value, and requests page allocation and collection for each page.

In addition, it controls the delay source route having various delay value change factors and requests correction of the delay output when the delay value changes, and controls the speed and the method. The address management unit 540 of each channel determines the required memory size according to the delay value received from the DVCU (Delay Value Comparison Unit) 590 in the initial state, Unit (560). Since each channel has different delay values to be performed, the number of required memory pages is also different. The page size can be programmable using an external input or register so that it can have an appropriate value for each situation.

6 is a conceptual diagram illustrating a coefficient control data memory according to an embodiment of the present invention.

As shown in FIG. 6, in the initial initial state, pages 600 of consecutive memory areas are allocated according to the channel order, and unused pages can be managed by a page pool management unit.

7 is a conceptual diagram illustrating a discontinued page memory according to an embodiment of the present invention.

FIG. 7 shows the case of page allocation of non-contiguous area.

If the delay value is continuously changed for each channel and page allocation and collection continue, the page 700 of the non-continuous area can be allocated. When the coefficient control data of each channel is inputted for the first time, since the write address pointer will be pointing to the first coefficient element of the first page, it is necessary to write to the first coefficient element of the allocated page memory area and write address Pointer) by 1 to prepare for writing to the next coefficient element. The coefficient value corrected by the delay line controller and the delay line is stored according to each channel and the delay value. If the delay value is changed next, the existing stored value of the coefficient can be read and used. The address management unit manages a write address pointer and a read address pointer. The address management unit manages the next address pointer (Next) of the memory page descriptor when writing and reading the coefficient control data. Address Pointer, Valid bit, and End bit of the received data. When a certain limit is reached (such as when the coefficient memory is insufficient or the coefficient memory corresponding to the delay value is not used for a long time), the currently allocated coefficient memory can be released.

8 is a conceptual diagram illustrating a memory page descriptor according to an embodiment of the present invention.

As shown in FIG. 8, a memory page descriptor 800 is configured to indicate a connection state of a coefficient control memory unit for each page, which is allocated for each channel, and a memory page descriptor (800), or may be configured directly in the coefficient control memory. If a new coefficient memory is required according to a delay value to be transmitted, a memory page descriptor 800 is formed after obtaining a necessary page, and if a large number of coefficient values to be stored according to a delay value are required, .

A page descriptor element corresponding to each page of the assigned coefficient control memory exists and refers to an end bit and a valid bit of a page descriptor element, The page of the coefficient control data memory corresponding to the next read and write can be fetched according to the value of the next address pointer. The address management unit of each channel accesses the last coefficient element of the page currently performing reading and writing and then refers to the value of the next address pointer of the next page descriptor element corresponding to each page Thereby managing the discontinuous coefficient control memory area.

The management of the coefficient memory according to the delay value can be considered in the following three ways.

In the first case, if the newly input delay value is the same as the current delay value, the number of related coefficient elements may be the same if the number of delay elements used is the same. At this time, the size of the memory used does not change.

In the second case, when a new delay value with a small value is applied, the delay value newly applied is smaller than the current delay value, so that the number of delay elements used and the number of the coefficient elements are reduced, Do. In this case, there are various ways of adjusting. If the difference between the current area and the reduced area becomes larger than one page size due to the reduced delay value by one method, the page memory is returned to the page pool management unit.

In the third case, when a new delay value having a large value is applied, the current applied delay value becomes smaller than the newly applied delay value, so that the number of delay elements and the number of coefficient elements used increases, need. At this time, memory of one page size can be allocated from the page pool management unit.

The above-described methods may be implemented in an application or may be implemented in the form of program instructions that may be executed through various computer components and recorded on a computer-readable recording medium. The computer-readable recording medium may include program commands, data files, data structures, and the like, alone or in combination.

The program instructions recorded on the computer-readable recording medium may be ones that are specially designed and configured for the present invention and are known and available to those skilled in the art of computer software.

Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tape, optical recording media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like.

Examples of program instructions include machine language code such as those generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware device may be configured to operate as one or more software modules for performing the processing according to the present invention, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

Claims (9)

Delay units that perform high-speed delays for real-time PVT (Process, Voltage, Temperature)
A plurality of delay lines for adjusting a delay skew of an input signal; And
And a delay line controller for controlling the plurality of delay lines,
Each of the plurality of delay lines including a data delay line and a reference clock delay line,
The data delay line receives and delays data,
Wherein the reference clock delay line receives the reference clock as an input and provides correction control information for correcting a delay value of the data delay line. The method according to claim 1,
Wherein the reference clock delay line receives a reference clock and provides the correction control information for correcting a delay value of the data delay line according to PVT (Process, Voltage, Temperature) and a change in the surrounding environment. unit. 3. The method of claim 2,
And a delay element on each of the reference clock delay line and the data delay line,
Wherein the delay element comprises a plurality of coarse delay elements and a plurality of fine delay elements,
The non-precision delay element outputs a first delayed primary delay signal,
Wherein the precision delay element further delays the first delay signal to output a second delay signal. The method of claim 3,
The plurality of precision delay elements including a first precision delay element and a second precision delay element,
Wherein the first precision delay element comprises a first lower precision delay element and a second lower precision delay element,
Wherein the second precision delay element comprises a third lower precision delay element and a fourth lower precision delay element,
Wherein the first lower precision delay element and the third lower precision delay element are used to implement an actual delay value,
Wherein the second lower precision delay element and the fourth lower precision delay element are used for correcting a delay value in accordance with a change in PVT (Process, Voltage, Temperature) and the surrounding environment. The method of claim 3,
Wherein the delay element further comprises a plurality of final tuning delay elements,
The plurality of final tuning delay elements each including a first final tuning delay element, a second final tuning delay element and a third final tuning delay element,
The first and second tuning delay elements compensate a delay value according to PVT (Process, Voltage, Temperature)
And the third final tuning delay element is used to implement an actual delay value. The method of claim 3,
Wherein the first fin tuning delay element receives a control signal (MinimumValue) implementing a minimum delay from the delay line controller, and the second final tuning delay element receives a control signal (MaximumValue) implementing a maximum delay from the delay line controller To the delay unit. The method according to claim 6,
Wherein the delay line controller controls a delay value of the delay element according to a phase difference between a reference clock and a feedback clock, which is an output signal passing through a delay line, to make the phase difference zero. 8. The method of claim 7,
Wherein the delay line controller comprises a coefficient control memory,
Wherein the coefficient control memory is a common place for temporarily storing a coefficient control element for controlling a variable delay element of each channel and is managed by dividing into a page unit size of a predetermined size for efficient memory management. unit. 9. The method of claim 8,
The delay line controller further includes a delay value comparison unit (DVCU)
The DVCU detects a delay value of each channel when a delay set value change request is received, compares a current value with a previous value, and requests memory allocation and collection in units of pages according to the current value,
Wherein the DVCU performs control of a delay source route having various delay value change factors and requests correction of the delay output when the delay value changes, and controls the speed and method thereof.

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