KR20190075315A - Method for storing and recovering of high speed data on memory and memory for performing the same - Google Patents

Abstract

Disclosed are a method for storing and recovering high speed data in a memory and a memory for performing the same. A structure of a hybrid memory using a dual-port DRAM comprises: a dual-port DRAM used as data cache for storing activated data and table control information; and a flash memory used as an inactive area for safely storing data. The dual-port DRAM may eliminate access conflicts between an external interface controller and an internal control controller.

Description

[0001] The present invention relates to a method for storing and restoring high-speed data on a memory and a memory for performing such a method,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of processing data in a memory, and more particularly, to a method of storing and restoring high-speed data on a memory and a memory performing the method.

Flash memory is nonvolatile as a storage medium, but its speed is limited by data writing. In addition, the flash memory has a limited limitation on the number of times of writing when the data writing operation is repeatedly performed. Dynamic random access memory (DRAM) has advantages in data processing and high speed, but it has disadvantages in that it requires special facilities in order to disable the volatile characteristics.

Traditionally, DRAM and flash memory based semiconductor memory disks and storage have used DRAM as a storage means for management tables and as a simple data buffer for transferring the contents of a flash memory to an external interface.

This method can use a small amount of DRAM, but the overall performance depends on the read / write speed of the flash memory. In addition, flash memory-based semiconductor memory disks have write speed limit and speed limit. In case of write operation, the data is deleted and rewritten to the corresponding block. In case of repeated writing operation due to high voltage added to the block during write operation, defective due to leakage current, Will be disabled. In this case, there is a stability problem in a server environment in which direct data entry is performed continuously.

KR 10-2007-0106069

One aspect of the present invention provides a method for storing and restoring high-speed data on a memory.

Another aspect of the present invention provides a memory for performing a high speed data storage and recovery method.

A hybrid memory structure using a dual-port DRAM according to one aspect of the present invention includes a dual-port DRAM (DRAM) used as a data cache for storing activated data and table control information, and a non-active area The dual-port DRAM can eliminate access conflicts between the external interface controller and the internal control controller.

The hybrid memory structure using the dual-port DRAM includes a DRAM controller for managing the dual-port DRAM, a flash controller for managing the flash memory, and a controller for writing and / or backing up or reading data of the dual- A backup / restoration controller for restoring the backup / restore controller and the flash controller, and a control signal related to reading and writing from the external interface controller and a signal corresponding to an external state change, and controlling the DRAM controller, the backup / Receives the signal of the external interface controller according to the status, reads the data through the DRAM controller or the flash controller and transfers the data to the external interface controller or transmits the data coming in through the external interface controller to the dual- And an I / O controller which is implemented to perform an operation of controlling to write to the I / O controller.

Also, the write / backup controller may back up the data of the dual-port DRAM changed when the power is turned off to the flash memory, or when the write command from the I / O controller enters the control signal, If a miss occurs in the DRAM, the data block can be backed up in the flash memory if the data block is modified.

In addition, the hybrid memory structure may determine whether the data read command exists, and when the data read command exists, transfer the data read command from the external interface controller to the I / O controller, Wherein the structure is configured to send the data read command to the DRAM controller from the I / O controller to read data from the dual-port DRAM in accordance with a logical address, to read data from the flash memory, to update the dual- Wherein the hybrid memory structure determines whether an existing page has been modified when updating the dual-port DRAM based on a determination as to whether a dyram miss has occurred, The dual- Wherein when the existing page is modified at the time of updating the dual DRAM, the modified DRAM backs up the modified DRAM page to the flash memory, and when the existing page is not modified at the time of updating the dual-port DRAM, And the hybrid memory structure may transmit data on the dual-port DRAM if the diramis miss is not generated based on a determination as to whether the diramis error has occurred.

In addition, the hybrid memory structure may determine whether a power flag is 0, perform backup of data when the power flag is 0, and if the power flag is 0, Setting a modified portion of the port DRAM and a number of pages in the management table area as a backup counter value and performing a backup from the dual port DRAM to the flash memory and the hybrid memory structure based on the counting for the backup counter The backup flag is set to 0 when the backup counter is 0, and the hybrid memory structure performs a judgment on a data write command when the power flag is not 0, and if there is the data write command, , And the hybrid memory structure determines whether the data When the write command is transmitted from the external interface controller to the I / O controller, whether or not the corresponding page is present in the dual-ported DRAM is determined, and the hybrid memory structure determines whether the dual- And if the dummy page has not been modified, reads the corresponding page from the flash memory to update the dual-port diram, and if the diram page is not modified, and when the DRAM page is modified, performing a log buffer write using the information in the log buffer management table. The hybrid memory structure determines whether the log buffer is in a full state, When the log buffer is full, the log buffer and the data buffer are merged, and the log buffer It may perform compression.

According to another aspect of the present invention, there is provided a method of operating a hybrid memory using a dual-port DRAM, including the steps of storing data and table control information that is used by a dual-port DRAM as a data cache, The dual-port DRAM can eliminate the access conflict between the external interface controller and the internal control controller.

The method for operating the hybrid memory using the dual-port DRAM includes the steps of transferring the data read command from the external interface controller to the I / O controller, the hybrid memory structure transferring the data read command from the I / Reading the data corresponding to the logical address from the dual-port DRAM by reading the data from the flash memory, and updating the dual-port DRAM by sending the data read command to the dual-port DRAM, Determining whether an existing page has been modified when the dual-port DRAM is updated when the dual-port DRAM is generated based on a determination as to whether the dual-port DRAM is updated; Page Backing up the modified DRAM page to the flash memory, if the existing page is not modified at the time of updating the dual port DRAM, transmitting the data on the flash memory, And transmitting the data on the dual-port DRAM if the diramis is not generated based on a determination as to whether or not the diramis is generated.

Also, a method of operating a hybrid memory using a dual-port DRAM may include the steps of: determining whether a power flag is 0 in the hybrid memory structure; performing backup of data when the power flag is 0; Setting a modified part of the dual port DRAM and a page number of a management table area as a backup counter value and performing a backup from the dual port DRAM to the flash memory when the power flag is 0, Setting the backup flag to 0 if the backup counter is 0 based on counting for the backup counter; if the power flag is not 0, And if there is the data write command, Determining whether a page exists in the dual-port DRAM when the data write command is transmitted from the external interface controller to the I / O controller; And if the hybrid memory structure is a DRAM hit, writing to the dual-ported DRAM is performed. If the hybrid memory structure is not the DYRAM miss, it is determined whether the DRAM page is modified. If the DRAM page is not modified, Reading the corresponding page from the flash memory, updating the dual-port DRAM to perform a DRAM write operation, and, when the DRAM page is modified, performing a log buffer write using the information in the log buffer management table can do.

Also, a method of operating a hybrid memory using a dual-port DRAM may include determining whether the hybrid memory structure is full or not, merging the log buffer and the data buffer when the log buffer is full, And performing log buffer compression.

The method and apparatus for storing and restoring high-speed data on a memory according to an embodiment of the present invention can improve performance of a memory by configuring a semiconductor memory disk of a hybrid type using a DRAM and a flash memory together. Specifically, a dual-port DRAM is used for performance improvement and data can be exchanged directly with an external interface using a DRAM interface.

In addition, by using a method of reducing the write time of the flash memory by separating the flash memory into the log buffer and the data buffer, providing the data by using the dual-port DRAM interface directly, and managing the management of the DRAM and the flash memory directly The performance of the memory can be improved.

1 is a block diagram illustrating a hybrid memory structure using a dual-port DRAM according to the present invention.
2 is a conceptual diagram illustrating a NAND data block and a related data block mapping table according to an embodiment of the present invention.
3 is a conceptual diagram illustrating a NAND log block and a related log page pool and a log page descriptor according to an embodiment of the present invention.
4 is a conceptual diagram illustrating a compression of a NAND log block and a log page descriptor copy operation according to an embodiment of the present invention.
5 is a conceptual diagram illustrating a merge operation between a NAND log block and a NAND data block.
6 is a flowchart illustrating a method of reading data in a hybrid memory structure using a dual-port DRAM according to an embodiment of the present invention.
7 is a flowchart illustrating a method of writing / backing data in a hybrid memory structure using a dual-port DRAM according to an embodiment of the present invention.

The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

A hybrid memory structure using a dual-port DRAM according to an embodiment of the present invention discloses a method of configuring a hybrid type semiconductor memory disk by using a DRAM and a flash memory together. Specifically, a method is disclosed in which a DRAM is used as a main area of read / write for improving performance and a DRAM of a large capacity can be used as a cache of a flash memory in some cases. To improve performance, dual-port DRAM is used and data can be exchanged directly with the external interface based on the DRAM interface. If a high-speed DRAM is used in cache form, a smaller capacity than a flash memory can be used. Therefore, if there is a miss, a write operation to the flash memory must be performed. If a conventional flash memory needs to write to the same area, a write operation must be performed after a time-consuming block erase is performed. Therefore, it takes a lot of time basically.

In the hybrid memory structure using the dual-port DRAM according to the embodiment of the present invention, the write time of the flash memory can be reduced by dividing the flash memory into the log buffer and the data buffer, and data can be directly provided through the dual port DRAM interface And management of the DRAM and the flash memory can be performed directly from the inside.

In order to solve the problem of high speed reading and writing, a hybrid memory structure using a dual port DRAM according to an embodiment of the present invention can be configured by combining a DRAM and a flash memory through a DRAM interface in a hybrid manner. The DRAM is used as a space for storing active data and table control information, and the flash memory can be used as an inactive area for stably storing data. A dual-port DRAM can be used to prevent collision with an external interface while the existing DRAM interface is being used intact.

A dual port DRAM can be used as a data cache to minimize access to flash memory. When the DRAM cache miss occurs or the power is turned off, the modified DRAM data can be stored in the flash memory via the write / backup controller. If new data is read when the power is turned on or a DRAM cache miss occurs, the corresponding data can be read from the flash memory via the read / restore controller. The flash controller can manage the flash memory by dividing it into a data block and a log block. In addition, the flash controller includes a data block mapping table for managing mapping of data blocks, and a log page pool for performing sequential page-by-page write and read operations in the log block. Pool) and a log page descriptor (log page descriptor).

In addition, the hybrid memory structure using dual port DRAM controls power on / off detection logic, status / control register to check operation status, I / O data processing, module operation control and direct memory access (DMA) / RTI > input / output < RTI ID = 0.0 > (I / O) < / RTI >

The page of the flash memory can be written only when it is in a free state after erasing it. If the data is changed, it can not be overwritten on the existing stored page, and the contents of the page may first be copied to the internal data buffer and then changed in the data buffer and written to another new free page. This can be expressed in terms of read-modify-write. That is, the data can not be changed without moving to another page, and in-place update may not be possible. When the changed data is completely written to the new page, the original page is displayed as stale and remains in that state until it is erased. Since pages can not be overwritten, pages that have become stale once must be deleted and then transferred to free state. However, deletion can not be performed on a single page basis, and it has to be performed entirely on the block containing the page and it takes a lot of time.

In the hybrid memory structure using the dual-port DRAM according to the embodiment of the present invention, the performance is improved by minimizing the collision due to the use of the dual port DRAM, and since the DRAM is used as the main storage area, The content of the page is modified, or the contents of the DRAM are backed up to the flash memory because the power is interrupted.

A temporary write can be performed to the log block in a sequential manner before writing to the data block of the flash memory. In addition, the log block compression method can be used to maximize the utilization of the log block, so that the merge operation with the data block can be minimized.

Hereinafter, a hybrid memory using a dual-port DRAM is specifically disclosed in the embodiment of the present invention.

1 is a block diagram illustrating a hybrid memory structure using a dual-port DRAM according to the present invention.

Referring to FIG. 1, a hybrid memory structure using a dual-port DRAM may include a DRAM block 120 and a flash block 130.

The hybrid memory structure using the dual-port DRAM includes a DRAM controller 102 and a flash controller 103 for managing each memory, a backup / restore controller 104 for writing / backing up or reading / A data buffer 106, a power on / off detection logic 101, a status / control register 105 for checking the operation status, a processing module for controlling input / And an input / output (I / O) controller 107 for managing the input / output (I / O)

The I / O controller 107 receives a control signal related to reading and writing from the external interface controller 200 and a signal corresponding to the external state change, and controls the DRAM controller 102, the backup / restore controller 104, The controller 103 can be controlled.

The I / O controller 107 receives the signal from the interface controller 200 according to the operation state, reads the data through the DRAM or the flash controller 102 and transfers the read data to the interface controller 200 or the interface controller 200 And to write the incoming data to the DRAM or flash memory.

In order to manage the hybrid memory structure using the dual-port DRAM, a lot of operations can be performed in the background between the DRAM and the flash memory internally.

An access conflict with the internal operation and the DRAM block 120 may occur in the read and write requests of the interface controller 200. As shown in FIG. 1, a request may be performed without a conflict by configuring the DRAM block 120 as a dual-port DRAM. When the DRAM block 120 is configured as a dual-port, access conflicts between the external DRAM interface controller 200 and the internal control controller 110 can be eliminated. Also, if the restoration start time of the internal control controller 110 is started before the read request of the external interface controller 200 when the power is on, the internal restoration speed is faster than the read speed of the external interface controller 200 It can be possible. Therefore, the external interface controller 200 can improve the performance by reducing the collision or the delay time by performing the read / write process without waiting for the completion of the restoration or performing the restoration by itself. The status register is configured to allow the I / O controller 107 to check operation status information, such as whether it is a normal operation, whether the backup is in progress, whether data restoration is in progress, whether the external interface controller 200 has saved the current status at the time of backup, do.

The write / backup controller 104 may back up the data of the changed DRAM block 120 to the flash memory when the power is turned off. When a miss occurs in the DRAM block 120 in which the write data is stored when the write command is received as a control signal from the I / O controller 107, the write / If it is modified, the data block can be backed up to flash memory. Upon receiving a write command from the I / O controller 107, the write / backup controller 104 writes directly to the DRAM if there is data corresponding to the DRAM (DRAM hit) (DRAM miss), the modified state of the page can be checked and corrected, and the flash controller 103 can be requested to write / back up and request a new data read. If external power is interrupted, a backup of the entire DRAM data block and related table information should be performed.

The flash block 130 stores data at a physical page address (PPN) position corresponding to a logical page address (LPN) of the DRAM block 120. In order to improve performance, Data blocks.

The internal control operations for reading and writing are as follows. When the power is first turned on, the DRAM does not have data in the initial state, so the internal control controller 110 can fetch data from the flash memory through the read / restore process (warm start) to the DRAM. When there is a read request from the external interface controller 200, the DRAM is first accessed to check whether a related page exists and if the page exists in the DRAM (DRAM hit), a read request is performed at high speed through the DRAM interface. (Log page pool) and the log page descriptor (Log Page Descriptor) in the flash controller 103, if there is no DRAM (DRAM miss) It is checked whether the corresponding page exists in the block. If the corresponding page exists, the page can be read from the log block and the corresponding data can be transferred to the DRAM and the external interface controller 200. If there is no corresponding page in the flash log block, the page can be read from the data block of the flash memory through the data block mapping table in the flash controller 103 and the corresponding data can be transferred to the DRAM and the external interface controller 200 have. The read / restore controller may store the latest page information in the DRAM and update the associated control information.

If there is a write request of the external interface controller 200, it is possible to first access the DRAM to check whether a related page exists, and to perform a write request at high speed through the DRAM interface if the page exists in the DRAM (DRAM hit). Conversely, if the page does not exist in the DRAM (DRAM miss), a log block management table (a log page pool and a log page descriptor) in the flash controller, such as a read request, It is possible to check whether or not the corresponding page exists in the block. Thereafter, when the corresponding page exists, the page is read from the log block, temporarily stored in the internal data buffer, write data is written to the corresponding location, and the corresponding data is transferred to the DRAM to update the latest page. On the contrary, if there is no corresponding page in the flash log block, the page is read from the data block of the flash memory through the data block mapping table in the flash controller 103, temporarily stored in the internal data buffer, You can then update the latest page by passing the appropriate data to the dyram. If the page does not exist in the DRAM (whether it is a read request or a write request) (DRAM miss), it is checked whether a page existing in the existing DRAM is modified before reading a new page from the flash memory. Write is performed using the log block of the flash memory to improve the performance. When the programmed value is reached through the programmed value in the internal control register according to the control algorithm, the self-log block compression A log block merge operation with the data block can be performed.

2 is a conceptual diagram illustrating a NAND data block and a related data block mapping table according to an embodiment of the present invention.

Referring to FIG. 2, a data block mapping table 200 includes information for mapping a logical block number (LBN) of a DRAM to a physical block number (PBN) of a flash memory, And a flash controller.

Referring to FIG. 2, the flash memory may perform page-level management, but may perform block-level management to reduce the control complexity and the area occupied by the management table.

3 is a conceptual diagram illustrating a NAND log block and a related log page pool and a log page descriptor according to an embodiment of the present invention.

The flash controller can manage the entire flash memory by dividing it into a data block and a log block. When a flash memory read / write request is issued from the backup / restore controller due to a read / write request of the external interface controller 200, reading and writing can be performed.

The log page pool 300 has page information of available log blocks and performs management of page allocation or page release at the request of the flash controller.

Each entry in the log page descriptor 320 sequentially displays a log block page valid in the log block. The log block page includes log block compression and data block It can be used for log block merging.

4 is a conceptual diagram illustrating a compression of a NAND log block and a log page descriptor copy operation according to an embodiment of the present invention.

Referring to FIG. 4, the logical block number 1 (Logical Page Number 1) to the physical page number (PPNa) are stored in the NAND log block 1 (Log Block 1). As a result of multiple writes to the same location, the value of LPN1 (Logical Page Number1) in PPNa (Physical Page Number a) becomes the last written value and the rest becomes the page with stale data. When a flash controller requests a write operation smaller than a page unit, the latest page data can be maintained in a read-modify-write manner through an internal data buffer. At this time, only the information of the PPNa having the latest data can be stored in the Log Page Descriptor 400. Therefore, the first entry of the log page descriptor 400 becomes LPN1: PPNa and the last entry number (LEN) has a value of a (a page of the log buffer). When the log block reaches a compression limit number (programmed value by a register) for performing compression, log block compression is performed. The first entry of the log page descriptor 400 entry from the first page to the previous page in the NAND log block 1 (Log Block 1) is stale data, and only the PPNa page is copied to the new NAND log block (Log Block 1) can do.

As a result, only four valid pages that are not the final stale are copied to the NAND log block n (Log Block n), so that only the four pages of the NAND log block n (Log Block n) Is switched to an empty state to perform compression, and the empty page is used to perform another writing operation. NAND log block 1 (Log Block 1) is displayed as a stale page and later used as a new NAND log block through erase, and new pages can be added and managed in the log page pool.

A log page descriptor 1 (descriptor corresponding to log block 1) is a descriptor corresponding to a log page descriptor n (log block n) Lt; / RTI >

5 is a conceptual diagram illustrating a merge operation between a NAND log block and a NAND data block.

5, when the NAND log block 500 reaches a merge limit number (programmed value by a register), it means that the number of available pages of the NAND log block 500 is insufficient. Thus, it is possible to perform a merge with the data block and free pages in the log buffer. After merging, the merged NAND log block 500 is displayed as a stale page and can be used as a new NAND log block 500 through deletion later, and new pages can be added to the log page pool and managed.

The log page pool may generate a control signal to perform log block compression and merging when the number of limits programmed to manage the allocation and release of log block pages is reached.

6 is a flowchart illustrating a method of reading data in a hybrid memory structure using a dual-port DRAM according to an embodiment of the present invention.

In FIG. 6, it is determined whether a data read command exists (S300)

If there is a data read command, data reading in the DRAM block may be performed (step S301).

A hybrid memory architecture using a dual-port DRAM is passed from the interface controller to the module's I / O controller and is sent a read command to the DRAM controller to read data that matches the logical address of the DRAM block (DRAM hit) Data can be read from the memory and the DRAM updated (DRAM miss).

It is determined whether or not a dyram miss has occurred (step S302). If a dyram miss occurs, it can be determined whether or not the existing page has been modified at the time of updating the dyram.

 If the existing page is modified at the time of updating the DRAM, the modified DRAM page can be backed up in the flash memory (S305).

If the existing page is not modified at the time of updating the DRAM, data can be transmitted from the flash memory (S303).

It is determined whether or not a dyram miss has occurred (step S302), and if a dyram miss has not occurred , The data can be transmitted in the DRAM block.

7 is a flowchart illustrating a method of writing / backing data in a hybrid memory structure using a dual-port DRAM according to an embodiment of the present invention.

Referring to FIG. 7, it is determined whether the power flag is 0 (S600). When the power flag is 0, the power is off and backup can be performed.

If the power flag is 0, the corrected portion of the DRAM and the number of pages of the management table area are set as the backup counter value (S611), and backup from the DRAM to the flash memory is performed (S612).

The backup counter is counted (S613). If the backup counter is 0 (S614), the backup flag can be set to 0 (S615).

If the power flag is not 0, the power is on and the data write command can be determined (S601).

If there is a data writing command, it is judged whether or not a DRAM error has occurred (S602).

When a data write command is transmitted from the interface controller to the I / O controller, it is checked whether or not the corresponding page exists in the DRAM, and it is judged whether or not a DRAM error has occurred.

Diram hits can be written to the diram (S604).

If the DRAM page is not modified, it is determined whether or not the DRAM page is modified (S603). If the DRAM page is not modified, the corresponding page is read from the flash memory (S605) Store the data, write the data, update the DRAM, and write the DRAM (S604).

When the DRAM page is modified, the log buffer write can be performed using the information in the log buffer management table (S606).

If the log buffer is full, the log buffer is merged with the data buffer (S608), and the log buffer compression may be performed (S610).

The above-described methods may be implemented in an application or may be implemented in the form of program instructions that may be executed through various computer components and recorded on a computer-readable recording medium. The computer-readable recording medium may include program commands, data files, data structures, and the like, alone or in combination.

The program instructions recorded on the computer-readable recording medium may be ones that are specially designed and configured for the present invention and are known and available to those skilled in the art of computer software.

Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tape, optical recording media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like.

Examples of program instructions include machine language code such as those generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware device may be configured to operate as one or more software modules for performing the processing according to the present invention, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

Claims (9)

A hybrid memory architecture using a dual-port DRAM,
A dual-port DRAM (DRAM) used as a data cache for storage of activated data and table control information; And
And a flash memory used as an inactive area for stably storing data,
Wherein the dual-port DRAM eliminates access conflicts between the external interface controller and the internal control controller. The method according to claim 1,
A DRAM controller for managing the dual-port DRAM;
A flash controller for managing the flash memory;
A backup / restore controller for writing and / or backing up, reading and / or restoring data of the dual-port DRAM; And
And a flash controller for controlling the DRAM controller, the backup / restore controller and the flash controller, and for controlling the signals of the external interface controller according to the operation state, O controller < / RTI > that is implemented to perform the operation of reading data through a DRAM controller or a flash controller and transferring the data to the external interface controller or writing data to the dual-port DRAM or the flash memory via the external interface controller Further comprising the step of: 3. The method of claim 2,
The write / backup controller backs up the data of the dual-port DRAM changed when the power is turned off to the flash memory or when the write command from the I / O controller enters the control signal, the write / And if the data block has been modified, the data block is backed up in the flash memory. The method of claim 3,

The hybrid memory structure determines whether or not the data read command exists, and when the data read command exists, transfers the data read command from the external interface controller to the I / O controller
The hybrid memory structure is configured to send the data read command to the DRAM controller from the I / O controller to read data from the dual-port DRAM or to read data from the flash memory, Update,
Wherein the hybrid memory structure is configured to determine whether an existing page has been modified when updating the dual-port DRAM based on a determination as to whether a diramis error has occurred,
Wherein the hybrid memory structure backs up a modified DRAM page to the flash memory if an existing page is modified at the time of updating the dual-
Wherein the hybrid memory structure transmits data on the flash memory when an existing page is not modified when the dual-port DRAM is updated,
Wherein the hybrid memory structure transmits data on the dual-port DRAM when the diramis miss is not generated based on a determination as to whether or not the diramis error has occurred. 5. The method of claim 4,
Wherein the hybrid memory structure determines whether a power flag is 0, performs a backup of data when the power flag is 0,
The hybrid memory structure sets a modified counter value of the dual-port DRAM and a page number of the management table area as a backup counter value when the power flag is 0, performs backup from the dual-port DRAM to the flash memory ,
Wherein the hybrid memory structure sets a backup flag to 0 if the backup counter is 0 based on the counting of the backup counter,
Wherein the hybrid memory structure determines whether or not the data write command is generated if the power flag is not 0,
Wherein the hybrid memory structure checks whether or not a corresponding page is present in the dual-ported DRAM when the data write command is transmitted from the external interface controller to the I / O controller,
The hybrid memory structure may be configured to write to the dual-port DRAM if the DRAM hit, and to determine whether to modify the DRAM page if the DRAM is missed. If the DRAM page is not modified, Reads the dual-port DRAM and performs a DRAM write operation, and when the DRAM page is modified, performs a log buffer write using the information of the log buffer management table,
Wherein the hybrid memory structure determines whether the log buffer is in a full state, merges the log buffer and the data buffer when the log buffer is full, and performs log buffer compression. A method of operating a hybrid memory using a dual-
Storing dual-port DRAM (DRAM) as data cache to enable active data and table control information;
Wherein the flash memory is used as an inactive area to stably store data,
Wherein the dual-port DRAM removes access conflicts between the external interface controller and the internal control controller. The method according to claim 6,
The hybrid memory structure transferring the data read command from the external interface controller to the I / O controller;
The hybrid memory structure sends the data read command to the DRAM controller from the I / O controller to read data from the dual-port DRAM or to read data from the flash memory and to update the dual- ;
Determining whether an existing page has been modified when updating the dual-port DRAM when the hybrid memory structure has generated a diramesis based on a determination as to whether a diramis occurred;
Backing up the modified DRAM page to the flash memory if the hybrid memory structure has modified an existing page when updating the dual-port DRAM;
Transmitting the data on the flash memory when the hybrid memory structure does not update an existing page when the dual port DRAM is updated; And
And transmitting the data on the dual-port DRAM if the hybrid memory structure does not generate the diramis based on a determination as to whether the diramis occurred. 8. The method of claim 7,
Determining whether a power flag of the hybrid memory structure is 0 and performing a backup of data when the power flag is 0;
Wherein when the power flag is 0, the hybrid memory structure sets the modified part of the dual-port DRAM and the number of pages of the management table area as a backup counter value and performs backup from the dual-port DRAM to the flash memory step;
Setting the backup flag to 0 if the hybrid memory structure is based on counting the backup counter, if the backup counter is 0;
Determining whether the data write command is generated if the power flag is not 0 and determining whether the data write command is generated if the data write command is present;
Checking whether a corresponding page exists in the dual-port DRAM when the data write command is transferred from the external interface controller to the I / O controller, and determining whether the data write command is generated; And
And if the hybrid memory structure is a DRAM hit, writes to the dual-port DRAM. If the hybrid memory structure is the DYRAM miss, it is determined whether or not the DRAM page is modified. If the DRAM page is not modified, Reading the dual-port DRAM and performing a DRAM write operation, and when the DRAM page is modified, performing a log buffer write using the information in the log buffer management table. How it works. 9. The method of claim 8,
Determining whether the log buffer is in a full state, and if the log buffer is full, merging the log buffer and the data buffer and performing log buffer compression. / RTI >

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