KR20190071277A - Light emitting device, and micor display device - Google Patents

Abstract

Embodiments of the present invention relate to a light emitting element and a micro display device. The micro display device can be realized without a process of transferring a micro light emitting diode to a substrate on which a transistor is formed by forming an anode electrode on the micro light emitting diode growing on a wafer substrate, and forming a transistor of a top gate structure. Moreover, an etching region of the micro light emitting diode is minimized to maximize light emitting efficiency of the micro light emitting diode. A chip size is reduced to increase the number of a pixel arranged per unit area so as to achieve a high resolution pattern of the micro display device.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting device,

Embodiments of the present invention relate to a light emitting device and a microdisplay device.

BACKGROUND ART [0002] As an information society develops, there is a growing demand for a display device for displaying an image, and a liquid crystal display device, a plasma display device, an organic light emitting display device, Various types of display devices are being utilized.

Such a display device may include a display panel in which a plurality of sub-pixels are arranged, and various driving circuits such as a gate driving circuit and a data driving circuit for driving the same.

In a conventional display device, a display panel is formed by forming transistors, various electrodes, various signal lines, and the like on a glass substrate, and a driving circuit, which can be implemented as an integrated circuit, is mounted on a printed circuit and electrically connected to the display panel.

Such a structure of the conventional display device is suitable for a large display device, but is not suitable for a small display device.

Recently, a display device (hereinafter also referred to as a "microdisplay device") using a micro light emitting diode (LED) having a structure suitable for a small display device has appeared, and a micro light emitting diode (LED) Quot; light emitting diode ".

Such a microdisplay device utilizes a micro light emitting diode (μLED) itself as a pixel and can be miniaturized and lightweight, and can be advantageously used in various applications such as a smart watch, a mobile device, a virtual reality device, an augmented reality device, and a flexible display device. to provide.

Such a microdisplay device can be realized, for example, by separating the micro light emitting diode (μLED) grown on the wafer substrate from the wafer substrate and transferring the separated micro light emitting diode (μLED) to the transistor substrate.

At this time, the process of transferring the micro-LED (μLED) to the transistor substrate has many difficulties because the size of the micro-LED (μLED) is very small. In addition, due to the difficulty of the transfer process, there is a limitation in implementing a microdisplay device having a high resolution by transferring a plurality of micro-LEDs (μLEDs).

Further, when a via-hole-like structure is formed in the micro-LED (μLED) for electrically connecting the micro-LED (μ LED) to the transistor, the size of the micro LED (μ LED) increases, There is a problem that the luminous efficiency is lowered due to the reduction of the light emitting area due to the via hole.

Accordingly, there is a need for a micro-LED (micro-LED) and a micro-display device which can realize a high resolution by overcoming the limitation of a transfer process by maintaining a small size of a micro-LED (μ LED) and maximizing luminous efficiency .

It is an object of embodiments of the present invention to provide a micro light emitting diode (μLED) that enables a micro display device to be implemented without transferring a micro light emitting diode (μLED) to a transistor substrate and a micro display device I have to.

It is an object of embodiments of the present invention to provide a microdisplay device in which the number of pixels per unit area is increased by improving the luminous efficiency of a micro-LED (μLED) and realizing a micro-LED (μLED) There is.

According to an aspect of the present invention, there is provided an organic light emitting display comprising: a common electrode; an n-type semiconductor layer disposed on the common electrode and divided into a boundary region between the light emitting region and the light emitting region; A plurality of p-type semiconductor layers respectively disposed on the plurality of active layers, a plurality of individual electrodes respectively disposed on the plurality of p-type semiconductor layers, and a plurality of individual electrodes There is provided a microdisplay device including a plurality of transistors connected to each other.

In another aspect, embodiments of the present invention include a panel in which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are arranged, and a light emitting element disposed in each of the plurality of subpixels, And a transistor located on the light emitting diode, wherein the light emitting diode includes a transparent electrode disposed on an entire region of the rear surface, and an opaque electrode disposed on a part of the upper surface and connected to the transistor.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a transparent first electrode; a first semiconductor layer disposed on the first electrode; an active layer disposed on the first semiconductor layer; And a second electrode disposed on the second electrode and including a source electrode, a drain electrode, and a gate electrode, wherein a first distance between the gate electrode and the second semiconductor layer is a source electrode or a drain electrode, And a transistor that is longer than a second distance between the drain electrode and the second semiconductor layer.

According to embodiments of the present invention, a transistor can be grown on a micro-LED (μLED) grown on a wafer substrate, thereby realizing a micro-display device without transferring the micro-LED (μ LED) to a transistor substrate.

According to the embodiments of the present invention, the transistors are formed in the top gate structure on the micro-LED (μLED), and the emission area of the micro-LED (μ LED) due to the electrical connection structure of the micro- It prevents reduction and size increase. Accordingly, it is possible to provide a very small size micro-LED (μLED) having a maximized luminous efficiency, and to provide a micro-display device having a fixed tax using the micro-LED (μLED).

1 is a diagram showing a schematic configuration of a microdisplay device according to embodiments of the present invention.
2 is a diagram illustrating an example of a circuit structure of a subpixel arranged in a microdisplay device according to embodiments of the present invention.
3 is a view illustrating an example of a cross-sectional structure of a light emitting device according to embodiments of the present invention.
4A to 4C are views illustrating an example of a process of implementing the light emitting device shown in FIG.
5 is a view illustrating an exemplary planar structure of a display panel in which light emitting devices are arranged according to embodiments of the present invention.
6 is a view showing an example of a cross-sectional structure of a portion AA 'in the display panel shown in FIG.
7 is a view showing another example of the sectional structure of a portion AA 'in the display panel shown in FIG.
8 is a view showing another example of the cross-sectional structure of the portion AA 'in the display panel shown in FIG.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 shows a schematic configuration of a micro-display device 100 according to embodiments of the present invention.

1, a micro display device 100 according to embodiments of the present invention includes a display panel 110 in which a plurality of sub pixels SP including a micro light emitting diode (μLED) are arranged, A gate driving circuit 120, a data driving circuit 130, a controller 140, and the like for driving the data driver 110.

A plurality of gate lines GL and a plurality of data lines DL are arranged in the display panel 110 and sub pixels SP are arranged in a region where the gate lines GL and the data lines DL intersect each other . Each of the subpixels SP may include a micro light emitting diode (μLED), and two or more subpixels SP may constitute one pixel.

The gate driving circuit 120 is controlled by the controller 140 and sequentially outputs scan signals to a plurality of gate lines GL disposed on the display panel 110 to sequentially output driving timing of a plurality of sub- .

The gate driving circuit 120 may include one or more gate driver integrated circuits (GDICs), and may be located only on one side of the display panel 110 or on both sides of the display panel 110 It is possible. Alternatively, the gate driving circuit 120 may be located on the back surface of the display panel 110. [

The data driving circuit 130 receives the video data from the controller 140 and converts the video data into an analog data voltage. The data voltages are outputted to the respective data lines DL in accordance with the timing of applying the scan signals through the gate lines GL so that each subpixel SP expresses the brightness according to the image data.

The data driving circuit 130 may include one or more source driver integrated circuits (SDICs).

The controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130 and controls the operations of the gate driving circuit 120 and the data driving circuit 130.

The controller 140 causes the gate driving circuit 120 to output a scan signal according to the timing to be implemented in each frame and converts the image data received from the outside into a data signal format used in the data driving circuit 130 And outputs the converted image data to the data driving circuit 130.

The controller 140 outputs various timing signals including the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the input data enable signal DE, and the clock signal CLK, (E.g., a host system).

The controller 140 can generate various control signals using various timing signals received from the outside and output them to the gate driving circuit 120 and the data driving circuit 130. [

For example, in order to control the gate driving circuit 120, the controller 140 generates a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal GOE, Gate Output Enable) and the like.

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driving circuit 120. The gate shift clock GSC is a clock signal commonly input to one or more gate driver ICs, and controls the shift timing of the scan signal. The gate output enable signal GOE specifies the timing information of one or more gate driver ICs.

In order to control the data driving circuit 130, the controller 140 generates a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE, Source Output Enable) and the like.

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits constituting the data driving circuit 130. The source sampling clock SSC is a clock signal for controlling sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the data driving circuit 130.

The micro display device 100 includes a power management integrated circuit (IC) 100 that supplies various voltages or currents to the display panel 110, the gate driving circuit 120, the data driving circuit 130, As shown in FIG.

A voltage line to which various signals and voltages are supplied may be disposed on the display panel 110 in addition to the gate line GL and the data line DL. Each sub-pixel SP may include a micro- A transistor for driving the transistor may be disposed.

2 shows an example of a circuit structure of a sub-pixel SP arranged in a display panel 110 of a micro-display device 100 according to embodiments of the present invention.

Referring to FIG. 2, a sub-pixel SP arranged in a display panel 110 of a micro-display device 100 according to an embodiment of the present invention includes a gate line GL and a data line DL, do. The driving voltage line DVL to which the driving voltage Vdd is supplied and the common voltage line CVL to which the common voltage Vcom is supplied can be arranged.

Each subpixel SP includes a switching transistor SWT for controlling the operation timing of the driving transistor DRT and a storage capacitor Cst for driving the driving transistor DRT. Etc. may be disposed.

The switching transistor SWT is electrically connected between the data line DL and the first node N1 of the driving transistor DRT and is turned on by a scan signal applied to the gate line GL, (Vdata) to be supplied to the first node N1 of the driving transistor DRT.

The driving transistor DRT applies the driving voltage Vdd to the anode electrode of the micro light emitting diode LED according to the data voltage Vdata applied to the first node N1.

The storage capacitor Cst is electrically connected between the first node N1 and the third node N3 of the driving transistor DRT and supplies the data voltage Vdata applied to the first node N1 to one frame .

The micro light emitting diode (μLED) receives the driving voltage (Vdd) supplied to the anode electrode in accordance with the data voltage (Vdata), and receives the common voltage (Vcom) as the cathode electrode. The brightness according to the voltage difference between the anode electrode and the cathode electrode can be expressed.

In this micro light emitting diode (μLED), the anode electrode may be connected to the third node N3 of the driving transistor DRT, but may be connected to the driving voltage line DVL. That is, a structure in which one of the anode electrode and the cathode electrode of the micro light emitting diode (μLED) is connected to the driving transistor (DRT) and the other electrode is connected to the common voltage line (CVL) or the driving voltage line (DVL) And may be included in the scope of embodiments of the present invention.

The subpixels SP of the microdisplay device 100 may be implemented by transferring a micro-LED (μ LED) grown on a wafer substrate to a transistor substrate.

Alternatively, the microdisplay device 100 may be implemented without a transfer process by growing a micro-LED (μLED) and a transistor together on a wafer substrate. That is, the micro-light emitting diode (μLED) and the transistor grown on the wafer substrate constitute one light emitting element, and one light emitting element may constitute one sub-pixel (SP).

3 illustrates an example of a cross-sectional structure of a light emitting device 200 according to embodiments of the present invention. An example of a light emitting device 200 including a micro-LED (μ LED, 210) and a transistor 220 .

Referring to FIG. 3, a light emitting device 200 according to embodiments of the present invention includes a micro light emitting diode 210 and a transistor 220 disposed on the micro light emitting diode 210.

The micro light emitting diode 210 includes a common electrode 211, an n-type semiconductor layer 212 disposed on the common electrode 211, an active layer 213 disposed on the n-type semiconductor layer 212, A p-type semiconductor layer 214 disposed on the active layer 213 and individual electrodes 215 disposed on the p-type semiconductor layer 214.

The common electrode 211 may be a cathode electrode to which a negative voltage is applied as the electrode to which the common voltage Vcom is applied. The common electrode 211 may be a transparent electrode. For example, the common electrode 211 may be formed of indium tin oxide (ITO) or indium zinc oxide (IZO).

The n-type semiconductor layer 212 may be a semiconductor layer made of an n-GaN-based material, which is a semiconductor layer in which free electrons having negative charges move as a carrier to generate a current. As the n-GaN-based semiconductor material, GaN, AlGaN, InGaN, AlInGaN or the like may be used. As the impurity used for doping the n-type semiconductor layer 212, Si, Ge, Se, Te, . Although not shown in the drawing, a buffer layer such as a GaN-based semiconductor layer that is not doped may be formed between the n-type semiconductor layer 212 and the common electrode 211.

The active layer 213 may have a multi quantum well (MQW) structure disposed on the n-type semiconductor layer 212 and having a barrier layer having a higher bandgap than that of the well layer and the well layer. The active layer 213 may have a multiple quantum well structure such as InGaN / GaN.

The p-type semiconductor layer 213 may be a semiconductor layer made of a p-GaN-based material, in which holes having a positive charge move as a carrier to generate a current. As the p-GaN semiconductor material, GaN, AlGaN, InGaN, AlInGaN or the like may be used. As the impurity used for doping the p-type semiconductor layer 213, Mg, Zn, Be and the like may be used.

The individual electrodes 215 are disposed on the p-type semiconductor layer 213 and can receive a voltage corresponding to the data voltage Vdata through the transistor 220. The individual electrode 215 may be an anode electrode to which a positive voltage is applied.

The individual electrodes 215 may be formed of a metal material having high conductivity since a voltage supplied through the transistor 220 must be transmitted to the p-type semiconductor layer 214. That is, it may be an opaque electrode. Since the individual electrodes 215 are electrically connected to the transistor 220, they may include a material having good bonding properties. For example, the individual electrode 215 may be made of a Ni / Au alloy or a Ti / Au alloy.

When a positive voltage is applied through the individual electrodes 215 and a negative voltage is applied through the common electrode 211, the electrons in the n-type semiconductor layer 212 and the holes in the p-type semiconductor layer 214 A current flows between the individual electrode 215 and the common electrode 211. [ The active layer 213 emits light by recombination of electrons and holes depending on the current flowing between the individual electrode 215 and the common electrode 211.

The transistor 220 may be located on a separate electrode 215 of the micro-light emitting diode 210.

That is, by forming the transistor 220 on the micro light emitting diode 210, the light emitting device 200 can be realized without transferring the micro light emitting diode 210 to the substrate on which the transistor 220 is formed.

In addition, since the transistor 220 is positioned on the micro-LED 210, the light emitting device 200 is implemented without etching the light emitting area of the micro light emitting diode 210, thereby maximizing the light emitting efficiency of the light emitting device 200 can do.

The transistor 220 disposed on the micro light emitting diode 210 includes a source electrode 221 and a drain electrode 222. The drain electrode 222 is connected to the individual electrodes 215 of the micro light emitting diode 210, And can be electrically connected. A channel layer 223 is disposed on the source electrode 221 and the drain electrode 222 and a gate insulating layer 224 is disposed on the channel layer 223. A gate electrode 225 is disposed on the gate insulating layer 224.

A data voltage Vdata applied to the source electrode 221 may be transmitted to the drain electrode 222 through the channel layer 223 and may be applied to the individual electrode 215 when a scan signal is applied to the gate electrode 225 . When a voltage corresponding to the data voltage Vdata is applied to the gate electrode 225, the driving voltage Vdd applied to the source electrode 221 is applied to the drain electrode 222 by a voltage corresponding to the data voltage Vdata And may be supplied to the individual electrodes 215.

Here, the transistor 220 may have a top gate structure in which the gate electrode 225 is located above the transistor 220. That is, the source electrode 221 and the drain electrode 222 are located adjacent to the p-type semiconductor layer 214 and the gate electrode 225 is formed from the p-type semiconductor layer 214 to the source electrode 221 and the drain electrode 222 ). ≪ / RTI > For example, the distance between the gate electrode 221 and the p-type semiconductor layer 214 may be d1, the distance between the source electrode 221 and the drain electrode 222 and the p-type semiconductor layer 214 may be d2, d2.

The source electrode 221 and the drain electrode 222 can be positioned adjacent to the p-type semiconductor layer 214 by allowing the gate electrode 225 to be positioned above the transistor 220 in this way.

Therefore, in order to electrically connect the drain electrode 222 of the transistor 220 and the individual electrode 215 of the micro light emitting diode 210, a structure similar to a via hole may not be formed. Therefore, it is possible to prevent the size of the micro light emitting diode 210 from increasing due to the formation of the via hole.

The light emitting device 200 may be implemented by growing a micro light emitting diode 210 on a wafer substrate and then growing the transistor 220 on the micro light emitting diode 210.

4A to 4C illustrate examples of a process of implementing the light emitting device 200 according to the embodiments of the present invention.

4A, an n-type semiconductor layer 212, an active layer 213, and a p-type semiconductor layer 214 are grown by performing an epitaxial process on a sapphire substrate 300.

Then, individual electrodes 215, which are anode electrodes, are formed on the p-type semiconductor layer 214. These individual electrodes 215 may be formed only in a part of the region on the p-type semiconductor layer 214.

Also, the individual electrodes 215 may be made of a metal material having good conductivity and bonding property, as described above.

After the formation of the n-type semiconductor layer 212, the active layer 213, the p-type semiconductor layer 214 and the individual electrodes 215 on the sapphire substrate 300, the transistor 220 is formed on the individual electrode 215, Is formed.

Referring to FIG. 4B, the planarization layer 230 is formed on the p-type semiconductor layer 214 after the individual electrodes 215 are formed. The planarization layer 230 may be disposed so as to expose the individual electrodes 215.

A source electrode 221 and a drain electrode 222 are formed on the planarization layer 230.

A channel layer 223 as a semiconductor material and a gate insulating layer 224 made of an insulating material are formed on the source electrode 221 and the drain electrode 222. A gate electrode 225 is formed on the gate insulating layer 224, .

A protective layer 240 for protecting the transistor 220 may be disposed on the gate electrode 225. The protective layer 240 may be made of SiO 2, and the protective layer 240 and the planarization layer 230 may be made of the same material.

After the formation of the transistor 220 is completed, a process of separating the n-type semiconductor layer 212 from the sapphire substrate 300 is performed.

For example, a laser may be irradiated on the lower surface of the sapphire substrate 300 to separate the n-type semiconductor layer 212 from the sapphire substrate 330 (LLO, Laser Lift Off).

When the n-type semiconductor layer 212 is separated from the sapphire substrate 330, the common electrode 211 is formed.

Referring to FIG. 4C, the common electrode 211 is formed on the lower surface of the n-type semiconductor layer 212 separated from the sapphire substrate 330.

The common electrode 211 may be a cathode electrode to which a negative voltage is applied, and may be made of ITO or IZO, which is a transparent conductive material, as described above.

As described above, in the light emitting device 200 according to the embodiments of the present invention, the p-type electrode and the n-type electrode of the micro light emitting diode 210 are arranged in the vertical direction. The electrode connected to the transistor 220 is made of a metal material having good conductivity and the electrode opposite to the electrode is made of a transparent conductive material so that light emitted from the active layer 213 can be emitted.

The transistor 220 is formed on the micro light emitting diode 210 so that the micro light emitting diode 210 can be implemented without transferring the micro light emitting diode 210 to the substrate on which the transistor 220 is formed.

That is, the microdisplay device 100 can be realized by forming the transistor 220 on the substrate on which the micro light emitting diode 210 is grown.

In addition, by arranging the transistor 220 disposed on the micro light emitting diode 210 in a top gate structure, it is possible to simplify the structure for electrically connecting the electrode of the micro light emitting diode 210 and the electrode of the transistor 200 have.

Therefore, since a structure such as a via hole is not required in the light emitting device 200, it is possible to prevent a reduction in the light emitting area and an increase in the chip size due to the formation of the via hole. By implementing the microdisplay device 100 using the light-emitting device 200 having the smallest light-emitting efficiency, the microdisplay device 100 can be fixed.

FIG. 5 illustrates an exemplary planar structure of a display panel 110 in which a light emitting device 200 according to embodiments of the present invention is disposed.

Referring to FIG. 5, each of the light emitting devices 200 may be disposed on a display panel 110 of a microdisplay device 100 according to an embodiment of the present invention.

Each of the light emitting devices 200 includes a micro light emitting diode 210 in which individual electrodes 215 as an anode electrode and a common electrode 211 as a cathode electrode are arranged in a vertical direction, (220).

The source electrode 221 and the drain electrode 222 of the transistor 220 constituting the light emitting element 200 are disposed between the gate electrode 225 and the micro light emitting diode 210 and are adjacent to the micro light emitting diode 210 A top gate structure.

Since the transistor 220 is formed on the micro light emitting diode 210, the light emitting device 200 can be formed without transferring the micro light emitting diode 210. The transistor 220 may be formed in a top gate structure so that the light emitting region of the micro light emitting diode 210 may be etched or the micro light emitting diode 210 and the transistor 220 may be formed without forming a via hole in the light emitting device 200. [ Can be electrically connected to each other.

Therefore, it is possible to maximize the light emitting area of the micro light emitting diode 210 and to provide the light emitting device 200 having a small chip size.

The microdisplay device 100 can be implemented through a process of fabricating the plurality of light emitting devices 200 by performing the process of forming the transistor 220 on the micro light emitting diode 210.

Here, the common electrode 211 located under the micro light emitting diode 210 may have a structure shared by the adjacent light emitting devices 200.

That is, the common voltage Vcom is supplied to the n-type semiconductor layer 212 of the adjacent light emitting device 200 through the common electrode 211, and the p-type semiconductor layer 214 is electrically connected to the n- The voltage is supplied to each of the light emitting devices 200 so that each of the light emitting devices 200 disposed in each of the sub pixels SP can be driven.

6 shows an example of a cross-sectional structure of a portion A-A 'shown in FIG. 5, and shows an example of a cross-sectional structure of a light emitting device 200 disposed in three adjacent sub-pixels SP.

6, each of the light emitting devices 200 disposed in three adjacent sub-pixels SP may include a micro light emitting diode 210 and a transistor 220 formed on the micro light emitting diode 210 have.

The micro light emitting diode 210 may include a common electrode 211, an n-type semiconductor layer 212, an active layer 213, a p-type semiconductor layer 214 and individual electrodes 215.

Here, the common electrode 211 may be arranged in a structure shared by the light emitting device 200 disposed in adjacent sub-pixels SP. The n-type semiconductor layer 212 disposed on the common electrode 211 may also be shared by the adjacent subpixels SP.

Specifically, the n-type semiconductor layer 212 is disposed on the common electrode 211. The n-type semiconductor layer 212 may be divided into a boundary area BA (BA) between the emission area EA where the light emitted from the active layer 213 is emitted and the emission area EA . That is, the boundary area BA may be a region corresponding to a boundary between adjacent subpixels SP.

The n-type semiconductor layer 212 may include a groove located in the boundary region BA. The depth of the groove may be smaller than the thickness of the n-type semiconductor layer 212.

The active layer 213 and the p-type semiconductor layer 214 may be stacked on the n-type semiconductor layer 212 in a region corresponding to the light emitting region EA.

That is, the n-type semiconductor layer 212 is disposed on the common electrode 211 and the active layer 213 and the p-type semiconductor layer 214 are separated on the n-type semiconductor layer 212 for each light emitting region EA So that one subpixel SP can be formed.

As described above, the active layer 213 and the p-type semiconductor layer 214, which are disposed in each subpixel SP, are arranged in a structure insulated by the boundary region BA, and p The insulating material 250 may be disposed in the boundary region BA between the first semiconductor layer 214 and the second semiconductor layer 214. The insulating material 250 may be disposed in a groove included in the n-type semiconductor layer 212. The insulating material 250 may be disposed to surround at least a part of the side surfaces of the active layer 213 and the p-type semiconductor layer 214 and the side surface of the n-type semiconductor layer 212.

the individual electrodes 215 may be disposed on the p-type semiconductor layer 214 and the individual electrodes 215 may be disposed on the light emitting region EA.

A transistor 220 is disposed on the individual electrode 215 and a transistor 220 may be disposed for each sub-pixel SP.

The transistor 220 may include a source electrode 221, a drain electrode 222, a channel layer 223, a gate insulating layer 224, and a gate electrode 225.

More specifically, the source electrode 221 and the drain electrode 222 are located on the individual electrodes 215 of the micro light emitting diode 210, and the individual electrodes 215 and the drain electrodes 222 are electrically connected to each other. have. A planarization layer 230 may be disposed between the source electrode 221 and the p-type semiconductor layer 214.

A channel layer 223 may be disposed on the source electrode 221 and the drain electrode 222 and the source electrode 221 and the drain electrode 222 may be electrically connected through the channel layer 223. [ A gate insulating layer 224 and a gate electrode 225 are sequentially disposed on the channel layer 223.

Therefore, the gate electrode 225 may have a top gate structure in which the gate electrode 225 is located above the source electrode 221 or the drain electrode 222, based on the position of the micro light emitting diode 210.

According to the structure of the light emitting device 200, the microdisplay device 100 can be implemented through a process of forming the micro light emitting diode 210 and the transistor 220 on the wafer substrate.

An n-type semiconductor layer 212, an active layer 213, and a p-type semiconductor layer 214 are grown on a sapphire substrate 300. [ Then, a portion corresponding to the boundary region BA is etched in the micro-light emitting diode 210 in which no electrode is formed.

The active layer 213 and the p-type semiconductor layer 214 are separated from each other by the etching process, and the n-type semiconductor layer 212 may have a groove located in the boundary region BA.

Then, individual electrodes 215 are formed on the separated p-type semiconductor layer 214, respectively. The individual electrodes 215 may be made of a metal alloy having good conductivity and good bonding property.

When formation of the individual electrodes 215 is completed, a process of forming the transistors 220 located on the individual electrodes 215 is performed.

A planarization layer 230 is disposed on the p-type semiconductor layer 214. The planarization layer 230 is disposed such that the individual electrodes 215 are exposed.

A source electrode 221 and a drain electrode 222 are formed on the planarization layer 230 and the individual electrodes 215.

The transistor 220 can be formed through a process of sequentially laminating a channel layer 223, a gate insulating layer 224 and a gate electrode 225 on the source electrode 221 and the drain electrode 222. [

A protective layer 240 may be formed on the transistor 220 and an insulating material 250 may be disposed on a portion corresponding to the boundary region BA in the micro light emitting diode 210. [ The insulating material 250 may be disposed in the process of forming the planarization layer 230 on the micro light emitting diode 210 or may be disposed in the process of forming the protective layer 240. In addition, the insulating material 250 may be the same material as the material of the planarization layer 230 or the protective layer 240.

When the formation of the transistor 220 is completed, the n-type semiconductor layer 212 is separated from the sapphire substrate 300, the common electrode 211 is formed on the lower surface of the separated n-type semiconductor layer 212, A plurality of light emitting devices 200 can be manufactured.

The microdisplay device 100 may be implemented by connecting a driving circuit for driving the display to the plurality of light emitting devices 200.

Accordingly, by implementing the light emitting device 200 through the process of forming the transistor 220 on the micro light emitting diode 210, the micro display device 100 can be realized without a transfer process. Since only the boundary region BA corresponding to the boundary of the subpixel SP is etched in the micro light emitting diode 210, the light emitting area of the microproluminescent diode 210 constituting the subpixel SP can be maximized .

The transistor 220 may be disposed in a top gate structure to directly connect the drain electrode 222 and the individual electrode 215 to form a separate structure for electrically connecting the micro light emitting diode 210 and the transistor 220. [ (For example, a via hole). In addition, since the structure like the via hole is not required, the size of the light emitting device 200 can be minimized so that the fixed cell can be formed.

Meanwhile, in the structure in which the plurality of light emitting devices 200 are integrally formed, the depth of the groove located in the boundary region BA of the micro light emitting diode 210 can be variously designed.

FIG. 7 illustrates another example of the cross-sectional structure of the portion A-A 'shown in FIG. 5, and shows an example of a structure in which the depth of the groove formed in the boundary region BA of the micro light-emitting diode 210 is differently implemented.

Referring to FIG. 7, the n-type semiconductor layers 212 may be arranged in a structure in which the light emitting devices 200 constituting the adjacent subpixels SP are separated from the light emitting devices 200.

The n-type semiconductor layer 212, the active layer 213, and the p-type semiconductor layer 214 are grown on the sapphire substrate 300. [ Then, a portion corresponding to the boundary region BA is etched in the micro-light emitting diode 210 having no electrode.

Here, the p-type semiconductor layer 214, the active layer 213, and the n-type semiconductor layer 212 can be separated by etching the portion corresponding to the boundary region BA. Alternatively, only the p-type semiconductor layer 214 and the active layer 213 may be separated through an etching process.

That is, in order for each light emitting element 200 constituting each subpixel SP to be driven independently, the p-type semiconductor layer 214 and the active layer 213 constituting any one of the light emitting elements 200 It should be insulated from the p-type semiconductor layer 214 and the active layer 213 constituting the other light emitting element 200.

Therefore, the groove may be formed at a portion corresponding to the boundary region in the micro-LED 210 having no electrode. The depth of the groove may be greater than the thickness of the p-type semiconductor layer 214 and the active layer 213, -Type semiconductor layer 214, the active layer 213, and the n-type semiconductor layer 212. In this case,

When the etching process is completed, individual electrodes 215 of the respective micro-light emitting diodes 210 are formed and transistors 220 located on the individual electrodes 215 are formed.

When the formation of the transistor 220 is completed, a protective layer 240 may be disposed on the transistor 220, and an insulating material 250 may be disposed in the groove formed in the micro light emitting diode 210.

Then, a process of separating the n-type semiconductor layer 212 from the sapphire substrate 330 is performed.

Since the plurality of light emitting devices 200 can be fixed by the protective layer 240 and the insulating material 250 or the like, the n-type semiconductor layer 212 is etched to be separated for each light emitting device 200 and the sapphire substrate 300 The plurality of light emitting devices 200 are not separated from each other.

When the sapphire substrate 300 is separated, the common electrode 211 may be formed on the lower surface of the n-type semiconductor layer 212 to complete a plurality of integrated light emitting devices 200. Since the plurality of light emitting devices 200 have a structure in which the common electrode 211 corresponding to the cathode electrode is shared, driving can be facilitated as compared with a structure in which the cathode electrode is separately formed for each light emitting device 200.

In addition, since the common electrode 211 is disposed as a transparent electrode, light can be emitted to a bottom surface of a plurality of light emitting devices 200 formed integrally, and an image can be displayed. A configuration for expressing hue may be disposed on the lower surface of the common electrode 211.

FIG. 8 shows another example of the cross-sectional structure of the portion AA 'shown in FIG. 5, and shows an example of a structure in which the light emitting device 200 according to the embodiments of the present invention further includes a structure for expressing colors .

Referring to FIG. 8, a plurality of integrally formed light emitting devices 200 may have a structure in which a micro light emitting diode 210 and a transistor 220 are stacked. The micro light emitting diode 210 includes a common electrode 211 and an n-type semiconductor layer 212 shared by the plurality of light emitting devices 200, an active layer 213 separated for each light emitting device 200, a p-type semiconductor layer 214 and individual electrodes 215.

The transistor 220 may be disposed in a top gate structure disposed on each of the micro-light emitting diodes 210 and the drain electrode 222 is positioned adjacent to the individual electrodes 215. [

The light emitting device 200 may further include color conversion layers 261, 262, and 263 disposed on the lower surface of the common electrode 211.

The color conversion layers 261, 262, and 263 may be disposed on the lower surface of the common electrode 211 in a region corresponding to the light emitting region EA. The light emitted from the micro light emitting diode 210 may be red, green, and blue light.

The color conversion layers 261, 262, and 263 may be formed of, for example, a phosphor that absorbs or emits light in a specific wavelength band, or may be formed of quantum dot or nano organic materials. Alternatively, it may be constituted by a color filter passing only light of a specific wavelength band. Alternatively, it may be composed of a phosphor emitting light of a specific wavelength band and a color filter passing light of a specific wavelength band.

That is, the color conversion layers 261, 262, and 263 may be formed of various materials that allow light emitted from the micro light emitting diode 210 to exhibit a specific color.

A barrier rib (for example, a black matrix) may be disposed between the adjacent color conversion layers 261, 262, and 263 to prevent color mixing. However, the light emitting device 200 according to embodiments of the present invention may include a color conversion layer 261, 262, and 263 may not include the barrier ribs.

This makes it possible to realize a very small size of the light emitting device 200 by disposing the transistor 220 of the top gate structure on the micro light emitting diode 210 whose electrodes are vertically arranged to configure the light emitting device 200.

Therefore, it may not be possible to recognize color mixing represented by the light emitted from the ultrasmall light emitting device 200, so that the barrier ribs may not be disposed between the color conversion layers 261, 262, and 263, (261, 262, 263) may be disposed in contact with each other.

According to the embodiments of the present invention, the transistor 220 is formed on the micro-LED 210, and the micro-LED 210 is transferred to the substrate on which the transistor 220 is disposed, ) And the microdisplay device 100 can be implemented.

In addition, since the electrodes of the micro light emitting diode 210 are vertically arranged and the transistor 220 is formed of a top gate structure, it is possible to prevent a decrease in the light emitting area and an increase in the chip size, (200).

Therefore, the sub pixels SP are formed by using the ultra-small light emitting device 200, so that the fixed tax of the micro display device 100 can be achieved. In addition, a plurality of light emitting devices 200 can be manufactured at the same time, and the plurality of light emitting devices 200 itself can constitute a display device, thereby facilitating the implementation of the micro display device 100.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the scope of the present invention but to limit the scope of the technical idea of the present invention. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: Micro display device 110: Display panel
120: Gate driving circuit 130: Data driving circuit
140: controller 200: light emitting element
210: micro light emitting diode 211: common electrode
212: n-type semiconductor layer 213: active layer
214: p-type semiconductor layer 215: individual electrode
220: transistor 221: source electrode
222: drain electrode 223: channel layer
224: gate insulating layer 225: gate electrode
230: planarization layer 240: protective layer
250: insulating material 261, 262, 263: color conversion layer
300: sapphire substrate

Claims (15)

A common electrode;
An n-type semiconductor layer disposed on the common electrode and divided into a boundary region between the light emitting region and the light emitting region;
A plurality of active layers disposed on the n-type semiconductor layer in the light emitting region;
A plurality of p-type semiconductor layers respectively disposed on the plurality of active layers;
A plurality of discrete electrodes disposed on the plurality of p-type semiconductor layers, respectively; And
A plurality of individual electrodes disposed on the plurality of individual electrodes, respectively,
Lt; / RTI >
The method according to claim 1,
Each of the plurality of transistors comprising:
A source electrode, a drain electrode, and a gate electrode,
Wherein a first distance between the gate electrode and the p-type semiconductor layer is longer than a second distance between the source electrode or the drain electrode and the p-type semiconductor layer.
The method according to claim 1,
Wherein each of the plurality of active layers disposed in the light emitting region is insulated from each other by the boundary region, and each of the plurality of p-type semiconductor layers disposed on the plurality of active layers is insulated from each other by the boundary region.
The method according to claim 1,
Type semiconductor layer,
And a groove located in the boundary region.
5. The method of claim 4,
Wherein a depth of the groove included in the n-type semiconductor layer is equal to or smaller than a thickness of the n-type semiconductor layer.
5. The method of claim 4,
And an insulating material located in the groove included in the n-type semiconductor layer,
Wherein the insulating material
Type semiconductor layer, the p-type semiconductor layer, the active layer, and the n-type semiconductor layer.
The method according to claim 1,
Wherein the common electrode is a transparent electrode and the plurality of discrete electrodes are opaque electrodes.
The method according to claim 1,
The p-type semiconductor layer is disposed in the entire region of the active layer, and the individual electrodes are disposed in a partial region on the p-type semiconductor layer.
The method according to claim 1,
A planarization layer disposed in a region between the p-type semiconductor layer and the transistor except a region where the individual electrodes are disposed; And
And a protective layer disposed on the transistor.
The method according to claim 1,
And a plurality of color conversion layers disposed on the back surface of the common electrode and arranged separately for each region corresponding to the light emitting region.
A panel in which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are arranged; And
And a light emitting element disposed in each of the plurality of subpixels,
The light-
A light emitting diode and a transistor located on the light emitting diode,
The light-
A transparent electrode disposed on the entire region of the back surface; and an opaque electrode disposed on a part of the upper surface and connected to the transistor.
12. The method of claim 11,
The transistor comprising:
A source electrode, a drain electrode, and a gate electrode,
Wherein a first distance between the gate electrode and the light emitting diode is longer than a second distance between the source electrode or the drain electrode and the light emitting diode.
A transparent first electrode;
A first semiconductor layer disposed on the first electrode;
An active layer disposed on the first semiconductor layer;
A second semiconductor layer disposed on the active layer;
An opaque second electrode disposed on the second semiconductor layer; And
Wherein a first distance between the gate electrode and the second semiconductor layer is greater than a distance between the source electrode or the drain electrode and the second semiconductor layer, the source electrode, the drain electrode and the gate electrode being located on the second electrode, A transistor longer than the second distance
.
14. The method of claim 13,
A planarization layer disposed in a region between the second semiconductor layer and the transistor except for a region where the second electrode is disposed; And
And a protective layer disposed on the transistor.
15. The method of claim 14,
The protective layer may be formed,
Wherein the first semiconductor layer surrounds the second semiconductor layer and the active layer, and surrounds at least a part of the outer surface of the first semiconductor layer.

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