KR20190064091A - Organic light emitting display device - Google Patents

Abstract

The present application relates to an organic light emitting display capable of reducing a voltage deviation of a reference power voltage by preventing a VSS rising phenomenon in which the potential of the reference power voltage rises due to a surface resistance of a source/drain metal layer and a cathode electrode for each region of a display panel. According to the present application, the organic light emitting display comprises: the display panel having a display region provided with pixels for displaying an image and a non-display region provided so as to surround the display region; a cathode electrode arranged integrally on the display region and the non-display region; and a plurality of reference power voltage lines arranged on the non-display region and supplying reference power voltages to the cathode electrode. Each of the plurality of reference power voltage lines supplies different reference power voltages.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

The present invention relates to an organic light emitting display.

Description of the Related Art [0002] A display device technology for displaying visual information as an image or an image in an information society has been developed. Among display devices, an organic light emitting display uses an organic light emitting diode that generates light by recombination of electrons and holes to display an image. The organic light emitting display device has a fast response speed and is capable of expressing low gradation according to the self light emission, and thus, it is attracting attention as a next generation display.

The organic light emitting display includes a display region provided with pixels for displaying an image and a display panel disposed outside the display region and having a non-display region that does not display an image. Each of the pixels is driven by a scan signal and emits light at a brightness corresponding to the magnitude of the data voltage.

Further, in order to drive the display panel, the reference power supply voltage (VSS voltage) must be supplied to the cathode electrode of the display panel. In order to supply the reference power source voltage, the reference power source voltage was supplied to the cathode electrode deposited on the entire surface of the display panel through the contact hole penetrating the planarization film, connected to the reference power source voltage line composed of one source / drain metal layer. In this case, a difference occurs in the reference power supply voltage of the cathode electrode within the plane of the display panel due to the surface resistance of the cathode electrode and the line resistance of the reference power supply voltage line.

The potential of the reference power supply voltage is lower than the potential of the ground voltage. Accordingly, the potential value of the reference power supply voltage has a negative value. A VSS Rising phenomenon occurs in which the potential of the reference power supply voltage rises due to the surface resistance of the source / drain metal layer and the cathode electrode in each region of the display panel. When the VSS rising phenomenon occurs, a voltage deviation of the reference power supply voltage occurs between the upper portion of the display panel, which is the portion where the reference power supply voltage is supplied from the display panel, and the lower portion of the display panel, which is the portion opposite to the portion where the reference power supply voltage is supplied . As a result of simulation, the lower part of the display panel is the point at which the most trouble occurs (Worst Point). When the reference power supply voltage is -2.5 V in the normal case, the reference power supply voltage is -2.18 V and the VSS rising phenomenon occurs 0.32 V in the lower part of the display panel.

The present invention relates to an organic light emitting diode (OLED) display device capable of preventing a VSS rising phenomenon, which is a phenomenon in which a potential of a reference power source voltage rises due to a surface resistance of a source / drain metal layer and a cathode electrode, Device.

The organic light emitting display according to the present application includes a display panel having a display region provided with pixels for displaying an image and a non-display region provided so as to surround the display region, a cathode electrode disposed integrally on the display region and the non- And a plurality of reference power supply voltage lines arranged in a non-display area for supplying a reference power supply voltage to the cathode electrodes. Each of the plurality of reference power supply voltage lines supplies different reference power supply voltages.

The present application can provide a structure for separating a reference power supply voltage line and applying a reference power supply voltage that supplies the reference power supply voltage line to each of the reference power supply voltage lines to reduce a voltage deviation for each region of the display panel. The present application can reduce the voltage deviation of the cathode electrode of the worst point when the VSS rising phenomenon occurs. As a result of a simulation in which the reference power supply voltage supplied to the top of the display panel is set to -2.5 V and the reference power supply voltage supplied to the lower portion of the display panel is set to -2.7 V, the VSS Rising level is 0.09 V, 70% less than 0.32V.

1 is a conceptual block diagram of an organic light emitting diode display according to the present application.
2 is an internal circuit diagram of a pixel according to an example of the present application.
3 is a cross-sectional view of a pixel according to an example of the present application.
4 is a plan view showing a plurality of reference power source voltage lines and a cathode electrode according to an example.
Fig. 5 is an equivalent circuit diagram of Fig.
6 is a plan view showing a plurality of reference power source voltage lines and a cathode electrode according to another example.
7 is a plan view showing a plurality of reference power supply voltage lines, an anode electrode, and a cathode electrode according to yet another example.
8 is a cross-sectional view showing I-I 'of Fig.
9 is a plan view showing a plurality of reference power supply voltage lines, an anode electrode, and a cathode electrode according to yet another example.
10 is a cross-sectional view showing II-II` of FIG.

Brief Description of the Drawings The advantages and features of the present application, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that this application is not limited to the examples disclosed herein, but may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein, To fully disclose the scope of the invention to those skilled in the art, and this application is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like described in the drawings for describing an example of the present application are illustrative, and thus the present application is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the description of the present application, a detailed description of known related arts will be omitted if it is determined that the gist of the present application may be unnecessarily obscured.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the scope of the present application.

The terms "first horizontal axis direction "," second horizontal axis direction ", and "vertical axis direction" should not be interpreted solely by the geometric relationship in which the relationship between them is vertical, It may mean having a wider directionality in the inside.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

Each of the features of the various embodiments of the present application may be combined or combined with each other partially or entirely, technically various interlocking and driving are possible, and the examples may be independently performed with respect to each other, .

Hereinafter, preferred embodiments of the organic light emitting display according to the present application will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings.

1 is a conceptual block diagram of an organic light emitting diode display according to the present application. The OLED display includes a display panel 100, a gate driver 110, a data driver 120, and a timing controller (T-CON) 130.

The display panel 100 includes a display area and a non-display area provided around the display area. The display area is an area where pixels P are provided to display an image. The non-display area is an area outside the display panel 100 and protects the display area from external impact. The display panel 100 is provided with gate lines GL1 to GLp, p is a positive integer of 2 or more, data lines DL1 to DLq, q is a positive integer of 2 or more, and sensing lines SL1 to SLq do.

The data lines DL1 to DLq and the sensing lines SL1 to SLq may intersect the gate lines GL1 to GLp. The data lines DL1 to DLq and the sensing lines SL1 to SLq may be parallel to each other. The display panel 100 may include a lower substrate on which pixels P are provided and an upper substrate that performs an encapsulation function to protect pixels P from foreign substances. Each of the pixels P may be connected to any one of the gate lines GL1 to GLp and one of the data lines DL1 to DLq and the sensing lines SL1 to SLq.

The gate driving unit 120 receives the gate driving unit control signal GCS from the timing controller 130 and generates gate signals according to the gate driving unit control signal GCS and supplies the gate signals to the gate lines GL1 to GLp.

The data driver 120 receives the data driver control signal DCS from the timing controller 130 and generates data voltages according to the data driver control signal DCS to supply the data voltages to the data lines DL1 to DLq. The data driver 120 senses voltage and current characteristics of each of the pixels P to generate sensing data SEN and supplies the sensing data SEN to the timing controller 130.

The timing controller 130 is supplied with digital video data DATA including a timing signal TS for controlling the display timing of an image from outside and color-specific information for implementing an image. A timing signal TS and digital video data DATA are input to the input terminal of the timing controller 130 according to a protocol set. The timing controller 130 receives the sensing data SEN according to the voltage and current characteristics of the pixels P from the data driver 120.

The timing signal TS includes a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal DE and a dot clock DCLK. . The timing controller 130 compensates the digital video data (DATA) based on the sensing data SEN.

The timing controller 130 generates driving unit control signals for controlling the operation timings of the gate driving unit 110, the data driving unit 120, the scan driving unit, and the sensing driving unit. The driving unit control signals include a gate driving unit control signal GCS for controlling the operation timing of the gate driving unit 110, a data driving unit control signal DCS for controlling the operation timing of the data driving unit 120, And a sensing driver control signal for controlling the operation timing of the sensing driver.

The timing controller 130 operates the data driver 120, the scan driver, and the sensing driver in one of a display mode and a sensing mode according to a mode signal. The display mode is a mode in which the pixels P of the display panel 100 display an image and the sensing mode is a mode of sensing the current of the drive transistor DT of each of the pixels P of the display panel 100. [ When the waveform of the scan signal and the waveform of the sensing signal supplied to each of the pixels P in the display mode and the sensing mode are changed, the data driver control signal DCS, the scan driver control signal, The sensing driver control signal can also be changed. Accordingly, the timing controller 130 generates the data driver control signal DCS, the scan driver control signal, and the sensing driver control signal according to the mode, depending on whether the display mode or the sensing mode.

The timing controller 130 outputs the gate driver control signal GCS to the gate driver 110. [ The timing controller 130 outputs the compensated digital video data and the data driver control signal DCS to the data driver 120. The timing controller 130 outputs a scan driver control signal to the scan driver. The timing controller 130 outputs a sensing driver control signal to the sensing driver.

The timing controller 130 generates a mode signal for driving the data driving unit 120, the scan driving unit, and the sensing driving unit depending on which of the display mode and the sensing mode is driven. The timing controller 130 operates the data driver 120, the scan driver, and the sensing driver in one of a display mode and a sensing mode according to a mode signal.

2 is an internal circuit diagram of a pixel P according to an example of the present application. The pixel P according to one example includes a driving transistor DT, a light emitting element EL, a storage capacitor Cst, and first through sixth transistors T1 through T6. In the following description, the driving transistor DT and the first to sixth transistors T1 to T6 according to an example of the present application have a gate electrode, a source electrode, and a drain electrode It is assumed that the MOSFET is implemented as a P-type MOSFET.

A gate electrode of the driving transistor DT is connected to a first node N1 to which one electrode of the storage capacitor Cst, a drain electrode of the first transistor T1, and a drain electrode of the fifth transistor T5 are connected, Respectively. The source electrode of the driving transistor DT is connected to the drain electrode of the third transistor T3 which receives the pixel driving power ELVDD as a source electrode. The drain electrode of the driving transistor DT is connected to the source electrode of the fourth transistor T4.

And is turned on when a voltage higher than the threshold voltage is supplied to the gate electrode of the driving transistor DT. The turned-on driving transistor DT passes a driving current from the source electrode to the drain electrode.

The light emitting element EL includes an anode electrode and a cathode electrode. The light emitting element EL flows a driving current from the anode electrode to the cathode electrode. The anode electrode of the light emitting device EL is connected to the second node N2 to which the drain electrode of the fourth transistor T4 is connected. The cathode electrode of the light emitting device EL is connected to the cathode electrode of the ground line where the low potential supply voltage ELVSS is formed. The light emitting element EL emits light with brightness corresponding to the driving current flowing from the driving transistor DT.

The storage capacitor Cst has both electrodes. One electrode of the storage capacitor Cst is connected to the first node N1. The other electrode of the storage capacitor Cst is connected to the pixel drive power supply ELVDD line.

The storage capacitor Cst stores the difference voltage between the pixel drive power source ELVDD and the first node N1 when the fifth transistor T5 connected to the first node N1 is turned on. The storage capacitor Cst maintains the difference voltage stored in the first node N1 when the fifth transistor T5 is turned off. Further, the storage capacitor Cst can control driving of the driving transistor DT by using the stored and held voltage.

The gate electrode of the first transistor T1 receives the second scan signal Scan2. The source electrode of the first transistor T1 is connected to the drain electrode of the driving transistor DT. The drain electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 is turned on by the second scan signal Scan2 so that the voltage of the first node N1 is set to Vdata which is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT. + Vtp.

The gate electrode of the second transistor T2 receives the second scan signal Scan2. The source electrode of the second transistor T2 is connected to the data line DL to receive the data voltage Vdata. The drain electrode of the second transistor T2 is connected to the source electrode of the driving transistor DT. The second transistor T1 is turned on by the second scan signal Scan2 and supplies the data voltage Vdata to the source electrode of the driving transistor DT.

The gate electrode of the third transistor T3 is supplied with the emission control signal EM. The source electrode of the third transistor T3 is supplied with the pixel driving power ELVDD. The drain electrode of the third transistor T3 is connected to the source electrode of the driving transistor DT. The third transistor T3 is turned on by the emission control signal EM and supplies the pixel driving power ELVDD to the driving transistor DT so that the driving transistor DT allows the driving current to flow.

The gate electrode of the fourth transistor T4 is supplied with the emission control signal EM. The source electrode of the fourth transistor T4 is connected to the drain electrode of the driving transistor DT. The drain electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 is turned on by the emission control signal EM so that a drive current flows through the light emitting element EL to emit the light emitting element EL.

The gate electrode of the fifth transistor T5 receives the first scan signal Scan1. The source electrode of the fifth transistor T5 is supplied with the initializing voltage Vinit. The drain electrode of the fifth transistor T5 is connected to the first node N1. The fifth transistor T5 is turned on by the first scan signal Scan1 to initialize the voltage of the first node N1 to the initialization voltage Vinit.

The gate electrode of the sixth transistor T6 receives the first scan signal Scan1. The source electrode of the sixth transistor T6 is supplied with the initializing voltage Vinit. The drain electrode of the sixth transistor T6 is connected to the second node N2. The sixth transistor T6 is turned on by the first scan signal Scan1 to initialize the voltage of the second node N2 to the initializing voltage Vinit.

The pixel P according to the first embodiment of the present invention includes seven thin film transistors (TFT) and one capacitor and is collectively referred to as a 7T1C compensation circuit. In addition, the pixel P according to the first embodiment of the present invention operates with two types of scan signals (Scan) and one type of emission control signal (EM).

The difference voltage Vgs between the gate voltage of the driving transistor DT and the source voltage maintains the gate-low voltage (VGL) state at the start of an arbitrary frame. Further, the emission control signal EM is also in a gate low voltage (VGL) state. Thus, the third and fourth transistors T3 and T4 are turned on. Accordingly, a predetermined amount of driving current flows through the driving transistor DT to cause the light emitting element EL to emit light.

Thereafter, the emission control signal EM has the gate high voltage VGH, and the source electrode and the drain electrode of the driving transistor DT are in the floating state.

Thereafter, the pixel P has an initialization step. In the initialization step, when the first scan signal Scan1 becomes the gate-low voltage VGL, the fifth transistor T5 is turned on and the initialization voltage Vinit is applied to the first node N1. When the first scan signal Scan1 again becomes the gate high voltage VGH after the initialization step, the fifth transistor T5 is turned off and the first node N1 becomes a floating state.

Thereafter, the pixel P has a Programming step. In the programming step, the first, second and sixth transistors T1, T2 and T6 are turned on when the second scan signal Scan2 becomes the gate-low voltage VGL. The light emitting element EL is reset by the sixth transistor T6. Further, the second transistor T2 is turned on, and the data voltage Vdata is supplied to the source electrode of the driving transistor DT.

The initialization voltage Vinit of the pixel P according to an example of the present application is lower than the data voltage Vdata. The data voltage Vdata is supplied to the source electrode of the driving transistor DT and the initializing voltage is supplied to the gate electrode of the driving transistor DT. Accordingly, the difference voltage Vgs between the gate voltage of the driving transistor DT and the source voltage has a negative (-) voltage value.

When the difference voltage Vgs between the gate voltage and the source voltage has a negative voltage value, the driving transistor DT operates in a linear region. As a result, the voltage of the drain electrode of the driving transistor DT rises. Since the first transistor T1 is in a turned-on state, the drain electrode and the gate electrode of the driving transistor can be regarded as electrically identical nodes. As a result, the voltage of the first node N1 rises to Vdata + Vth, which is the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT. Here, the threshold voltage Vth has a negative voltage value.

Thereafter, the pixel P has a step of sensing a threshold voltage Vth. Since the voltage of the first node N1 is raised to the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT in the threshold voltage Vth sensing step, So that only the subthreshold current flows.

At this time, the threshold voltage Vth can be sensed by sensing Vdata + Vth, which is the voltage of the gate electrode of the driving transistor DT, based on the data voltage Vdata.

Thereafter, the pixel driving voltage ELVDD is supplied to the drain electrode of the driving transistor when the emission control signal EM becomes the gate-low voltage VGL again. As a result, the next frame starts, and the light emitting element EL emits light.

3 is a cross-sectional view of a pixel P according to an example of the present application. The pixel P according to one example includes a base layer 210, a buffer layer 220, a semiconductor layer 230, a gate insulating layer 235, a gate metal layer 240, a first bridge 241, a source / The first interlayer insulating film 260, the intermediate metal layer 270, the second interlayer insulating film 280, the planarization film 290, the anode electrode 300, the light emitting layer 320, the cathode electrode 330, And barrier ribs 340.

The base layer 210 forms the lowest layer of the organic light emitting display. The base layer 210 may support the circuit elements and the wirings constituting the upper circuit portion. Alternatively, the base layer 210 may be formed of flexible plastic so that the OLED display is flexible.

The buffer layer 220 covers the top of the base layer 210. The buffer layer 220 is formed of a material having excellent insulating properties. The buffer layer 220 protects the circuit elements and the wirings constituting the circuit portion provided on the base layer 210 from external impact or static electricity.

The semiconductor layer 230 is disposed on the buffer layer 220. The semiconductor layer 230 is made of a doped semiconductor. The semiconductor layer 230 forms the channel of the thin film transistor constituting the pixel P. The semiconductor layer 230 includes a gate channel 231, a first channel 232, and a second channel 233. The gate channel 231 forms the channel of the gate electrode of the thin film transistor. The first and second electrode layers 233 form channels of the source electrode and the drain electrode of the thin film transistor.

A gate insulating layer 235 is disposed on the buffer layer 220 and the semiconductor layer 230. The gate insulating layer 235 entirely covers the buffer layer 220 and the semiconductor layer 230. The gate insulating layer 235 is formed of a material having excellent insulating properties. The gate insulating layer 235 prevents shorting of the semiconductor layer 230 with the gate metal layer 240 and distinguishes the channel of the thin film transistor formed by the semiconductor layer 230.

A gate metal layer 240 is disposed on top of the gate insulating layer 235. The gate metal layer 240 is a gate metal layer forming the gate electrode and the gate lines GL1 to GLp of the thin film transistor. The gate metal layer 240 may be formed of a metal or an alloy having excellent electrical conductivity.

The first interlayer insulating film 260 is disposed on the gate metal layer 240 and the first bridge 241. The first interlayer insulating film 260 is formed of a material having excellent electrical insulation properties.

The intermediate metal layer 270 is disposed on the first interlayer insulating film 260. The intermediate metal layer 270 overlaps the gate metal layer 240 forming the gate electrode of the thin film transistor in the gate metal layer 240. The intermediate metal layer 270 forms a mutual capacitance with the gate metal layer 240 forming the gate electrode of the thin film transistor. The intermediate metal layer 270 functions as one electrode of the storage capacitance.

The second interlayer insulating film 280 is disposed on the first interlayer insulating film 260 and the intermediate metal layer 270. The second interlayer insulating film 280 is formed of a material having excellent electrical insulation properties.

The source / drain metal layer 250 is disposed on the second interlayer insulating film 280. The source / drain metal layer 250 forms the first electrode 251 and the second electrode 252 of the thin film transistor constituting the pixel P. The source / drain metal layer 250 forms the first electrode 253 of the first connection transistor CT1, the reverse enable line 254, the enable line 255, and the lighting inspection data line 256. The source / drain metal layer 250 is a source / drain metal layer disposed on top of the gate metal layer 240. The source / drain metal layer 250 may be formed of a metal or an alloy having excellent electrical conductivity.

The planarization film 290 is disposed on the second interlayer insulating film 280 and the source / drain metal layer 250. The planarizing film 290 reduces the height difference of the top surface. Accordingly, the height of the planarization film 290 in the Z-axis direction with respect to the base layer 210 can be prevented from varying according to the region.

The anode electrode 300 is disposed on the planarizing film 290. The anode electrode 300 is connected to the second electrode 252 of the thin film transistor constituting the pixel P. The anode electrode 300 supplies a driving voltage or a data voltage to the second electrode 252 of the thin film transistor. The anode electrode 300 may be divided into the pixels P. Between the anode electrodes 300 adjacent to each other can be electrically isolated due to the barrier ribs 340.

The light emitting layer 320 is provided on the anode electrode 300. The light emitting layer 320 may include a hole transporting layer, an organic light emitting layer, and an electron transporting layer. When a voltage is applied to the anode electrode 300 and the cathode electrode 330, the light emitting layer 320 moves the holes and electrons to the organic light emitting layer through the hole transporting layer and the electron transporting layer, respectively.

A cathode electrode 330 is provided on the light emitting layer 320 and the bank 340. The cathode electrode 330 supplies a driving voltage.

The bank 340 is provided between the anode electrodes 300 of the pixels P. [ The bank 340 delimits the pixels P. [

4 is a plan view showing a plurality of reference power source voltage lines (VSSL1 to VSSL3) and a cathode electrode 330 according to an example.

The plurality of reference power supply voltage lines VSSL1 to VSS3 according to an example may include first to third reference power supply voltage lines VSSL1 to VSSL3. However, the present invention is not limited to this, and the number of the plurality of reference power supply voltage lines VSSL1 to VSS3 may be more or less than three.

The first reference power supply voltage line VSSL1 is disposed in the innermost of the plurality of reference power supply voltage lines VSSL1 to VSS3. The first reference power supply voltage line VSSL1 is disposed adjacent to the display area. The first reference power supply voltage line VSSL1 supplies the first reference power supply voltage VSS1.

The second reference power supply voltage line VSSL2 is disposed outside the first reference power supply voltage line VSSL1. The second reference power supply voltage line VSSL2 is electrically separated from the first reference power supply voltage line VSSL1. The second reference power supply voltage line VSSL2 is disposed apart from the display region from the first reference power supply voltage line VSSL1. The second reference power supply voltage line VSSL2 supplies the second reference power supply voltage VSS2.

And the third reference power supply voltage line VSSL3 is disposed outside the second reference power supply voltage line VSSL2. And the third reference power supply voltage line VSSL3 is electrically separated from the second reference power supply voltage line VSSL2. The third reference power supply voltage line VSSL3 is disposed apart from the display region from the second reference power supply voltage line VSSL2. The third reference power supply voltage line VSSL3 supplies the third reference power supply voltage VSS3.

The cathode electrode 330 is integrally disposed on the entire display region and on a part of the non-display region. The cathode electrode 330 is partially or wholly overlapped with the first to third reference power supply voltage lines VSSL1 to VSSL3 on the non-display region. The cathode electrode 330 overlaps with each of the first to third reference power supply voltage lines VSSL1 to VSSL3 at least in a partial region. For example, the cathode electrode 330 may be disposed in all regions on the first and second reference power supply voltage lines VSSL1 to VSSL2, and may be disposed in a partial region on the third reference power supply voltage line VSSL3.

The organic light emitting display device according to one example includes a display panel 100 having a display region provided with pixels P for displaying an image and a non-display region provided so as to surround the display region, And a plurality of reference power source voltage lines VSSL1 to VSSL3 for supplying reference power source voltages VSS1 to VSS3 to the cathode electrode 330 in the non-display region.

In the case of having a plurality of reference power supply voltage lines (VSSL1 to VSSL3), when a reference power supply voltage having a single size is supplied in a single reference power supply voltage line, characteristics of regions of the contrast display panel 100 and the cathode electrode 330 So that the reference power supply voltage of a proper size can be supplied. This makes it possible to more stably supply the reference power supply voltage, thereby improving the image quality and increasing the driving stability.

In particular, each of the plurality of reference power supply voltage lines VSSL1 to VSSL3 according to an example supplies different reference power supply voltages VSS1 to VSS3. Accordingly, different reference power supply voltages VSS1 to VSS3 can be supplied to the display panel 100 and the cathode electrode 330, respectively. Different reference power supply voltages VSS1 to VSS3 are set to reflect the deviation of the reference power supply voltage for each distance and area according to the line resistance of the plurality of reference power supply voltage lines VSSL1 to VSSL3, . Accordingly, it is possible to reduce the deviation of the reference power supply voltage for each distance and each region according to the line resistance of the plurality of reference power supply voltage lines VSSL1 to VSSL3.

The first reference power supply voltage VSS1 according to an example has a potential higher than the second reference power supply voltage VSS2. The reference power supply voltage refers to the potential of the cathode electrode of the light emitting element EL and is a voltage supplied to the layer opposite to the drain electrode of the driving transistor DT to which the pixel driving power supply ELVDD is supplied. Thus, the potential of the reference power supply voltage has a negative (-) potential lower than the ground voltage. Since the second reference power supply voltage VSS2 has a potential lower than the first reference power supply voltage VSS1, the magnitude of the absolute value of the second reference power supply voltage VSS2 is smaller than the absolute value of the first reference power supply voltage VSS1 . For example, when the first reference power supply voltage VSS1 is -2.5V, the second reference power supply voltage VSS2 may be -2.6V.

Also, the second reference power supply voltage VSS2 according to one example has a potential higher than the third reference power supply voltage VSS3. Since the third reference power supply voltage VSS3 has a potential lower than the second reference power supply voltage VSS2, the magnitude of the absolute value of the third reference power supply voltage VSS3 is smaller than the absolute value of the second reference power supply voltage VSS2 . For example, when the second reference power supply voltage VSS2 is -2.6V, the third reference power supply voltage VSS3 may be -2.7V.

The reference power supply voltage should have a negative negative voltage and it approaches the ground voltage due to the line resistance of the plurality of reference power supply voltage lines VSSL1 to VSSL3 and the surface resistance of the cathode electrode 330. [ That is, a VSS Rising phenomenon occurs in which the potential of the reference power supply voltage rises. The rising value of the potential of the reference power supply voltage due to the VSS rising phenomenon increases as the length of the reference power supply voltage line increases. In addition, the rising value of the potential of the reference power supply voltage due to the VSS rising phenomenon increases as the distance from the point where the reference power supply voltage is supplied becomes larger. Thereby, a voltage deviation of the reference power supply voltage occurs between the upper portion of the display panel 100, which is the portion where the reference power supply voltage is supplied from the display panel 100, and the lower portion of the display panel, which is the portion opposite to the portion where the reference power supply voltage is supplied do.

The first reference power supply voltage VSS1 is supplied to the first reference power supply voltage line VSSL1 for supplying the reference power supply voltage to the upper portion of the display panel 100 in the plurality of reference power supply voltage lines VSSL1 to VSSL3, do. The second reference power supply voltage line VSSL2 for supplying the reference power supply voltage to the central region of the display panel 100 supplies the second reference power supply voltage VSS2. The third reference power supply voltage line VSSL3 for supplying the reference power supply voltage to the lower region of the display panel 100 supplies the third reference power supply voltage VSS3.

Accordingly, the first reference power supply voltage VSS1 having the same potential as the reference power supply voltage originally supplied can be supplied directly to the upper portion of the display panel 100 according to an example. At the same time, the second reference power supply voltage VSS2 having a potential lower than the first reference power supply voltage VSS1 is supplied to the center of the display panel 100 to compensate for the VSS rising phenomenon at the center of the display panel 100 have. At the same time, a third reference power supply voltage VSS3 having a lower potential than the second reference power supply voltage VSS2 is supplied to the lower portion of the display panel 100 to compensate for the VSS rising phenomenon in the lower portion of the display panel 100 .

In the case where the reference power supply voltage is increased for each region of the display panel 100 in accordance with the VSS rising phenomenon and a voltage of a potential lower than the calculated voltage increase value is supplied to the corresponding region as the reference power supply voltage, The magnitudes of the reference power supply voltages in the upper, middle, and lower portions of the reference power supply voltage can all be made equal. This makes it possible to reduce the deviation of the reference power supply voltage for each region of the display panel 100, thereby improving the luminance variation and the driving stability of the display panel 100.

The first reference power supply voltage line VSSL1 is connected to the cathode electrode 330 through the first contact hole CNT1 and the fourth contact hole CNT4 and the second reference power supply voltage line VSSL2 is connected to the cathode electrode 330 through the first contact hole CNT1 and the fourth contact hole CNT4, The third reference power supply voltage line VSSL3 is connected to the third contact hole CNT3 and the sixth contact hole CNT6 through the second contact hole CNT2 and the fifth contact hole CNT5, ), And the seventh contact hole CNT7. The first to seventh contact holes CNT1 to CNT7 are formed on the same layer. The first to seventh contact holes CNT1 to CNT7 are formed so as not to overlap each other. The first to seventh contact holes CNT1 to CNT7 are formed through the planarization film 290. [

The first contact hole CNT1 and the fourth contact hole CNT4 are connected to the cathode electrode 330 receiving the first reference power source voltage VSS1 among the overlapping regions of the first reference power source voltage line VSSL1 and the cathode electrode 330 300). For example, when the first reference power source voltage VSS1 is supplied from the upper portion of the cathode electrode 330, the first contact hole CNT1 is disposed at the upper left of the cathode electrode 330, and the fourth contact hole CNT4 May be disposed on the upper right side of the cathode electrode 330. [ The first contact hole CNT1 and the fourth contact hole CNT4 may be disposed symmetrically on both sides of the cathode electrode 330. [

The second contact hole CNT2 and the fifth contact hole CNT5 are connected to the cathode electrode 330 receiving the second reference power source voltage VSS2 among the overlapping regions of the second reference power source voltage line VSSL2 and the cathode electrode 330 300). For example, when the second reference power supply voltage VSS2 is supplied from the upper portion of the cathode electrode 330, the second contact hole CNT2 is disposed at the left central portion of the cathode electrode 330, and the fifth contact hole CNT5 May be disposed at the center of the right side of the cathode electrode 330. The second contact hole CNT2 and the fifth contact hole CNT5 may be disposed symmetrically with the central portions on both sides of the cathode electrode 330. [

The third contact hole CNT3 and the sixth contact hole CNT6 are connected to the cathode electrode 330 receiving the third reference power supply voltage VSS3 among the overlapping regions of the third reference power supply voltage line VSSL3 and the cathode electrode 330 330, respectively. For example, when the third reference power supply voltage VSS3 is supplied from the upper portion of the cathode electrode 330, the third contact hole CNT3 is disposed at the lower left of the cathode electrode 330, and the sixth contact hole CNT6 May be disposed on the lower right side of the cathode electrode 330. The third contact hole CNT3 and the sixth contact hole CNT6 may be disposed symmetrically to the lower portions of both sides of the cathode electrode 330. [

The fourth contact hole CNT4 is disposed under the cathode electrode 330 receiving the third reference power supply voltage VSS3 among the regions where the third reference power supply voltage line VSSL3 and the cathode electrode 330 overlap. For example, when the third reference power supply voltage VSS3 is supplied from the upper portion of the cathode electrode 330, the fourth contact hole CNT4 is disposed at the lower center of the cathode electrode 330. [

The size of the fourth contact hole CNT4 may be larger than the sizes of the first through third contact holes CNT1 through CNT3 and the fifth through seventh contact holes CNT5 through CNT7. The fourth contact hole CNT4 is connected to the lower center of the lower portion of the cathode electrode 330 to which the third reference power supply voltage VSS3 is supplied, the farthest from the supply point of the third reference power supply voltage VSS3. In order to smoothly supply the third reference power source voltage VSS3, the fourth contact hole CNT4 is electrically connected to the first through third contact holes CNT1 through CNT3 at the lower center of the cathode electrode 330, 5th to 7th contact holes CNT5 to CNT7.

In addition, when the area of the fourth contact hole CNT4 is increased, the area in which the third reference power source voltage line VSSL3 and the cathode electrode 330 contact with each other in the fourth contact hole CNT4 also increases. Accordingly, the contact resistance between the third reference power supply voltage line VSSL3 and the cathode electrode 330 is reduced, thereby reducing the VSS rising phenomenon due to the voltage drop due to the contact resistance in the fourth contact hole CNT4.

4, the first reference power supply voltage line VSSL1 is arranged to surround the display region, and the second reference power supply voltage line VSSL2 is arranged to surround the first reference power supply voltage line VSSL1 , And the third reference power supply voltage line VSSL3 is disposed so as to surround the second reference power supply voltage line VSSL2.

Each of the first to third reference power supply voltage lines VSSL1 to VSSL3 is formed so as to extend on both the side edges and the bottom edge of the display region with the display region as the center. The first to third reference power supply voltage lines VSSL1 to VSSL3 are connected to a desired region on the cathode electrode 330 while the first to third reference power supply voltage lines Lines VSSL1 to VSSL3 can be formed, so that the additional manufacturing cost for forming the first to third reference power supply voltage lines VSSL1 to VSSL3 can be minimized.

Fig. 5 is an equivalent circuit diagram of Fig. 5, the line resistance of the first to third reference power supply voltage lines VSSL1 to VSSL3 and the area resistance of the cathode electrode 330 on the display panel 100 are set to a resistance R Respectively.

The distance from the point where the first to third reference power supply voltages VSS1 to VSS3 are supplied increases in the direction of the lower region of the cathode electrode 330. [ When the surface resistance of the cathode electrode 330 is uniform, the VSS rising phenomenon according to the voltage drop principle of the first to third reference power supply voltages VSS1 to VSS3 increases as the direction of the lower region of the cathode electrode 330 increases do.

5, when the first to third reference power supply voltage lines VSSL1 to VSSL3 are arranged, the first to third reference power supply voltages VSS1 to VSS3 are applied to the upper, middle, and lower portions of the cathode electrode 330, Supplied separately. The line resistance of the first to third reference power supply voltage lines VSSL1 to VSSL3 and the surface resistances of the cathode electrode 330 on the display panel 100 are different from each other, It is possible to reduce the variation of the resistance to the lower portion.

6 is a plan view showing a plurality of reference power source voltage lines (VSSL1 to VSSL3) and a cathode electrode 330 according to another example.

The first reference power supply voltage line VSSL1 according to another example is arranged at a corner of the non-display region, the second reference power supply voltage line VSSL2 is arranged to extend beyond the first reference power supply voltage line VSSL1, The three reference power supply voltage lines VSSL3 are arranged to extend from the second reference power supply voltage line VSSL2.

The first reference power supply voltage line VSSL1 extends from the point where the first reference power supply voltage VSS1 is supplied to the point where the first and fourth contact holes CNT1 and CNT4 are disposed. For example, when the first reference power supply voltage VSS1 is supplied from the upper center of the display panel 100, one side of the first reference power supply voltage line VSSL1 is connected to one side of the non- Extending from the center to the upper left side. The other side of the first reference power source voltage line VSSL1 extends from the upper center to the upper right side of the non-display area where the cathode electrode 330 is formed.

The second reference power supply voltage line VSSL2 extends from the point where the second reference power supply voltage VSS2 is supplied to the point where the second and fifth contact holes CNT2 and CNT5 are disposed. For example, when the second reference power source voltage VSS3 is supplied from the upper center of the display panel 100, one side of the second reference power source voltage line VSSL2 is connected to one side of the non- And extends from the center to the left central portion. The other side of the second reference power source voltage line VSSL2 extends from the upper center to the right center of the non-display area where the cathode 330 is formed.

The third reference power supply voltage line VSSL3 is connected from the point where the third reference power supply voltage VSS3 is supplied to the point where the third, sixth, and seventh contact holes CNT3, CNT6, CNT7 are disposed . For example, when the third reference power supply voltage VSS3 is supplied from the upper center of the display panel 100, one side of the third reference power supply voltage line VSSL3 is connected to one of the non- It extends from the center to the lower left. The other side of the third reference power supply voltage line VSSL3 extends from the upper center to the lower right side of the non-display area where the cathode electrode 330 is formed. In addition, the third reference power source voltage line VSSL3 is formed in the entire region where the seventh lower contact hole CNT7 is formed among the non-display regions where the cathode electrode 330 is formed. Accordingly, the third reference power supply voltage line VSSL3 is disposed so as to surround the display region, the first reference power supply voltage line VSSL1, and the second reference power supply voltage line VSSL2.

The width of the region where the second and fifth contact holes CNT2 and CNT5 are formed in the second reference power source voltage line VSSL2 according to another example is wider than the width of the first reference power source voltage line VSSL1, The width of the region where the third and sixth contact holes CNT2 and CNT5 of the voltage line VSSL3 is formed is wider than the width of the second reference power source voltage line VSSL2.

The region where the second and fifth contact holes CNT2 and CNT5 of the second reference power supply voltage line VSSL2 are formed can be defined as an extended portion of the second reference power supply voltage line VSSL2. The region where the third, sixth, and seventh contact holes CNT3, CNT6, and CNT7 are formed in the third reference power supply voltage line VSSL2 is formed by extending the third reference power supply voltage line VSSL3 It can be defined as a part.

The width of the second reference power supply voltage line VSSL2 in the extended portion of the second reference power supply voltage line VSSL2 is thicker than the width of the remaining portion of the second reference power supply voltage line VSSL2. In the extended portion of the second reference power supply voltage line (VSSL2), the second reference power supply voltage line (VSSL2) increases in width toward the first reference power supply voltage line (VSSL1). The second reference power supply voltage line VSSL2 has a width of the remaining portion of the second reference power supply voltage line VSSL2 in the extended portion, a width of the first reference power supply voltage line VSSL1, VSSL1, and VSSL2, respectively.

The width of the third reference power supply voltage line VSSL3 in the extended portion of the third reference power supply voltage line VSSL3 is thicker than the width of the remaining portion of the third reference power supply voltage line VSSL3. In the extended portion of the third reference power supply voltage line VSSL3, the third reference power supply voltage line VSSL3 increases in width toward the first and second reference power supply voltage lines VSSL1 and VSSL2. The third reference power supply voltage line VSSL3 has a width that is thicker than the sum of the widths of the first and second reference power supply voltage lines VSSL1 to VSSL3 in the extended portion.

When the width of the second and third reference power source voltage lines VSSL2 and VSSL3 is increased in this manner, the second through third and fifth through seventh contact holes CNT2 through CNT3 and CNT5 through CNT7, It is possible to increase the area of the area in which this is disposed. The second and third reference power source voltage lines VSSL2 and VSSL3 are connected to the cathode electrode 330 more stably with the second through third and fifth through seventh contact holes CNT2 through CNT3 and CNT5 through CNT7 . In addition, when increasing the area of the region where the second to third and fifth to seventh contact holes CNT2 to CNT3, CNT5 to CNT7 are disposed, the second and third reference power source voltage lines VSSL2 and VSSL3 and the cathode The contact area of the electrode 330 can be increased. Accordingly, the contact resistance between the second and third reference power source voltage lines VSSL2 and VSSL3 and the cathode electrode 330 is reduced, thereby preventing the VSS rising phenomenon due to the voltage drop due to the contact resistance.

7 is a plan view showing a plurality of reference power source voltage lines VSSL1 to VSSL3, an anode electrode 300, and a cathode electrode 330 according to another example.

The OLED display according to another example further includes an anode electrode 300 disposed on a non-display region. The anode electrode 300 is disposed along a plurality of reference power supply voltage lines VSSL1 to VSSL3. 7, only a plurality of reference power supply voltage lines VSSL1 to VSSL3 and an anode electrode 300 disposed on one side of the cathode electrode 330 are shown. A plurality of reference power source voltage lines VSSL1 to VSSL3 and an anode electrode 300 are disposed on both sides and the entire bottom edge of the cathode electrode 330. [ The node electrode 300 is disposed so as to overlap both the plurality of reference power supply voltage lines VSSL1 to VSSL3 and the cathode electrode 330 in at least some of the non-display regions.

Each of the first to third reference power supply voltage lines VSSL1 to VSSL3 is connected to the anode electrode 300. [ The first reference power supply voltage line VSSL1 is connected to the anode electrode 300 through the first contact hole CNT1 with the first to third reference power supply voltage lines VSSL1 to VSSL3 provided on one side. The second reference power supply voltage line VSSL2 is connected to the anode electrode 300 through the second contact hole CNT2. The third reference power supply voltage line VSSL3 is connected to the anode electrode 300 through the third contact hole CNT3.

In this manner, the first reference power supply voltage line VSSL1 provided on the other side is connected to the anode electrode 300 through the fourth contact hole CNT4. The second reference power supply voltage line VSSL2 is connected to the anode electrode 300 through the fifth contact hole CNT5. The third reference power supply voltage line VSSL3 is connected to the anode electrode 300 through the sixth contact hole CNT6.

Also, the third reference power supply voltage line VSSL3 is connected to the anode electrode 300 through the seventh contact hole CNT3.

8 is a cross-sectional view showing I-I 'of Fig.

Each of the first to third reference power supply voltage lines VSSL1 to VSSL3 according to an exemplary embodiment includes a source / drain metal layer 250. Each of the first to third reference power supply voltage lines VSSL1 to VSSL3 is disposed in the same layer using the same material as the source electrode and the drain electrode of the thin film transistor of the pixel P. [

The anode electrode 300 and the first to third reference power supply voltage lines VSSL1 to VSSL3 according to an exemplary embodiment are connected to each other through a contact hole passing through the planarization layer 290 disposed on the source / And is electrically connected.

The cathode electrode 330 and the anode electrode 300 are electrically connected to each other through a contact hole passing through the electrode separation layer 310 disposed on the anode electrode 300. The electrode separation layer 310 is disposed on the anode electrode 300 to separate the anode electrode 300 and the cathode electrode 330 from each other. The electrode separating layer 310 may be formed of an inorganic material that is excellent in electrical insulation and is easy to form a contact hole.

As described above, the first to seventh contact holes CNT1 to CNT7 according to an exemplary embodiment of the present invention have a double contact hole structure including a contact hole passing through the planarization layer 290 and a contact hole passing through the electrode separation layer 310 . The first to seventh contact holes CNT1 to CNT7 are connected to the first to third reference power source voltage lines VSSL1 to VSSL3 through the anode electrode 300 and the cathode electrode 330, The power supply voltages VSS1 to VSS3 can be supplied.

The anode electrode 300 according to an example is disposed entirely above the first to third reference power supply voltage lines VSSL1 to VSSL3.

The anode electrode 300 according to an exemplary embodiment is connected to each of the first to third reference power supply voltage lines VSSL1 to VSSL3 through the contact holes CNT1 to CNT7. Different reference power supply voltages are supplied through the respective contact holes CNT1 to CNT7. The first and fourth contact holes CNT1 and CNT4 are connected to the first reference power supply voltage line VSSL1 so that the first reference power supply voltage VSSL1 through the first and fourth contact holes CNT1 and CNT4 VSS1) is supplied. Since the second and fifth contact holes CNT2 and CNT5 are connected to the second reference power supply voltage line VSSL2, the second reference power supply voltage VSS2 through the second and fifth contact holes CNT2 and CNT5, Is supplied. Since the third, sixth, and seventh contact holes CNT3, CNT6, and CNT7 are connected to the third reference power supply voltage line VSSL3, the third, sixth, and seventh contact holes, And the third reference power supply voltage VSS3 is supplied through the seventh contact holes CNT3, CNT6, and CNT7.

9 is a plan view showing a plurality of reference power source voltage lines VSSL1 to VSSL3, an anode electrode 300, and a cathode electrode 330 according to yet another example. 10 is a cross-sectional view showing II-II` of FIG.

The anode electrode 300 according to another example is patterned and disposed on the first to third reference power supply voltage lines VSSL1 to VSSL3. The anode electrode 300 is patterned and disposed for each of the first through seventh contact holes CNT1 through CNT7.

Different reference power supply voltages are supplied to each of the patterned anode electrodes 300 according to another example. Since the first and fourth contact holes CNT1 and CNT4 are connected to the first reference power supply voltage line VSSL1, the anode electrode 300 disposed on the first and fourth contact holes CNT1 and CNT4, The first reference power supply voltage VSS1 is supplied. Since the second and fifth contact holes CNT2 and CNT5 are connected to the second reference power supply voltage line VSSL2, the anode electrode 300 disposed on the second and fifth contact holes CNT2 and CNT5 The second reference power supply voltage VSS2 is supplied. Since the third, sixth, and seventh contact holes CNT3, CNT6, and CNT7 are connected to the third reference power supply voltage line VSSL3, the third, sixth, and seventh contact holes, The third reference power supply voltage VSS3 is supplied to the anode electrode 300 disposed on the seventh contact holes CNT3, CNT6 and CNT7.

In this case, when the anode electrodes 300 are arranged in a single layer, the anode electrode 300 having a different reference power supply voltage may be disposed for each region of the cathode electrode 330 on the contrast display panel 100. Accordingly, a different reference power supply voltage can be supplied to match the characteristics of the cathode electrode 330 in each region. In particular, a reference power supply voltage having a lower potential than the upper region can be supplied to the lower region of the cathode electrode 330, so that even if a VSS rising phenomenon occurs in the lower region of the cathode electrode 330, the reference power supply voltage can be compensated.

The present application can provide a structure for separating a reference power supply voltage line and applying a reference power supply voltage that supplies the reference power supply voltage line to each of the reference power supply voltage lines to reduce a voltage deviation for each region of the display panel. The present application can reduce the voltage deviation of the cathode electrode of the worst point when the VSS rising phenomenon occurs. As a result of a simulation in which the reference power supply voltage supplied to the top of the display panel is set to -2.5 V and the reference power supply voltage supplied to the lower portion of the display panel is set to -2.7 V, the VSS Rising level is 0.09 V, 70% less than 0.32V.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: gate driver
120: Data driver 130: Timing controller
P: pixel DT: driving transistor
EL: light emitting element Cst: storage capacitor
T1 to T6: first to sixth transistors
VSSL1 to VSSL3: first to third reference power supply voltage lines
210: base layer 220: buffer layer
230: semiconductor layer 235: gate insulating layer
240: gate metal layer 250: source / drain metal layer
260: first interlayer insulating film 270: intermediate metal layer
280: second interlayer insulating film 290: planarization film
300: anode electrode 310: electrode separation layer
320: light emitting layer 330: cathode electrode
340: Bank

Claims (9)

A display panel having a display area provided with pixels for displaying an image and a non-display area provided so as to surround the display area;
A cathode electrode integrally disposed on the display region and the non-display region; And
And a plurality of reference power supply voltage lines arranged in the non-display area to supply a reference power supply voltage to the cathode electrode,
Wherein each of the plurality of reference power supply voltage lines supplies different reference power supply voltages. The method according to claim 1,
The plurality of reference power supply voltage lines
A first reference power supply voltage line disposed adjacent to the display region to supply a first reference power supply voltage;
A second reference power supply voltage line arranged apart from the display region and supplying a second reference power supply voltage to the first reference power supply voltage line; And
And a third reference power supply voltage line that is disposed apart from the display region and supplies a third reference power supply voltage than the second reference power supply voltage line,
Wherein the first reference power supply voltage has a potential higher than the second reference power supply voltage,
Wherein the second reference power supply voltage has a potential higher than the third reference power supply voltage. 3. The method of claim 2,
The first reference power supply voltage line is connected to the cathode electrode through a first contact hole and a fourth contact hole,
The second reference power supply voltage line is connected to the cathode electrode through the second contact hole and the fifth contact hole,
And the third reference power supply voltage line is connected to the cathode electrode through a third contact hole, a sixth contact hole, and a seventh contact hole. 3. The method of claim 2,
Wherein the first reference power supply voltage line is arranged to surround the display region,
The second reference power supply voltage line is arranged to surround the first reference power supply voltage line,
And the third reference power supply voltage line is arranged to surround the second reference power supply voltage line. 3. The method of claim 2,
The first reference power supply voltage line is disposed at a corner of the non-display region,
Wherein the second reference power supply voltage line is arranged to extend from the first reference power supply voltage line,
The third reference power supply voltage line is arranged to extend from the second reference power supply voltage line,
The width of the extended portion of the second reference power supply voltage line is wider than the width of the first reference power supply voltage line,
Wherein a width of an extended portion of the third reference power supply voltage line is greater than a width of the second reference power supply voltage line. 3. The method of claim 2,
And an anode electrode disposed on the non-display region,
And each of the first to third reference power supply voltage lines is connected to the anode electrode. The method according to claim 6,
Each of the first to third reference power supply voltage lines is composed of a source / drain metal layer,
The anode electrode and the first to third reference power supply voltage lines are electrically connected through contact holes passing through the planarization layer disposed on the source / drain metal layer,
And the cathode electrode and the anode electrode are electrically connected through a contact hole passing through the electrode separation layer disposed on the anode electrode. The method according to claim 6,
Wherein the anode electrode is disposed entirely above the first to third reference power supply voltage lines,
The anode electrode is connected to each of the first to third reference power supply voltage lines through a contact hole,
And different reference power supply voltages are supplied through the contact holes. The method according to claim 6,
The anode electrode is patterned on the first to third reference power supply voltage lines,
And each of the patterned anode electrodes is supplied with a different reference power supply voltage.

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