KR20190047298A - Display apparatus - Google Patents

Abstract

The present invention provides a display device to increase reliability of a gate driving circuit. According to the present invention, the display device comprises: the gate driving circuit dividing a display area of a display panel into a plurality of horizontal blocks, and driving gate lines in the horizontal block by a horizontal block unit for each display section of one frame; a monitoring circuit connected to the gate driving circuit to output a node monitoring signal; and a voltage control unit generating a node control value varied based on the node monitoring signal supplied from the monitoring circuit to provide the gate control voltage to the gate driving circuit. The gate driving circuit supplies a scan pulse to the gate lines included in a corresponding horizontal block for each display section based on stage drive power including the node control voltage, and outputs a carry signal after a touch sensing section.

Description

Display device {DISPLAY APPARATUS}

The present application relates to a display device having a touch sensor.

As the information society develops, the demand for display devices for displaying images has increased in various forms, and various types of display devices such as liquid crystal display devices and light emitting display devices have been utilized. Also, among display devices, mobile devices such as a mobile phone, a smart phone, a smart watch, a personal computer, or a watch phone, and a smart television, Medium and large-sized devices such as a monitor provide a touch screen type user interface for user input convenience. Such a touch-enabled display device is being developed to provide more various functions, and user demands are also becoming more diverse.

A display device having a touch screen type user interface includes a display drive for displaying an image on a display panel, a time division driving for temporally dividing a touch drive for sensing a touch position and / or a touch force according to a user touch, .

The user interface of the time division driving type is a vertical blanking method in which a frame is driven in a time division manner in a display period and a touch sensing period to perform a touch report once during one frame and a vertical blanking method in which a display period and a touch sensing period are divided into several times And a horizontal blanking method in which a touch report is performed several times during one frame. Among the time division driving methods, the horizontal blanking method has a touch report rate of 120 Hz or more, so that the touch sensitivity can be improved as compared with the horizontal blanking method.

The horizontal blanking type display device includes a gate driving circuit having a shift register for time division driving. The shift register is embedded (or integrated) in a display panel, and includes a plurality of driving stage blocks for driving a display and a plurality of holding stage blocks for touch driving.

Each of the plurality of driving stage blocks and the plurality of holding stage blocks is composed of a stage circuit having a plurality of oxide thin film transistors having a high mobility with respect to the amorphous thin film transistor for implementing a thin bezel width of the display device, There is a problem that deterioration is not restored. In particular, the stage circuit of each of the plurality of holding stage blocks serves to hold the output signal of the front stage driving stage block for the touch sensing period, so that deterioration of the oxide thin film transistors constituting the stage circuit of each of the plurality of holding stage blocks is accelerated Therefore, the output signal can not be stably maintained during the touch sensing period, thereby decreasing the reliability of the gate driving circuit.

The contents of the background art described above are technical information acquired by the inventor of the present application for the purpose of deriving the present application or acquired in the process of deriving the present application, There is no number.

The present invention is directed to a display device capable of improving the reliability of a gate driving circuit.

A display device according to the present application includes a gate driving circuit for dividing a display area of a display panel into a plurality of horizontal blocks and driving gate lines in a horizontal block in units of horizontal blocks for each of a plurality of display periods in one frame, A sensing circuit connected to the gate driving circuit for outputting a node monitoring signal; and a control circuit for receiving the variable control signal based on the node monitoring signal supplied from the monitoring circuit, And a gate driving circuit for generating a plurality of gate lines included in the corresponding horizontal block for each display period based on a stage driving power source including a node control voltage, In the After supplying cans pulse may output a carry signal after the touch sensing period.

The display device according to the present application changes the node control voltage supplied to the gate driving circuit based on the node monitoring signal output from the monitoring circuit connected to the gate driving circuit, thereby reducing deterioration of the specific thin film transistors to which the node control voltage is applied in the gate driving circuit The reliability of the gate driving circuit can be improved.

In addition to the effects of the present application discussed above, other features and advantages of the present application will be set forth below, or may be apparent to those skilled in the art to which the present application belongs from such description and description.

1 is a view for explaining a display device according to an example of the present application.
Fig. 2 is a view for explaining the display area shown in Fig. 1. Fig.
3 is a waveform diagram showing the time-division driving signal, the high-potential driving voltage, the low-potential driving voltage, and the node control voltage shown in FIG.
4 is a diagram for explaining a gate driving circuit according to an example of the present application.
FIG. 5 is a view for explaining a first driving stage group according to an example shown in FIG.
6 is a waveform diagram showing a plurality of gate start signals and a plurality of gate shift clocks shown in FIG.
FIG. 7 is a view for explaining a first holding stage group according to an example shown in FIG.
8 is a view for explaining the internal configuration of the first driving stage shown in FIG.
9 is a view for explaining the internal configuration of the first holding stage shown in FIG.
10 is a driving waveform diagram of the first holding stage according to the example shown in FIG.
11 is a diagram for explaining an internal configuration of a monitoring circuit and a voltage control circuit according to an example of the present application shown in Figs. 1 and 9. Fig.
FIG. 12 is a diagram showing a connection structure between the first holding stage and the monitoring circuit and the voltage control circuit according to another example of the present application shown in FIG. 7;
Fig. 13 is a diagram for explaining the internal configuration of the monitoring circuit and the voltage control circuit according to another example of the present application shown in Fig. 12; Fig.
14 is a diagram for explaining a gate driving circuit according to another example of the present application.
15 is a view for explaining a display device according to another example of the present application.
16 is a diagram for explaining the gate driving circuit shown in Fig.
FIG. 17 is a waveform diagram of a change in voltage of the first control node in the holding stage according to the present application. FIG.
18 is a graph showing a change in the node control voltage according to the present application.

Brief Description of the Drawings The advantages and features of the present application, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that the present invention may be embodied in many different forms and should not be construed as limited to the particular embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art. And the scope of the invention is to be defined only by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like described in the drawings for describing an example of the present application are illustrative, and thus the present application is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description of the present application, a detailed description of related art will be omitted if it is determined that the subject matter of the present application may be unnecessarily obscured.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the scope of the present application.

It should be understood that the term " at least one " includes all possible combinations from one or more related items. For example, the meaning of " at least one of the first item, the second item and the third item " means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

Each of the features of the various embodiments of the present application may be combined or combined with each other partially or entirely, technically various interlocking and driving are possible, and the examples may be independently performed with respect to each other, .

Hereinafter, preferred embodiments of the display device according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to the constituent elements of the drawings, the same constituent elements may have the same sign as possible even if they are displayed on different drawings

FIG. 1 is a view for explaining a display device according to an example of the present application, FIG. 2 is a view for explaining a display region shown in FIG. 1, FIG. 3 is a timing chart of the time- A driving voltage, a low-potential driving voltage, and a node control voltage.

1 to 3, a display device according to an example of the present application includes a display panel 100, a display driver, a touch driving circuit 600, a monitoring circuit 700, and a voltage control circuit 800 do.

The display panel 100 may be a liquid crystal display panel having an in-cell touch type structure using a capacitive method. For example, the display panel 100 may have an in-cell touch type structure using a self-capacitance type. The display panel 100 may operate in a display mode and a touch sensing mode. For example, the display panel 100 displays an image using light emitted from a backlight unit during a display mode, and serves as a touch panel for touch sensing during a touch sensing mode. The display mode may be performed for each of a plurality of display periods set within one frame, and the touch sensing mode may be performed for each of a plurality of touch sensing periods set immediately before or after a plurality of display periods within one frame.

The display panel 100 according to an example includes a display region 101 provided on a substrate and a non-display region 102 provided at an edge of the substrate so as to surround the display region 101. [

The display region 101 includes a plurality of data lines DL, a plurality of gate lines GL, a plurality of sub-pixels SP, a plurality of touch electrodes TE, and a plurality of touch routing lines TL do.

Each of the plurality of data lines DL receives a data signal in a display mode. Each of the plurality of gate lines GL receives a scan pulse in a display mode. Each of the plurality of data lines DL and the plurality of gate lines GL is provided on the substrate so as to intersect with each other to define a plurality of sub-pixel regions.

Each of the plurality of sub-pixels SP may include a thin film transistor connected to the adjacent gate line GL and the data line DL, a pixel electrode connected to the thin film transistor, and a storage capacitor connected to the pixel electrode.

The thin film transistor may include a gate terminal, a semiconductor layer, a first terminal, and a second terminal. The first terminal and the second terminal of the thin film transistor may be defined as a source terminal or a drain terminal according to a current direction. The thin film transistor may have a bottom gate structure in which the gate terminal is located below the semiconductor layer and / or a top gate structure in which the gate terminal is located on the semiconductor layer. These thin film transistors are covered by a protective layer (or planarization layer).

The pixel electrode is formed of a transparent conductive material on the passivation layer in the sub pixel region and is connected to the second terminal of the thin film transistor through a via hole provided in the passivation layer.

The storage capacitor may be formed between the second terminal of the thin film transistor and the touch electrode TE or between the pixel electrode and the touch electrode TE. The storage capacitor charges the data signal supplied through the thin film transistor and maintains the electric field formed between the pixel electrode and the touch electrode TE by using the charging voltage when the thin film transistor is turned off.

Each of the plurality of touch electrodes TE serves as a touch sensor for sensing a touch by a touch object or as a common electrode for driving a liquid crystal by forming an electric field together with the pixel electrode. That is, each of the plurality of touch electrodes TE is used as a touch sensor in the touch sensing mode and as a common electrode in the display mode. Each of the plurality of touch electrodes TE may be formed of a transparent conductive material such as ITO (Indium Tin Oxide) because it is also used as a common electrode for liquid crystal driving. The touch object may be a user finger or a touch pen, such as an active pen.

Since each of the plurality of touch electrodes TE is used as a touch sensor of a self-capacitance type in the touch sensing mode, it must have a size larger than a minimum contact size between the touch object and the display panel 100. [ Accordingly, each of the plurality of touch electrodes TE may have a size corresponding to the size of one or more sub-pixels SP.

Each of the plurality of touch routing lines TL is individually connected to each of the plurality of touch electrodes TE. Each of the plurality of touch routing lines TL supplies the common voltage Vcom to the corresponding touch electrode TE in the display mode and supplies the touch drive pulse to the corresponding touch electrode TE in the touch sensing mode, And provides a change in capacitance of the corresponding touch electrode TE to the display driver.

In this manner, the display area 101 is divided into n horizontal blocks HB1 through HBn, where n is a natural number of 2 or more, and an image is displayed in units of horizontal blocks in accordance with time division driving or touch sensing is performed. Each of the n horizontal blocks HB1 to HBn according to an example may include i gate lines GL (or a horizontal line) i (i is a natural number of 2 or more), and the i gate lines GL may include one Can be overlapped with the touch electrode (TE). For example, the first horizontal block HB1 may include first to i-th gate lines, and the second horizontal block HB2 may include i + 1 to 2i-th gate lines.

The display driver time-divides the display area 101 of the display panel 100 into n horizontal blocks HB1 to HBn and outputs the sub-pixels in units of horizontal blocks for every first period DP of the time- A data driving circuit 200 and a gate driving circuit 300 for supplying a data signal to the data driver SP.

The data driving circuit 200 converts pixel data R / G / B into analog data signals on the basis of a data control signal DCS and supplies the data signals to a plurality of data lines DL in a display mode.

The data driving circuit 200 according to an exemplary embodiment supplies a data signal to the sub-pixels SP of the corresponding horizontal block through a plurality of data lines DL for every first period DP of the time- do.

The data driving circuit 200 according to another example supplies a data signal to the sub-pixels SP of the corresponding horizontal block through a plurality of data lines DL for every first period DP of the time- And supplies a data load free signal to each of the plurality of data lines DL for every second period TP of the time division driving signal TDS. The data load pre-signal is in phase with the touch driving pulse supplied to the touch electrode TE in the touch sensing mode, so that the data load pre- TE can be reduced to improve the touch sensitivity.

The gate driving circuit 300 is embedded (or integrated) in one side non-display region of the display panel 100 together with a thin film transistor manufacturing process for forming a thin film transistor in the sub-pixel SP, One-to-one. The gate driving circuit 300 generates scan pulses in a predetermined order based on the gate control signal GCS and supplies the generated scan pulses to the gate line GL corresponding to the predetermined sequence. The scan pulse supplied to the gate line is synchronized with the data signal supplied to the data line.

The gate driving circuit 300 according to an exemplary embodiment includes the stage driving power source including the node control voltage Vnc and is included in the horizontal block group in units of horizontal blocks for every first period DP of the time division driving signal TDS And sequentially outputs a carry signal after the second period TP of the time-division driving signal TDS.

The gate drive circuit 300 according to another example is included in a horizontal block group in units of horizontal blocks for every first period DP of the time division drive signal TDS based on the stage drive power source including the node control voltage Vnc A gate load free signal is supplied to each of the plurality of gate lines GL for every second period TP of the time division driving signal TDS after sequentially supplying scan pulses to the i number of gate lines And outputs a carry signal after the second section TP of the time-division driving signal TDS. In this case, the gate-load-free signal is in phase with the touch driving pulse supplied to the touch electrode TE in the touch sensing mode, so that the gate-load pre- TE can be reduced to improve the touch sensitivity.

The display driver according to the present application further includes a timing control circuit 400 and a power generation circuit 500. [

The timing control circuit 400 receives the timing synchronization signal TSS and the input data Idata provided from the host control unit (or the host system) and displays the input data Idata on the basis of the timing synchronization signal TSS (R / G / B) so as to be suitable for time-divisional driving of the panel 100 and supplies the data to the data driving circuit 200. [

The timing control circuit 400 generates a time division driving signal TDS for time-division driving the display panel 100 on a horizontal block basis based on a timing synchronization signal TSS. The time-division driving signal TDS according to an exemplary embodiment includes two or more first periods DP and two or more second periods TP for one frame according to the vertical synchronization signal Vsync of the timing synchronization signal TSS can do. The time-division driving signal TDS may be generated such that the second section TP starts earlier than the first section DP. Here, the first section DP of the time division driving signal TDS may be defined as a display section, and the second section TP of the time division driving signal TDS may be defined as a touch sensing section.

The timing control circuit 400 also generates and outputs the data control signal DCS and the gate control signal GCS based on the timing synchronization signal TSS and the time division drive signal TDS. Here, the data control signal DCS may include a source start signal, a source shift signal, a source enable signal, and a polarity control signal. The gate control signal GCS may include first to fourth gate start signals, first to eighth gate shift clocks, first to fourth scan holding clocks, first to fourth stage reset clocks, and the like have.

Alternatively, the time-division driving signal TDS may be generated in the host control unit (or host system) and provided to the timing control circuit 400. [

The power generation circuit 500 generates various power supplies such as a driving power source and a circuit driving voltage necessary for driving the display device based on the input power source Vin and outputs the generated power. In particular, the power supply generation circuit 500 according to the present invention generates and supplies the high-potential driving voltage Vdd and the low-potential driving voltage Vss to the gate driving circuit 300, respectively, based on the input power supply Vin.

The high-potential driving voltage Vdd according to an example may be set to a constant voltage level of 20 V, but is not limited thereto. The low-potential driving voltage Vss according to an example may be set to a constant-voltage level of -10 V, but is not limited thereto. The low-potential driving voltage Vss is used as a gate-off voltage for turning off the thin film transistors provided in the pixels.

The power generation circuit 500 according to the present application may be implemented as a power management integrated circuit.

In addition, the power supply generation circuit 500 according to the present application includes a common voltage generation circuit for generating a common voltage Vcom, a touch drive pulse generation circuit for generating a touch drive pulse, a first load-free signal Generating circuit, and a second load-free signal generating circuit for generating a gate-load-free signal. Here, the common voltage generating circuit and the touch driving pulse generating circuit may be incorporated in the touch driving circuit 600. [ The common voltage generation circuit, the touch drive pulse generation circuit, the first load-free signal generation circuit, and the second load-free signal generation circuit may be implemented by a touch power integrated circuit.

The touch driving circuit 600 is connected to the plurality of touch electrodes TE in a one-to-one manner via a plurality of touch routing lines TL provided in the display panel 100. The touch driving circuit 600 is connected to the plurality of touch electrodes TS through each of the plurality of touch routing lines TL in the display mode in accordance with the first section DP of the time division driving signal TDS provided from the timing control circuit 400. [ And the common voltage Vcom is supplied to each of the transistors TE. The touch driving circuit 400 senses the touch by the touch object through the touch electrodes TE in the horizontal block in units of horizontal blocks according to the second section TP of the time division driving signal TDS.

The touch driving circuit 600 according to an example is configured to apply a voltage to the plurality of touch electrodes TE through each of the plurality of touch routing lines TL in the touch sensing mode corresponding to the second section TP of the time- And generates touch row data by sensing a capacitance change of the corresponding touch electrode TE through each of the plurality of touch routing lines TL to supply the generated touch row data to the host control unit (Or host system).

The touch driving circuit 600 according to another example senses the pen touch through the pen sensing period in the touch sensing mode corresponding to the second section TP of the time division driving signal TDS, Can be sensed. For example, the touch driving circuit 600 may include a touch pen synchronization signal on the touch electrodes TE in the corresponding horizontal block for each pen sensing period set in a part of a plurality of second intervals TP set within one frame And generates touch row data corresponding to the pen touch position by sensing a signal transmitted from the touch pen through the corresponding touch electrodes TE. At this time, the touch pen receives the touch pen synchronization signal through the conductive tip, and transmits the downlink signal including the pen position data to the display panel 100 based on the received touch pen synchronization signal. The touch driving circuit 600 supplies a touch driving pulse to the touch electrodes TE in the corresponding horizontal block for each of the finger sensing intervals set in the remaining one of the plurality of second intervals TP set within one frame, It is possible to generate the touch row data corresponding to the finger touch position by sensing the capacitance change of the corresponding touch electrode TE.

The host control unit is an MCU (Micro Controller Unit) or an application processor. The host control unit receives touch row data supplied from the touch driving circuit 600 and executes two-dimensional or three-dimensional Dimensional touch coordinate information, and executes an application corresponding to the touch coordinate information.

The monitoring circuit 700 is provided in the non-display area 102 of the display panel 100 and is connected to the gate driving circuit 300 to output a node monitoring signal NMS. Among the thin film transistors constituting the gate driving circuit 300, the specific thin film transistors are deteriorated by the bias stress due to the voltage applied to the node for a long time according to the time division driving of the horizontal blanking method, Resulting in deterioration of the output characteristic and causing image quality deterioration of the display device. The specific thin film transistors are switched in response to a node control voltage Vnc applied to the node, and the degradation rate of the specific thin film transistors may be determined according to a level of a node control voltage Vnc applied to the node. Accordingly, in order to monitor the degree of deterioration of the specific thin film transistors, the monitoring circuit 700 is electrically connected to the node controlling the switching of the feature thin film transistors in the gate driving circuit 300, Generates a node monitoring signal (NMS) and provides it to the voltage control circuit (800).

The voltage control circuit 800 generates a node control voltage Vnc that varies based on the node monitoring signal NMS supplied from the monitoring circuit 700 and provides the node control voltage Vnc to the gate driving circuit 300, Increases reliability and reliability margin. The level of the node control voltage Vnc according to the present application may rise with the lapse of time. The node control voltage Vnc rises stepwise from the initial voltage level Vini to the rated maximum output voltage Vmax of the voltage control circuit 800 in accordance with the node monitoring signal NMS representing the degree of deterioration of the specific thin film transistors Thereby reducing the bias stress applied to the specific thin film transistors connected to the node, thereby reducing the deterioration of the specific thin film transistors.

The initial voltage level Vini of the node control voltage Vnc according to an example has a voltage level lower than the rated maximum output voltage Vmax of the voltage control circuit 800, Can be set to a voltage level capable of normally turning on the thin film transistor having the voltage. For example, when the rated maximum output voltage Vmax of the voltage control circuit 800 is 20V and the initial threshold voltage of the thin film transistor is 1V, the initial voltage level Vini of the node control voltage Vnc is set to 2V .

The display device according to one example of the present application is provided with the node control voltage VSS supplied to the gate driving circuit 300 based on the node monitoring signal NMS output from the monitoring circuit 700 connected to the gate driving circuit 300, The deterioration of the specific thin film transistors to which the node control voltage Vnc is applied in the gate driving circuit 300 can be reduced by varying the gate voltage Vnc, thereby improving the reliability of the gate driving circuit 300.

FIG. 4 is a view for explaining a gate driving circuit according to an example of the present application, FIG. 5 is a view for explaining a first driving stage group according to the example shown in FIG. 4, and FIG. FIG. 7 is a view for explaining a first holding stage group according to an example shown in FIG. 4. FIG. 7 is a waveform chart showing a plurality of gate start signals and a plurality of gate shift clocks shown in FIG.

4 to 7, the gate driving circuit 300 according to an example of the present application includes n driving stage groups DSG1 to DSGn, k (where k is a natural number, n-1) holding stage groups HSG1 A shift clock line unit 301, a scan holding clock line unit 302, a power supply line unit 303, and a reset clock line unit 304. [

Each of the n driving stage groups DSG1 to DSGn is connected to the corresponding one of the horizontal driving blocks Vdd and Vss for each display period based on the voltages of the first node and the second node by the stage driving power Vdd and Vss, And a plurality of driving stages for supplying scan pulses to a plurality of gate lines included in the plurality of gate lines HB1 to HBn. Each of the n driving stage groups DSG1 to DSGn according to an example sequentially supplies scan pulses to i gate lines GL included in the corresponding horizontal blocks HB1 to HBn during the first section of the time- And may include i driving stages DST1 to DSTi. In this case, the gate driving circuit 300 may include a number of driving stages corresponding to the total number of gate lines.

Each of the i driving stages DST1 to DSTi includes an output node connected to i gate lines GL one to one. For example, the first to i-th driving stages DST1 to DSTi of the first driving stage group DSG1 may be connected one-to-one with the first to i-th gate lines GL1 to GLi.

Each of the first to fourth driving stages DST1 to DST4 is enabled by a stage set signal which is a corresponding gate start signal among the first to fourth gate start signals Vst1 to Vst4, The corresponding gate shift clocks of the clocks GCLK1 to GCLK4 are supplied to the first to fourth gate lines GL1 to GL4 as scan pulses and the corresponding one of the fifth to eighth drive stages DST5 to DST8 And can be reset by a stage reset signal which is an output signal of the stage.

Each of the fifth to (i-4) th driving stages DST5 to DSTi-4 is enabled by the output signal of the corresponding fourth driving stage, and each of the corresponding gate shift clocks GCLK is used as a scan pulse, To the (i-4) th gate lines GL5 to GLi-4, respectively, and reset by the output signal of the corresponding fourth driving stage.

Each of the i-3th to i-th driving stages DSTi-3 to DSTi is enabled by the corresponding output signal of the fourth driving stage, and each of the gate shift clocks GCLK is used as a scan pulse, 3 to the i-th gate lines GLi-3 to GLi, respectively, and reset by the corresponding first to fourth stage reset clocks RST1 to RST4, respectively. In one example, the i-3 and i-2 driving stages DSTi-3 and DSTi-2 may be simultaneously reset by the second stage reset clock RST2 and the i-1 and i- DSTi-1, DSTi) can be reset simultaneously by the fourth stage reset clock RST4. In another example, the i-3 and i-1 driving stages DSTi-3 and DSTi-1 may be simultaneously reset by the second stage reset clock RST2 and the i-2 and i- DSTi-2, DSTi) can be reset simultaneously by the fourth stage reset clock RST4.

The output signals of the first to i-th driving stages DST1 to DSTi are supplied to the gate start signal (or stage set signal) of the next fourth driving stage. The output signal of each of the fifth to i-th driving stages DST5 to DSTi is supplied to the stage reset signal of the previous fourth driving stage.

Each of the k holding stage groups HSG1 to HSGk is located between the n driving stage groups DSG1 to DSGn and is controlled by the output signal from the front stage driving stage group and the first control by the stage driving power sources Vss and Vnc And at least one holding stage for providing a carry signal to the rear stage driving stage group based on the voltage of the node and the second control node.

Each of the k holding stage groups HSG1 to HSGk according to an example includes a node control voltage Vnc and a low potential driving voltage Vss and a front stage driving stage group DSG1 to DSGn-1 during a second period of the time- Sequentially provides the four carry signals CS1 to CS4 to the rear stage driving stage group in accordance with the voltage of the first control node and the voltage of the second control node based on the four output signals Vpre1 to Vpre4 provided from the four stages The carry signals CS1 to CS4 are applied to the first to fourth driving stages of the rear stage driving stage group as the gate start signals Vst1 to Vst4, respectively. For example, the four carry signals CS1 to CS4 sequentially output from the first holding stage group HSG1 are supplied as the first to fourth gate start signals Vst1 to Vst4 to the second driving stage group DSG2 May be applied to each of the first to fourth drive stages. The four carry signals CS1 to CS4 sequentially output from the k-th holding stage group HSGk are sequentially output from the first to fourth gate start signals Vst1 to Vst4 to the first to nth driving stage groups DSGn, Can be applied to each of the fourth driving stages.

Each of the k holding stage groups HSG1 to HSGk according to an example may include first to fourth holding stages HS1, HS2, HS3 and HS4.

Each of the first to fourth holding stages HS1, HS2, HS3 and HS4 is enabled by a stage set signal which is a corresponding one of the four output signals Vpre1 to Vpre4 supplied from the preceding stage driving stage group, Holding clocks among the first to fourth scan-holding clocks HCLK1 to HCLK4 as the carry signals CS1 to CS4 to the corresponding driving stages of the first to fourth driving stages of the rear stage driving stage groups DSG2 to DSGn And reset by a stage reset signal which is an output signal of the output signals of the first to fourth driving stages of each of the rear stage driving stage groups DSG2 to DSGn, respectively.

Each of the first to fourth holding stages HS1, HS2, HS3 and HS4 according to an example includes an output node sequentially connected to the first to fourth driving stages of the rear stage driving stage groups DSG2 to DSGn. For example, the first holding stage HS1 of each of the k holding stage groups HSG1 to HSGk is connected to the first driving stage of the rear stage driving stage group DSG2 to DSGn, respectively, and the k holding stage groups HSG1 to HSGk, HSGk may be respectively connected to the fourth driving stage of the rear stage driving stage group DSG2 to DSGn.

The shift clock line unit 301 includes first to eighth shift clock lines to which first to eighth gate shift clocks GCLK1 to GCLK8 having phases shifted sequentially from the timing control circuit are supplied. At this time, the shift clock line of j (j is a natural number between 1 and 8) may be connected to the 8th driving stage DST8a-b, where 8a-b (a is a natural number and b is a natural number 8-j). Thus, the j-th gate shift clock can be supplied to the eighth-ab driving stage DST8a-b through the j-th shift clock line.

Each of the first to eighth gate shift clocks GCLK1 to GCLK8 includes a first voltage section and a second voltage section which are cyclically repeated in a preset period. Here, the first voltage section may have a gate high voltage level (H) capable of turning on the transistor, and the second voltage section may have a gate low voltage level (L) capable of turning off the transistor. Each of the first voltage section and the second voltage section of each of the first to eighth gate shift clocks GCLK1 to GCLK8 has four horizontal periods and each of the first to eighth gate shift clocks GCLK1 to GCLK8 has a first voltage The section is shifted by one horizontal period so that the first voltage section of the adjacent gate shift clock can be overlapped during the three horizontal periods 3H.

The scan holding clock line unit 302 includes first through fourth scan holding clock lines to which first through fourth scan holding clocks HCLK1 through HCLK4 having phases shifted sequentially from the timing control circuit are supplied. At this time, each of the first to fourth scan-holding clock lines is connected to a corresponding one of the first to fourth holding stages HS1, HS2, HS3, HS4 of the k holding stage groups HSG1 to HSGk. Accordingly, each of the first to fourth scan-holding clocks HCLK1 to HCLK4 is applied to the corresponding one of the first to fourth holding stages HS1, HS2, HS3 and HS4 of the k holding stage groups HSG1 to HSGk, Can be supplied to the stage.

Each of the first to fourth scan-holding clocks HCLK1 to HCLK4 may be raised or lowered from a low voltage level to a high voltage level immediately after the end of the second section of the time- division driving signal or at the beginning of the first section of the time- ) And may be dropped to a low voltage level at a high voltage level after a predetermined period of time. In this case, each of the first to fourth scan-holding clocks HCLK1 to HCLK4 may be driven immediately after the end of each of the plurality of second sections included in the time-division driving signal within one frame period or once per each starting point of each of the plurality of first sections Lt; / RTI > For example, each of the first to fourth scan-hold clocks HCLK1 to HCLK4 may be generated immediately after the end of each of the plurality of touch sensing periods or at the start of each of the plurality of display periods within one frame period, ≪ / RTI >

The high voltage level of each of the first to fourth scan holding clocks HCLK1 to HCLK4 according to an exemplary embodiment may have a pulse width corresponding to four horizontal periods that are the same as the gate start signal Vst. Each of the first to fourth scan-holding clocks HCLK1 to HCLK4 outputs the scan pulse (or output signal) in each of the first to fourth drive stages of the second to nth drive stage groups DSG2 to DSGn, It must be generated immediately after the end of the touch sensing period or at the beginning of the display period since it can be defined as a signal for determining the timing. If the first to fourth scan-holding clocks HCLK1 to HCLK4 are generated within the touch sensing period, a scan pulse is output from the second to n-th driving stage groups DSG2 to DSGn to terminate the touch sensing period The display period is switched to the display period, and the touch sensing for the horizontal block can not be completed due to the decrease in the touch sensing time.

The power supply line unit 303 includes a first power supply line and a second power supply line to which the high potential driving voltage Vdd and the low potential driving voltage Vss are respectively supplied from the power generation circuit, And a third power supply line to which the control voltage Vnc is supplied.

The high potential driving voltage Vdd is commonly supplied to the driving stages included in each of the n driving stage groups DSG1 to DSGn through the first power supply line.

The low potential driving voltage Vss is supplied to the driving stages included in each of the n driving stage groups DSG1 to DSGn and the holding stages included in each of the k holding stage groups HSG1 to HSGk through the second power supply line . In addition, the low-potential driving voltage Vss may be switched to the gate-load-free signal during the touch sensing period. At this time, the gate-load-free signal has a voltage level lower than the lowermost driving voltage Vss, Phase.

The node control voltage Vnc is commonly supplied to the holding stages included in each of the k holding stage groups HSG1 to HSGk through the third power supply line.

The reset clock line unit 304 includes first to fourth reset clock lines to which first to fourth stage reset clocks RST1 to RST4 each having a phase sequentially shifted from the timing control circuit are supplied. At this time, each of the first to fourth reset clock lines is connected to a corresponding one of the first to fourth holding stages HS1, HS2, HS3, HS4 of the k holding stage groups HSG1 to HSGk. Thus, each of the first to fourth stage reset clocks RST1 to RST4 is provided with a corresponding one of the first to fourth holding stages HS1, HS2, HS3, HS4 of the k holding stage groups HSG1 to HSGk, Can be supplied to the stage.

Each of the first to fourth stage reset clocks RST1 to RST4 may have a high voltage level and a low voltage level. At this time, the high voltage level of each of the first to fourth stage reset clocks RST1 to RST4 may have the same width as the pulse width of the gate start signal Vst having four horizontal periods.

8 is a view for explaining the internal configuration of the first driving stage shown in FIG.

Referring to FIG. 8, the first driving stage DST1 according to the present example includes a scan output unit 310 and a scan node control unit 330. Referring to FIG.

The scan output unit 310 outputs the first scan pulse Vout1 according to the voltages of the first node Q and the second node QB. The scan output unit 310 according to the embodiment includes a pull-up thin film transistor Tu and a pull-down thin film transistor Td.

The pull-up thin film transistor Tu includes a gate terminal connected to the first node Q, a first terminal connected to the first shift clock line, and a second terminal connected to the output node No. The pull-up thin film transistor Tu is turned on according to the voltage of the first node Q to output the gate high voltage level of the first gate shift clock GCLK1 as the first scan pulse Vout1. The first scan pulse Vout1 is supplied to the first gate line and simultaneously supplied to the stage set signal of the fifth driving stage.

The pull-down thin film transistor Td includes a gate terminal connected to the second node QB, a first terminal receiving the low potential driving voltage Vss, and a second terminal connected to the output node No. This pull-down thin film transistor Td is turned on according to the voltage of the second node QB to supply the low potential driving voltage Vss as the gate-off voltage to the first gate line via the output node No . That is, the pull-down thin film transistor Td is turned on according to the voltage of the second node QB to discharge the voltage of the first gate line to the low potential driving voltage Vss.

The scan node controller 330 controls the scan node controller 330 based on the first gate start pulse Vst1, the fifth drive stage output signal Vout5, the high potential drive voltage Vdd, and the low potential drive voltage Vss. (Q) and the second node (QB). The scan node control unit 330 according to an exemplary embodiment includes a node charging circuit 331, a first node discharging circuit 333, a noise removing circuit 335, a second node discharging circuit 337, and an inverter circuit 338 .

The node charging circuit 331 controls the voltage of the first node Q in response to the first gate start pulse Vst1. The node charging circuit 331 according to one example may include a first thin film transistor T1. The first thin film transistor T1 includes a gate terminal receiving the first gate start pulse Vst1, a first terminal coupled to the high potential driving voltage Vdd, and a second terminal coupled to the first node Q . This first thin film transistor T1 is turned on by the first gate start pulse Vst1 to charge the first node Q with the first driving voltage of the high potential driving voltage Vdd.

The first node discharging circuit 333 discharges the voltage of the first node Q in response to the output signal Vout5 of the fifth driving stage. The first node discharge circuit 333 according to an example may include a second thin film transistor T2. The second thin film transistor T2 includes a gate terminal receiving the output signal Vout5 of the fifth driving stage, a first terminal receiving the low potential driving voltage Vss, and a second terminal coupled to the second node QB. . ≪ / RTI > This second thin film transistor T2 is turned on by the output signal Vout5 of the fifth driving stage to discharge the voltage of the first node Q to the low potential driving voltage Vss.

The noise canceling circuit 335 controls the voltage of the first node Q in response to the voltage of the second node QB. That is, the noise eliminating circuit 335 supplies the low-potential driving voltage Vss to the first node Q in response to the voltage of the second node QB, thereby generating a noise component generated at the first node Q Remove. The noise removing circuit 335 according to one example may include a third thin film transistor T3. The third thin film transistor T3 may include a gate terminal connected to the second node QB and a first terminal receiving the low potential driving voltage Vss and a second terminal connected to the first node Q . The third thin film transistor T3 is turned on by the voltage of the second node QB to discharge the voltage of the first node Q to the low potential driving voltage Vss. The third thin film transistor T3 discharges the voltage of the first node Q to the low potential driving voltage Vss while the pull-up thin film transistor Tu of the scan output unit 310 maintains the off state The coupling between the gate electrode and the source electrode of the pull-up thin film transistor Tu occurs in the rising period of the first gate shift clock GCLK1 supplied to the pull-up thin film transistor Tu, Thereby removing the generated noise component.

The second node discharging circuit 337 controls the voltage of the second node QB in response to the first gate start pulse Vst1. The second node discharge circuit 337 according to an example may include a fourth thin film transistor T4. The fourth thin film transistor T4 includes a gate terminal receiving the first gate start pulse Vst1, a first terminal receiving the low potential driving voltage Vss, and a second terminal connected to the second node QB can do. The fourth thin film transistor T4 is turned on by the first gate start pulse Vst1 to discharge the voltage of the second node QB to the low potential driving voltage Vss.

The inverter circuit 338 controls the voltage of the second node QB in response to the node control voltage Vnc and the voltage of the first node Q. [ In other words, the inverter circuit 338 charges the node control voltage Vnc to the second node QB in response to the voltage of the first node Q or changes the voltage of the second node QB to the low potential drive voltage Vss). The inverter circuit 338 according to an exemplary embodiment may include the fifth to seventh TFTs T51, T52, T53, and T54.

The 5-1 thin film transistor T51 may include a gate terminal receiving the node control voltage Vnc, a first terminal, and a second terminal connected to the internal node Ni. The 5-1th thin film transistor T51 is turned on by the node control voltage Vnc to supply the node control voltage Vnc to the internal node Ni.

The 5-2 th thin film transistor T52 may include a gate terminal connected to the internal node Ni and a first terminal receiving the node control voltage Vnc and a second terminal connected to the second node QB . The 5-2 th thin film transistor T52 is turned on or off according to the voltage of the internal node Ni and supplies the turn-on node control voltage Vnc to the second node QB.

The fifth transistor T53 may include a gate terminal connected to the first node Q, a first terminal receiving the low potential driving voltage Vss, and a second terminal connected to the internal node Ni. have. This fifth-to-third thin film transistor T53 is turned on or off according to the voltage of the first node Q and is turned off to discharge the voltage of the internal node Ni to the low potential driving voltage Vss .

The fifth to fourth thin film transistor T54 includes a gate terminal connected to the first node Q, a first terminal receiving the low potential driving voltage Vss and a second terminal connected to the second node QB . The fifth to fourth thin film transistor T54 is turned on or off according to the voltage of the first node Q and is turned on when the voltage of the second node QB is set to the low potential driving voltage Vss Discharge.

When the fifth-third thin film transistor T53 and the fifth-fourth thin film transistor T54 are turned off according to the voltage of the first node Q, the inverter circuit 338 outputs the node control voltage Vnc The 5-2 thin film transistor T51 turned on by the voltage of the internal node Ni charges the node control voltage Vnc to the internal node Ni through the 5-1th thin film transistor T51 turned on by the internal node Ni, And the node control voltage Vnc is charged to the second node QB through the transistor T52. On the other hand, when the fifth-third thin film transistor T53 and the fifth-fourth thin film transistor T54 are turned on according to the voltage of the first node Q, the inverter circuit 338 turns on the fifth -Thin film transistor T53 to a low potential driving voltage Vss through which the fifth-thin film transistor T52 is turned off and the first node And discharges the voltage of the second node QB to the low potential driving voltage Vss through the fifth through fourth thin film transistor T54 turned on by the voltage of the second node Q. At this time, even if the node control voltage Vnc is supplied to the internal node Ni through the 5-1th thin film transistor T51 turned on by the node control voltage Vnc, the voltage of the internal node Ni is turned on The fifth-thin-film transistor T52 is discharged to the low-potential driving voltage Vss via the fifth-third thin-film transistor T53, thereby turning off the fifth-thin-film transistor T52 connected to the internal node Ni. To this end, the fifth-third thin film transistor T53 has a relatively larger channel size than the fifth-first thin film transistor T51.

Each of the thin film transistors constituting the first driving stage DST1 according to this embodiment includes an oxide semiconductor layer such as zinc oxide (ZnO), indium zinc oxide (InZnO), or indium gallium zinc oxide (InGaZnO) can do.

Hereinafter, the operation of the first driving stage DST1 according to this example will be described with reference to FIGS. 6 and 8. FIG.

First, when the first gate start pulse Vst1 is supplied, the first thin film transistor T1 of the node charging circuit 331 is turned on by the first gate start pulse Vst1, The fourth thin film transistor T4 of the second thin film transistor 337 is turned on. Thus, the voltage of the first node Q is precharged to the node control voltage Vnc supplied through the first thin film transistor T1 turned on by the first gate start pulse Vst1, The voltage of the sustain pulse QB is discharged to the low potential driving voltage Vss through the fourth thin film transistor T4 turned on in accordance with the first gate start pulse Vst1. Accordingly, the pull-up thin film transistor Tu of the scan output unit 310 is turned on by the node control voltage Vnc charged to the first node Q and is supplied to the first shift clock line, And supplies the gate-low voltage level of the shift clock GCLK1 to the first gate line through the output node No. At this time, the pull-down thin film transistor Td of the scan output unit 310 is turned off by the voltage of the second node QB discharged through the fourth thin film transistor T4 to the low potential driving voltage Vss do.

Next, when the first gate shift clock signal GCLK1 of the gate high voltage level is supplied to the first shift clock line, the voltage of the first node Q precharged to the node control voltage Vnc is supplied to the scan output unit 310 The first gate shift clock GCLK1 of the gate high voltage level is supplied to the pull-up thin film transistor Tu of the scan output unit 310 and is bootstrapped to rise to a higher voltage, The pull-up thin film transistor Tu of the transistor Q2 becomes a complete turn-on state. Accordingly, the first gate shift clock signal GCLK1 having the gate high voltage level is supplied to the first scan pulse Vout1 as the first scan pulse Vout1 through the pull-up thin film transistor Tu of the scan output unit 310, 1 gate line. At this time, the voltage of the second node QB is changed according to the voltage of the first node Q by the fifth-third thin film transistor T53 and the fifth 5-4th thin film transistor T54 of the inverter circuit 338 The pull-down thin film transistor Td of the scan output unit 310 maintains the turn-off state by discharging to the low-potential driving voltage Vss through the scan line.

Next, when the output signal Vout5 of the high voltage level is supplied from the fifth driving stage, the second thin film transistor T2 of the first node discharging circuit 333 is driven by the output signal Vout5 of the fifth driving stage The voltage of the first node Q1 is discharged through the second thin film transistor T2 to the low potential driving voltage Vss by turning on the first thin film transistor T2 so that the pull-up thin film transistor Tu is turned off. At the same time, in the inverter circuit 338, each of the fifth-third thin film transistor T53 and the fifth-fourth thin film transistor T54 is turned off by the voltage of the first node Q, Vnc is supplied to the internal node Ni via the 5-1th thin film transistor T51 and the 5-2 th thin film transistor T52 is supplied with the node control voltage Vnc supplied to the internal node Ni - and the node control voltage Vnc is supplied to the second node QB via the fifth-and-second thin film transistor T52 to turn on the pull-down thin film transistor Td. Thus, the voltage of the output node No is discharged to the low potential driving voltage Vss by the turn-on pull-down thin film transistor Td, so that the gate-off voltage is supplied to the first gate line.

The first driving stage DST1 according to this example is connected to the second node QB based on the node control voltage Vnc that varies based on the node monitoring signal NMS output from the monitoring circuit 700 The bias stress applied to the third thin film transistor T3 of the noise canceling circuit 335 which is switched in response to the voltage of the second node QB is reduced by controlling the voltage so that the deterioration of the third thin film transistor T3 is reduced The reliability of the gate driving circuit 300 can be improved, and the reliability of the gate driving circuit 300 can be improved.

On the other hand, among the driving stages constituting each of the n driving stage groups DSG1 to DSGn, the configuration and operation of each of the other driving stages except for the first driving stage are the same as those of the first driving stage DST1 described above, The description of which will be omitted.

FIG. 9 is a view for explaining the internal configuration of the first holding stage according to an example of the present application shown in FIG. 7, and FIG. 10 is a driving waveform diagram of the first holding stage according to the example shown in FIG. 9 .

9 and 10 are combined with FIG. 7, the first holding stage HS1 according to the present example includes a carry output unit 350 and a carry node control unit 370. FIG.

The carry output unit 350 outputs the first carry signal CS1 according to the voltages of the first control node N1 and the second control node N2. The carry output 350 in accordance with one embodiment includes a first output transistor cTu and a second output transistor cTd.

The first output transistor cTu (or the pull-up transistor for carry) includes a gate terminal connected to the first control node N1, a first terminal receiving the first scan holding clock HCLK1, And a second terminal connected to the second terminal. The first output transistor cTu is turned on according to the voltage of the first control node N1 to output a high voltage level of the first scan holding clock HCLK1 as a first carry signal CS1. The first carry signal CS1 is supplied to the first driving stage of the second driving stage group DSG2 as a gate start signal (or stage set signal).

The second output transistor cTd (or pull-down transistor for carry) has a gate terminal connected to the second control node N2, a first terminal receiving the low potential driving voltage Vss, And a second terminal connected to the second terminal. The second output transistor cTd is turned on according to the voltage of the second node N2 to output the low potential driving voltage Vss as the first carry signal CS1 through the node No to the second driving stage group (DSG2). That is, the second output transistor cTd is turned on according to the voltage of the second node N1 to discharge the voltage of the output node No to the low potential driving voltage Vss.

The carry node control unit 370 outputs the output signal Vpre1 of the previous fourth driving stage (hereinafter referred to as a first holding start signal Vpre1), the output of the first driving stage of the second driving stage group DSG2 Based on the signal Vnext1 (hereinafter referred to as a 'first holding reset signal Vnext1'), the node control voltage Vnc, the low potential driving voltage Vss and the first stage reset clock RST1, And controls the voltages of the control node N1 and the second control node N2, respectively.

The carry node control unit 370 according to an example includes a first drive unit 371 (or a carry node charge circuit), a second drive unit 373 (or a first node discharge circuit for carry), a third drive unit 375 (Or a carry noise eliminating circuit), a fourth driving section 377 (or a second node discharging circuit for carry), and a fifth driving section 378 (or an inverter circuit for carry).

The first driving unit 371 controls the voltage of the first control node N1 in response to the first holding start signal Vpre1. The first driver 371 according to an exemplary embodiment may include a first transistor cT1. The first transistor cT1 includes a gate terminal receiving a first holding start signal Vpre1 provided from a front stage driving stage group, a first terminal receiving a node control voltage Vnc, And a second terminal connected thereto. The first transistor cT1 is turned on by the first holding start signal Vpre1 to charge the first control node N1 with the node control voltage Vnc.

The second driving unit 373 discharges the voltage of the first control node N1 in response to the first holding reset signal Vnext1. The second driver 373 according to one example includes a second transistor cT2. The second transistor (cT2) includes a gate terminal receiving a first holding reset signal (Vnext1) provided from a rear stage driving stage group, a first terminal receiving a low potential driving voltage (Vss) And a second terminal connected to the second terminal. The second transistor cT2 is turned on by the first holding reset signal Vnext1 to discharge the voltage of the first control node N1 to the low potential driving voltage Vss.

The third driving unit 375 controls the voltage of the first control node N1 in response to the voltage of the second control node N2. That is, the third driving unit 375 supplies the low-potential driving voltage Vss to the first control node N1 in response to the voltage of the second control node N2, Remove the ingredients. The third driver 375 according to an exemplary embodiment may include a third transistor cT3 (or a transistor for removing noise). The third transistor cT3 may include a gate terminal connected to the second control node N2, a first terminal receiving a low potential driving voltage Vss and a second terminal connected to the first control node N1 have. The third transistor cT3 is turned on by the voltage of the second control node N2 to electrically connect the first control node N1 to the low potential driving voltage Vss. The third transistor cT3 changes the voltage of the first control node N1 to the low potential driving voltage Vss while the first output transistor cTu of the carry output unit 350 maintains the turn- The coupling between the gate electrode of the first output transistor cTu and the source electrode of the first output transistor cTu is generated at the rising edge of the first scan clock HCLK1 supplied to the first output transistor cTu, N1.

The fourth driving unit 377 controls the voltage of the second control node N2 in response to the first holding start signal Vpre1. The fourth driver 377 according to an exemplary embodiment may include a fourth transistor cT4. The fourth transistor (cT4) includes a gate terminal receiving a first holding start signal (Vpre1) provided from a front stage driving stage group, a first terminal receiving a low potential driving voltage (Vss) And a second terminal connected to the second terminal. The fourth transistor cT4 is turned on by the first holding start signal Vpre1 to discharge the voltage of the second control node N2 to the low potential driving voltage Vss.

The fifth driver 378 controls the voltage of the second control node N2 in response to the node control voltage Vnc and the voltage of the first control node N1. That is, the fifth driver 378 charges the second control node N2 with the node control voltage Vnc in response to the voltage of the first control node N1 or charges the second control node N2 with the voltage of the second control node N2 And discharges to the potential driving voltage Vss. The fifth driver 378 according to one example may include the fifth through fifth transistors cT51, cT52, cT53, and cT54.

The fifth transistor cT51 may include a gate terminal receiving the node control voltage Vnc and a first terminal and a second terminal connected to the intermediate node N3. The fifth transistor cT51 is turned on by the node control voltage Vnc to supply the node control voltage Vnc to the intermediate node N3.

The fifth transistor cT52 may include a gate terminal connected to the intermediate node N3 and a first terminal receiving the node control voltage Vnc and a second terminal connected to the second control node N2 . The fifth transistor cT52 is turned on or off according to the voltage of the intermediate node N3 and supplies the node control voltage Vnc at the turn-on time to the second control node N2.

The fifth transistor cT53 may include a gate terminal connected to the first control node N1, a first terminal receiving the low potential driving voltage Vss and a second terminal connected to the intermediate node N3 have. The fifth transistor cT53 is turned on or off according to the voltage of the first control node N1 and the voltage of the intermediate node N3 is discharged to the low potential driving voltage Vss at the turn- .

In order to discharge the node control voltage Vnc applied to the intermediate node N3 through the fifth transistor cT51 turned on by the node control voltage Vnc, And has a relatively larger channel size than the 5 < th > -layer thin film transistor T51.

The fifth transistor (cT54) includes a gate terminal connected to the first control node N1, a first terminal receiving the low potential driving voltage Vss, and a second terminal connected to the second control node N2 can do. The fifth-fourth transistor cT54 is turned on or off according to the voltage of the first control node N1 and is turned on when the voltage of the second control node N2 is lowered to the low potential driving voltage Vss. .

When the fifth transistor (cT53) and the fifth transistor (cT54) are turned off according to the voltage of the first control node (N1) during the display period, the fifth driver (378) The intermediate node N3 is charged with the node control voltage Vnc through the fifth transistor cT51 turned on by the voltage Vnc and the fifth node N3 is turned on by the voltage of the intermediate node N3, The second control node N2 is charged with the node control voltage Vnc through the second transistor cT52. On the other hand, when the fifth to tenth transistors cT53 and cT54 are turned on according to the voltage of the first control node N1 during the touch period, the fifth driving unit 378 turns on the fifth- Transistor cT52 is turned off by discharging the voltage of the intermediate node N3 to the low potential driving voltage Vss through the turned on fifth through third transistor cT53, And discharges the voltage of the second control node N2 to the low potential driving voltage Vss via the fifth through fourth transistors cT54 turned on by the voltage of the node N1.

Each of the transistors constituting the first holding stage HS1 according to this embodiment includes an oxide semiconductor layer such as zinc oxide (ZnO), indium zinc oxide (InZnO), or indium gallium zinc oxide (InGaZnO) And may include the same oxide semiconductor layer as the thin film transistor constituting the first driving stage DS1.

Hereinafter, the operation of the first holding stage HS1 according to this embodiment will be described with reference to FIGS. 9 and 10. FIG.

The first holding stage HS1 according to this example is driven by a display period and a touch sensing period.

First, during the display period, the first holding stage HS1 supplies the first driving stage of the second driving stage group DSG2 through the output node No as the gate-off voltage of the low potential driving voltage Vss. That is, in the first holding stage HS1, the second control node N2 receives the node control voltage Vnc through the fifth driving unit 378, and the voltage of the first control node N1 is controlled by the second control And is discharged to the low potential driving voltage Vss via the third transistor cT3 turned on by the voltage of the node N2. Accordingly, during the display period, the first output transistor cTu maintains the turn-off state by the voltage of the first control node N1, which is maintained at the low potential drive voltage Vss, and the second output transistor cTd, On state by the voltage of the second control node N2 held at the node control voltage Vnc. Accordingly, during the display period, the first holding stage HS1 supplies the first carry signal having the low potential driving voltage Vss through the second output transistor cTd turned on to the first driving stage group DSG2 of the second driving stage group DSG2 To the stage.

Next, during the touch sensing period, the first holding stage HS1 maintains the voltage of the first control node N1 for a predetermined time in response to the first holding start signal Vpre1 supplied from the fourth driving stage And supplies the first scan holding clock HCLK1 as the first carry signal CS1 to the first drive stage of the second drive stage group DSG2 through the output node No.

Specifically, during the touch sensing period, when the first holding start signal Vpre1 supplied from the fourth driving stage is supplied to the first holding stage HS1, the first holding transistor HS1 is turned on by the first holding start signal Vpre1, And the fourth transistor cT4 are turned on so that the voltage of the first control node N1 is lower than the node control voltage Vcc1 supplied through the first transistor cT1 turned on by the first holding start signal Vpre1 And the voltage of the second control node N2 is discharged to the low potential driving voltage Vss via the fourth transistor cT4 turned on according to the first holding start signal Vpre1. Accordingly, the first output transistor cTu of the carry output unit 350 is turned on by the node control voltage Vnc charged to the first control node N1, and is turned on by the low level of the first scan holding clock HCLK1 The voltage level is supplied to the first driving stage of the second driving stage group DSG2 through the output node No and the first driving stage of the second driving stage group DSG2 is supplied with the low voltage It is not enabled by level. At this time, the second output transistor cTd of the scan output unit 350 is turned off by the voltage of the second control node N2, which is discharged through the fourth thin film transistor cT4 to the low potential drive voltage Vss. do.

Next, when the first scan holding clock HCLK1 of the high voltage level is supplied immediately after the end of the touch sensing period TP or the start of the next display period DP, the first holding stage HS1 outputs a node control voltage The voltage of the first control node N1 held at the voltage level precharged by the first scan voltage holding unit Vnc is applied to the first output transistor cTu of the carry output unit 350 by the first scan holding clock HCLK1 Is bootstrapped and rises to a higher voltage, thereby causing the first output transistor (cTu) to be in a complete turn-on state. Accordingly, the first scan holding clock HCLK1 of the high voltage level is supplied to the first output transistor cTu of the carry-over unit 350, which has been turned on completely, as the first carry signal CS1, And is supplied to the first driving stage of the stage group DSG2. At this time, the first output transistor (cTu) receives a relatively small bias stress by the precharged node control voltage (Vnc) during the touch sensing period (TP), and only a relatively large bias stress . This allows the present application to minimize degradation of the first output transistor (cTu).

The first holding stage HS1 according to this example is connected to the first control node N1 based on the node control voltage Vnc that varies based on the node monitoring signal NMS output from the monitoring circuit 700, The bias stress applied to the first output transistor cTu of the carry output unit 350, which is switched in response to the voltage of the first control node N1, by controlling the voltage of the first control node N1 and the voltage of the second control node N2, The deterioration of the first output transistor cTu decreases and the bias stress applied to the third transistor cT3 of the third driver 375 which is switched in response to the voltage of the second control node N2 decreases As the deterioration of the third thin film transistor (cT3) decreases, the reliability improves as the reliability improves, thereby improving the reliability of the gate drive circuit (300).

On the other hand, among the holding stages constituting each of the k holding stage groups (HSG1 to HSGk), the configuration and operation of each of the remaining holding stages except for the first holding stage are the same as those of the first holding stage HS1 described above, The description of which will be omitted.

11 is a diagram for explaining an internal configuration of a monitoring circuit and a voltage control circuit according to an example of the present application shown in Figs. 1 and 9. Fig.

9, the monitoring circuit 700 according to an exemplary embodiment of the present application is configured to monitor the voltage of the node N2 in response to the voltage of the second control node N2 of the holding stage included in any one of the plurality of holding stage groups, And outputs the signal (NMS) to the voltage control circuit 800. For example, the monitoring circuit 700 may include a holding stage HS included in the first holding stage group of the plurality of holding stage groups or a second control node N2 of the holding stage HS included in the k- And outputs the node monitoring signal NMS to the voltage control circuit 800 in response to the voltage of the node monitoring signal NMS. The following description assumes that the monitoring circuit 700 outputs the node monitoring signal NMS in response to the voltage of the second control node N2 of the holding stage HS included in the first holding stage group .

The monitoring circuit 700 according to one example may include a monitoring thin film transistor Tm.

The monitoring thin film transistor Tm has a gate terminal connected to the second control node N2 of the holding stage HS included in the first holding stage group, a first terminal connected to the voltage control circuit 800, And a second terminal receiving the input voltage V1. The monitoring thin film transistor Tm according to one example may have the same size as the third transistor cT3 of the third driving unit 375 included in the holding stage HS. That is, the monitoring thin film transistor Tm is deteriorated due to the bias stress caused by the voltage applied to the second control node N2 for a long time according to the time division driving of the horizontal blanking method and the reliability of the third transistor cT3 The third transistor cT3 is formed to have the same size as the third transistor cT3. This monitoring thin film transistor Tm is turned on in accordance with the voltage of the second control node N2 to generate a current corresponding to the voltage of the second control node N2 using the monitoring power supply voltage V1, NMS).

The voltage control circuit 800 according to an exemplary embodiment of the present invention includes a node control voltage Vnc that varies based on a reference voltage Vref supplied from a reference power supply and a node monitoring signal NMS supplied from the monitoring circuit 700, And provides it to the gate driving circuit 300. [

The voltage control circuit 800 according to an example includes a voltage dividing circuit 801 for outputting a monitoring voltage Vm based on a node monitoring signal NMS, an output terminal OT for outputting a node control voltage Vnc, An operational amplifier OA having an inverting terminal (-) receiving a reference voltage Vref from a reference power supply and a non-inverting terminal (+) receiving a monitoring voltage Vm from a voltage dividing circuit 801, an operational amplifier OA A gain resistor Ra connected between the inverting terminal (-) of the operational amplifier OA and the output terminal OT and an input resistor Rb connected between the inverting terminal (-) of the operational amplifier OA and the reference power source .

The voltage divider circuit 801 outputs the monitoring voltage Vm based on the node monitoring signal NMS supplied from the monitoring circuit 700. [ The voltage dividing circuit 801 according to an example includes a voltage dividing node Nd connected to the non-inverting terminal (+) of the operational amplifier OA and receiving the node monitoring signal NMS from the monitoring circuit 700, A first voltage dividing resistor Rd1 connected between an initial voltage supply providing a voltage Vset and a voltage dividing node Nd and a second voltage dividing resistor Rd2 connected between a ground voltage providing a ground voltage V2 and the voltage dividing node Nd, (Rd2). The voltage divider circuit 801 outputs the monitoring voltage Vm through the voltage distribution of the node monitoring signal NMS according to the resistance ratio of the first and second voltage dividing resistors Rd1 and Rd2.

The initial set voltage Vset has a voltage level lower than the high power supply voltage VH applied to the operational amplifier OA (or the rated maximum output voltage of the voltage control circuit) And is set to a voltage level at which the transistor cT3 can be normally turned on.

The operational amplifier OA outputs the node control voltage Vnc amplified by the difference voltage between the monitoring voltage Vm and the reference voltage Vref based on the resistance ratio between the gain resistor Ra and the input resistor Rb do. That is, the node control voltage Vnc output from the operational amplifier OA corresponds to the node monitoring signal Vcc due to deterioration of the monitoring thin film transistor Tm that represents the output characteristic of the third transistor cT3 included in the holding stage HS. When the monitoring voltage Vm is changed due to a change in the NMS and a voltage difference between the reference voltages Vref is generated, the difference is amplified by the difference voltage between the monitoring voltage Vm and the reference voltage Vref. Accordingly, the node control voltage Vnc output from the operational amplifier OA is dynamically varied corresponding to the change of the monitoring voltage Vm due to the change of the node monitoring signal NMS. For example, the level of the node control voltage Vnc output from the operational amplifier OA may rise stepwise from the initial set voltage Vset to the high power supply VH with the lapse of time.

In this way, the voltage control circuit 800 according to the present application changes the node control voltage Vnc applied to the gate drive circuit in response to the node monitoring signal NMS, thereby changing the node control voltage Vnc according to the node control voltage Vnc Thereby reducing deterioration of the thin film transistors T3 and Tc3 to be switched.

FIG. 12 is a diagram showing a connection structure between a first holding stage, a monitoring circuit, and a voltage control circuit according to another example of the present application shown in FIG. 7, and FIG. Circuit and a voltage control circuit according to an embodiment of the present invention.

Referring to FIG. 12, the first holding stage HS1 according to another example of the present application includes a carry output unit 350 and a carry node control unit 370. FIG.

 The carry output section 350 includes a first output transistor cTu and a second output transistor cTd which are the same as the carry output section of the first holding stage HS1 shown in FIG. The redundant description will be omitted.

The carry node control unit 370 includes first to fifth drive units 371, 373, 375, 377 and 378. The first drive unit 371 receives the first node control voltage Vnc1, The fifth embodiment is the same as the carry node control unit of the first holding stage HS1 shown in FIG. 9 except that the fifth driving unit 378 receives the second node control voltage Vnc2, do. That is, one node control voltage is commonly supplied to the first driver 371 and the fifth driver 378 in the carry node controller of the first holding stage HS1 shown in FIG. On the other hand, in this example, since the degradation speed of the first output transistor cTu, which is switched according to the voltage of the first control node, is relatively slow as compared with the third transistor cT3 that is switched according to the voltage of the second control node, The node control voltages supplied to the first driving unit 371 and the fifth driving unit 378 are set to the first and second node control voltages (< RTI ID = 0.0 > Vnc1, and Vnc2, respectively.

Accordingly, the first holding stage HS1 according to this example is configured to control the voltage of the first control node N1 and the voltage of the first control node N1 based on the first and second node control voltages Vnc1 and Vnc2 output from the monitoring circuit 700, The bias stress applied to the first output transistor cTu of the carry output section 350 switched in response to the voltage of the first control node N1 is reduced by controlling the voltages of the two control nodes N2 individually The deterioration of the first output transistor cTu decreases and the bias stress applied to the third transistor cT3 of the third driver 375 which is switched in response to the voltage of the second control node N2 decreases, As the deterioration of the thin film transistor (cT3) decreases, the reliability improves as the reliability improves, thereby improving the reliability of the gate drive circuit (300).

12 and 13, the monitoring circuit 700 according to another example of the present application may control the voltage of the first control node N1 of the holding stage included in any one of the plurality of holding stage groups, And outputs the first and second node monitoring signals NMS1 and NMS2 to the voltage control circuit 800 in response to each of the voltages of the node N2. For example, the monitoring circuit 700 may include a holding stage (HS) included in a first holding stage group of a plurality of holding stage groups or a first and a second control of a holding stage (HS) included in a kth holding stage group And outputs the first and second node monitoring signals NMS1 and NMS2 to the voltage control circuit 800 in response to the voltage of each of the nodes N1 and N2. In the following description, it is assumed that the monitoring circuit 700 is responsive to the voltages of the first and second control nodes N1 and N2 of the holding stage HS included in the first holding stage group, (NMS1, NMS2).

The monitoring circuit 700 according to the present example may include a first monitoring thin film transistor Tm1 and a second monitoring thin film transistor Tm2.

The first monitoring thin film transistor Tm1 includes a gate terminal connected to the first control node N1 of the holding stage HS included in the first holding stage group and a first terminal connected to the voltage control circuit 800, And a second terminal receiving the voltage V1. The first monitoring thin film transistor Tm1 according to an example may have the same size as the first output transistor cTu of the carry output unit 350 included in the holding stage HS. That is, the first monitoring transistor Tm1 is connected to the first output transistor cTu, which is deteriorated by the bias stress caused by the voltage applied to the first control node N1 for a long time according to the time division driving of the horizontal blanking scheme, The first output transistor cTu is formed to have the same size as the first output transistor cTu. The first monitoring thin film transistor Tm1 is turned on according to the voltage of the first control node N1 to generate a current corresponding to the voltage of the first control node N1 using the first monitoring power supply voltage V1, And outputs the first node monitoring signal NMS1.

The second monitoring thin film transistor Tm2 includes a gate terminal connected to the second control node N2 of the holding stage HS included in the first holding stage group and a first terminal connected to the voltage control circuit 800, And a second terminal receiving the voltage V1. The second monitoring thin film transistor Tm2 according to one example may have the same size as the third transistor cT3 of the third driving unit 375 included in the holding stage HS. That is, the second monitoring TFT Tm2 is connected to the third transistor cT3, which is deteriorated by the bias stress caused by the voltage applied to the second control node N2 for a long time according to the time division driving of the horizontal blanking method, Is formed to have the same size as that of the third transistor (cT3) in order to monitor the characteristic change. This second monitoring thin film transistor Tm2 is turned on in accordance with the voltage of the second control node N2 to generate a current corresponding to the voltage of the second control node N2 by using the monitoring power supply voltage V1, And outputs the node monitoring signal NMS2.

The voltage control circuit 800 according to another example of the present application includes a first node control signal VSS that varies based on the reference voltage Vref supplied from the reference power supply and the first node monitoring signal NMS1 supplied from the monitoring circuit 700, And the voltage Vnc1 is supplied to the gate driving circuit 300. At the same time, based on the reference voltage Vref supplied from the reference power supply and the second node monitoring signal NMS2 supplied from the monitoring circuit 700, And supplies the generated second node control voltage Vnc2 to the gate driving circuit 300. [

The voltage control circuit 800 according to an exemplary embodiment may include a first voltage variable circuit 810 and a second voltage variable circuit 830.

The first voltage variable circuit 810 is connected to the reference voltage Vref supplied from the reference power source and the first monitoring voltage Vm1 according to the first node monitoring signal NMS1 supplied from the monitoring circuit 700 Thereby varying the first node control voltage Vnc1.

The first voltage variable circuit 810 includes a first voltage dividing circuit 811 for outputting a first monitoring voltage Vm1 based on the first node monitoring signal NMS1, (-) receiving the reference voltage Vref from the reference power supply and a non-inverting terminal (-) receiving the first monitoring voltage Vm1 from the first voltage dividing circuit 811 A first gain resistor Ra1 connected between the inverting terminal (-) of the first operational amplifier OA1 and the output terminal OT and a second gain resistor Ra2 connected between the first operational amplifier OA1 and the first operational amplifier OA1, And a first input resistance Rb1 connected between the inverting terminal (-) of the reference voltage source and the reference power source.

The first voltage divider circuit 811 outputs the first monitoring voltage Vm1 based on the first node monitoring signal NMS1 supplied from the monitoring circuit 700, Circuit 801, and thus a duplicate description thereof will be omitted. However, the initial set voltage Vset of the first voltage divider circuit 811 has a voltage level lower than the high power supply VH (or the rated maximum output voltage of the voltage control circuit) applied to the first operational amplifier OA1 And is set to a voltage level that can be normally turned on of the first output transistor (cTu) included in the holding stage (HS).

The first operational amplifier OA1 amplifies the difference between the first monitoring voltage Vm1 and the reference voltage Vref based on the resistance ratio between the first gain resistor Ra1 and the first input resistor Rb1 11 except for outputting the first node control voltage Vnc1, so that a duplicate description thereof will be omitted. Accordingly, the first node control voltage Vnc1 output from the first operational amplifier OA1 is the first monitoring transistor Tm1 representing the output characteristic of the first output transistor cTu included in the holding stage HS The first node monitoring signal NMS1 is changed dynamically corresponding to the change of the first monitoring voltage Vm1 due to the deterioration of the first node monitoring signal NMS1. For example, the level of the first node control voltage Vnc1 output from the first operational amplifier OA1 may rise stepwise from the initial set voltage Vset to the high power supply VH with the lapse of time.

On the other hand, the first node control voltage Vnc1 output from the first operational amplifier OA1 may be supplied to the node set circuit of the driving stages configured in the gate driving circuit, in which case the pull- The image quality can be deteriorated due to an abnormal output of the scan pulse. On the other hand, in the holding stages configured in the gate driving circuit, the first output transistor (cTu) does not participate in the driving of the gate line but only the holding and transferring of the output signal between the driving stage groups, Even if the precharge voltage of the first control node N1 is low due to the first node control voltage Vnc1, it is possible to output a normal carry signal through bootstrapping according to the scan holding clock. Therefore, the first node control voltage Vnc1 output from the first operational amplifier OA1 is supplied only to the holding stages, not to the driving stages configured in the gate driving circuit.

The second voltage varying circuit 830 is connected to the difference voltage between the reference voltage Vref supplied from the reference power supply and the second monitoring voltage Vm2 according to the second node monitoring signal NMS2 supplied from the monitoring circuit 700 Thereby varying the second node control voltage Vnc2.

The second voltage variable circuit 830 according to an example includes a second voltage dividing circuit 831 for outputting the second monitoring voltage Vm2 based on the second node monitoring signal NMS2, (-) for receiving the reference voltage Vref from the reference power source and a non-inverting terminal (-) for receiving the second monitoring voltage Vm2 from the second voltage dividing circuit 831 A second gain resistor Ra2 connected between the inverting terminal (-) and the output terminal OT of the second operational amplifier OA2 and a second gain resistor Ra2 connected between the second operational amplifier OA2 and the second operational amplifier OA2, And a second input resistor Rb2 connected between the inverting terminal (-) of the reference voltage source and the reference power source.

The second voltage dividing circuit 831 outputs the second monitoring voltage Vm2 based on the second node monitoring signal NMS2 supplied from the monitoring circuit 700, Circuit 801, and thus a duplicate description thereof will be omitted.

The second operational amplifier OA2 amplifies the difference voltage between the second monitoring voltage Vm2 and the reference voltage Vref based on the resistance ratio between the second gain resistor Ra2 and the second input resistor Rb2 11 except for outputting the second node control voltage Vnc2, so that redundant description thereof will be omitted. The second node control voltage Vnc2 output from the second operational amplifier OA2 is supplied to the second monitoring thin film transistor Tm2 that represents the output characteristic of the third transistor cT3 included in the holding stage HS, Is dynamically varied corresponding to the change of the second monitoring voltage Vm2 due to the change of the second node monitoring signal NMS2 due to the deterioration of the second monitoring voltage Vm2. For example, the level of the second node control voltage Vnc2 output from the second operational amplifier OA2 may rise stepwise from the initial set voltage Vset to the high power supply VH with the lapse of time.

The second node control voltage Vnc2 output from the second operational amplifier OA2 is supplied to the gate driving circuit. That is, in the gate drive circuit, the inverter circuit 338 of the drive stages included in each of the plurality of drive stage groups charges the second node with the second node control voltage Vnc2.

As described above, the voltage control circuit 800 according to the present invention controls the first and second node control voltages Vnc1 and Vnc2 applied to the gate driving circuit in response to the first and second node monitoring signals NMS1 and NMS2, respectively. (CTu) switched in accordance with the first node control voltage (Vnc1) in the gate drive circuit by individually varying the first node control voltage (Vnc2) and the third node control voltage The deterioration of the transistors T3 and cT3 can be reduced.

FIG. 14 is a diagram for explaining a gate driving circuit according to another example of the present application, which is constructed by changing the configuration of a group of gate control signals and holding stages.

14, the gate driving circuit 300 according to another example of the present application includes n driving stage groups DSG1 to DSGn, k holding stage groups HSG1 to HSGk, a shift clock line unit 301, A scan holding clock line unit 302, a power supply line unit 303, and a reset clock line unit 304.

Each of the n driving stage groups DSG1 to DSGn sequentially supplies scan pulses to the i gate lines GL included in the corresponding horizontal blocks HB1 to HBn during the first section of the time division driving signal. Each of the n driving stage groups DSG1 to DSGn according to an example may include i driving stages. In this case, the gate driving circuit 300 may include a number of driving stages corresponding to the total number of gate lines.

Each of the i driving stages includes an output node connected to i gate lines GL one to one. For example, the first to i-th driving stages of the first driving stage group DSG1 may be connected one-to-one with the first to i-th gate lines GL1 to GLi.

The first one of the i driving stages is enabled in response to the gate start signal Vst provided from the timing control circuit and can be reset in response to the output signal of the second driving stage. Each of the second to (i-1) th driving stages is enabled in response to the output signal of the front stage driving stage, and can be reset in response to the output signal of the rear stage driving stage. The i-th driving stage is enabled in response to the output signal of the (i-1) -th driving stage and can be reset in response to the stage reset clock RST supplied from the reset clock line unit 304.

Each of the i driving stages has the same configuration as the first driving stage shown in Fig. 8 except that one gate start signal (Vst) and one stage reset clock (RST) are supplied from the timing control circuit , And a duplicate description thereof will be omitted.

Each of the k holding stage groups HSG1 to HSGk is located between the n driving stage groups DSG1 to DSGn and is controlled by the output signal from the front stage driving stage group and the first control by the stage driving power sources Vss and Vnc The carry signal CS is supplied as the gate start signal Vst to the first driving stage of the rear stage driving stage group based on the voltage of the node and the second control node to the first driving stage of the rear stage driving stage group . Each of these k holding stage groups HSG1 to HSGk is the same as the k holding stage groups shown in Fig. 4 except that it outputs one carry signal CS.

Each of the k holding stage groups (HSG1 to HSGk) according to an example may include one holding stage.

Each of the holding stages receives an output signal of the last driving stage of the preceding stage driving stage group as a holding start signal Vpre and is enabled to turn the scan holding clock HCLK into a carry signal CS, To the first driving stage of each of the groups DSG2 to DSGn, and reset by the stage reset clock RST, respectively. Such a holding stage has the same configuration as the first holding stage HS1 shown in Figs. 9 and 10, and a description of the configuration and operation thereof will be omitted.

The shift clock line unit 301 includes first to eighth shift clock lines to which first to eighth gate shift clocks GCLK1 to GCLK8 having phases shifted sequentially from the timing control circuit are supplied. At this time, the shift clock line of j (j is a natural number between 1 and 8) may be connected to the 8th driving stage DST8a-b, where 8a-b (a is a natural number and b is a natural number 8-j). Thus, the j-th gate shift clock can be supplied to the eighth-ab driving stage DST8a-b through the j-th shift clock line.

Each of the first to eighth gate shift clocks GCLK1 to GCLK8 includes a first voltage section and a second voltage section which are cyclically repeated in one horizontal period. Here, the first voltage section may have a high voltage level (H) capable of turning on the transistor, and the second voltage section may have a low voltage level (L) capable of turning off the transistor. The first voltage section of each of the first to eighth gate shift clocks GCLK1 to GCLK8 is shifted by one horizontal period so that the first voltage section of the adjacent gate shift clock is not overlapped.

The scan holding clock line unit 302 includes one scan holding clock line to which a scan holding clock (HCLK) is supplied from the timing control circuit. This one scan holding clock line may be commonly connected to the holding stages of each of k holding stage groups (HSG1 to HSGk).

The scan holding clock signal HCLK is raised from the low voltage level to the high voltage level immediately after the end of the second section of the time division driving signal or at the start time of the first section of the time division driving signal, Can be polled to a low voltage level. At this time, the scan holding clock HCLK is generated one time immediately after the end of each of the plurality of second sections included in the time division driving signal within one frame period or every starting point of each of the plurality of first sections. If the scan holding clock HCLK is generated within the touch sensing period, scan pulses are output from the second to n < th > drive stage groups DSG2 to DSGn to be switched to the display period before the touch sensing period ends, The touch sensing for the horizontal block can not be completed due to the decrease of the touch sensing time due to the touch sensing.

The power supply line unit 303 includes a first power supply line and a second power supply line to which the high potential driving voltage Vdd and the low potential driving voltage Vss are respectively supplied from the power generation circuit, And a third power supply line to which the control voltage Vnc is supplied. Since the power line unit 303 is the same as the power line unit shown in FIG. 4, a duplicate description thereof will be omitted.

The reset clock line unit 304 includes one reset clock line to which a stage reset clock RST is supplied from the timing control circuit. This reset clock line may be connected to the last driving stage of each of the n driving stage groups DSG1 to DSGn, and may be connected to the holding stage of each of the k holding stage groups (HSG1 to HSGk).

The stage reset clock RST may have a high voltage level and a low voltage level. At this time, the high voltage level of the stage reset clock RST may have the same width as the pulse width of the gate start signal Vst having one horizontal period.

As described above, the gate driving circuit 300 according to another example of the present application is configured such that each of the first to n < th > driving stage groups DSG1 to DSGn is outputted from the holding stage of each of the gate start signal Vst or the preceding stage group 1 except that each of the first to k-th holding stage groups HSG1 to HSGk is enabled by an output signal of the last driving stage of the preceding stage driving stage group DSG2 to DSGn, To the gate driving circuit shown in FIG. 10, so that a duplicate description thereof will be omitted.

The display device including the gate driving circuit 300 according to another example of the present application described above is connected to the gate driving circuit 300 based on the node monitoring signal NMS output from the monitoring circuit 700 connected to the gate driving circuit 300 The deterioration of the specific thin film transistors to which the node control voltage Vnc is applied in the gate driving circuit 300 is reduced due to the variation of the node control voltage Vnc supplied to the gate driving circuit 300, Can be improved.

FIG. 15 is a view for explaining a display device according to another example of the present application, and FIG. 16 is a view for explaining the gate drive circuit shown in FIG. 15, The configuration is changed. Accordingly, only the gate driving circuit and the related structure will be described in the following description, and the overlapping description of the same structure will be omitted.

15 and 16, the gate driving circuit 300 according to the present example drives a plurality of gate lines GL in accordance with an interlacing scheme of a single feeding scheme. The gate driving circuit 300 according to an exemplary embodiment includes a first shift register 300a and a second shift register 300b.

The first shift register 300a is embedded (or integrated) in one side non-display area (or left non-display area) of the display panel 100 and is connected to the odd-numbered gate lines GL of the plurality of gate lines GL one- . The first shift register 300a includes a first shift register 300a and a second shift register 300b. The first shift register 300a includes a gate control signal GCS provided from a timing control circuit, And sequentially supplies scan pulses to the odd-numbered gate lines.

The first shift register 300a according to an example includes n driving stage groups 1DSG1 to 1DSGn, k holding stage groups 1HSG1 to 1HSGk, a reception shift clock line unit 301a, A scan holding clock line unit 302a, a receiving power line unit 303a, and an accepting reset clock line unit 304a.

Each of the n driving stage groups 1DSG1 to 1DSGn for the base is connected to the odd-numbered gate lines among the i gate lines GL included in the corresponding horizontal blocks HB1 to HBn during the first section of the time- Respectively. Each of the n driving stage groups 1DSG1 to 1DSGn according to an example may include i / 2 driving stages. In this case, the first shift register 300a may include a number of driving stages corresponding to half of the total number of gate lines.

Each of the driving stages included in each of the n driving stage groups 1DSG1 to 1DSGn is enabled by each of the first and third gate start signals Vst1 and Vst3 to sequentially apply scan pulses to the odd- 8, except for the above-described configuration, and thus the description of the configuration and operation thereof will be omitted.

Each of the k holding stage groups 1HSG1 to 1HSGk is located between the group of n driving stage groups 1DSG1 to 1DSGn for accepting the output signals from the front stage driving stage group and the stage driving power sources Vss and Vnc And sequentially supplying the first and third carry signals to the group of the rear stage driving stage based on the voltages of the first control node and the second control node due to the first and third gate signals, Is applied to each of the first and second driving stages of the group of the rear end stage driving stage as signals Vst1 and Vst3.

Each of the k holding stage groups 1HSG1 to 1HSGk according to an example may include first and second holding stages.

Each of the first and second holding stages is enabled by a corresponding one of the two output signals supplied from each of the i-1 and i-th driving stages of the group of the preceding-stage driving stage groups, The corresponding one of the first and second driving stages of the second to n < th > driving stage groups 1DSG2 to 1DSGn of the first to third driving stages is set as a first and a third carry signal among the holding clocks HCLK1 and HCLK3, And may be sequentially reset by the corresponding stage reset clock among the first and third stage reset clocks RST1 and RST3.

Each of the holding stages included in each of the k holding stage groups 1HSG1 to 1HSGk is enabled by each of the two output signals supplied from each of the i-1 and i-th driving stages of the group of preceding- 9 and 10, except that the first and third carry signals are sequentially output. Therefore, a description of the configuration and operation of the first holding stage HS1 will be omitted .

The capacitor shift clock line unit 301a includes odd-numbered gate shift clocks GCLK1, GCLK3, GCLK5, and GCLK7 among the first to eighth gate shift clocks GCLK1 to GCLK8 having phases shifted sequentially from the timing control circuit, 4 to 6 except for the four shift clock lines to which the clock signal is supplied. Therefore, a duplicate description thereof will be omitted.

The holding scan holding clock line unit 302a includes first and third scan holding clocks HCLK1 and HCLK3 among the first to fourth scan holding clocks HCLK1 to HCLK4 sequentially shifted from the timing control circuit, 4 to 7 except that the scan-holding clock line includes two supplied scan-holding clock lines. Therefore, a duplicate description thereof will be omitted.

The power supply line unit 303a includes a first power supply line and a second power supply line to which the high potential driving voltage Vdd and the low potential driving voltage Vss are respectively supplied from the power generation circuit, And a third power supply line to which the node control voltage Vnc is supplied, which is the same as that shown in FIG. 4 to FIG. 7, so that a duplicate description thereof will be omitted.

The capacitor reception reset clock line unit 304a includes two reset clock lines RST1 and RST3 supplied with the first and third stage reset clocks RST1 and RST3 of the first to fourth stage reset clocks RST1 to RST4 from the timing control circuit, 4 to 7, except for the fact that it is the same as that shown in FIG.

The second shift register 300b is embedded (or integrated) in the other non-display area (or the right non-display area) of the display panel 100 and is connected to the gate lines GL of the plurality of gate lines GL one- . The second shift register 300b includes a first shift register 300b and a second shift register 300b. The second shift register 300b includes a gate control signal GCS provided from a timing control circuit, And the scan pulse is sequentially supplied to the odd-numbered gate lines.

The second shift register 300b according to an exemplary embodiment includes n driving stage groups 2DSG1 to 2DSGn for excellent use, k holding stage groups 2HSG1 to 2HSGk for good use, an excellent shift clock line unit 301b, A scan holding clock line unit 302b, an even power line unit 303b, and an excellent reset clock line unit 304b.

Each of the n number of driving stage groups 2DSG1 to 2DSGn for the good is connected to the even gate line GL of the i gate lines GL included in the corresponding horizontal blocks HB1 to HBn during the first section of the time- Respectively. Each of the n driving stage groups 2DSG1 to 2DSGn for example according to an example may include i / 2 driving stages. In this case, the second shift register 300b may include a number of driving stages corresponding to half of the total number of gate lines.

Each of the driving stages included in each of the n driving stage groups 2DSG1 to 2DSGn for the superior is enabled by each of the second and fourth gate start signals Vst2 and Vst4 to sequentially supply scan pulses to the even- 8, except for the above-described configuration, and thus the description of the configuration and operation thereof will be omitted.

Each of the k holding stage groups 2HSG1 to 2HSGk for the good is located between the n driving stage groups 2DSG1 to 2DSGn for superior and is connected to the stage driving power sources Vss and Vnc by an output signal provided from the front- And the second and fourth carry signals are sequentially supplied to the succeeding stage of the succeeding stage group based on the voltages of the first control node and the second control node due to the second and fourth gate signals, Signals Vst2 and Vst4, respectively, to the first and second driving stages of the back stage driving stage group for superior driving.

Each of the k holding stage groups 2HSG1 to 2HHSGk for example according to an example may include first and second holding stages.

Each of the first and second holding stages is enabled by a corresponding one of the two output signals supplied from each of the i-1 and i-th driving stages of the group of front stage driving stages for superior, The corresponding scan holding clocks of the holding clocks HCLK2 and HCLK4 are used as the second and fourth carry signals and the corresponding one of the first and second driving stages of the second to nth driving stage groups 2DSG2 to 2DSGn And may be sequentially reset by the corresponding stage reset clock of the second and fourth stage reset clocks RST2 and RST4.

Each of the holding stages included in each of the k holding stage groups (2HSG1 to 2HSGk) for the superior is enabled by each of the two output signals supplied from each of the i-th and (i) th driving stages of the front- 9 and 10, except that the second and fourth carry signals are sequentially output. Therefore, the description of the configuration and operation of the first holding stage HS1 is omitted .

The superior shift clock line unit 301b includes even-numbered gate shift clocks GCLK2, GCLK4, GCLK6, and GCLK8 among the first to eighth gate shift clocks GCLK1 to GCLK8 having phases shifted sequentially from the timing control circuit, 4 to 6 except for the four shift clock lines to which the clock signal is supplied. Therefore, a duplicate description thereof will be omitted.

The superior scan holding clock line 302b includes second and fourth scan holding clocks HCLK2 and HCLK4 among the first to fourth scan holding clocks HCLK1 to HCLK4 having phases shifted sequentially from the timing control circuit, 4 to 7 except that the scan-holding clock line includes two supplied scan-holding clock lines. Therefore, a duplicate description thereof will be omitted.

The power supply line unit 303b includes a first power supply line and a second power supply line to which the high potential driving voltage Vdd and the low potential driving voltage Vss are respectively supplied from the power generation circuit, And a third power supply line to which the node control voltage Vnc is supplied, which is the same as that shown in FIG. 4 to FIG. 7, so that a duplicate description thereof will be omitted.

The resetting reset clock line unit 304b receives reset clock lines RST2 and RST4 from the timing control circuit, which are supplied with the second and fourth stage reset clocks RST2 and RST4 of the first to fourth stage reset clocks RST1 to RST4, 4 to 7, except for the fact that it is the same as that shown in FIG.

The display device including the gate driving circuit 300 according to the present embodiment has a first shift register 300a and a second shift register 300b while providing the same effect as the display device according to the example of the present application The data charging period can be ensured at high-speed driving of 120 Hz or more through the left and right overlap driving of the scan pulse using the interlacing method using the single feeding method using the scan pulse.

Meanwhile, each of the first and second shift registers 300a and 300b of the gate driving circuit 300 shown in FIGS. 15 and 16 may have the same configuration as the gate driving circuit shown in FIGS. 5 to 10. In this case, the first shift register 300a supplies scan pulses to one side of each of the plurality of gate lines, and at the same time, the second shift register 300b supplies scan pulses to the other side of each of the plurality of gate lines. Accordingly, each of the plurality of gate lines is driven by a double feeding method in which scan pulses are simultaneously supplied from both sides, thereby minimizing the voltage drop of the scan pulse according to the line resistance of each of the plurality of gate lines, Can be improved.

On the other hand, each of the first and second shift registers 300a and 300b of the gate driving circuit 300 shown in Figs. 15 and 16 may be configured as the gate driving circuit shown in Fig.

FIG. 17 is a waveform diagram of a change in voltage of the first control node in the holding stage according to the present application. FIG.

17, the voltage of the first control node in the holding stage according to the present application is controlled by the variable node control (NMS) based on the node monitoring signal (NMS) output from the monitoring circuit 700 connected to the gate driving circuit 300 Even if precharged to a voltage lower than the conventional high potential driving voltage by the voltage Vnc, it can be ascertained that the scanning holding clock is normally output as a carry signal normally due to bootstrapping according to the scanning holding clock. Thus, the present application can reduce the deterioration of the specific thin film transistors to which the node control voltage Vnc is applied in the gate driving circuit 300, thereby improving the reliability of the gate driving circuit 300. [

18 is a graph showing a change in the node control voltage according to the present application. In Fig. 18, the horizontal axis represents time, and the vertical axis represents voltage level.

As can be seen from FIG. 18, it can be seen that the node control voltage according to the present application increases with time. Therefore, the present application is based on the fact that the node control voltage Vnc is dynamically varied by applying the node monitoring signal NMS output from the monitoring circuit 700 connected to the gate driving circuit 300 The initial deterioration of the specific thin film transistors can be reduced and the reliability and reliability margin of the gate driving circuit 300 can be increased.

A display device according to an embodiment of the present invention includes a gate driving circuit for dividing a display area of a display panel into a plurality of horizontal blocks and driving gate lines in horizontal blocks in units of horizontal blocks for each of a plurality of display periods in one frame, A touch sensing circuit for sensing a touch through touch sensors in a horizontal block in horizontal block units for each of a plurality of touch sensing intervals, a monitoring circuit connected to the gate driving circuit for outputting a node monitoring signal, And a voltage control circuit for generating a node control voltage varying on the basis of the node control voltage and providing the generated node control voltage to the gate drive circuit, The gate of After supplying the scan pulse to the can output a carry signal after the touch sensing period.

In the present application, the level of the node control voltage can rise with the lapse of time.

In the present application, the gate driving circuit scans a plurality of gate lines included in a corresponding horizontal block for each display period based on the voltage of the first node and the second node by the stage driving power supply, the stage set signal, A plurality of driving stage groups having a plurality of driving stages for supplying pulses; And at least one of a plurality of driving stage groups which are provided between the output stage of the stage driving group and the stage driving power supply and which supply carry signals to the rear stage driving stage group based on the voltages of the first control node and the second control node, And a plurality of holding stage groups having one holding stage.

In the present application, the display panel has a non-display area surrounding the display area, and the monitoring circuit is provided in a non-display area of the display panel, and the voltage of the second control node of the holding stage included in any one of the plurality of holding stage groups The voltage control circuit may output a node control voltage that varies based on a reference voltage supplied from the reference power supply and a node monitoring signal supplied from the monitoring circuit.

In the present application, the monitoring circuit includes a monitoring thin film transistor outputting a node monitoring signal, the monitoring thin film transistor having a gate terminal connected to a second control node of a holding stage included in any one of a plurality of holding stage groups, And a second terminal receiving the monitoring power supply voltage.

In the present application, the voltage control circuit comprises: a voltage divider circuit for outputting a monitoring voltage based on a node monitoring signal; An operational amplifier having an output terminal for outputting a node control voltage, an inverting terminal for receiving a reference voltage from a reference power supply, and a non-inverting terminal for receiving a monitoring voltage; A gain resistor coupled between the inverting and output terminals of the operational amplifier; And an input resistance connected between the inverting terminal of the operational amplifier and the reference power supply.

In the present application, the voltage control circuit includes a first voltage control circuit for outputting a first node control voltage varying in accordance with a difference between a reference voltage supplied from a reference power supply and a first monitoring voltage according to a first node monitoring signal supplied from the monitoring circuit, And a second voltage variable circuit for outputting a second node control voltage varying in accordance with a difference voltage between a reference voltage supplied from the reference power supply and a second monitoring voltage according to a second node monitoring signal supplied from the monitoring circuit can do.

In the present application, at least one holding stage can output a scan holding clock as a carry signal according to the voltage of the first control node.

In the present application, the scan holding clock may be raised to a high voltage level at a low voltage level immediately after the end of a touch sensing period or at the beginning of a display period, and may be polled to a low voltage level at a high voltage level after a predetermined period of time.

In the present application, the gate driving circuit includes a first shift register including a plurality of driving stage groups and a plurality of holding stage groups and supplying scan pulses to the odd-numbered gate lines among the plurality of gate lines; And a second shift register including a plurality of driving stage groups and a plurality of holding stage groups and supplying scan pulses to even-numbered gate lines among the plurality of gate lines.

In the present application, the touch driving circuit supplies a common voltage to the touch electrodes included in the corresponding horizontal block for each display period, senses a touch on the touch object through the touch electrodes included in the corresponding horizontal block for each touch sensing period can do.

In the present application, the touch driving circuit supplies a common voltage to the touch electrodes included in the corresponding horizontal block for each display period, and supplies a common voltage to the touch electrodes included in the corresponding horizontal blocks for each pen sensing period A plurality of touch sensing electrodes for sensing a signal transmitted from the touch pen, supplying a touch pen synchronous signal to the touch electrodes, sensing the signals transmitted from the touch pen, And the capacitance change of the corresponding touch electrodes can be sensed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the scope of the present application is to be defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present application.

100: display panel 200: data driving circuit
300: Gate driving circuit 300a: First shift register
300b: second shift register 310: scan output section
330: scan node control unit 350: carry output unit
370: Carry node control unit 400: Timing control circuit
500: power generation circuit 600: touch driving circuit
700: Monitoring circuit 800: Voltage control circuit

Claims (27)

A display panel having a display region including a plurality of gate lines, a plurality of data lines, and a plurality of touch sensors;
A gate driving circuit for dividing a display area of the display panel into a plurality of horizontal blocks and driving gate lines in horizontal blocks in units of horizontal blocks for each of a plurality of display periods in one frame;
A touch driving circuit for sensing a touch through touch sensors in a horizontal block in units of horizontal blocks for each of a plurality of touch sensing periods of the frame;
A monitoring circuit connected to the gate driving circuit and outputting a node monitoring signal; And
And a voltage control circuit for generating a variable node control voltage based on the node monitoring signal supplied from the monitoring circuit and providing the node control voltage to the gate driving circuit,
Wherein the gate driving circuit supplies a scan pulse to a plurality of gate lines included in a corresponding horizontal block for each display period based on a stage driving power source including the node control voltage, And outputs the output signal. The method according to claim 1,
And the level of the node control voltage rises with passage of time. The method according to claim 1,
Wherein the gate driving circuit comprises:
And a plurality of gate lines for supplying scan pulses to the plurality of gate lines included in the corresponding horizontal block for each display period based on the voltage of the first node and the second node by the stage driving power source, the stage set signal, A plurality of driving stage groups having driving stages; And
A carry signal is provided to the rear stage driving stage group based on the output signal provided from the front stage driving stage group and the voltage of the first control node and the second control node by the stage driving power source, And a plurality of holding stage groups having at least one holding stage for performing at least one of the plurality of holding stages. The method of claim 3,
Wherein the display panel has a non-display area surrounding the display area,
Wherein the monitoring circuit outputs a node monitoring signal in response to a voltage of a second control node of a holding stage provided in a non-display area of the display panel and included in any one of the plurality of holding stage groups,
Wherein the voltage control circuit outputs the node control voltage varying based on a reference voltage supplied from a reference power supply and a node monitoring signal supplied from the monitoring circuit. 5. The method of claim 4,
Wherein the monitoring circuit includes a monitoring thin film transistor for outputting the node monitoring signal,
The monitoring thin film transistor includes a gate terminal connected to a second control node of a holding stage included in any one of the plurality of holding stage groups, a first terminal connected to the voltage control circuit, and a second terminal receiving a monitoring power supply voltage / RTI > 5. The method of claim 4,
The voltage control circuit includes:
A voltage divider circuit for outputting a monitoring voltage based on the node monitoring signal;
An operational amplifier having an output terminal for outputting the node control voltage, an inverting terminal for receiving a reference voltage from a reference power supply, and a non-inverting terminal for receiving the monitoring voltage;
A gain resistor connected between the inverting terminal and the output terminal of the operational amplifier; And
And an input resistance connected between the inverting terminal of the operational amplifier and the reference power supply. The method according to claim 6,
The voltage divider circuit includes:
A voltage divider node connected to a non-inverting terminal of the operational amplifier and receiving a node monitoring signal from the monitoring circuit;
A first voltage dividing resistor connected between an initial voltage source for providing an initial set voltage and the voltage divider node; And
And a second voltage dividing resistor connected between the voltage divider node and a ground power supply for providing a ground voltage. The method of claim 3,
Wherein the node control voltage comprises a first node control voltage and a second node control voltage,
Wherein the monitoring circuit is provided in a non-display area of the display panel and is responsive to voltages of a first control node and a second control node of a holding stage included in any one of the plurality of holding stage groups, Outputs a two-node monitoring signal,
Wherein the voltage control circuit outputs the first node control voltage varying based on a reference voltage supplied from a reference power supply and a first node monitoring signal supplied from the monitoring circuit, And outputs the second node control voltage which is varied based on a second node monitoring signal supplied thereto. 9. The method of claim 8,
Wherein the monitoring circuit includes a first monitoring thin film transistor for outputting the first node monitoring signal and a second monitoring thin film transistor for outputting the second node monitoring signal,
The first monitoring thin film transistor has a gate terminal connected to a first control node of a holding stage included in any one of the plurality of holding stage groups, a first terminal connected to the voltage control circuit, Terminal,
The second monitoring thin film transistor includes a gate terminal connected to a second control node of a holding stage included in any one of the plurality of holding stage groups, a first terminal connected to the voltage control circuit, 2 terminal, and the display device. 9. The method of claim 8,
The voltage control circuit includes:
A first voltage variable circuit that outputs the first node control voltage varying according to a difference voltage between a reference voltage supplied from the reference power supply and a first monitoring voltage according to a first node monitoring signal supplied from the monitoring circuit; And
And a second voltage variable circuit for outputting the second node control voltage varying according to a difference voltage between a reference voltage supplied from the reference power supply and a second monitoring voltage according to a second node monitoring signal supplied from the monitoring circuit , A display device. 11. The method of claim 10,
Wherein the first voltage variable circuit comprises:
A first voltage dividing circuit for outputting a first monitoring voltage based on the first node monitoring signal;
A first operational amplifier having an output terminal for outputting the first node control voltage, an inverting terminal for receiving a reference voltage from a reference power supply, and a non-inverting terminal for receiving the first monitoring voltage;
A first gain resistor connected between an inverting terminal and an output terminal of the first operational amplifier; And
And a first input resistance connected between the inverting terminal of the first operational amplifier and the reference power supply. 12. The method of claim 11,
The first voltage divider circuit includes:
A voltage divider node connected to a non-inverting terminal of the first operational amplifier and receiving a first node monitoring signal from the monitoring circuit;
A first voltage dividing resistor connected between an initial voltage source for providing an initial set voltage and the voltage divider node; And
And a second voltage dividing resistor connected between the voltage divider node and a ground power supply for providing a ground voltage. 11. The method of claim 10,
Wherein the second voltage variable circuit comprises:
A second voltage dividing circuit for outputting a second monitoring voltage based on the second node monitoring signal;
A second operational amplifier having an output terminal for outputting the second node control voltage, an inverting terminal for receiving a reference voltage from a reference power supply, and a non-inverting terminal for receiving the second monitoring voltage;
A second gain resistor connected between an inverting terminal and an output terminal of the second operational amplifier; And
And a second input resistor connected between the inverting terminal of the second operational amplifier and the reference power supply. 14. The method of claim 13,
Wherein the second voltage variable circuit comprises:
A voltage divider node connected to a non-inverting terminal of the second operational amplifier and receiving a second node monitoring signal from the monitoring circuit;
A first voltage dividing resistor connected between an initial voltage source for providing an initial set voltage and the voltage divider node; And
And a second voltage dividing resistor connected between the voltage divider node and a ground power supply for providing a ground voltage. The method of claim 3,
Wherein each of the plurality of drive stages includes:
A scan output unit for outputting the scan pulse in response to a voltage of the first node and a voltage of the second node;
A node charging circuit that charges the high potential driving voltage to the first node in response to the stage set signal which is an output signal provided from the front stage driving stage group;
A first node discharging circuit for discharging the voltage of the first node to a low potential driving voltage in response to the stage reset signal which is an output signal provided from the rear stage driving stage group;
A noise elimination circuit for discharging the voltage of the first node to the low potential driving voltage in response to the voltage of the second node;
A second node discharging circuit for discharging the voltage of the second node to the low potential driving voltage in response to the stage set signal; And
And an inverter circuit for charging the node control voltage to the second node or discharging the voltage of the second node to the low potential drive voltage in response to the node control voltage and the voltage of the first node. 16. The method of claim 15,
The inverter circuit includes:
A 5-1 thin film transistor having a gate terminal receiving the node control voltage, a first terminal and a second terminal connected to the internal node;
A 5-2 thin film transistor having a gate terminal connected to the internal node, a first terminal receiving the node control voltage, and a second terminal connected to the second node;
A fifth transistor having a gate terminal connected to the first node, a first terminal receiving the low potential driving voltage, and a second terminal connected to the internal node; And
And a fifth-fourth thin film transistor having a gate terminal connected to the first node, a first terminal receiving the low potential driving voltage, and a second terminal connected to the second node. The method of claim 3,
Wherein the at least one holding stage comprises:
A carry output unit for outputting the carry signal in response to a voltage of the first control node and a voltage of the second control node;
A first driver that charges the node control voltage to the first control node in response to the stage set signal which is an output signal provided from the group of the front stage driving stage;
A second driving unit for discharging the voltage of the first control node to a low potential driving voltage in response to the stage reset signal which is an output signal provided from the rear stage driving stage group;
A third driver for discharging the voltage of the first control node to the low potential driving voltage in response to the voltage of the second control node;
A fourth driver for discharging the voltage of the second control node to the low potential driving voltage in response to the stage set signal; And
And a fifth driver for charging the node control voltage to the second control node or discharging the voltage of the second control node to the low potential drive voltage in response to the node control voltage and the voltage of the first control node , A display device. 18. The method of claim 17,
Wherein the fifth driver comprises:
A fifth transistor having a gate terminal receiving the node control voltage, and a second terminal connected to the first terminal and the intermediate node;
A fifth transistor having a gate terminal connected to the intermediate node, a first terminal receiving the node control voltage, and a second terminal connected to the second control node;
A fifth transistor having a gate terminal connected to the first control node, a first terminal receiving the low potential driving voltage, and a second terminal connected to the intermediate node; And
And a fifth transistor having a gate terminal connected to the first control node, a first terminal receiving the low potential driving voltage, and a second terminal connected to the second control node. 18. The method of claim 17,
And the third driving unit includes a noise removing transistor for discharging the voltage of the first control node to the low potential driving voltage in response to the voltage of the second control node,
Wherein the monitoring thin film transistor has the same size as the noise removing transistor. 10. The method of claim 9,
Wherein the at least one holding stage comprises:
A carry output unit for outputting the carry signal in response to a voltage of the first control node and a voltage of the second control node;
A first driver for charging the first control node with the first node control voltage in response to the stage set signal which is an output signal provided from the group of the front stage driving stage;
A second driving unit for discharging the voltage of the first control node to a low potential driving voltage in response to the stage reset signal which is an output signal provided from the rear stage driving stage group;
A third driver for discharging the voltage of the first control node to the low potential driving voltage in response to the voltage of the second control node;
A fourth driver for discharging the voltage of the second control node to the low potential driving voltage in response to the stage set signal; And
A fifth node for charging the second node control voltage to the second control node or discharging the voltage of the second control node to the low potential drive voltage in response to the second node control voltage and the voltage of the first control node, And a driving unit. 21. The method of claim 20,
Wherein the fifth driver comprises:
A fifth transistor having a gate terminal receiving the second node control voltage, and a second terminal connected to a first terminal and an intermediate node;
A fifth transistor having a gate terminal coupled to the intermediate node, a first terminal receiving the second node control voltage, and a second terminal coupled to the second control node;
A fifth transistor having a gate terminal connected to the first control node, a first terminal receiving the low potential driving voltage, and a second terminal connected to the intermediate node; And
And a fifth transistor having a gate terminal connected to the first control node, a first terminal receiving the low potential driving voltage, and a second terminal connected to the second control node. 21. The method of claim 20,
Wherein the carry output section includes a carry-up pull-up transistor for outputting the carry signal in response to a voltage of the first control node,
And the third driving unit includes a noise removing transistor for discharging the voltage of the first control node to the low potential driving voltage in response to the voltage of the second control node,
The first monitoring thin film transistor has the same size as the pull-up transistor for carrying,
And the second monitoring thin film transistor has the same size as the noise removing transistor. 23. The method according to any one of claims 3 to 22,
Wherein the at least one holding stage outputs a scan holding clock as the carry signal according to a voltage of the first control node. 24. The method of claim 23,
Wherein the scan holding clock is polled from the high voltage level to the low voltage level immediately after the end of the touch sensing period or at the start time of the display period to a high voltage level at a low voltage level and after a predetermined period, . 24. The method of claim 23,
Wherein the gate driving circuit comprises:
A first shift register including the plurality of driving stage groups and the plurality of holding stage groups and supplying scan pulses to odd-numbered gate lines of the plurality of gate lines; And
And a second shift register including the plurality of driving stage groups and the plurality of holding stage groups and supplying scan pulses to even-numbered gate lines among the plurality of gate lines. 23. The method according to any one of claims 1 to 22,
The touch driving circuit supplies a common voltage to the touch sensors included in the corresponding horizontal block for each display period and senses a touch on the touch object through the touch sensors included in the corresponding horizontal block for each of the touch sensing periods , A display device. 23. The method according to any one of claims 1 to 22,
The touch-
A common voltage is supplied to the touch sensors included in the corresponding horizontal block for each display period,
Supplying a touch pen synchronization signal to touch sensors included in a corresponding horizontal block for each pen sensing period of the plurality of touch sensing intervals and sensing a signal transmitted from the touch pen through the corresponding touch sensors,
And supplying a touch driving pulse to the touch sensors included in the corresponding horizontal block for each of the finger sensing intervals set in the remaining portion of the plurality of touch sensing intervals and sensing a change in capacitance of the corresponding touch sensors.

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